MipsSEISelLowering.h revision 280031
1178172Simp//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===// 2178172Simp// 3178172Simp// The LLVM Compiler Infrastructure 4178172Simp// 5178172Simp// This file is distributed under the University of Illinois Open Source 6178172Simp// License. See LICENSE.TXT for details. 7178172Simp// 8178172Simp//===----------------------------------------------------------------------===// 9178172Simp// 10178172Simp// Subclass of MipsTargetLowering specialized for mips32/64. 11178172Simp// 12178172Simp//===----------------------------------------------------------------------===// 13178172Simp 14178172Simp#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 15178172Simp#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 16178172Simp 17178172Simp#include "MipsISelLowering.h" 18178172Simp#include "MipsRegisterInfo.h" 19178172Simp 20178172Simpnamespace llvm { 21178172Simp class MipsSETargetLowering : public MipsTargetLowering { 22178172Simp public: 23178172Simp explicit MipsSETargetLowering(const MipsTargetMachine &TM, 24178172Simp const MipsSubtarget &STI); 25178172Simp 26178172Simp /// \brief Enable MSA support for the given integer type and Register 27178172Simp /// class. 28178172Simp void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 29178172Simp /// \brief Enable MSA support for the given floating-point type and 30178172Simp /// Register class. 31178172Simp void addMSAFloatType(MVT::SimpleValueType Ty, 32178172Simp const TargetRegisterClass *RC); 33178172Simp 34178172Simp bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0, 35178172Simp unsigned Align = 1, 36178172Simp bool *Fast = nullptr) const override; 37178172Simp 38178172Simp SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 39178172Simp 40178172Simp SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 41218266Stijl 42217155Stijl MachineBasicBlock * 43217155Stijl EmitInstrWithCustomInserter(MachineInstr *MI, 44206715Sjmallett MachineBasicBlock *MBB) const override; 45217155Stijl 46217155Stijl bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 47206715Sjmallett EVT VT) const override { 48206715Sjmallett return false; 49178172Simp } 50178172Simp 51217156Stijl const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 52217156Stijl 53217156Stijl private: 54217155Stijl bool isEligibleForTailCallOptimization( 55217156Stijl const CCState &CCInfo, unsigned NextStackOffset, 56217156Stijl const MipsFunctionInfo &FI) const override; 57217156Stijl 58217155Stijl void 59217156Stijl getOpndList(SmallVectorImpl<SDValue> &Ops, 60217156Stijl std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 61217156Stijl bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 62217155Stijl bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 63217156Stijl SDValue Chain) const override; 64217155Stijl 65178172Simp SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 66217156Stijl SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 67217156Stijl 68217156Stijl SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, 69217155Stijl SelectionDAG &DAG) const; 70217156Stijl 71217156Stijl SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 72217156Stijl SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 73217155Stijl SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 74217156Stijl SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 75217156Stijl SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 76217156Stijl /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions 77217155Stijl /// depending on the indices in the shuffle. 78217156Stijl SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 79217155Stijl 80178172Simp MachineBasicBlock *emitBPOSGE32(MachineInstr *MI, 81178172Simp MachineBasicBlock *BB) const; 82178172Simp MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI, 83217156Stijl MachineBasicBlock *BB, 84217156Stijl unsigned BranchOp) const; 85217156Stijl /// \brief Emit the COPY_FW pseudo instruction 86217155Stijl MachineBasicBlock *emitCOPY_FW(MachineInstr *MI, 87217156Stijl MachineBasicBlock *BB) const; 88217156Stijl /// \brief Emit the COPY_FD pseudo instruction 89217156Stijl MachineBasicBlock *emitCOPY_FD(MachineInstr *MI, 90217155Stijl MachineBasicBlock *BB) const; 91217156Stijl /// \brief Emit the INSERT_FW pseudo instruction 92217156Stijl MachineBasicBlock *emitINSERT_FW(MachineInstr *MI, 93217156Stijl MachineBasicBlock *BB) const; 94217155Stijl /// \brief Emit the INSERT_FD pseudo instruction 95217156Stijl MachineBasicBlock *emitINSERT_FD(MachineInstr *MI, 96217155Stijl MachineBasicBlock *BB) const; 97178172Simp /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction 98217156Stijl MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI, 99217156Stijl MachineBasicBlock *BB, 100217156Stijl unsigned EltSizeInBytes, 101217155Stijl bool IsFP) const; 102217156Stijl /// \brief Emit the FILL_FW pseudo instruction 103217156Stijl MachineBasicBlock *emitFILL_FW(MachineInstr *MI, 104217156Stijl MachineBasicBlock *BB) const; 105217155Stijl /// \brief Emit the FILL_FD pseudo instruction 106217156Stijl MachineBasicBlock *emitFILL_FD(MachineInstr *MI, 107217156Stijl MachineBasicBlock *BB) const; 108217156Stijl /// \brief Emit the FEXP2_W_1 pseudo instructions. 109217155Stijl MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI, 110217156Stijl MachineBasicBlock *BB) const; 111217155Stijl /// \brief Emit the FEXP2_D_1 pseudo instructions. 112178172Simp MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI, 113217156Stijl MachineBasicBlock *BB) const; 114217156Stijl }; 115217156Stijl} 116217155Stijl 117217156Stijl#endif 118217156Stijl