MipsSEISelLowering.h revision 280031 
1//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
15#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
16
17#include "MipsISelLowering.h"
18#include "MipsRegisterInfo.h"
19
20namespace llvm {
21  class MipsSETargetLowering : public MipsTargetLowering  {
22  public:
23    explicit MipsSETargetLowering(const MipsTargetMachine &TM,
24                                  const MipsSubtarget &STI);
25
26    /// \brief Enable MSA support for the given integer type and Register
27    /// class.
28    void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
29    /// \brief Enable MSA support for the given floating-point type and
30    /// Register class.
31    void addMSAFloatType(MVT::SimpleValueType Ty,
32                         const TargetRegisterClass *RC);
33
34    bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0,
35                                        unsigned Align = 1,
36                                        bool *Fast = nullptr) const override;
37
38    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
39
40    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
41
42    MachineBasicBlock *
43    EmitInstrWithCustomInserter(MachineInstr *MI,
44                                MachineBasicBlock *MBB) const override;
45
46    bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
47                            EVT VT) const override {
48      return false;
49    }
50
51    const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
52
53  private:
54    bool isEligibleForTailCallOptimization(
55        const CCState &CCInfo, unsigned NextStackOffset,
56        const MipsFunctionInfo &FI) const override;
57
58    void
59    getOpndList(SmallVectorImpl<SDValue> &Ops,
60                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
61                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
62                bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
63                SDValue Chain) const override;
64
65    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
66    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
67
68    SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
69                        SelectionDAG &DAG) const;
70
71    SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
72    SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
73    SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
74    SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
75    SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
76    /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
77    /// depending on the indices in the shuffle.
78    SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
79
80    MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
81                                    MachineBasicBlock *BB) const;
82    MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
83                                            MachineBasicBlock *BB,
84                                            unsigned BranchOp) const;
85    /// \brief Emit the COPY_FW pseudo instruction
86    MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
87                                   MachineBasicBlock *BB) const;
88    /// \brief Emit the COPY_FD pseudo instruction
89    MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
90                                   MachineBasicBlock *BB) const;
91    /// \brief Emit the INSERT_FW pseudo instruction
92    MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
93                                     MachineBasicBlock *BB) const;
94    /// \brief Emit the INSERT_FD pseudo instruction
95    MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
96                                     MachineBasicBlock *BB) const;
97    /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
98    MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
99                                          MachineBasicBlock *BB,
100                                          unsigned EltSizeInBytes,
101                                          bool IsFP) const;
102    /// \brief Emit the FILL_FW pseudo instruction
103    MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
104                                   MachineBasicBlock *BB) const;
105    /// \brief Emit the FILL_FD pseudo instruction
106    MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
107                                   MachineBasicBlock *BB) const;
108    /// \brief Emit the FEXP2_W_1 pseudo instructions.
109    MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI,
110                                     MachineBasicBlock *BB) const;
111    /// \brief Emit the FEXP2_D_1 pseudo instructions.
112    MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
113                                     MachineBasicBlock *BB) const;
114  };
115}
116
117#endif
118