MipsSEISelLowering.h revision 277320
167754Smsmith//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===// 267754Smsmith// 377424Smsmith// The LLVM Compiler Infrastructure 483174Smsmith// 567754Smsmith// This file is distributed under the University of Illinois Open Source 667754Smsmith// License. See LICENSE.TXT for details. 767754Smsmith// 867754Smsmith//===----------------------------------------------------------------------===// 967754Smsmith// 1067754Smsmith// Subclass of MipsTargetLowering specialized for mips32/64. 1167754Smsmith// 1271867Smsmith//===----------------------------------------------------------------------===// 1370243Smsmith 1467754Smsmith#ifndef MIPSSEISELLOWERING_H 1567754Smsmith#define MIPSSEISELLOWERING_H 1667754Smsmith 1767754Smsmith#include "MipsISelLowering.h" 1867754Smsmith#include "MipsRegisterInfo.h" 1967754Smsmith 2067754Smsmithnamespace llvm { 2167754Smsmith class MipsSETargetLowering : public MipsTargetLowering { 2267754Smsmith public: 2367754Smsmith explicit MipsSETargetLowering(MipsTargetMachine &TM, 2467754Smsmith const MipsSubtarget &STI); 2567754Smsmith 2667754Smsmith /// \brief Enable MSA support for the given integer type and Register 2767754Smsmith /// class. 2867754Smsmith void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 2967754Smsmith /// \brief Enable MSA support for the given floating-point type and 3067754Smsmith /// Register class. 3167754Smsmith void addMSAFloatType(MVT::SimpleValueType Ty, 3267754Smsmith const TargetRegisterClass *RC); 3367754Smsmith 3467754Smsmith bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0, 3567754Smsmith bool *Fast = nullptr) const override; 3667754Smsmith 3767754Smsmith SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 3867754Smsmith 3967754Smsmith SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 4067754Smsmith 4167754Smsmith MachineBasicBlock * 4267754Smsmith EmitInstrWithCustomInserter(MachineInstr *MI, 4367754Smsmith MachineBasicBlock *MBB) const override; 4467754Smsmith 4567754Smsmith bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 4667754Smsmith EVT VT) const override { 4767754Smsmith return false; 4867754Smsmith } 4967754Smsmith 5067754Smsmith const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 5167754Smsmith 5267754Smsmith private: 5367754Smsmith bool isEligibleForTailCallOptimization( 5467754Smsmith const CCState &CCInfo, unsigned NextStackOffset, 5567754Smsmith const MipsFunctionInfo &FI) const override; 5667754Smsmith 5767754Smsmith void 5867754Smsmith getOpndList(SmallVectorImpl<SDValue> &Ops, 5967754Smsmith std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 6067754Smsmith bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 6167754Smsmith CallLoweringInfo &CLI, SDValue Callee, 6267754Smsmith SDValue Chain) const override; 6367754Smsmith 6467754Smsmith SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 6567754Smsmith SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 6667754Smsmith 6767754Smsmith SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, 6867754Smsmith SelectionDAG &DAG) const; 6967754Smsmith 7067754Smsmith SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 7167754Smsmith SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 7267754Smsmith SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 7367754Smsmith SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 7467754Smsmith SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 7567754Smsmith /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions 7667754Smsmith /// depending on the indices in the shuffle. 7767754Smsmith SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 7867754Smsmith 7967754Smsmith MachineBasicBlock *emitBPOSGE32(MachineInstr *MI, 8067754Smsmith MachineBasicBlock *BB) const; 8167754Smsmith MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI, 8267754Smsmith MachineBasicBlock *BB, 8367754Smsmith unsigned BranchOp) const; 8467754Smsmith /// \brief Emit the COPY_FW pseudo instruction 8567754Smsmith MachineBasicBlock *emitCOPY_FW(MachineInstr *MI, 8667754Smsmith MachineBasicBlock *BB) const; 8767754Smsmith /// \brief Emit the COPY_FD pseudo instruction 8867754Smsmith MachineBasicBlock *emitCOPY_FD(MachineInstr *MI, 8967754Smsmith MachineBasicBlock *BB) const; 9067754Smsmith /// \brief Emit the INSERT_FW pseudo instruction 9167754Smsmith MachineBasicBlock *emitINSERT_FW(MachineInstr *MI, 9267754Smsmith MachineBasicBlock *BB) const; 9367754Smsmith /// \brief Emit the INSERT_FD pseudo instruction 9467754Smsmith MachineBasicBlock *emitINSERT_FD(MachineInstr *MI, 9567754Smsmith MachineBasicBlock *BB) const; 9667754Smsmith /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction 9767754Smsmith MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI, 9867754Smsmith MachineBasicBlock *BB, 9967754Smsmith unsigned EltSizeInBytes, 10067754Smsmith bool IsFP) const; 10167754Smsmith /// \brief Emit the FILL_FW pseudo instruction 10267754Smsmith MachineBasicBlock *emitFILL_FW(MachineInstr *MI, 10367754Smsmith MachineBasicBlock *BB) const; 10467754Smsmith /// \brief Emit the FILL_FD pseudo instruction 10567754Smsmith MachineBasicBlock *emitFILL_FD(MachineInstr *MI, 10667754Smsmith MachineBasicBlock *BB) const; 10767754Smsmith /// \brief Emit the FEXP2_W_1 pseudo instructions. 10867754Smsmith MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI, 10967754Smsmith MachineBasicBlock *BB) const; 11067754Smsmith /// \brief Emit the FEXP2_D_1 pseudo instructions. 11167754Smsmith MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI, 11267754Smsmith MachineBasicBlock *BB) const; 11367754Smsmith }; 11467754Smsmith} 11567754Smsmith 11667754Smsmith#endif // MipsSEISELLOWERING_H 11767754Smsmith