MipsSEISelLowering.h revision 277320 
1//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSSEISELLOWERING_H
15#define MIPSSEISELLOWERING_H
16
17#include "MipsISelLowering.h"
18#include "MipsRegisterInfo.h"
19
20namespace llvm {
21  class MipsSETargetLowering : public MipsTargetLowering  {
22  public:
23    explicit MipsSETargetLowering(MipsTargetMachine &TM,
24                                  const MipsSubtarget &STI);
25
26    /// \brief Enable MSA support for the given integer type and Register
27    /// class.
28    void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
29    /// \brief Enable MSA support for the given floating-point type and
30    /// Register class.
31    void addMSAFloatType(MVT::SimpleValueType Ty,
32                         const TargetRegisterClass *RC);
33
34    bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0,
35                                       bool *Fast = nullptr) const override;
36
37    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
38
39    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
40
41    MachineBasicBlock *
42    EmitInstrWithCustomInserter(MachineInstr *MI,
43                                MachineBasicBlock *MBB) const override;
44
45    bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
46                            EVT VT) const override {
47      return false;
48    }
49
50    const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
51
52  private:
53    bool isEligibleForTailCallOptimization(
54        const CCState &CCInfo, unsigned NextStackOffset,
55        const MipsFunctionInfo &FI) const override;
56
57    void
58    getOpndList(SmallVectorImpl<SDValue> &Ops,
59                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
60                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
61                CallLoweringInfo &CLI, SDValue Callee,
62                SDValue Chain) const override;
63
64    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
65    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
66
67    SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
68                        SelectionDAG &DAG) const;
69
70    SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
71    SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
72    SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
73    SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
74    SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
75    /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
76    /// depending on the indices in the shuffle.
77    SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
78
79    MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
80                                    MachineBasicBlock *BB) const;
81    MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
82                                            MachineBasicBlock *BB,
83                                            unsigned BranchOp) const;
84    /// \brief Emit the COPY_FW pseudo instruction
85    MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
86                                   MachineBasicBlock *BB) const;
87    /// \brief Emit the COPY_FD pseudo instruction
88    MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
89                                   MachineBasicBlock *BB) const;
90    /// \brief Emit the INSERT_FW pseudo instruction
91    MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
92                                     MachineBasicBlock *BB) const;
93    /// \brief Emit the INSERT_FD pseudo instruction
94    MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
95                                     MachineBasicBlock *BB) const;
96    /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
97    MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
98                                          MachineBasicBlock *BB,
99                                          unsigned EltSizeInBytes,
100                                          bool IsFP) const;
101    /// \brief Emit the FILL_FW pseudo instruction
102    MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
103                                   MachineBasicBlock *BB) const;
104    /// \brief Emit the FILL_FD pseudo instruction
105    MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
106                                   MachineBasicBlock *BB) const;
107    /// \brief Emit the FEXP2_W_1 pseudo instructions.
108    MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI,
109                                     MachineBasicBlock *BB) const;
110    /// \brief Emit the FEXP2_D_1 pseudo instructions.
111    MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
112                                     MachineBasicBlock *BB) const;
113  };
114}
115
116#endif // MipsSEISELLOWERING_H
117