1234285Sdim//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim// 10234285Sdim// This is the Conditional Moves implementation. 11234285Sdim// 12234285Sdim//===----------------------------------------------------------------------===// 13234285Sdim 14234285Sdim// Conditional moves: 15234285Sdim// These instructions are expanded in 16234285Sdim// MipsISelLowering::EmitInstrWithCustomInserter if target does not have 17234285Sdim// conditional move instructions. 18234285Sdim// cond:int, data:int 19261991Sdimclass CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, 20249423Sdim InstrItinClass Itin> : 21249423Sdim InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F), 22261991Sdim !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> { 23234285Sdim let Constraints = "$F = $rd"; 24234285Sdim} 25234285Sdim 26234285Sdim// cond:int, data:float 27261991Sdimclass CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, 28249423Sdim InstrItinClass Itin> : 29249423Sdim InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F), 30288943Sdim !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>, 31288943Sdim HARDFLOAT { 32234285Sdim let Constraints = "$F = $fd"; 33234285Sdim} 34234285Sdim 35234285Sdim// cond:float, data:int 36261991Sdimclass CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 37249423Sdim SDPatternOperator OpNode = null_frag> : 38261991Sdim InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F), 39261991Sdim !strconcat(opstr, "\t$rd, $rs, $fcc"), 40261991Sdim [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))], 41288943Sdim Itin, FrmFR, opstr>, HARDFLOAT { 42234285Sdim let Constraints = "$F = $rd"; 43234285Sdim} 44234285Sdim 45234285Sdim// cond:float, data:float 46261991Sdimclass CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 47249423Sdim SDPatternOperator OpNode = null_frag> : 48261991Sdim InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F), 49261991Sdim !strconcat(opstr, "\t$fd, $fs, $fcc"), 50261991Sdim [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))], 51288943Sdim Itin, FrmFR, opstr>, HARDFLOAT { 52234285Sdim let Constraints = "$F = $fd"; 53234285Sdim} 54234285Sdim 55234285Sdim// select patterns 56234285Sdimmulticlass MovzPats0<RegisterClass CRC, RegisterClass DRC, 57234285Sdim Instruction MOVZInst, Instruction SLTOp, 58234285Sdim Instruction SLTuOp, Instruction SLTiOp, 59234285Sdim Instruction SLTiuOp> { 60239462Sdim def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 61239462Sdim (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>; 62249423Sdim def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 63249423Sdim (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>; 64249423Sdim def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F), 65249423Sdim (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>; 66249423Sdim def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F), 67249423Sdim (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>; 68249423Sdim def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 69249423Sdim (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>; 70249423Sdim def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 71249423Sdim (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>; 72249423Sdim def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)), 73249423Sdim DRC:$T, DRC:$F), 74249423Sdim (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>; 75249423Sdim def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)), 76249423Sdim DRC:$T, DRC:$F), 77249423Sdim (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)), 78249423Sdim DRC:$F)>; 79234285Sdim} 80234285Sdim 81234285Sdimmulticlass MovzPats1<RegisterClass CRC, RegisterClass DRC, 82234285Sdim Instruction MOVZInst, Instruction XOROp> { 83239462Sdim def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 84239462Sdim (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; 85239462Sdim def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F), 86239462Sdim (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>; 87234285Sdim} 88234285Sdim 89239462Sdimmulticlass MovzPats2<RegisterClass CRC, RegisterClass DRC, 90239462Sdim Instruction MOVZInst, Instruction XORiOp> { 91239462Sdim def : MipsPat< 92239462Sdim (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F), 93239462Sdim (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>; 94239462Sdim} 95239462Sdim 96234285Sdimmulticlass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst, 97234285Sdim Instruction XOROp> { 98239462Sdim def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 99239462Sdim (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; 100239462Sdim def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F), 101239462Sdim (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>; 102239462Sdim def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F), 103239462Sdim (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>; 104234285Sdim} 105234285Sdim 106234285Sdim// Instantiation of instructions. 107276479Sdimdef MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>, 108276479Sdim ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; 109261991Sdim 110276479Sdimlet isCodeGenOnly = 1 in { 111276479Sdim def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>, 112276479Sdim ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; 113276479Sdim def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>, 114276479Sdim ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; 115276479Sdim def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>, 116276479Sdim ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; 117234285Sdim} 118234285Sdim 119276479Sdimdef MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>, 120276479Sdim ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; 121261991Sdim 122276479Sdimlet isCodeGenOnly = 1 in { 123276479Sdim def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>, 124276479Sdim ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; 125276479Sdim def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>, 126276479Sdim ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; 127276479Sdim def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>, 128276479Sdim ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; 129234285Sdim} 130234285Sdim 131276479Sdimdef MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, 132276479Sdim CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6; 133234285Sdim 134261991Sdimlet isCodeGenOnly = 1 in 135276479Sdimdef MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>, 136276479Sdim CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, 137276479Sdim AdditionalRequires<[HasMips64]>; 138261991Sdim 139276479Sdimdef MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>, 140276479Sdim CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6; 141234285Sdim 142261991Sdimlet isCodeGenOnly = 1 in 143276479Sdimdef MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>, 144276479Sdim CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, 145276479Sdim AdditionalRequires<[IsGP64bit]>; 146261991Sdim 147276479Sdimdef MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, 148276479Sdim II_MOVZ_D>, CMov_I_F_FM<18, 17>, 149276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 150276479Sdimdef MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, 151276479Sdim II_MOVN_D>, CMov_I_F_FM<19, 17>, 152276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 153261991Sdim 154276479Sdimlet DecoderNamespace = "Mips64" in { 155276479Sdim def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>, 156276479Sdim CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 157276479Sdim def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>, 158276479Sdim CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 159261991Sdim let isCodeGenOnly = 1 in { 160276479Sdim def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>, 161276479Sdim CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 162276479Sdim def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>, 163276479Sdim CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 164234982Sdim } 165234285Sdim} 166234285Sdim 167276479Sdimdef MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>, 168276479Sdim CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6; 169234285Sdim 170261991Sdimlet isCodeGenOnly = 1 in 171276479Sdimdef MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>, 172276479Sdim CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, 173276479Sdim AdditionalRequires<[IsGP64bit]>; 174234285Sdim 175276479Sdimdef MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>, 176276479Sdim CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6; 177261991Sdim 178261991Sdimlet isCodeGenOnly = 1 in 179276479Sdimdef MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>, 180276479Sdim CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, 181276479Sdim AdditionalRequires<[IsGP64bit]>; 182261991Sdim 183276479Sdimdef MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>, 184276479Sdim CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6; 185276479Sdimdef MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>, 186276479Sdim CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6; 187234285Sdim 188276479Sdimdef MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, 189276479Sdim MipsCMovFP_T>, CMov_F_F_FM<17, 1>, 190276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 191276479Sdimdef MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, 192276479Sdim MipsCMovFP_F>, CMov_F_F_FM<17, 0>, 193276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 194261991Sdim 195276479Sdimlet DecoderNamespace = "Mips64" in { 196276479Sdim def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>, 197276479Sdim CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 198276479Sdim def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>, 199276479Sdim CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 200234285Sdim} 201234285Sdim 202234285Sdim// Instantiation of conditional move patterns. 203276479Sdimdefm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>, 204276479Sdim INSN_MIPS4_32_NOT_32R6_64R6; 205276479Sdimdefm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; 206276479Sdimdefm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6; 207234285Sdim 208276479Sdimdefm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>, 209276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 210276479Sdimdefm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>, 211276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 212276479Sdimdefm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>, 213276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 214276479Sdimdefm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>, 215276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 216276479Sdimdefm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>, 217276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 218276479Sdimdefm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>, 219276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 220276479Sdimdefm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>, 221276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 222276479Sdimdefm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>, 223276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 224276479Sdimdefm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>, 225276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 226234285Sdim 227276479Sdimdefm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; 228234285Sdim 229276479Sdimdefm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 230276479Sdim GPR_64; 231276479Sdimdefm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 232276479Sdim GPR_64; 233276479Sdimdefm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 234276479Sdim GPR_64; 235276479Sdim 236276479Sdimdefm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>, 237276479Sdim INSN_MIPS4_32_NOT_32R6_64R6; 238276479Sdimdefm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; 239276479Sdimdefm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; 240276479Sdim 241276479Sdimdefm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>, 242276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 243276479Sdimdefm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 244276479Sdim GPR_64; 245276479Sdimdefm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 246276479Sdim GPR_64; 247276479Sdim 248276479Sdimdefm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>, 249276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 250276479Sdimdefm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 251276479Sdim FGR_32; 252276479Sdimdefm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 253276479Sdim FGR_32; 254276479Sdim 255276479Sdimdefm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>, 256276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 257276479Sdimdefm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>, 258276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 259276479Sdimdefm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 260276479Sdim FGR_64; 261276479Sdimdefm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>, 262276479Sdim INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 263276479Sdimdefm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 264276479Sdim FGR_64; 265276479Sdimdefm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 266276479Sdim FGR_64; 267280031Sdim 268280031Sdim// For targets that don't have conditional-move instructions 269280031Sdim// we have to match SELECT nodes with pseudo instructions. 270280031Sdimlet usesCustomInserter = 1 in { 271280031Sdim class Select_Pseudo<RegisterOperand RC> : 272280031Sdim PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), 273280031Sdim [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>, 274280031Sdim ISA_MIPS1_NOT_4_32; 275280031Sdim 276280031Sdim class SelectFP_Pseudo_T<RegisterOperand RC> : 277280031Sdim PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), 278280031Sdim [(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>, 279280031Sdim ISA_MIPS1_NOT_4_32; 280280031Sdim 281280031Sdim class SelectFP_Pseudo_F<RegisterOperand RC> : 282280031Sdim PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), 283280031Sdim [(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>, 284280031Sdim ISA_MIPS1_NOT_4_32; 285280031Sdim} 286280031Sdim 287280031Sdimdef PseudoSELECT_I : Select_Pseudo<GPR32Opnd>; 288280031Sdimdef PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>; 289280031Sdimdef PseudoSELECT_S : Select_Pseudo<FGR32Opnd>; 290280031Sdimdef PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32; 291280031Sdimdef PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64; 292280031Sdim 293280031Sdimdef PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>; 294280031Sdimdef PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>; 295280031Sdimdef PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>; 296280031Sdimdef PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32; 297280031Sdimdef PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64; 298280031Sdim 299280031Sdimdef PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>; 300280031Sdimdef PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>; 301280031Sdimdef PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>; 302280031Sdimdef PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32; 303280031Sdimdef PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64; 304