1//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the Conditional Moves implementation.
11//
12//===----------------------------------------------------------------------===//
13
14// Conditional moves:
15// These instructions are expanded in
16// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
17// conditional move instructions.
18// cond:int, data:int
19class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
20                  InstrItinClass Itin> :
21  InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
22         !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
23  let Constraints = "$F = $rd";
24}
25
26// cond:int, data:float
27class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
28                  InstrItinClass Itin> :
29  InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
30         !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>,
31  HARDFLOAT {
32  let Constraints = "$F = $fd";
33}
34
35// cond:float, data:int
36class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
37                  SDPatternOperator OpNode = null_frag> :
38  InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
39         !strconcat(opstr, "\t$rd, $rs, $fcc"),
40         [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
41         Itin, FrmFR, opstr>, HARDFLOAT {
42  let Constraints = "$F = $rd";
43}
44
45// cond:float, data:float
46class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
47                  SDPatternOperator OpNode = null_frag> :
48  InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
49         !strconcat(opstr, "\t$fd, $fs, $fcc"),
50         [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
51         Itin, FrmFR, opstr>, HARDFLOAT {
52  let Constraints = "$F = $fd";
53}
54
55// select patterns
56multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
57                     Instruction MOVZInst, Instruction SLTOp,
58                     Instruction SLTuOp, Instruction SLTiOp,
59                     Instruction SLTiuOp> {
60  def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
61                (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
62  def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
63                (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
64  def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
65                (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
66  def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
67                (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
68  def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
69                (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
70  def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
71                (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
72  def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
73                        DRC:$T, DRC:$F),
74                (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
75  def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),
76                        DRC:$T, DRC:$F),
77                (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
78                          DRC:$F)>;
79}
80
81multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
82                     Instruction MOVZInst, Instruction XOROp> {
83  def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
84                (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
85  def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
86                (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
87}
88
89multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
90                     Instruction MOVZInst, Instruction XORiOp> {
91  def : MipsPat<
92            (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
93            (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
94}
95
96multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
97                    Instruction XOROp> {
98  def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
99                (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
100  def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
101                (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
102  def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
103                (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
104}
105
106// Instantiation of instructions.
107def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
108               ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
109
110let isCodeGenOnly = 1 in {
111  def MOVZ_I_I64   : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
112                     ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
113  def MOVZ_I64_I   : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,
114                     ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
115  def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>,
116                     ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
117}
118
119def MOVN_I_I       : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
120                     ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
121
122let isCodeGenOnly = 1 in {
123  def MOVN_I_I64   : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
124                     ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
125  def MOVN_I64_I   : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
126                     ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
127  def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
128                     ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
129}
130
131def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
132               CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
133
134let isCodeGenOnly = 1 in
135def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
136                 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6,
137                 AdditionalRequires<[HasMips64]>;
138
139def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
140               CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
141
142let isCodeGenOnly = 1 in
143def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
144                 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6,
145                 AdditionalRequires<[IsGP64bit]>;
146
147def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
148                                    II_MOVZ_D>, CMov_I_F_FM<18, 17>,
149                 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
150def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
151                                    II_MOVN_D>, CMov_I_F_FM<19, 17>,
152                 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
153
154let DecoderNamespace = "Mips64" in {
155  def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
156                   CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
157  def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
158                   CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
159  let isCodeGenOnly = 1 in {
160    def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>,
161                       CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
162    def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,
163                       CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
164  }
165}
166
167def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
168             CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6;
169
170let isCodeGenOnly = 1 in
171def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
172               CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6,
173               AdditionalRequires<[IsGP64bit]>;
174
175def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
176             CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6;
177
178let isCodeGenOnly = 1 in
179def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
180               CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6,
181               AdditionalRequires<[IsGP64bit]>;
182
183def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
184             CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6;
185def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
186             CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6;
187
188def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
189                                  MipsCMovFP_T>, CMov_F_F_FM<17, 1>,
190               INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
191def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
192                                  MipsCMovFP_F>, CMov_F_F_FM<17, 0>,
193               INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
194
195let DecoderNamespace = "Mips64" in {
196  def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
197                 CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
198  def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
199                 CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
200}
201
202// Instantiation of conditional move patterns.
203defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204       INSN_MIPS4_32_NOT_32R6_64R6;
205defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
206defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;
207
208defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
209       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
210defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
211       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
212defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
213       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
214defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
215       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
216defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
217       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
218defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
219       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
220defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
221       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
222defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
223       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
224defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
225       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
226
227defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
228
229defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
230       GPR_64;
231defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
232       GPR_64;
233defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
234       GPR_64;
235
236defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
237       INSN_MIPS4_32_NOT_32R6_64R6;
238defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
239defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
240
241defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,
242       INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
243defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
244       GPR_64;
245defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
246       GPR_64;
247
248defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
249       INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
250defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
251       FGR_32;
252defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
253       FGR_32;
254
255defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
256       INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
257defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>,
258       INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
259defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
260       FGR_64;
261defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>,
262       INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
263defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
264       FGR_64;
265defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
266       FGR_64;
267
268// For targets that don't have conditional-move instructions
269// we have to match SELECT nodes with pseudo instructions.
270let usesCustomInserter = 1 in {
271  class Select_Pseudo<RegisterOperand RC> :
272    PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
273            [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
274    ISA_MIPS1_NOT_4_32;
275
276  class SelectFP_Pseudo_T<RegisterOperand RC> :
277    PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
278             [(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>,
279    ISA_MIPS1_NOT_4_32;
280
281  class SelectFP_Pseudo_F<RegisterOperand RC> :
282    PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
283             [(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>,
284    ISA_MIPS1_NOT_4_32;
285}
286
287def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>;
288def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>;
289def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>;
290def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32;
291def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64;
292
293def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>;
294def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>;
295def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>;
296def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32;
297def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64;
298
299def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>;
300def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>;
301def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>;
302def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32;
303def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64;
304