1//=-  MicroMips64r6InstrInfo.td - Instruction Information  -*- tablegen -*- -=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes MicroMips64r6 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15//
16// Instruction Encodings
17//
18//===----------------------------------------------------------------------===//
19
20class DAUI_MMR6_ENC : DAUI_FM_MMR6;
21class DAHI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10001>;
22class DATI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10000>;
23class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
24class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
25class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
26class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
27class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
28class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
29class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
30class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
31
32//===----------------------------------------------------------------------===//
33//
34// Instruction Descriptions
35//
36//===----------------------------------------------------------------------===//
37
38class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
39    : MMR6Arch<instr_asm>, MipsR6Inst {
40  dag OutOperandList = (outs GPROpnd:$rt);
41  dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
42  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
43  list<dag> Pattern = [];
44}
45class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>;
46
47class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
48    : MMR6Arch<instr_asm>, MipsR6Inst {
49  dag OutOperandList = (outs GPROpnd:$rs);
50  dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
51  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
52  string Constraints = "$rs = $rt";
53}
54class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>;
55class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
56
57class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
58                        Operand SizeOpnd, SDPatternOperator Op = null_frag>
59    : MMR6Arch<instr_asm>, MipsR6Inst {
60  dag OutOperandList = (outs RO:$rt);
61  dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
62  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
63  list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
64  InstrItinClass Itinerary = II_EXT;
65  Format Form = FrmR;
66  string BaseOpcode = instr_asm;
67}
68// TODO: Add 'pos + size' constraint check to dext* instructions
69//       DEXT: 0 < pos + size <= 63
70//       DEXTM, DEXTU: 32 < pos + size <= 64
71class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5,
72                                         uimm5_plus1, MipsExt>;
73class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
74                                          uimm5_plus33, MipsExt>;
75class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
76                                          uimm5_plus1, MipsExt>;
77
78class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
79                      Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
80  dag OutOperandList = (outs GPROpnd:$rd);
81  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
82  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
83  list<dag> Pattern = [];
84}
85
86class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
87
88class DDIV_MM64R6_DESC : ArithLogicR<"ddiv", GPR32Opnd>;
89class DMOD_MM64R6_DESC : ArithLogicR<"dmod", GPR32Opnd>;
90class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
91class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
92
93//===----------------------------------------------------------------------===//
94//
95// Instruction Definitions
96//
97//===----------------------------------------------------------------------===//
98
99let DecoderNamespace = "MicroMipsR6" in {
100  def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
101  def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
102  def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
103  def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
104                    ISA_MICROMIPS64R6;
105  def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
106                     ISA_MICROMIPS64R6;
107  def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
108                     ISA_MICROMIPS64R6;
109  def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
110                      ISA_MICROMIPS64R6;
111  def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
112                    ISA_MICROMIPS64R6;
113  def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
114                    ISA_MICROMIPS64R6;
115  def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
116                     ISA_MICROMIPS64R6;
117  def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
118                     ISA_MICROMIPS64R6;
119}
120