1//===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the MipsAsmBackend class. 11// 12//===----------------------------------------------------------------------===// 13// 14 15#include "MCTargetDesc/MipsFixupKinds.h" 16#include "MCTargetDesc/MipsAsmBackend.h" 17#include "MCTargetDesc/MipsMCTargetDesc.h" 18#include "llvm/MC/MCAsmBackend.h" 19#include "llvm/MC/MCAssembler.h" 20#include "llvm/MC/MCContext.h" 21#include "llvm/MC/MCDirectives.h" 22#include "llvm/MC/MCELFObjectWriter.h" 23#include "llvm/MC/MCFixupKindInfo.h" 24#include "llvm/MC/MCObjectWriter.h" 25#include "llvm/MC/MCSubtargetInfo.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/MathExtras.h" 28#include "llvm/Support/raw_ostream.h" 29 30using namespace llvm; 31 32// Prepare value for the target space for it 33static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 34 MCContext *Ctx = nullptr) { 35 36 unsigned Kind = Fixup.getKind(); 37 38 // Add/subtract and shift 39 switch (Kind) { 40 default: 41 return 0; 42 case FK_Data_2: 43 case FK_GPRel_4: 44 case FK_Data_4: 45 case FK_Data_8: 46 case Mips::fixup_Mips_LO16: 47 case Mips::fixup_Mips_GPREL16: 48 case Mips::fixup_Mips_GPOFF_HI: 49 case Mips::fixup_Mips_GPOFF_LO: 50 case Mips::fixup_Mips_GOT_PAGE: 51 case Mips::fixup_Mips_GOT_OFST: 52 case Mips::fixup_Mips_GOT_DISP: 53 case Mips::fixup_Mips_GOT_LO16: 54 case Mips::fixup_Mips_CALL_LO16: 55 case Mips::fixup_MICROMIPS_LO16: 56 case Mips::fixup_MICROMIPS_GOT_PAGE: 57 case Mips::fixup_MICROMIPS_GOT_OFST: 58 case Mips::fixup_MICROMIPS_GOT_DISP: 59 case Mips::fixup_MIPS_PCLO16: 60 break; 61 case Mips::fixup_Mips_PC16: 62 // The displacement is then divided by 4 to give us an 18 bit 63 // address range. Forcing a signed division because Value can be negative. 64 Value = (int64_t)Value / 4; 65 // We now check if Value can be encoded as a 16-bit signed immediate. 66 if (!isInt<16>(Value) && Ctx) { 67 Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup"); 68 return 0; 69 } 70 break; 71 case Mips::fixup_MIPS_PC19_S2: 72 // Forcing a signed division because Value can be negative. 73 Value = (int64_t)Value / 4; 74 // We now check if Value can be encoded as a 19-bit signed immediate. 75 if (!isInt<19>(Value) && Ctx) { 76 Ctx->reportError(Fixup.getLoc(), "out of range PC19 fixup"); 77 return 0; 78 } 79 break; 80 case Mips::fixup_Mips_26: 81 // So far we are only using this type for jumps. 82 // The displacement is then divided by 4 to give us an 28 bit 83 // address range. 84 Value >>= 2; 85 break; 86 case Mips::fixup_Mips_HI16: 87 case Mips::fixup_Mips_GOT_Local: 88 case Mips::fixup_Mips_GOT_HI16: 89 case Mips::fixup_Mips_CALL_HI16: 90 case Mips::fixup_MICROMIPS_HI16: 91 case Mips::fixup_MIPS_PCHI16: 92 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 93 Value = ((Value + 0x8000) >> 16) & 0xffff; 94 break; 95 case Mips::fixup_Mips_HIGHER: 96 // Get the 3rd 16-bits. 97 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 98 break; 99 case Mips::fixup_Mips_HIGHEST: 100 // Get the 4th 16-bits. 101 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 102 break; 103 case Mips::fixup_MICROMIPS_26_S1: 104 Value >>= 1; 105 break; 106 case Mips::fixup_MICROMIPS_PC7_S1: 107 Value -= 4; 108 // Forcing a signed division because Value can be negative. 109 Value = (int64_t) Value / 2; 110 // We now check if Value can be encoded as a 7-bit signed immediate. 111 if (!isInt<7>(Value) && Ctx) { 112 Ctx->reportError(Fixup.getLoc(), "out of range PC7 fixup"); 113 return 0; 114 } 115 break; 116 case Mips::fixup_MICROMIPS_PC10_S1: 117 Value -= 2; 118 // Forcing a signed division because Value can be negative. 119 Value = (int64_t) Value / 2; 120 // We now check if Value can be encoded as a 10-bit signed immediate. 121 if (!isInt<10>(Value) && Ctx) { 122 Ctx->reportError(Fixup.getLoc(), "out of range PC10 fixup"); 123 return 0; 124 } 125 break; 126 case Mips::fixup_MICROMIPS_PC16_S1: 127 Value -= 4; 128 // Forcing a signed division because Value can be negative. 129 Value = (int64_t)Value / 2; 130 // We now check if Value can be encoded as a 16-bit signed immediate. 131 if (!isInt<16>(Value) && Ctx) { 132 Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup"); 133 return 0; 134 } 135 break; 136 case Mips::fixup_MIPS_PC18_S3: 137 // Forcing a signed division because Value can be negative. 138 Value = (int64_t)Value / 8; 139 // We now check if Value can be encoded as a 18-bit signed immediate. 140 if (!isInt<18>(Value) && Ctx) { 141 Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup"); 142 return 0; 143 } 144 break; 145 case Mips::fixup_MIPS_PC21_S2: 146 // Forcing a signed division because Value can be negative. 147 Value = (int64_t) Value / 4; 148 // We now check if Value can be encoded as a 21-bit signed immediate. 149 if (!isInt<21>(Value) && Ctx) { 150 Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup"); 151 return 0; 152 } 153 break; 154 case Mips::fixup_MIPS_PC26_S2: 155 // Forcing a signed division because Value can be negative. 156 Value = (int64_t) Value / 4; 157 // We now check if Value can be encoded as a 26-bit signed immediate. 158 if (!isInt<26>(Value) && Ctx) { 159 Ctx->reportError(Fixup.getLoc(), "out of range PC26 fixup"); 160 return 0; 161 } 162 break; 163 } 164 165 return Value; 166} 167 168MCObjectWriter * 169MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { 170 return createMipsELFObjectWriter(OS, 171 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 172} 173 174// Little-endian fixup data byte ordering: 175// mips32r2: a | b | x | x 176// microMIPS: x | x | a | b 177 178static bool needsMMLEByteOrder(unsigned Kind) { 179 return Kind != Mips::fixup_MICROMIPS_PC10_S1 && 180 Kind >= Mips::fixup_MICROMIPS_26_S1 && 181 Kind < Mips::LastTargetFixupKind; 182} 183 184// Calculate index for microMIPS specific little endian byte order 185static unsigned calculateMMLEIndex(unsigned i) { 186 assert(i <= 3 && "Index out of range!"); 187 188 return (1 - i / 2) * 2 + i % 2; 189} 190 191/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 192/// data fragment, at the offset specified by the fixup and following the 193/// fixup kind as appropriate. 194void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 195 unsigned DataSize, uint64_t Value, 196 bool IsPCRel) const { 197 MCFixupKind Kind = Fixup.getKind(); 198 Value = adjustFixupValue(Fixup, Value); 199 200 if (!Value) 201 return; // Doesn't change encoding. 202 203 // Where do we start in the object 204 unsigned Offset = Fixup.getOffset(); 205 // Number of bytes we need to fixup 206 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 207 // Used to point to big endian bytes 208 unsigned FullSize; 209 210 switch ((unsigned)Kind) { 211 case FK_Data_2: 212 case Mips::fixup_Mips_16: 213 case Mips::fixup_MICROMIPS_PC10_S1: 214 FullSize = 2; 215 break; 216 case FK_Data_8: 217 case Mips::fixup_Mips_64: 218 FullSize = 8; 219 break; 220 case FK_Data_4: 221 default: 222 FullSize = 4; 223 break; 224 } 225 226 // Grab current value, if any, from bits. 227 uint64_t CurVal = 0; 228 229 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); 230 231 for (unsigned i = 0; i != NumBytes; ++i) { 232 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 233 : i) 234 : (FullSize - 1 - i); 235 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 236 } 237 238 uint64_t Mask = ((uint64_t)(-1) >> 239 (64 - getFixupKindInfo(Kind).TargetSize)); 240 CurVal |= Value & Mask; 241 242 // Write out the fixed up bytes back to the code/data bits. 243 for (unsigned i = 0; i != NumBytes; ++i) { 244 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 245 : i) 246 : (FullSize - 1 - i); 247 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 248 } 249} 250 251bool MipsAsmBackend::getFixupKind(StringRef Name, MCFixupKind &MappedKind) const { 252 if (Name == "R_MIPS_NONE") { 253 MappedKind = (MCFixupKind)Mips::fixup_Mips_NONE; 254 return true; 255 } 256 if (Name == "R_MIPS_32") { 257 MappedKind = FK_Data_4; 258 return true; 259 } 260 return MCAsmBackend::getFixupKind(Name, MappedKind); 261} 262 263const MCFixupKindInfo &MipsAsmBackend:: 264getFixupKindInfo(MCFixupKind Kind) const { 265 const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = { 266 // This table *must* be in same the order of fixup_* kinds in 267 // MipsFixupKinds.h. 268 // 269 // name offset bits flags 270 { "fixup_Mips_NONE", 0, 0, 0 }, 271 { "fixup_Mips_16", 0, 16, 0 }, 272 { "fixup_Mips_32", 0, 32, 0 }, 273 { "fixup_Mips_REL32", 0, 32, 0 }, 274 { "fixup_Mips_26", 0, 26, 0 }, 275 { "fixup_Mips_HI16", 0, 16, 0 }, 276 { "fixup_Mips_LO16", 0, 16, 0 }, 277 { "fixup_Mips_GPREL16", 0, 16, 0 }, 278 { "fixup_Mips_LITERAL", 0, 16, 0 }, 279 { "fixup_Mips_GOT_Global", 0, 16, 0 }, 280 { "fixup_Mips_GOT_Local", 0, 16, 0 }, 281 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 282 { "fixup_Mips_CALL16", 0, 16, 0 }, 283 { "fixup_Mips_GPREL32", 0, 32, 0 }, 284 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 285 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 286 { "fixup_Mips_64", 0, 64, 0 }, 287 { "fixup_Mips_TLSGD", 0, 16, 0 }, 288 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 289 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 290 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 291 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 292 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 293 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 294 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 295 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 296 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 297 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 298 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 299 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 300 { "fixup_Mips_HIGHER", 0, 16, 0 }, 301 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 302 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 303 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 304 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 305 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 306 { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 307 { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 308 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 309 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 310 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 311 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 312 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 313 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 314 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 315 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 316 { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, 317 { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 318 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 319 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 320 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 321 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 322 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 323 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, 324 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, 325 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 326 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 327 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 328 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } 329 }; 330 331 const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = { 332 // This table *must* be in same the order of fixup_* kinds in 333 // MipsFixupKinds.h. 334 // 335 // name offset bits flags 336 { "fixup_Mips_NONE", 0, 0, 0 }, 337 { "fixup_Mips_16", 16, 16, 0 }, 338 { "fixup_Mips_32", 0, 32, 0 }, 339 { "fixup_Mips_REL32", 0, 32, 0 }, 340 { "fixup_Mips_26", 6, 26, 0 }, 341 { "fixup_Mips_HI16", 16, 16, 0 }, 342 { "fixup_Mips_LO16", 16, 16, 0 }, 343 { "fixup_Mips_GPREL16", 16, 16, 0 }, 344 { "fixup_Mips_LITERAL", 16, 16, 0 }, 345 { "fixup_Mips_GOT_Global", 16, 16, 0 }, 346 { "fixup_Mips_GOT_Local", 16, 16, 0 }, 347 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 348 { "fixup_Mips_CALL16", 16, 16, 0 }, 349 { "fixup_Mips_GPREL32", 0, 32, 0 }, 350 { "fixup_Mips_SHIFT5", 21, 5, 0 }, 351 { "fixup_Mips_SHIFT6", 21, 5, 0 }, 352 { "fixup_Mips_64", 0, 64, 0 }, 353 { "fixup_Mips_TLSGD", 16, 16, 0 }, 354 { "fixup_Mips_GOTTPREL", 16, 16, 0 }, 355 { "fixup_Mips_TPREL_HI", 16, 16, 0 }, 356 { "fixup_Mips_TPREL_LO", 16, 16, 0 }, 357 { "fixup_Mips_TLSLDM", 16, 16, 0 }, 358 { "fixup_Mips_DTPREL_HI", 16, 16, 0 }, 359 { "fixup_Mips_DTPREL_LO", 16, 16, 0 }, 360 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 361 { "fixup_Mips_GPOFF_HI", 16, 16, 0 }, 362 { "fixup_Mips_GPOFF_LO", 16, 16, 0 }, 363 { "fixup_Mips_GOT_PAGE", 16, 16, 0 }, 364 { "fixup_Mips_GOT_OFST", 16, 16, 0 }, 365 { "fixup_Mips_GOT_DISP", 16, 16, 0 }, 366 { "fixup_Mips_HIGHER", 16, 16, 0 }, 367 { "fixup_Mips_HIGHEST", 16, 16, 0 }, 368 { "fixup_Mips_GOT_HI16", 16, 16, 0 }, 369 { "fixup_Mips_GOT_LO16", 16, 16, 0 }, 370 { "fixup_Mips_CALL_HI16", 16, 16, 0 }, 371 { "fixup_Mips_CALL_LO16", 16, 16, 0 }, 372 { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel }, 373 { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 374 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, 375 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 376 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 377 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 378 { "fixup_MICROMIPS_26_S1", 6, 26, 0 }, 379 { "fixup_MICROMIPS_HI16", 16, 16, 0 }, 380 { "fixup_MICROMIPS_LO16", 16, 16, 0 }, 381 { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, 382 { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, 383 { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, 384 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 385 { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, 386 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, 387 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, 388 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 }, 389 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 }, 390 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 }, 391 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, 392 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, 393 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, 394 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 } 395 }; 396 397 if (Kind < FirstTargetFixupKind) 398 return MCAsmBackend::getFixupKindInfo(Kind); 399 400 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 401 "Invalid kind!"); 402 403 if (IsLittle) 404 return LittleEndianInfos[Kind - FirstTargetFixupKind]; 405 return BigEndianInfos[Kind - FirstTargetFixupKind]; 406} 407 408/// WriteNopData - Write an (optimal) nop sequence of Count bytes 409/// to the given output. If the target cannot generate such a sequence, 410/// it should return an error. 411/// 412/// \return - True on success. 413bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 414 // Check for a less than instruction size number of bytes 415 // FIXME: 16 bit instructions are not handled yet here. 416 // We shouldn't be using a hard coded number for instruction size. 417 418 // If the count is not 4-byte aligned, we must be writing data into the text 419 // section (otherwise we have unaligned instructions, and thus have far 420 // bigger problems), so just write zeros instead. 421 OW->WriteZeros(Count); 422 return true; 423} 424 425/// processFixupValue - Target hook to process the literal value of a fixup 426/// if necessary. 427void MipsAsmBackend::processFixupValue(const MCAssembler &Asm, 428 const MCAsmLayout &Layout, 429 const MCFixup &Fixup, 430 const MCFragment *DF, 431 const MCValue &Target, 432 uint64_t &Value, 433 bool &IsResolved) { 434 // At this point we'll ignore the value returned by adjustFixupValue as 435 // we are only checking if the fixup can be applied correctly. We have 436 // access to MCContext from here which allows us to report a fatal error 437 // with *possibly* a source code location. 438 (void)adjustFixupValue(Fixup, Value, &Asm.getContext()); 439} 440 441// MCAsmBackend 442MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 443 const MCRegisterInfo &MRI, 444 const Triple &TT, StringRef CPU) { 445 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, 446 /*Is64Bit*/ false); 447} 448 449MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 450 const MCRegisterInfo &MRI, 451 const Triple &TT, StringRef CPU) { 452 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, 453 /*Is64Bit*/ false); 454} 455 456MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 457 const MCRegisterInfo &MRI, 458 const Triple &TT, StringRef CPU) { 459 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); 460} 461 462MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 463 const MCRegisterInfo &MRI, 464 const Triple &TT, StringRef CPU) { 465 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, 466 /*Is64Bit*/ true); 467} 468