ARMInstrFormats.td revision 243830
1234353Sdim//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===// 2206083Srdivacky// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7206083Srdivacky// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// 12193323Sed// ARM Instruction Format Definitions. 13193323Sed// 14193323Sed 15193323Sed// Format specifies the encoding used by the instruction. This is part of the 16193323Sed// ad-hoc solution used to emit machine instruction encodings by our machine 17193323Sed// code emitter. 18205407Srdivackyclass Format<bits<6> val> { 19205407Srdivacky bits<6> Value = val; 20193323Sed} 21193323Sed 22193323Seddef Pseudo : Format<0>; 23193323Seddef MulFrm : Format<1>; 24193323Seddef BrFrm : Format<2>; 25193323Seddef BrMiscFrm : Format<3>; 26193323Sed 27193323Seddef DPFrm : Format<4>; 28226633Sdimdef DPSoRegRegFrm : Format<5>; 29193323Sed 30193323Seddef LdFrm : Format<6>; 31193323Seddef StFrm : Format<7>; 32193323Seddef LdMiscFrm : Format<8>; 33193323Seddef StMiscFrm : Format<9>; 34193323Seddef LdStMulFrm : Format<10>; 35193323Sed 36205407Srdivackydef LdStExFrm : Format<11>; 37200581Srdivacky 38205407Srdivackydef ArithMiscFrm : Format<12>; 39212904Sdimdef SatFrm : Format<13>; 40212904Sdimdef ExtFrm : Format<14>; 41193323Sed 42212904Sdimdef VFPUnaryFrm : Format<15>; 43212904Sdimdef VFPBinaryFrm : Format<16>; 44212904Sdimdef VFPConv1Frm : Format<17>; 45212904Sdimdef VFPConv2Frm : Format<18>; 46212904Sdimdef VFPConv3Frm : Format<19>; 47212904Sdimdef VFPConv4Frm : Format<20>; 48212904Sdimdef VFPConv5Frm : Format<21>; 49212904Sdimdef VFPLdStFrm : Format<22>; 50212904Sdimdef VFPLdStMulFrm : Format<23>; 51212904Sdimdef VFPMiscFrm : Format<24>; 52193323Sed 53212904Sdimdef ThumbFrm : Format<25>; 54212904Sdimdef MiscFrm : Format<26>; 55193323Sed 56212904Sdimdef NGetLnFrm : Format<27>; 57212904Sdimdef NSetLnFrm : Format<28>; 58212904Sdimdef NDupFrm : Format<29>; 59212904Sdimdef NLdStFrm : Format<30>; 60212904Sdimdef N1RegModImmFrm: Format<31>; 61212904Sdimdef N2RegFrm : Format<32>; 62212904Sdimdef NVCVTFrm : Format<33>; 63212904Sdimdef NVDupLnFrm : Format<34>; 64212904Sdimdef N2RegVShLFrm : Format<35>; 65212904Sdimdef N2RegVShRFrm : Format<36>; 66212904Sdimdef N3RegFrm : Format<37>; 67212904Sdimdef N3RegVShFrm : Format<38>; 68212904Sdimdef NVExtFrm : Format<39>; 69212904Sdimdef NVMulSLFrm : Format<40>; 70212904Sdimdef NVTBLFrm : Format<41>; 71226633Sdimdef DPSoRegImmFrm : Format<42>; 72194710Sed 73198090Srdivacky// Misc flags. 74198090Srdivacky 75218893Sdim// The instruction has an Rn register operand. 76198090Srdivacky// UnaryDP - Indicates this is a unary data processing instruction, i.e. 77198090Srdivacky// it doesn't have a Rn operand. 78198090Srdivackyclass UnaryDP { bit isUnaryDataProc = 1; } 79193323Sed 80198090Srdivacky// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 81198090Srdivacky// a 16-bit Thumb instruction if certain conditions are met. 82198090Srdivackyclass Xform16Bit { bit canXformTo16Bit = 1; } 83198090Srdivacky 84193323Sed//===----------------------------------------------------------------------===// 85205407Srdivacky// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 86195340Sed// 87193323Sed 88218893Sdim// FIXME: Once the JIT is MC-ized, these can go away. 89195340Sed// Addressing mode. 90218893Sdimclass AddrMode<bits<5> val> { 91218893Sdim bits<5> Value = val; 92195340Sed} 93212904Sdimdef AddrModeNone : AddrMode<0>; 94212904Sdimdef AddrMode1 : AddrMode<1>; 95212904Sdimdef AddrMode2 : AddrMode<2>; 96212904Sdimdef AddrMode3 : AddrMode<3>; 97212904Sdimdef AddrMode4 : AddrMode<4>; 98212904Sdimdef AddrMode5 : AddrMode<5>; 99212904Sdimdef AddrMode6 : AddrMode<6>; 100212904Sdimdef AddrModeT1_1 : AddrMode<7>; 101212904Sdimdef AddrModeT1_2 : AddrMode<8>; 102212904Sdimdef AddrModeT1_4 : AddrMode<9>; 103212904Sdimdef AddrModeT1_s : AddrMode<10>; 104212904Sdimdef AddrModeT2_i12 : AddrMode<11>; 105212904Sdimdef AddrModeT2_i8 : AddrMode<12>; 106212904Sdimdef AddrModeT2_so : AddrMode<13>; 107212904Sdimdef AddrModeT2_pc : AddrMode<14>; 108195340Seddef AddrModeT2_i8s4 : AddrMode<15>; 109218893Sdimdef AddrMode_i12 : AddrMode<16>; 110195340Sed 111195340Sed// Load / store index mode. 112195340Sedclass IndexMode<bits<2> val> { 113195340Sed bits<2> Value = val; 114195340Sed} 115195340Seddef IndexModeNone : IndexMode<0>; 116195340Seddef IndexModePre : IndexMode<1>; 117195340Seddef IndexModePost : IndexMode<2>; 118205218Srdivackydef IndexModeUpd : IndexMode<3>; 119195340Sed 120198892Srdivacky// Instruction execution domain. 121219077Sdimclass Domain<bits<3> val> { 122219077Sdim bits<3> Value = val; 123198892Srdivacky} 124198892Srdivackydef GenericDomain : Domain<0>; 125198892Srdivackydef VFPDomain : Domain<1>; // Instructions in VFP domain only 126198892Srdivackydef NeonDomain : Domain<2>; // Instructions in Neon domain only 127198892Srdivackydef VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 128219077Sdimdef VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 129198892Srdivacky 130195340Sed//===----------------------------------------------------------------------===// 131198090Srdivacky// ARM special operands. 132198090Srdivacky// 133198090Srdivacky 134226633Sdim// ARM imod and iflag operands, used only by the CPS instruction. 135226633Sdimdef imod_op : Operand<i32> { 136226633Sdim let PrintMethod = "printCPSIMod"; 137212904Sdim} 138212904Sdim 139218893Sdimdef ProcIFlagsOperand : AsmOperandClass { 140218893Sdim let Name = "ProcIFlags"; 141226633Sdim let ParserMethod = "parseProcIFlagsOperand"; 142218893Sdim} 143218893Sdimdef iflags_op : Operand<i32> { 144218893Sdim let PrintMethod = "printCPSIFlag"; 145218893Sdim let ParserMatchClass = ProcIFlagsOperand; 146218893Sdim} 147218893Sdim 148198090Srdivacky// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 149198090Srdivacky// register whose default is 0 (no register). 150226633Sdimdef CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } 151226633Sdimdef pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), 152198090Srdivacky (ops (i32 14), (i32 zero_reg))> { 153198090Srdivacky let PrintMethod = "printPredicateOperand"; 154212904Sdim let ParserMatchClass = CondCodeOperand; 155226633Sdim let DecoderMethod = "DecodePredicateOperand"; 156198090Srdivacky} 157198090Srdivacky 158198090Srdivacky// Conditional code result for instructions whose 's' bit is set, e.g. subs. 159226633Sdimdef CCOutOperand : AsmOperandClass { let Name = "CCOut"; } 160198090Srdivackydef cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 161218893Sdim let EncoderMethod = "getCCOutOpValue"; 162198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 163218893Sdim let ParserMatchClass = CCOutOperand; 164226633Sdim let DecoderMethod = "DecodeCCOutOperand"; 165198090Srdivacky} 166198090Srdivacky 167198090Srdivacky// Same as cc_out except it defaults to setting CPSR. 168198090Srdivackydef s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 169218893Sdim let EncoderMethod = "getCCOutOpValue"; 170198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 171218893Sdim let ParserMatchClass = CCOutOperand; 172226633Sdim let DecoderMethod = "DecodeCCOutOperand"; 173198090Srdivacky} 174198090Srdivacky 175205218Srdivacky// ARM special operands for disassembly only. 176205218Srdivacky// 177234353Sdimdef SetEndAsmOperand : ImmAsmOperand { 178226633Sdim let Name = "SetEndImm"; 179226633Sdim let ParserMethod = "parseSetEndImm"; 180226633Sdim} 181218893Sdimdef setend_op : Operand<i32> { 182218893Sdim let PrintMethod = "printSetendOperand"; 183226633Sdim let ParserMatchClass = SetEndAsmOperand; 184218893Sdim} 185205218Srdivacky 186226633Sdimdef MSRMaskOperand : AsmOperandClass { 187226633Sdim let Name = "MSRMask"; 188226633Sdim let ParserMethod = "parseMSRMaskOperand"; 189226633Sdim} 190205218Srdivackydef msr_mask : Operand<i32> { 191205218Srdivacky let PrintMethod = "printMSRMaskOperand"; 192226633Sdim let DecoderMethod = "DecodeMSRMask"; 193218893Sdim let ParserMatchClass = MSRMaskOperand; 194205218Srdivacky} 195205218Srdivacky 196221345Sdim// Shift Right Immediate - A shift right immediate is encoded differently from 197221345Sdim// other shift immediates. The imm6 field is encoded like so: 198221345Sdim// 199221345Sdim// Offset Encoding 200221345Sdim// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 201221345Sdim// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 202221345Sdim// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 203221345Sdim// 64 64 - <imm> is encoded in imm6<5:0> 204234353Sdimdef shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; } 205221345Sdimdef shr_imm8 : Operand<i32> { 206221345Sdim let EncoderMethod = "getShiftRight8Imm"; 207226633Sdim let DecoderMethod = "DecodeShiftRight8Imm"; 208234353Sdim let ParserMatchClass = shr_imm8_asm_operand; 209205218Srdivacky} 210234353Sdimdef shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; } 211221345Sdimdef shr_imm16 : Operand<i32> { 212221345Sdim let EncoderMethod = "getShiftRight16Imm"; 213226633Sdim let DecoderMethod = "DecodeShiftRight16Imm"; 214234353Sdim let ParserMatchClass = shr_imm16_asm_operand; 215221345Sdim} 216234353Sdimdef shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; } 217221345Sdimdef shr_imm32 : Operand<i32> { 218221345Sdim let EncoderMethod = "getShiftRight32Imm"; 219226633Sdim let DecoderMethod = "DecodeShiftRight32Imm"; 220234353Sdim let ParserMatchClass = shr_imm32_asm_operand; 221221345Sdim} 222234353Sdimdef shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; } 223221345Sdimdef shr_imm64 : Operand<i32> { 224221345Sdim let EncoderMethod = "getShiftRight64Imm"; 225226633Sdim let DecoderMethod = "DecodeShiftRight64Imm"; 226234353Sdim let ParserMatchClass = shr_imm64_asm_operand; 227221345Sdim} 228205218Srdivacky 229198090Srdivacky//===----------------------------------------------------------------------===// 230226633Sdim// ARM Assembler alias templates. 231226633Sdim// 232226633Sdimclass ARMInstAlias<string Asm, dag Result, bit Emit = 0b1> 233226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>; 234226633Sdimclass tInstAlias<string Asm, dag Result, bit Emit = 0b1> 235226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>; 236226633Sdimclass t2InstAlias<string Asm, dag Result, bit Emit = 0b1> 237226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>; 238226633Sdimclass VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1> 239226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>; 240226633Sdimclass VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1> 241226633Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>; 242234353Sdimclass NEONInstAlias<string Asm, dag Result, bit Emit = 0b1> 243234353Sdim : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>; 244226633Sdim 245234353Sdim 246234353Sdimclass VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 247234353Sdim Requires<[HasVFP2]>; 248234353Sdimclass NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 249234353Sdim Requires<[HasNEON]>; 250234353Sdim 251226633Sdim//===----------------------------------------------------------------------===// 252193323Sed// ARM Instruction templates. 253193323Sed// 254193323Sed 255226633Sdim 256224145Sdimclass InstTemplate<AddrMode am, int sz, IndexMode im, 257201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 258193323Sed : Instruction { 259193323Sed let Namespace = "ARM"; 260193323Sed 261193323Sed AddrMode AM = am; 262224145Sdim int Size = sz; 263193323Sed IndexMode IM = im; 264193323Sed bits<2> IndexModeBits = IM.Value; 265193323Sed Format F = f; 266205407Srdivacky bits<6> Form = F.Value; 267198892Srdivacky Domain D = d; 268193323Sed bit isUnaryDataProc = 0; 269198090Srdivacky bit canXformTo16Bit = 0; 270226633Sdim // The instruction is a 16-bit flag setting Thumb instruction. Used 271226633Sdim // by the parser to determine whether to require the 'S' suffix on the 272226633Sdim // mnemonic (when not in an IT block) or preclude it (when in an IT block). 273226633Sdim bit thumbArithFlagSetting = 0; 274206083Srdivacky 275218893Sdim // If this is a pseudo instruction, mark it isCodeGenOnly. 276218893Sdim let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 277218893Sdim 278226633Sdim // The layout of TSFlags should be kept in sync with ARMBaseInfo.h. 279218893Sdim let TSFlags{4-0} = AM.Value; 280224145Sdim let TSFlags{6-5} = IndexModeBits; 281224145Sdim let TSFlags{12-7} = Form; 282224145Sdim let TSFlags{13} = isUnaryDataProc; 283224145Sdim let TSFlags{14} = canXformTo16Bit; 284224145Sdim let TSFlags{17-15} = D.Value; 285226633Sdim let TSFlags{18} = thumbArithFlagSetting; 286206274Srdivacky 287193323Sed let Constraints = cstr; 288198090Srdivacky let Itinerary = itin; 289193323Sed} 290193323Sed 291201360Srdivackyclass Encoding { 292201360Srdivacky field bits<32> Inst; 293234353Sdim // Mask of bits that cause an encoding to be UNPREDICTABLE. 294234353Sdim // If a bit is set, then if the corresponding bit in the 295234353Sdim // target encoding differs from its value in the "Inst" field, 296234353Sdim // the instruction is UNPREDICTABLE (SoftFail in abstract parlance). 297234353Sdim field bits<32> Unpredictable = 0; 298234353Sdim // SoftFail is the generic name for this field, but we alias it so 299234353Sdim // as to make it more obvious what it means in ARM-land. 300234353Sdim field bits<32> SoftFail = Unpredictable; 301201360Srdivacky} 302201360Srdivacky 303224145Sdimclass InstARM<AddrMode am, int sz, IndexMode im, 304201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 305226633Sdim : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding { 306226633Sdim let DecoderNamespace = "ARM"; 307226633Sdim} 308201360Srdivacky 309201360Srdivacky// This Encoding-less class is used by Thumb1 to specify the encoding bits later 310201360Srdivacky// on by adding flavors to specific instructions. 311224145Sdimclass InstThumb<AddrMode am, int sz, IndexMode im, 312201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 313226633Sdim : InstTemplate<am, sz, im, f, d, cstr, itin> { 314226633Sdim let DecoderNamespace = "Thumb"; 315226633Sdim} 316201360Srdivacky 317234353Sdim// Pseudo-instructions for alternate assembly syntax (never used by codegen). 318234353Sdim// These are aliases that require C++ handling to convert to the target 319234353Sdim// instruction, while InstAliases can be handled directly by tblgen. 320234353Sdimclass AsmPseudoInst<string asm, dag iops> 321234353Sdim : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 322234353Sdim "", NoItinerary> { 323234353Sdim let OutOperandList = (outs); 324234353Sdim let InOperandList = iops; 325234353Sdim let Pattern = []; 326234353Sdim let isCodeGenOnly = 0; // So we get asm matcher for it. 327234353Sdim let AsmString = asm; 328234353Sdim let isPseudo = 1; 329234353Sdim} 330234353Sdim 331234353Sdimclass ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 332234353Sdim Requires<[IsARM]>; 333234353Sdimclass tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 334234353Sdim Requires<[IsThumb]>; 335234353Sdimclass t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 336234353Sdim Requires<[IsThumb2]>; 337234353Sdimclass VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 338234353Sdim Requires<[HasVFP2]>; 339234353Sdimclass NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 340234353Sdim Requires<[HasNEON]>; 341234353Sdim 342234353Sdim// Pseudo instructions for the code generator. 343218893Sdimclass PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 344224145Sdim : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, 345224145Sdim GenericDomain, "", itin> { 346193323Sed let OutOperandList = oops; 347193323Sed let InOperandList = iops; 348193323Sed let Pattern = pattern; 349221345Sdim let isCodeGenOnly = 1; 350224145Sdim let isPseudo = 1; 351193323Sed} 352193323Sed 353218893Sdim// PseudoInst that's ARM-mode only. 354224145Sdimclass ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 355218893Sdim list<dag> pattern> 356218893Sdim : PseudoInst<oops, iops, itin, pattern> { 357224145Sdim let Size = sz; 358218893Sdim list<Predicate> Predicates = [IsARM]; 359218893Sdim} 360218893Sdim 361218893Sdim// PseudoInst that's Thumb-mode only. 362224145Sdimclass tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 363218893Sdim list<dag> pattern> 364218893Sdim : PseudoInst<oops, iops, itin, pattern> { 365224145Sdim let Size = sz; 366218893Sdim list<Predicate> Predicates = [IsThumb]; 367218893Sdim} 368218893Sdim 369218893Sdim// PseudoInst that's Thumb2-mode only. 370224145Sdimclass t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 371218893Sdim list<dag> pattern> 372218893Sdim : PseudoInst<oops, iops, itin, pattern> { 373224145Sdim let Size = sz; 374218893Sdim list<Predicate> Predicates = [IsThumb2]; 375218893Sdim} 376224145Sdim 377224145Sdimclass ARMPseudoExpand<dag oops, dag iops, int sz, 378224145Sdim InstrItinClass itin, list<dag> pattern, 379224145Sdim dag Result> 380224145Sdim : ARMPseudoInst<oops, iops, sz, itin, pattern>, 381224145Sdim PseudoInstExpansion<Result>; 382224145Sdim 383224145Sdimclass tPseudoExpand<dag oops, dag iops, int sz, 384224145Sdim InstrItinClass itin, list<dag> pattern, 385224145Sdim dag Result> 386224145Sdim : tPseudoInst<oops, iops, sz, itin, pattern>, 387224145Sdim PseudoInstExpansion<Result>; 388224145Sdim 389224145Sdimclass t2PseudoExpand<dag oops, dag iops, int sz, 390224145Sdim InstrItinClass itin, list<dag> pattern, 391224145Sdim dag Result> 392224145Sdim : t2PseudoInst<oops, iops, sz, itin, pattern>, 393224145Sdim PseudoInstExpansion<Result>; 394224145Sdim 395193323Sed// Almost all ARM instructions are predicable. 396224145Sdimclass I<dag oops, dag iops, AddrMode am, int sz, 397206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 398198090Srdivacky string opc, string asm, string cstr, 399193323Sed list<dag> pattern> 400198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 401218893Sdim bits<4> p; 402218893Sdim let Inst{31-28} = p; 403193323Sed let OutOperandList = oops; 404205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 405218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 406193323Sed let Pattern = pattern; 407193323Sed list<Predicate> Predicates = [IsARM]; 408193323Sed} 409212904Sdim 410200581Srdivacky// A few are not predicable 411224145Sdimclass InoP<dag oops, dag iops, AddrMode am, int sz, 412206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 413206083Srdivacky string opc, string asm, string cstr, 414206083Srdivacky list<dag> pattern> 415200581Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 416200581Srdivacky let OutOperandList = oops; 417200581Srdivacky let InOperandList = iops; 418208599Srdivacky let AsmString = !strconcat(opc, asm); 419200581Srdivacky let Pattern = pattern; 420200581Srdivacky let isPredicable = 0; 421200581Srdivacky list<Predicate> Predicates = [IsARM]; 422200581Srdivacky} 423193323Sed 424212904Sdim// Same as I except it can optionally modify CPSR. Note it's modeled as an input 425212904Sdim// operand since by default it's a zero register. It will become an implicit def 426212904Sdim// once it's "flipped". 427224145Sdimclass sI<dag oops, dag iops, AddrMode am, int sz, 428198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 429198090Srdivacky string opc, string asm, string cstr, 430193323Sed list<dag> pattern> 431198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 432218893Sdim bits<4> p; // Predicate operand 433218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 434218893Sdim let Inst{31-28} = p; 435218893Sdim let Inst{20} = s; 436218893Sdim 437193323Sed let OutOperandList = oops; 438205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 439218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 440193323Sed let Pattern = pattern; 441193323Sed list<Predicate> Predicates = [IsARM]; 442193323Sed} 443193323Sed 444193323Sed// Special cases 445224145Sdimclass XI<dag oops, dag iops, AddrMode am, int sz, 446198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 447198090Srdivacky string asm, string cstr, list<dag> pattern> 448198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 449193323Sed let OutOperandList = oops; 450193323Sed let InOperandList = iops; 451208599Srdivacky let AsmString = asm; 452193323Sed let Pattern = pattern; 453193323Sed list<Predicate> Predicates = [IsARM]; 454193323Sed} 455193323Sed 456198090Srdivackyclass AI<dag oops, dag iops, Format f, InstrItinClass itin, 457198090Srdivacky string opc, string asm, list<dag> pattern> 458224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 459198090Srdivacky opc, asm, "", pattern>; 460198090Srdivackyclass AsI<dag oops, dag iops, Format f, InstrItinClass itin, 461198090Srdivacky string opc, string asm, list<dag> pattern> 462224145Sdim : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 463198090Srdivacky opc, asm, "", pattern>; 464198090Srdivackyclass AXI<dag oops, dag iops, Format f, InstrItinClass itin, 465193323Sed string asm, list<dag> pattern> 466224145Sdim : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 467193323Sed asm, "", pattern>; 468200581Srdivackyclass AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 469206083Srdivacky string opc, string asm, list<dag> pattern> 470224145Sdim : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 471206083Srdivacky opc, asm, "", pattern>; 472193323Sed 473193323Sed// Ctrl flow instructions 474198090Srdivackyclass ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 475198090Srdivacky string opc, string asm, list<dag> pattern> 476224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 477198090Srdivacky opc, asm, "", pattern> { 478193323Sed let Inst{27-24} = opcod; 479193323Sed} 480198090Srdivackyclass ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 481198090Srdivacky string asm, list<dag> pattern> 482224145Sdim : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 483198090Srdivacky asm, "", pattern> { 484193323Sed let Inst{27-24} = opcod; 485193323Sed} 486193323Sed 487193323Sed// BR_JT instructions 488198090Srdivackyclass JTI<dag oops, dag iops, InstrItinClass itin, 489198090Srdivacky string asm, list<dag> pattern> 490224145Sdim : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin, 491193323Sed asm, "", pattern>; 492193323Sed 493200581Srdivacky// Atomic load/store instructions 494200581Srdivackyclass AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 495200581Srdivacky string opc, string asm, list<dag> pattern> 496224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 497200581Srdivacky opc, asm, "", pattern> { 498218893Sdim bits<4> Rt; 499226633Sdim bits<4> addr; 500200581Srdivacky let Inst{27-23} = 0b00011; 501200581Srdivacky let Inst{22-21} = opcod; 502212904Sdim let Inst{20} = 1; 503226633Sdim let Inst{19-16} = addr; 504218893Sdim let Inst{15-12} = Rt; 505200581Srdivacky let Inst{11-0} = 0b111110011111; 506200581Srdivacky} 507200581Srdivackyclass AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 508200581Srdivacky string opc, string asm, list<dag> pattern> 509224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 510200581Srdivacky opc, asm, "", pattern> { 511218893Sdim bits<4> Rd; 512218893Sdim bits<4> Rt; 513221345Sdim bits<4> addr; 514200581Srdivacky let Inst{27-23} = 0b00011; 515200581Srdivacky let Inst{22-21} = opcod; 516212904Sdim let Inst{20} = 0; 517221345Sdim let Inst{19-16} = addr; 518218893Sdim let Inst{15-12} = Rd; 519200581Srdivacky let Inst{11-4} = 0b11111001; 520218893Sdim let Inst{3-0} = Rt; 521200581Srdivacky} 522218893Sdimclass AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 523226633Sdim : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> { 524218893Sdim bits<4> Rt; 525218893Sdim bits<4> Rt2; 526226633Sdim bits<4> addr; 527218893Sdim let Inst{27-23} = 0b00010; 528218893Sdim let Inst{22} = b; 529218893Sdim let Inst{21-20} = 0b00; 530226633Sdim let Inst{19-16} = addr; 531218893Sdim let Inst{15-12} = Rt; 532218893Sdim let Inst{11-4} = 0b00001001; 533218893Sdim let Inst{3-0} = Rt2; 534234353Sdim 535234982Sdim let Unpredictable{11-8} = 0b1111; 536234353Sdim let DecoderMethod = "DecodeSwap"; 537218893Sdim} 538200581Srdivacky 539193323Sed// addrmode1 instructions 540198090Srdivackyclass AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 541198090Srdivacky string opc, string asm, list<dag> pattern> 542224145Sdim : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 543198090Srdivacky opc, asm, "", pattern> { 544193323Sed let Inst{24-21} = opcod; 545212904Sdim let Inst{27-26} = 0b00; 546193323Sed} 547198090Srdivackyclass AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 548198090Srdivacky string opc, string asm, list<dag> pattern> 549224145Sdim : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 550198090Srdivacky opc, asm, "", pattern> { 551193323Sed let Inst{24-21} = opcod; 552212904Sdim let Inst{27-26} = 0b00; 553193323Sed} 554198090Srdivackyclass AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 555198090Srdivacky string asm, list<dag> pattern> 556224145Sdim : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 557198090Srdivacky asm, "", pattern> { 558193323Sed let Inst{24-21} = opcod; 559212904Sdim let Inst{27-26} = 0b00; 560193323Sed} 561193323Sed 562193323Sed// loads 563193323Sed 564218893Sdim// LDR/LDRB/STR/STRB/... 565218893Sdimclass AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 566218893Sdim Format f, InstrItinClass itin, string opc, string asm, 567218893Sdim list<dag> pattern> 568224145Sdim : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm, 569218893Sdim "", pattern> { 570218893Sdim let Inst{27-25} = op; 571218893Sdim let Inst{24} = 1; // 24 == P 572218893Sdim // 23 == U 573218893Sdim let Inst{22} = isByte; 574218893Sdim let Inst{21} = 0; // 21 == W 575218893Sdim let Inst{20} = isLd; 576193323Sed} 577218893Sdim// Indexed load/stores 578218893Sdimclass AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 579218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 580218893Sdim string asm, string cstr, list<dag> pattern> 581224145Sdim : I<oops, iops, AddrMode2, 4, im, f, itin, 582198090Srdivacky opc, asm, cstr, pattern> { 583218893Sdim bits<4> Rt; 584212904Sdim let Inst{27-26} = 0b01; 585218893Sdim let Inst{24} = isPre; // P bit 586218893Sdim let Inst{22} = isByte; // B bit 587218893Sdim let Inst{21} = isPre; // W bit 588218893Sdim let Inst{20} = isLd; // L bit 589218893Sdim let Inst{15-12} = Rt; 590193323Sed} 591226633Sdimclass AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops, 592218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 593218893Sdim string asm, string cstr, list<dag> pattern> 594218893Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 595218893Sdim pattern> { 596218893Sdim // AM2 store w/ two operands: (GPR, am2offset) 597218893Sdim // {12} isAdd 598218893Sdim // {11-0} imm12/Rm 599218893Sdim bits<14> offset; 600218893Sdim bits<4> Rn; 601226633Sdim let Inst{25} = 1; 602218893Sdim let Inst{23} = offset{12}; 603218893Sdim let Inst{19-16} = Rn; 604226633Sdim let Inst{11-5} = offset{11-5}; 605226633Sdim let Inst{4} = 0; 606226633Sdim let Inst{3-0} = offset{3-0}; 607226633Sdim} 608226633Sdim 609226633Sdimclass AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops, 610226633Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 611226633Sdim string asm, string cstr, list<dag> pattern> 612226633Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 613226633Sdim pattern> { 614226633Sdim // AM2 store w/ two operands: (GPR, am2offset) 615226633Sdim // {12} isAdd 616226633Sdim // {11-0} imm12/Rm 617226633Sdim bits<14> offset; 618226633Sdim bits<4> Rn; 619226633Sdim let Inst{25} = 0; 620226633Sdim let Inst{23} = offset{12}; 621226633Sdim let Inst{19-16} = Rn; 622218893Sdim let Inst{11-0} = offset{11-0}; 623193323Sed} 624226633Sdim 625226633Sdim 626221345Sdim// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 627221345Sdim// but for now use this class for STRT and STRBT. 628221345Sdimclass AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 629221345Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 630221345Sdim string asm, string cstr, list<dag> pattern> 631221345Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 632221345Sdim pattern> { 633221345Sdim // AM2 store w/ two operands: (GPR, am2offset) 634221345Sdim // {17-14} Rn 635221345Sdim // {13} 1 == Rm, 0 == imm12 636221345Sdim // {12} isAdd 637221345Sdim // {11-0} imm12/Rm 638221345Sdim bits<18> addr; 639221345Sdim let Inst{25} = addr{13}; 640221345Sdim let Inst{23} = addr{12}; 641221345Sdim let Inst{19-16} = addr{17-14}; 642221345Sdim let Inst{11-0} = addr{11-0}; 643221345Sdim} 644193323Sed 645193323Sed// addrmode3 instructions 646218893Sdimclass AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 647218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 648224145Sdim : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 649198090Srdivacky opc, asm, "", pattern> { 650218893Sdim bits<14> addr; 651218893Sdim bits<4> Rt; 652198090Srdivacky let Inst{27-25} = 0b000; 653218893Sdim let Inst{24} = 1; // P bit 654218893Sdim let Inst{23} = addr{8}; // U bit 655218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 656218893Sdim let Inst{21} = 0; // W bit 657218893Sdim let Inst{20} = op20; // L bit 658218893Sdim let Inst{19-16} = addr{12-9}; // Rn 659218893Sdim let Inst{15-12} = Rt; // Rt 660218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 661218893Sdim let Inst{7-4} = op; 662218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 663226633Sdim 664226633Sdim let DecoderMethod = "DecodeAddrMode3Instruction"; 665193323Sed} 666218893Sdim 667226633Sdimclass AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops, 668218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 669218893Sdim string asm, string cstr, list<dag> pattern> 670224145Sdim : I<oops, iops, AddrMode3, 4, im, f, itin, 671218893Sdim opc, asm, cstr, pattern> { 672218893Sdim bits<4> Rt; 673198090Srdivacky let Inst{27-25} = 0b000; 674218893Sdim let Inst{24} = isPre; // P bit 675218893Sdim let Inst{21} = isPre; // W bit 676218893Sdim let Inst{20} = op20; // L bit 677218893Sdim let Inst{15-12} = Rt; // Rt 678218893Sdim let Inst{7-4} = op; 679193323Sed} 680221345Sdim 681221345Sdim// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 682221345Sdim// but for now use this class for LDRSBT, LDRHT, LDSHT. 683226633Sdimclass AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops, 684221345Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 685221345Sdim string asm, string cstr, list<dag> pattern> 686226633Sdim : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> { 687221345Sdim // {13} 1 == imm8, 0 == Rm 688221345Sdim // {12-9} Rn 689221345Sdim // {8} isAdd 690221345Sdim // {7-4} imm7_4/zero 691221345Sdim // {3-0} imm3_0/Rm 692226633Sdim bits<4> addr; 693221345Sdim bits<4> Rt; 694221345Sdim let Inst{27-25} = 0b000; 695226633Sdim let Inst{24} = 0; // P bit 696226633Sdim let Inst{21} = 1; 697226633Sdim let Inst{20} = isLoad; // L bit 698226633Sdim let Inst{19-16} = addr; // Rn 699221345Sdim let Inst{15-12} = Rt; // Rt 700221345Sdim let Inst{7-4} = op; 701221345Sdim} 702221345Sdim 703193323Sed// stores 704218893Sdimclass AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 705198090Srdivacky string opc, string asm, list<dag> pattern> 706224145Sdim : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 707198090Srdivacky opc, asm, "", pattern> { 708218893Sdim bits<14> addr; 709218893Sdim bits<4> Rt; 710198090Srdivacky let Inst{27-25} = 0b000; 711218893Sdim let Inst{24} = 1; // P bit 712218893Sdim let Inst{23} = addr{8}; // U bit 713218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 714218893Sdim let Inst{21} = 0; // W bit 715218893Sdim let Inst{20} = 0; // L bit 716218893Sdim let Inst{19-16} = addr{12-9}; // Rn 717218893Sdim let Inst{15-12} = Rt; // Rt 718218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 719218893Sdim let Inst{7-4} = op; 720218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 721226633Sdim let DecoderMethod = "DecodeAddrMode3Instruction"; 722193323Sed} 723193323Sed 724193323Sed// addrmode4 instructions 725218893Sdimclass AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 726218893Sdim string asm, string cstr, list<dag> pattern> 727224145Sdim : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> { 728218893Sdim bits<4> p; 729218893Sdim bits<16> regs; 730218893Sdim bits<4> Rn; 731218893Sdim let Inst{31-28} = p; 732193323Sed let Inst{27-25} = 0b100; 733193323Sed let Inst{22} = 0; // S bit 734218893Sdim let Inst{19-16} = Rn; 735218893Sdim let Inst{15-0} = regs; 736193323Sed} 737193323Sed 738193323Sed// Unsigned multiply, multiply-accumulate instructions. 739198090Srdivackyclass AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 740198090Srdivacky string opc, string asm, list<dag> pattern> 741224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 742198090Srdivacky opc, asm, "", pattern> { 743193323Sed let Inst{7-4} = 0b1001; 744193323Sed let Inst{20} = 0; // S bit 745193323Sed let Inst{27-21} = opcod; 746193323Sed} 747198090Srdivackyclass AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 748198090Srdivacky string opc, string asm, list<dag> pattern> 749224145Sdim : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 750198090Srdivacky opc, asm, "", pattern> { 751193323Sed let Inst{7-4} = 0b1001; 752193323Sed let Inst{27-21} = opcod; 753193323Sed} 754193323Sed 755193323Sed// Most significant word multiply 756218893Sdimclass AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 757218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 758224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 759198090Srdivacky opc, asm, "", pattern> { 760218893Sdim bits<4> Rd; 761218893Sdim bits<4> Rn; 762218893Sdim bits<4> Rm; 763218893Sdim let Inst{7-4} = opc7_4; 764193323Sed let Inst{20} = 1; 765193323Sed let Inst{27-21} = opcod; 766218893Sdim let Inst{19-16} = Rd; 767218893Sdim let Inst{11-8} = Rm; 768218893Sdim let Inst{3-0} = Rn; 769193323Sed} 770218893Sdim// MSW multiple w/ Ra operand 771218893Sdimclass AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 772218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 773218893Sdim : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 774218893Sdim bits<4> Ra; 775218893Sdim let Inst{15-12} = Ra; 776218893Sdim} 777193323Sed 778193323Sed// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 779218893Sdimclass AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 780218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 781224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 782198090Srdivacky opc, asm, "", pattern> { 783218893Sdim bits<4> Rn; 784218893Sdim bits<4> Rm; 785193323Sed let Inst{4} = 0; 786193323Sed let Inst{7} = 1; 787193323Sed let Inst{20} = 0; 788193323Sed let Inst{27-21} = opcod; 789218893Sdim let Inst{6-5} = bit6_5; 790218893Sdim let Inst{11-8} = Rm; 791218893Sdim let Inst{3-0} = Rn; 792193323Sed} 793218893Sdimclass AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 794218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 795218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 796218893Sdim bits<4> Rd; 797218893Sdim let Inst{19-16} = Rd; 798218893Sdim} 799193323Sed 800218893Sdim// AMulxyI with Ra operand 801218893Sdimclass AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 802218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 803218893Sdim : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 804218893Sdim bits<4> Ra; 805218893Sdim let Inst{15-12} = Ra; 806218893Sdim} 807218893Sdim// SMLAL* 808218893Sdimclass AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 809218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 810218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 811218893Sdim bits<4> RdLo; 812218893Sdim bits<4> RdHi; 813218893Sdim let Inst{19-16} = RdHi; 814218893Sdim let Inst{15-12} = RdLo; 815218893Sdim} 816218893Sdim 817193323Sed// Extend instructions. 818198090Srdivackyclass AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 819198090Srdivacky string opc, string asm, list<dag> pattern> 820224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin, 821198090Srdivacky opc, asm, "", pattern> { 822218893Sdim // All AExtI instructions have Rd and Rm register operands. 823218893Sdim bits<4> Rd; 824218893Sdim bits<4> Rm; 825218893Sdim let Inst{15-12} = Rd; 826218893Sdim let Inst{3-0} = Rm; 827193323Sed let Inst{7-4} = 0b0111; 828218893Sdim let Inst{9-8} = 0b00; 829193323Sed let Inst{27-20} = opcod; 830239462Sdim 831239462Sdim let Unpredictable{9-8} = 0b11; 832193323Sed} 833193323Sed 834193323Sed// Misc Arithmetic instructions. 835218893Sdimclass AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 836218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 837224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 838198090Srdivacky opc, asm, "", pattern> { 839218893Sdim bits<4> Rd; 840218893Sdim bits<4> Rm; 841193323Sed let Inst{27-20} = opcod; 842218893Sdim let Inst{19-16} = 0b1111; 843218893Sdim let Inst{15-12} = Rd; 844218893Sdim let Inst{11-8} = 0b1111; 845218893Sdim let Inst{7-4} = opc7_4; 846218893Sdim let Inst{3-0} = Rm; 847193323Sed} 848193323Sed 849243830Sdim// Division instructions. 850243830Sdimclass ADivA1I<bits<3> opcod, dag oops, dag iops, 851243830Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 852243830Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 853243830Sdim opc, asm, "", pattern> { 854243830Sdim bits<4> Rd; 855243830Sdim bits<4> Rn; 856243830Sdim bits<4> Rm; 857243830Sdim let Inst{27-23} = 0b01110; 858243830Sdim let Inst{22-20} = opcod; 859243830Sdim let Inst{19-16} = Rd; 860243830Sdim let Inst{15-12} = 0b1111; 861243830Sdim let Inst{11-8} = Rm; 862243830Sdim let Inst{7-4} = 0b0001; 863243830Sdim let Inst{3-0} = Rn; 864243830Sdim} 865243830Sdim 866218893Sdim// PKH instructions 867234353Sdimdef PKHLSLAsmOperand : ImmAsmOperand { 868226633Sdim let Name = "PKHLSLImm"; 869226633Sdim let ParserMethod = "parsePKHLSLImm"; 870226633Sdim} 871226633Sdimdef pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{ 872226633Sdim let PrintMethod = "printPKHLSLShiftImm"; 873226633Sdim let ParserMatchClass = PKHLSLAsmOperand; 874226633Sdim} 875226633Sdimdef PKHASRAsmOperand : AsmOperandClass { 876226633Sdim let Name = "PKHASRImm"; 877226633Sdim let ParserMethod = "parsePKHASRImm"; 878226633Sdim} 879226633Sdimdef pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{ 880226633Sdim let PrintMethod = "printPKHASRShiftImm"; 881226633Sdim let ParserMatchClass = PKHASRAsmOperand; 882226633Sdim} 883226633Sdim 884218893Sdimclass APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 885218893Sdim string opc, string asm, list<dag> pattern> 886224145Sdim : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 887218893Sdim opc, asm, "", pattern> { 888218893Sdim bits<4> Rd; 889218893Sdim bits<4> Rn; 890218893Sdim bits<4> Rm; 891226633Sdim bits<5> sh; 892218893Sdim let Inst{27-20} = opcod; 893218893Sdim let Inst{19-16} = Rn; 894218893Sdim let Inst{15-12} = Rd; 895226633Sdim let Inst{11-7} = sh; 896218893Sdim let Inst{6} = tb; 897218893Sdim let Inst{5-4} = 0b01; 898218893Sdim let Inst{3-0} = Rm; 899218893Sdim} 900218893Sdim 901193323Sed//===----------------------------------------------------------------------===// 902193323Sed 903193323Sed// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 904193323Sedclass ARMPat<dag pattern, dag result> : Pat<pattern, result> { 905193323Sed list<Predicate> Predicates = [IsARM]; 906193323Sed} 907223017Sdimclass ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { 908223017Sdim list<Predicate> Predicates = [IsARM, HasV5T]; 909223017Sdim} 910193323Sedclass ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 911193323Sed list<Predicate> Predicates = [IsARM, HasV5TE]; 912193323Sed} 913243830Sdim// ARMV5MOPat - Same as ARMV5TEPat with UseMulOps. 914243830Sdimclass ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> { 915243830Sdim list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps]; 916243830Sdim} 917193323Sedclass ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 918193323Sed list<Predicate> Predicates = [IsARM, HasV6]; 919193323Sed} 920193323Sed 921193323Sed//===----------------------------------------------------------------------===// 922193323Sed// Thumb Instruction Format Definitions. 923193323Sed// 924193323Sed 925224145Sdimclass ThumbI<dag oops, dag iops, AddrMode am, int sz, 926198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 927201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 928198090Srdivacky let OutOperandList = oops; 929198090Srdivacky let InOperandList = iops; 930208599Srdivacky let AsmString = asm; 931193323Sed let Pattern = pattern; 932193323Sed list<Predicate> Predicates = [IsThumb]; 933193323Sed} 934193323Sed 935218893Sdim// TI - Thumb instruction. 936198090Srdivackyclass TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 937224145Sdim : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 938193323Sed 939198090Srdivacky// Two-address instructions 940206083Srdivackyclass TIt<dag oops, dag iops, InstrItinClass itin, string asm, 941206083Srdivacky list<dag> pattern> 942224145Sdim : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst", 943206083Srdivacky pattern>; 944193323Sed 945201360Srdivacky// tBL, tBX 32-bit instructions 946201360Srdivackyclass TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 947206083Srdivacky dag oops, dag iops, InstrItinClass itin, string asm, 948206083Srdivacky list<dag> pattern> 949224145Sdim : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>, 950206083Srdivacky Encoding { 951201360Srdivacky let Inst{31-27} = opcod1; 952201360Srdivacky let Inst{15-14} = opcod2; 953212904Sdim let Inst{12} = opcod3; 954201360Srdivacky} 955198090Srdivacky 956193323Sed// BR_JT instructions 957206083Srdivackyclass TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 958206083Srdivacky list<dag> pattern> 959224145Sdim : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 960193323Sed 961198090Srdivacky// Thumb1 only 962224145Sdimclass Thumb1I<dag oops, dag iops, AddrMode am, int sz, 963198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 964201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 965198090Srdivacky let OutOperandList = oops; 966198090Srdivacky let InOperandList = iops; 967208599Srdivacky let AsmString = asm; 968198090Srdivacky let Pattern = pattern; 969218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 970194710Sed} 971193323Sed 972198090Srdivackyclass T1I<dag oops, dag iops, InstrItinClass itin, 973198090Srdivacky string asm, list<dag> pattern> 974224145Sdim : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 975198090Srdivackyclass T1Ix2<dag oops, dag iops, InstrItinClass itin, 976198090Srdivacky string asm, list<dag> pattern> 977224145Sdim : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 978194710Sed 979198090Srdivacky// Two-address instructions 980198090Srdivackyclass T1It<dag oops, dag iops, InstrItinClass itin, 981205218Srdivacky string asm, string cstr, list<dag> pattern> 982224145Sdim : Thumb1I<oops, iops, AddrModeNone, 2, itin, 983205218Srdivacky asm, cstr, pattern>; 984198090Srdivacky 985198090Srdivacky// Thumb1 instruction that can either be predicated or set CPSR. 986224145Sdimclass Thumb1sI<dag oops, dag iops, AddrMode am, int sz, 987198090Srdivacky InstrItinClass itin, 988198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 989201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 990205407Srdivacky let OutOperandList = !con(oops, (outs s_cc_out:$s)); 991205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 992218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 993194754Sed let Pattern = pattern; 994226633Sdim let thumbArithFlagSetting = 1; 995218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 996226633Sdim let DecoderNamespace = "ThumbSBit"; 997195098Sed} 998195098Sed 999198090Srdivackyclass T1sI<dag oops, dag iops, InstrItinClass itin, 1000198090Srdivacky string opc, string asm, list<dag> pattern> 1001224145Sdim : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1002195098Sed 1003195098Sed// Two-address instructions 1004198090Srdivackyclass T1sIt<dag oops, dag iops, InstrItinClass itin, 1005198090Srdivacky string opc, string asm, list<dag> pattern> 1006224145Sdim : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1007218893Sdim "$Rn = $Rdn", pattern>; 1008195098Sed 1009198090Srdivacky// Thumb1 instruction that can be predicated. 1010224145Sdimclass Thumb1pI<dag oops, dag iops, AddrMode am, int sz, 1011198090Srdivacky InstrItinClass itin, 1012198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1013201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1014198090Srdivacky let OutOperandList = oops; 1015205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1016218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1017198090Srdivacky let Pattern = pattern; 1018218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1019195098Sed} 1020195098Sed 1021198090Srdivackyclass T1pI<dag oops, dag iops, InstrItinClass itin, 1022198090Srdivacky string opc, string asm, list<dag> pattern> 1023224145Sdim : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1024198090Srdivacky 1025198090Srdivacky// Two-address instructions 1026198090Srdivackyclass T1pIt<dag oops, dag iops, InstrItinClass itin, 1027198090Srdivacky string opc, string asm, list<dag> pattern> 1028224145Sdim : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1029218893Sdim "$Rn = $Rdn", pattern>; 1030198090Srdivacky 1031206083Srdivackyclass T1pIs<dag oops, dag iops, 1032198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1033224145Sdim : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>; 1034198090Srdivacky 1035201360Srdivackyclass Encoding16 : Encoding { 1036201360Srdivacky let Inst{31-16} = 0x0000; 1037201360Srdivacky} 1038201360Srdivacky 1039201360Srdivacky// A6.2 16-bit Thumb instruction encoding 1040201360Srdivackyclass T1Encoding<bits<6> opcode> : Encoding16 { 1041201360Srdivacky let Inst{15-10} = opcode; 1042201360Srdivacky} 1043201360Srdivacky 1044201360Srdivacky// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1045201360Srdivackyclass T1General<bits<5> opcode> : Encoding16 { 1046201360Srdivacky let Inst{15-14} = 0b00; 1047201360Srdivacky let Inst{13-9} = opcode; 1048201360Srdivacky} 1049201360Srdivacky 1050201360Srdivacky// A6.2.2 Data-processing encoding. 1051201360Srdivackyclass T1DataProcessing<bits<4> opcode> : Encoding16 { 1052201360Srdivacky let Inst{15-10} = 0b010000; 1053201360Srdivacky let Inst{9-6} = opcode; 1054201360Srdivacky} 1055201360Srdivacky 1056201360Srdivacky// A6.2.3 Special data instructions and branch and exchange encoding. 1057201360Srdivackyclass T1Special<bits<4> opcode> : Encoding16 { 1058201360Srdivacky let Inst{15-10} = 0b010001; 1059218893Sdim let Inst{9-6} = opcode; 1060201360Srdivacky} 1061201360Srdivacky 1062201360Srdivacky// A6.2.4 Load/store single data item encoding. 1063201360Srdivackyclass T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1064201360Srdivacky let Inst{15-12} = opA; 1065212904Sdim let Inst{11-9} = opB; 1066201360Srdivacky} 1067212904Sdimclass T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1068201360Srdivacky 1069223017Sdimclass T1BranchCond<bits<4> opcode> : Encoding16 { 1070223017Sdim let Inst{15-12} = opcode; 1071223017Sdim} 1072223017Sdim 1073218893Sdim// Helper classes to encode Thumb1 loads and stores. For immediates, the 1074218893Sdim// following bits are used for "opA" (see A6.2.4): 1075218893Sdim// 1076218893Sdim// 0b0110 => Immediate, 4 bytes 1077218893Sdim// 0b1000 => Immediate, 2 bytes 1078218893Sdim// 0b0111 => Immediate, 1 byte 1079218893Sdimclass T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1080218893Sdim InstrItinClass itin, string opc, string asm, 1081218893Sdim list<dag> pattern> 1082224145Sdim : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1083218893Sdim T1LoadStore<0b0101, opcode> { 1084218893Sdim bits<3> Rt; 1085218893Sdim bits<8> addr; 1086218893Sdim let Inst{8-6} = addr{5-3}; // Rm 1087218893Sdim let Inst{5-3} = addr{2-0}; // Rn 1088218893Sdim let Inst{2-0} = Rt; 1089218893Sdim} 1090218893Sdimclass T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1091218893Sdim InstrItinClass itin, string opc, string asm, 1092218893Sdim list<dag> pattern> 1093224145Sdim : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1094218893Sdim T1LoadStore<opA, {opB,?,?}> { 1095218893Sdim bits<3> Rt; 1096218893Sdim bits<8> addr; 1097218893Sdim let Inst{10-6} = addr{7-3}; // imm5 1098218893Sdim let Inst{5-3} = addr{2-0}; // Rn 1099218893Sdim let Inst{2-0} = Rt; 1100218893Sdim} 1101218893Sdim 1102201360Srdivacky// A6.2.5 Miscellaneous 16-bit instructions encoding. 1103201360Srdivackyclass T1Misc<bits<7> opcode> : Encoding16 { 1104201360Srdivacky let Inst{15-12} = 0b1011; 1105201360Srdivacky let Inst{11-5} = opcode; 1106201360Srdivacky} 1107201360Srdivacky 1108195098Sed// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1109224145Sdimclass Thumb2I<dag oops, dag iops, AddrMode am, int sz, 1110198090Srdivacky InstrItinClass itin, 1111195098Sed string opc, string asm, string cstr, list<dag> pattern> 1112198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1113195098Sed let OutOperandList = oops; 1114205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1115218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1116195098Sed let Pattern = pattern; 1117195340Sed list<Predicate> Predicates = [IsThumb2]; 1118226633Sdim let DecoderNamespace = "Thumb2"; 1119194754Sed} 1120194754Sed 1121212904Sdim// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1122212904Sdim// input operand since by default it's a zero register. It will become an 1123212904Sdim// implicit def once it's "flipped". 1124218893Sdim// 1125195098Sed// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1126195098Sed// more consistent. 1127224145Sdimclass Thumb2sI<dag oops, dag iops, AddrMode am, int sz, 1128198090Srdivacky InstrItinClass itin, 1129195098Sed string opc, string asm, string cstr, list<dag> pattern> 1130198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1131218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1132218893Sdim let Inst{20} = s; 1133218893Sdim 1134195098Sed let OutOperandList = oops; 1135205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1136218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 1137195098Sed let Pattern = pattern; 1138195340Sed list<Predicate> Predicates = [IsThumb2]; 1139226633Sdim let DecoderNamespace = "Thumb2"; 1140195098Sed} 1141194754Sed 1142195098Sed// Special cases 1143224145Sdimclass Thumb2XI<dag oops, dag iops, AddrMode am, int sz, 1144198090Srdivacky InstrItinClass itin, 1145195098Sed string asm, string cstr, list<dag> pattern> 1146198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1147195098Sed let OutOperandList = oops; 1148195098Sed let InOperandList = iops; 1149208599Srdivacky let AsmString = asm; 1150195098Sed let Pattern = pattern; 1151195340Sed list<Predicate> Predicates = [IsThumb2]; 1152226633Sdim let DecoderNamespace = "Thumb2"; 1153194754Sed} 1154194754Sed 1155224145Sdimclass ThumbXI<dag oops, dag iops, AddrMode am, int sz, 1156206083Srdivacky InstrItinClass itin, 1157206083Srdivacky string asm, string cstr, list<dag> pattern> 1158200581Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1159200581Srdivacky let OutOperandList = oops; 1160200581Srdivacky let InOperandList = iops; 1161208599Srdivacky let AsmString = asm; 1162200581Srdivacky let Pattern = pattern; 1163218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1164226633Sdim let DecoderNamespace = "Thumb"; 1165200581Srdivacky} 1166200581Srdivacky 1167198090Srdivackyclass T2I<dag oops, dag iops, InstrItinClass itin, 1168198090Srdivacky string opc, string asm, list<dag> pattern> 1169224145Sdim : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1170198090Srdivackyclass T2Ii12<dag oops, dag iops, InstrItinClass itin, 1171198090Srdivacky string opc, string asm, list<dag> pattern> 1172224145Sdim : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>; 1173198090Srdivackyclass T2Ii8<dag oops, dag iops, InstrItinClass itin, 1174198090Srdivacky string opc, string asm, list<dag> pattern> 1175224145Sdim : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>; 1176198090Srdivackyclass T2Iso<dag oops, dag iops, InstrItinClass itin, 1177198090Srdivacky string opc, string asm, list<dag> pattern> 1178224145Sdim : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>; 1179198090Srdivackyclass T2Ipc<dag oops, dag iops, InstrItinClass itin, 1180198090Srdivacky string opc, string asm, list<dag> pattern> 1181224145Sdim : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>; 1182218893Sdimclass T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1183226633Sdim string opc, string asm, string cstr, list<dag> pattern> 1184226633Sdim : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1185201360Srdivacky pattern> { 1186218893Sdim bits<4> Rt; 1187218893Sdim bits<4> Rt2; 1188218893Sdim bits<13> addr; 1189218893Sdim let Inst{31-25} = 0b1110100; 1190212904Sdim let Inst{24} = P; 1191218893Sdim let Inst{23} = addr{8}; 1192212904Sdim let Inst{22} = 1; 1193212904Sdim let Inst{21} = W; 1194218893Sdim let Inst{20} = isLoad; 1195218893Sdim let Inst{19-16} = addr{12-9}; 1196218893Sdim let Inst{15-12} = Rt{3-0}; 1197218893Sdim let Inst{11-8} = Rt2{3-0}; 1198218893Sdim let Inst{7-0} = addr{7-0}; 1199201360Srdivacky} 1200226633Sdimclass T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops, 1201226633Sdim InstrItinClass itin, string opc, string asm, string cstr, 1202226633Sdim list<dag> pattern> 1203226633Sdim : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1204226633Sdim pattern> { 1205226633Sdim bits<4> Rt; 1206226633Sdim bits<4> Rt2; 1207226633Sdim bits<4> addr; 1208226633Sdim bits<9> imm; 1209226633Sdim let Inst{31-25} = 0b1110100; 1210226633Sdim let Inst{24} = P; 1211226633Sdim let Inst{23} = imm{8}; 1212226633Sdim let Inst{22} = 1; 1213226633Sdim let Inst{21} = W; 1214226633Sdim let Inst{20} = isLoad; 1215226633Sdim let Inst{19-16} = addr; 1216226633Sdim let Inst{15-12} = Rt{3-0}; 1217226633Sdim let Inst{11-8} = Rt2{3-0}; 1218226633Sdim let Inst{7-0} = imm{7-0}; 1219226633Sdim} 1220195098Sed 1221198090Srdivackyclass T2sI<dag oops, dag iops, InstrItinClass itin, 1222198090Srdivacky string opc, string asm, list<dag> pattern> 1223224145Sdim : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1224195098Sed 1225198090Srdivackyclass T2XI<dag oops, dag iops, InstrItinClass itin, 1226198090Srdivacky string asm, list<dag> pattern> 1227224145Sdim : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1228198090Srdivackyclass T2JTI<dag oops, dag iops, InstrItinClass itin, 1229198090Srdivacky string asm, list<dag> pattern> 1230224145Sdim : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1231195098Sed 1232218893Sdim// Move to/from coprocessor instructions 1233224145Sdimclass T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern> 1234224145Sdim : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> { 1235224145Sdim let Inst{31-28} = opc; 1236218893Sdim} 1237198090Srdivacky 1238205218Srdivacky// Two-address instructions 1239205218Srdivackyclass T2XIt<dag oops, dag iops, InstrItinClass itin, 1240205218Srdivacky string asm, string cstr, list<dag> pattern> 1241224145Sdim : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>; 1242198090Srdivacky 1243226633Sdim// T2Ipreldst - Thumb2 pre-indexed load / store instructions. 1244226633Sdimclass T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre, 1245201360Srdivacky dag oops, dag iops, 1246201360Srdivacky AddrMode am, IndexMode im, InstrItinClass itin, 1247195340Sed string opc, string asm, string cstr, list<dag> pattern> 1248224145Sdim : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1249195340Sed let OutOperandList = oops; 1250205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1251218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1252195340Sed let Pattern = pattern; 1253195340Sed list<Predicate> Predicates = [IsThumb2]; 1254226633Sdim let DecoderNamespace = "Thumb2"; 1255226633Sdim 1256226633Sdim bits<4> Rt; 1257226633Sdim bits<13> addr; 1258201360Srdivacky let Inst{31-27} = 0b11111; 1259201360Srdivacky let Inst{26-25} = 0b00; 1260212904Sdim let Inst{24} = signed; 1261212904Sdim let Inst{23} = 0; 1262201360Srdivacky let Inst{22-21} = opcod; 1263212904Sdim let Inst{20} = load; 1264226633Sdim let Inst{19-16} = addr{12-9}; 1265226633Sdim let Inst{15-12} = Rt{3-0}; 1266212904Sdim let Inst{11} = 1; 1267201360Srdivacky // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1268212904Sdim let Inst{10} = pre; // The P bit. 1269226633Sdim let Inst{9} = addr{8}; // Sign bit 1270212904Sdim let Inst{8} = 1; // The W bit. 1271226633Sdim let Inst{7-0} = addr{7-0}; 1272195340Sed 1273226633Sdim let DecoderMethod = "DecodeT2LdStPre"; 1274226633Sdim} 1275218893Sdim 1276226633Sdim// T2Ipostldst - Thumb2 post-indexed load / store instructions. 1277226633Sdimclass T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre, 1278226633Sdim dag oops, dag iops, 1279226633Sdim AddrMode am, IndexMode im, InstrItinClass itin, 1280226633Sdim string opc, string asm, string cstr, list<dag> pattern> 1281226633Sdim : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1282226633Sdim let OutOperandList = oops; 1283226633Sdim let InOperandList = !con(iops, (ins pred:$p)); 1284226633Sdim let AsmString = !strconcat(opc, "${p}", asm); 1285226633Sdim let Pattern = pattern; 1286226633Sdim list<Predicate> Predicates = [IsThumb2]; 1287226633Sdim let DecoderNamespace = "Thumb2"; 1288226633Sdim 1289218893Sdim bits<4> Rt; 1290218893Sdim bits<4> Rn; 1291226633Sdim bits<9> offset; 1292226633Sdim let Inst{31-27} = 0b11111; 1293226633Sdim let Inst{26-25} = 0b00; 1294226633Sdim let Inst{24} = signed; 1295226633Sdim let Inst{23} = 0; 1296226633Sdim let Inst{22-21} = opcod; 1297226633Sdim let Inst{20} = load; 1298226633Sdim let Inst{19-16} = Rn; 1299218893Sdim let Inst{15-12} = Rt{3-0}; 1300226633Sdim let Inst{11} = 1; 1301226633Sdim // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1302226633Sdim let Inst{10} = pre; // The P bit. 1303226633Sdim let Inst{9} = offset{8}; // Sign bit 1304226633Sdim let Inst{8} = 1; // The W bit. 1305226633Sdim let Inst{7-0} = offset{7-0}; 1306226633Sdim 1307226633Sdim let DecoderMethod = "DecodeT2LdStPre"; 1308204642Srdivacky} 1309204642Srdivacky 1310198090Srdivacky// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1311198090Srdivackyclass Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1312218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1313198090Srdivacky} 1314195340Sed 1315198090Srdivacky// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1316198090Srdivackyclass T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1317218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1318198090Srdivacky} 1319198090Srdivacky 1320223017Sdim// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. 1321223017Sdimclass T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { 1322223017Sdim list<Predicate> Predicates = [IsThumb2, HasV6T2]; 1323223017Sdim} 1324223017Sdim 1325195098Sed// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1326195098Sedclass T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1327195340Sed list<Predicate> Predicates = [IsThumb2]; 1328195098Sed} 1329195098Sed 1330193323Sed//===----------------------------------------------------------------------===// 1331193323Sed 1332193323Sed//===----------------------------------------------------------------------===// 1333193323Sed// ARM VFP Instruction templates. 1334193323Sed// 1335193323Sed 1336198090Srdivacky// Almost all VFP instructions are predicable. 1337224145Sdimclass VFPI<dag oops, dag iops, AddrMode am, int sz, 1338198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1339198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1340198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1341218893Sdim bits<4> p; 1342218893Sdim let Inst{31-28} = p; 1343198090Srdivacky let OutOperandList = oops; 1344205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1345218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1346198090Srdivacky let Pattern = pattern; 1347218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1348226633Sdim let DecoderNamespace = "VFP"; 1349198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1350198090Srdivacky} 1351198090Srdivacky 1352198090Srdivacky// Special cases 1353224145Sdimclass VFPXI<dag oops, dag iops, AddrMode am, int sz, 1354198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1355198090Srdivacky string asm, string cstr, list<dag> pattern> 1356198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1357218893Sdim bits<4> p; 1358218893Sdim let Inst{31-28} = p; 1359198090Srdivacky let OutOperandList = oops; 1360198090Srdivacky let InOperandList = iops; 1361208599Srdivacky let AsmString = asm; 1362198090Srdivacky let Pattern = pattern; 1363218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1364226633Sdim let DecoderNamespace = "VFP"; 1365198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1366198090Srdivacky} 1367198090Srdivacky 1368198090Srdivackyclass VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1369198090Srdivacky string opc, string asm, list<dag> pattern> 1370224145Sdim : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 1371218893Sdim opc, asm, "", pattern> { 1372218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1373218893Sdim} 1374198090Srdivacky 1375193323Sed// ARM VFP addrmode5 loads and stores 1376193323Sedclass ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1377198090Srdivacky InstrItinClass itin, 1378193323Sed string opc, string asm, list<dag> pattern> 1379224145Sdim : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1380206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1381218893Sdim // Instruction operands. 1382218893Sdim bits<5> Dd; 1383218893Sdim bits<13> addr; 1384218893Sdim 1385218893Sdim // Encode instruction operands. 1386218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1387218893Sdim let Inst{22} = Dd{4}; 1388218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1389218893Sdim let Inst{15-12} = Dd{3-0}; 1390218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1391218893Sdim 1392193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1393193323Sed let Inst{27-24} = opcod1; 1394193323Sed let Inst{21-20} = opcod2; 1395218893Sdim let Inst{11-9} = 0b101; 1396218893Sdim let Inst{8} = 1; // Double precision 1397198892Srdivacky 1398218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1399206274Srdivacky let D = VFPNeonDomain; 1400193323Sed} 1401193323Sed 1402193323Sedclass ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1403198090Srdivacky InstrItinClass itin, 1404193323Sed string opc, string asm, list<dag> pattern> 1405224145Sdim : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1406206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1407218893Sdim // Instruction operands. 1408218893Sdim bits<5> Sd; 1409218893Sdim bits<13> addr; 1410218893Sdim 1411218893Sdim // Encode instruction operands. 1412218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1413218893Sdim let Inst{22} = Sd{0}; 1414218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1415218893Sdim let Inst{15-12} = Sd{4-1}; 1416218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1417218893Sdim 1418193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1419193323Sed let Inst{27-24} = opcod1; 1420193323Sed let Inst{21-20} = opcod2; 1421218893Sdim let Inst{11-9} = 0b101; 1422218893Sdim let Inst{8} = 0; // Single precision 1423218893Sdim 1424218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1425218893Sdim let D = VFPNeonDomain; 1426193323Sed} 1427193323Sed 1428218893Sdim// VFP Load / store multiple pseudo instructions. 1429218893Sdimclass PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1430218893Sdim list<dag> pattern> 1431224145Sdim : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain, 1432218893Sdim cstr, itin> { 1433218893Sdim let OutOperandList = oops; 1434218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1435218893Sdim let Pattern = pattern; 1436218893Sdim list<Predicate> Predicates = [HasVFP2]; 1437218893Sdim} 1438218893Sdim 1439193323Sed// Load / store multiple 1440212904Sdimclass AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1441205218Srdivacky string asm, string cstr, list<dag> pattern> 1442224145Sdim : VFPXI<oops, iops, AddrMode4, 4, im, 1443206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1444218893Sdim // Instruction operands. 1445218893Sdim bits<4> Rn; 1446218893Sdim bits<13> regs; 1447218893Sdim 1448218893Sdim // Encode instruction operands. 1449218893Sdim let Inst{19-16} = Rn; 1450218893Sdim let Inst{22} = regs{12}; 1451218893Sdim let Inst{15-12} = regs{11-8}; 1452218893Sdim let Inst{7-0} = regs{7-0}; 1453218893Sdim 1454193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1455193323Sed let Inst{27-25} = 0b110; 1456218893Sdim let Inst{11-9} = 0b101; 1457218893Sdim let Inst{8} = 1; // Double precision 1458193323Sed} 1459193323Sed 1460212904Sdimclass AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1461205218Srdivacky string asm, string cstr, list<dag> pattern> 1462224145Sdim : VFPXI<oops, iops, AddrMode4, 4, im, 1463206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1464218893Sdim // Instruction operands. 1465218893Sdim bits<4> Rn; 1466218893Sdim bits<13> regs; 1467218893Sdim 1468218893Sdim // Encode instruction operands. 1469218893Sdim let Inst{19-16} = Rn; 1470218893Sdim let Inst{22} = regs{8}; 1471218893Sdim let Inst{15-12} = regs{12-9}; 1472218893Sdim let Inst{7-0} = regs{7-0}; 1473218893Sdim 1474193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1475193323Sed let Inst{27-25} = 0b110; 1476218893Sdim let Inst{11-9} = 0b101; 1477218893Sdim let Inst{8} = 0; // Single precision 1478193323Sed} 1479193323Sed 1480193323Sed// Double precision, unary 1481203954Srdivackyclass ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1482203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1483203954Srdivacky string asm, list<dag> pattern> 1484198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1485218893Sdim // Instruction operands. 1486218893Sdim bits<5> Dd; 1487218893Sdim bits<5> Dm; 1488218893Sdim 1489218893Sdim // Encode instruction operands. 1490218893Sdim let Inst{3-0} = Dm{3-0}; 1491218893Sdim let Inst{5} = Dm{4}; 1492218893Sdim let Inst{15-12} = Dd{3-0}; 1493218893Sdim let Inst{22} = Dd{4}; 1494218893Sdim 1495203954Srdivacky let Inst{27-23} = opcod1; 1496203954Srdivacky let Inst{21-20} = opcod2; 1497203954Srdivacky let Inst{19-16} = opcod3; 1498218893Sdim let Inst{11-9} = 0b101; 1499218893Sdim let Inst{8} = 1; // Double precision 1500203954Srdivacky let Inst{7-6} = opcod4; 1501203954Srdivacky let Inst{4} = opcod5; 1502193323Sed} 1503193323Sed 1504193323Sed// Double precision, binary 1505203954Srdivackyclass ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1506206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1507206083Srdivacky list<dag> pattern> 1508198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1509218893Sdim // Instruction operands. 1510218893Sdim bits<5> Dd; 1511218893Sdim bits<5> Dn; 1512218893Sdim bits<5> Dm; 1513193323Sed 1514218893Sdim // Encode instruction operands. 1515218893Sdim let Inst{3-0} = Dm{3-0}; 1516218893Sdim let Inst{5} = Dm{4}; 1517218893Sdim let Inst{19-16} = Dn{3-0}; 1518218893Sdim let Inst{7} = Dn{4}; 1519218893Sdim let Inst{15-12} = Dd{3-0}; 1520218893Sdim let Inst{22} = Dd{4}; 1521218893Sdim 1522206083Srdivacky let Inst{27-23} = opcod1; 1523206083Srdivacky let Inst{21-20} = opcod2; 1524218893Sdim let Inst{11-9} = 0b101; 1525218893Sdim let Inst{8} = 1; // Double precision 1526212904Sdim let Inst{6} = op6; 1527212904Sdim let Inst{4} = op4; 1528206083Srdivacky} 1529206083Srdivacky 1530193323Sed// Single precision, unary 1531203954Srdivackyclass ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1532203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1533203954Srdivacky string asm, list<dag> pattern> 1534198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1535218893Sdim // Instruction operands. 1536218893Sdim bits<5> Sd; 1537218893Sdim bits<5> Sm; 1538218893Sdim 1539218893Sdim // Encode instruction operands. 1540218893Sdim let Inst{3-0} = Sm{4-1}; 1541218893Sdim let Inst{5} = Sm{0}; 1542218893Sdim let Inst{15-12} = Sd{4-1}; 1543218893Sdim let Inst{22} = Sd{0}; 1544218893Sdim 1545203954Srdivacky let Inst{27-23} = opcod1; 1546203954Srdivacky let Inst{21-20} = opcod2; 1547203954Srdivacky let Inst{19-16} = opcod3; 1548218893Sdim let Inst{11-9} = 0b101; 1549218893Sdim let Inst{8} = 0; // Single precision 1550203954Srdivacky let Inst{7-6} = opcod4; 1551203954Srdivacky let Inst{4} = opcod5; 1552193323Sed} 1553193323Sed 1554218893Sdim// Single precision unary, if no NEON. Same as ASuI except not available if 1555218893Sdim// NEON is enabled. 1556203954Srdivackyclass ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1557203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1558203954Srdivacky string asm, list<dag> pattern> 1559203954Srdivacky : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1560203954Srdivacky pattern> { 1561198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1562198090Srdivacky} 1563198090Srdivacky 1564193323Sed// Single precision, binary 1565203954Srdivackyclass ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1566203954Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1567198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1568218893Sdim // Instruction operands. 1569218893Sdim bits<5> Sd; 1570218893Sdim bits<5> Sn; 1571218893Sdim bits<5> Sm; 1572218893Sdim 1573218893Sdim // Encode instruction operands. 1574218893Sdim let Inst{3-0} = Sm{4-1}; 1575218893Sdim let Inst{5} = Sm{0}; 1576218893Sdim let Inst{19-16} = Sn{4-1}; 1577218893Sdim let Inst{7} = Sn{0}; 1578218893Sdim let Inst{15-12} = Sd{4-1}; 1579218893Sdim let Inst{22} = Sd{0}; 1580218893Sdim 1581203954Srdivacky let Inst{27-23} = opcod1; 1582203954Srdivacky let Inst{21-20} = opcod2; 1583218893Sdim let Inst{11-9} = 0b101; 1584218893Sdim let Inst{8} = 0; // Single precision 1585212904Sdim let Inst{6} = op6; 1586212904Sdim let Inst{4} = op4; 1587193323Sed} 1588193323Sed 1589218893Sdim// Single precision binary, if no NEON. Same as ASbI except not available if 1590218893Sdim// NEON is enabled. 1591203954Srdivackyclass ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1592206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1593206083Srdivacky list<dag> pattern> 1594203954Srdivacky : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1595198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1596218893Sdim 1597218893Sdim // Instruction operands. 1598218893Sdim bits<5> Sd; 1599218893Sdim bits<5> Sn; 1600218893Sdim bits<5> Sm; 1601218893Sdim 1602218893Sdim // Encode instruction operands. 1603218893Sdim let Inst{3-0} = Sm{4-1}; 1604218893Sdim let Inst{5} = Sm{0}; 1605218893Sdim let Inst{19-16} = Sn{4-1}; 1606218893Sdim let Inst{7} = Sn{0}; 1607218893Sdim let Inst{15-12} = Sd{4-1}; 1608218893Sdim let Inst{22} = Sd{0}; 1609198090Srdivacky} 1610198090Srdivacky 1611193323Sed// VFP conversion instructions 1612203954Srdivackyclass AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1613203954Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1614203954Srdivacky list<dag> pattern> 1615198090Srdivacky : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1616203954Srdivacky let Inst{27-23} = opcod1; 1617203954Srdivacky let Inst{21-20} = opcod2; 1618203954Srdivacky let Inst{19-16} = opcod3; 1619203954Srdivacky let Inst{11-8} = opcod4; 1620193323Sed let Inst{6} = 1; 1621203954Srdivacky let Inst{4} = 0; 1622193323Sed} 1623193323Sed 1624203954Srdivacky// VFP conversion between floating-point and fixed-point 1625203954Srdivackyclass AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1626206083Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1627206083Srdivacky list<dag> pattern> 1628203954Srdivacky : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1629234353Sdim bits<5> fbits; 1630203954Srdivacky // size (fixed-point number): sx == 0 ? 16 : 32 1631203954Srdivacky let Inst{7} = op5; // sx 1632234353Sdim let Inst{5} = fbits{0}; 1633234353Sdim let Inst{3-0} = fbits{4-1}; 1634203954Srdivacky} 1635203954Srdivacky 1636198090Srdivacky// VFP conversion instructions, if no NEON 1637203954Srdivackyclass AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1638198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1639198090Srdivacky string opc, string asm, list<dag> pattern> 1640203954Srdivacky : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1641203954Srdivacky pattern> { 1642198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1643198090Srdivacky} 1644198090Srdivacky 1645193323Sedclass AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1646198090Srdivacky InstrItinClass itin, 1647198090Srdivacky string opc, string asm, list<dag> pattern> 1648198090Srdivacky : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1649193323Sed let Inst{27-20} = opcod1; 1650193323Sed let Inst{11-8} = opcod2; 1651193323Sed let Inst{4} = 1; 1652193323Sed} 1653193323Sed 1654198090Srdivackyclass AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1655198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1656198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1657193323Sed 1658206083Srdivackyclass AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1659198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1660198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1661193323Sed 1662198090Srdivackyclass AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1663198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1664198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1665193323Sed 1666198090Srdivackyclass AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1667198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1668198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1669193323Sed 1670193323Sed//===----------------------------------------------------------------------===// 1671193323Sed 1672194710Sed//===----------------------------------------------------------------------===// 1673194710Sed// ARM NEON Instruction templates. 1674194710Sed// 1675193323Sed 1676205407Srdivackyclass NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1677205407Srdivacky InstrItinClass itin, string opc, string dt, string asm, string cstr, 1678205407Srdivacky list<dag> pattern> 1679224145Sdim : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1680194710Sed let OutOperandList = oops; 1681205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1682218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1683194710Sed let Pattern = pattern; 1684194710Sed list<Predicate> Predicates = [HasNEON]; 1685226633Sdim let DecoderNamespace = "NEON"; 1686193323Sed} 1687193323Sed 1688199989Srdivacky// Same as NeonI except it does not have a "data type" specifier. 1689206083Srdivackyclass NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1690206083Srdivacky InstrItinClass itin, string opc, string asm, string cstr, 1691206083Srdivacky list<dag> pattern> 1692224145Sdim : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1693199989Srdivacky let OutOperandList = oops; 1694205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1695218893Sdim let AsmString = !strconcat(opc, "${p}", "\t", asm); 1696199989Srdivacky let Pattern = pattern; 1697199989Srdivacky list<Predicate> Predicates = [HasNEON]; 1698226633Sdim let DecoderNamespace = "NEON"; 1699193323Sed} 1700194710Sed 1701198090Srdivackyclass NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1702198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1703199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1704205407Srdivacky : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1705205407Srdivacky cstr, pattern> { 1706198090Srdivacky let Inst{31-24} = 0b11110100; 1707212904Sdim let Inst{23} = op23; 1708198396Srdivacky let Inst{21-20} = op21_20; 1709212904Sdim let Inst{11-8} = op11_8; 1710212904Sdim let Inst{7-4} = op7_4; 1711218893Sdim 1712218893Sdim let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1713226633Sdim let DecoderNamespace = "NEONLoadStore"; 1714218893Sdim 1715218893Sdim bits<5> Vd; 1716218893Sdim bits<6> Rn; 1717218893Sdim bits<4> Rm; 1718218893Sdim 1719218893Sdim let Inst{22} = Vd{4}; 1720218893Sdim let Inst{15-12} = Vd{3-0}; 1721218893Sdim let Inst{19-16} = Rn{3-0}; 1722218893Sdim let Inst{3-0} = Rm{3-0}; 1723198090Srdivacky} 1724198090Srdivacky 1725218893Sdimclass NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1726218893Sdim dag oops, dag iops, InstrItinClass itin, 1727218893Sdim string opc, string dt, string asm, string cstr, list<dag> pattern> 1728218893Sdim : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1729218893Sdim dt, asm, cstr, pattern> { 1730218893Sdim bits<3> lane; 1731218893Sdim} 1732218893Sdim 1733212904Sdimclass PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1734224145Sdim : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1735212904Sdim itin> { 1736212904Sdim let OutOperandList = oops; 1737212904Sdim let InOperandList = !con(iops, (ins pred:$p)); 1738212904Sdim list<Predicate> Predicates = [HasNEON]; 1739212904Sdim} 1740212904Sdim 1741218893Sdimclass PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1742218893Sdim list<dag> pattern> 1743224145Sdim : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1744218893Sdim itin> { 1745218893Sdim let OutOperandList = oops; 1746218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1747218893Sdim let Pattern = pattern; 1748218893Sdim list<Predicate> Predicates = [HasNEON]; 1749218893Sdim} 1750218893Sdim 1751206083Srdivackyclass NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1752199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1753206083Srdivacky : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1754206083Srdivacky pattern> { 1755194710Sed let Inst{31-25} = 0b1111001; 1756218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1757226633Sdim let DecoderNamespace = "NEONData"; 1758194710Sed} 1759194710Sed 1760206083Srdivackyclass NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1761206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1762206083Srdivacky : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1763206083Srdivacky cstr, pattern> { 1764199989Srdivacky let Inst{31-25} = 0b1111001; 1765218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1766226633Sdim let DecoderNamespace = "NEONData"; 1767199989Srdivacky} 1768199989Srdivacky 1769194710Sed// NEON "one register and a modified immediate" format. 1770194710Sedclass N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1771194710Sed bit op5, bit op4, 1772198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1773206083Srdivacky string opc, string dt, string asm, string cstr, 1774206083Srdivacky list<dag> pattern> 1775206083Srdivacky : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1776212904Sdim let Inst{23} = op23; 1777194710Sed let Inst{21-19} = op21_19; 1778212904Sdim let Inst{11-8} = op11_8; 1779212904Sdim let Inst{7} = op7; 1780212904Sdim let Inst{6} = op6; 1781212904Sdim let Inst{5} = op5; 1782212904Sdim let Inst{4} = op4; 1783218893Sdim 1784218893Sdim // Instruction operands. 1785218893Sdim bits<5> Vd; 1786218893Sdim bits<13> SIMM; 1787218893Sdim 1788218893Sdim let Inst{15-12} = Vd{3-0}; 1789218893Sdim let Inst{22} = Vd{4}; 1790218893Sdim let Inst{24} = SIMM{7}; 1791218893Sdim let Inst{18-16} = SIMM{6-4}; 1792218893Sdim let Inst{3-0} = SIMM{3-0}; 1793226633Sdim let DecoderMethod = "DecodeNEONModImmInstruction"; 1794194710Sed} 1795194710Sed 1796194710Sed// NEON 2 vector register format. 1797194710Sedclass N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1798194710Sed bits<5> op11_7, bit op6, bit op4, 1799198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1800199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1801206083Srdivacky : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1802194710Sed let Inst{24-23} = op24_23; 1803194710Sed let Inst{21-20} = op21_20; 1804194710Sed let Inst{19-18} = op19_18; 1805194710Sed let Inst{17-16} = op17_16; 1806212904Sdim let Inst{11-7} = op11_7; 1807212904Sdim let Inst{6} = op6; 1808212904Sdim let Inst{4} = op4; 1809218893Sdim 1810218893Sdim // Instruction operands. 1811218893Sdim bits<5> Vd; 1812218893Sdim bits<5> Vm; 1813218893Sdim 1814218893Sdim let Inst{15-12} = Vd{3-0}; 1815218893Sdim let Inst{22} = Vd{4}; 1816218893Sdim let Inst{3-0} = Vm{3-0}; 1817218893Sdim let Inst{5} = Vm{4}; 1818194710Sed} 1819194710Sed 1820199989Srdivacky// Same as N2V except it doesn't have a datatype suffix. 1821199989Srdivackyclass N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1822206083Srdivacky bits<5> op11_7, bit op6, bit op4, 1823206083Srdivacky dag oops, dag iops, InstrItinClass itin, 1824206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1825206083Srdivacky : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1826198396Srdivacky let Inst{24-23} = op24_23; 1827198396Srdivacky let Inst{21-20} = op21_20; 1828199989Srdivacky let Inst{19-18} = op19_18; 1829199989Srdivacky let Inst{17-16} = op17_16; 1830212904Sdim let Inst{11-7} = op11_7; 1831212904Sdim let Inst{6} = op6; 1832212904Sdim let Inst{4} = op4; 1833218893Sdim 1834218893Sdim // Instruction operands. 1835218893Sdim bits<5> Vd; 1836218893Sdim bits<5> Vm; 1837218893Sdim 1838218893Sdim let Inst{15-12} = Vd{3-0}; 1839218893Sdim let Inst{22} = Vd{4}; 1840218893Sdim let Inst{3-0} = Vm{3-0}; 1841218893Sdim let Inst{5} = Vm{4}; 1842198396Srdivacky} 1843198396Srdivacky 1844194710Sed// NEON 2 vector register with immediate. 1845198396Srdivackyclass N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1846206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1847199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1848206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1849212904Sdim let Inst{24} = op24; 1850212904Sdim let Inst{23} = op23; 1851194710Sed let Inst{11-8} = op11_8; 1852212904Sdim let Inst{7} = op7; 1853212904Sdim let Inst{6} = op6; 1854212904Sdim let Inst{4} = op4; 1855218893Sdim 1856218893Sdim // Instruction operands. 1857218893Sdim bits<5> Vd; 1858218893Sdim bits<5> Vm; 1859218893Sdim bits<6> SIMM; 1860218893Sdim 1861218893Sdim let Inst{15-12} = Vd{3-0}; 1862218893Sdim let Inst{22} = Vd{4}; 1863218893Sdim let Inst{3-0} = Vm{3-0}; 1864218893Sdim let Inst{5} = Vm{4}; 1865218893Sdim let Inst{21-16} = SIMM{5-0}; 1866194710Sed} 1867194710Sed 1868194710Sed// NEON 3 vector register format. 1869221345Sdim 1870223017Sdimclass N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1871223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1872223017Sdim string opc, string dt, string asm, string cstr, 1873223017Sdim list<dag> pattern> 1874206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1875212904Sdim let Inst{24} = op24; 1876212904Sdim let Inst{23} = op23; 1877194710Sed let Inst{21-20} = op21_20; 1878212904Sdim let Inst{11-8} = op11_8; 1879212904Sdim let Inst{6} = op6; 1880212904Sdim let Inst{4} = op4; 1881221345Sdim} 1882218893Sdim 1883221345Sdimclass N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1884221345Sdim dag oops, dag iops, Format f, InstrItinClass itin, 1885221345Sdim string opc, string dt, string asm, string cstr, list<dag> pattern> 1886221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1887221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1888218893Sdim // Instruction operands. 1889218893Sdim bits<5> Vd; 1890218893Sdim bits<5> Vn; 1891218893Sdim bits<5> Vm; 1892218893Sdim 1893218893Sdim let Inst{15-12} = Vd{3-0}; 1894218893Sdim let Inst{22} = Vd{4}; 1895218893Sdim let Inst{19-16} = Vn{3-0}; 1896218893Sdim let Inst{7} = Vn{4}; 1897218893Sdim let Inst{3-0} = Vm{3-0}; 1898218893Sdim let Inst{5} = Vm{4}; 1899194710Sed} 1900194710Sed 1901223017Sdimclass N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1902223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1903223017Sdim string opc, string dt, string asm, string cstr, 1904223017Sdim list<dag> pattern> 1905221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1906221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1907221345Sdim 1908221345Sdim // Instruction operands. 1909221345Sdim bits<5> Vd; 1910221345Sdim bits<5> Vn; 1911221345Sdim bits<5> Vm; 1912221345Sdim bit lane; 1913221345Sdim 1914221345Sdim let Inst{15-12} = Vd{3-0}; 1915221345Sdim let Inst{22} = Vd{4}; 1916221345Sdim let Inst{19-16} = Vn{3-0}; 1917221345Sdim let Inst{7} = Vn{4}; 1918221345Sdim let Inst{3-0} = Vm{3-0}; 1919221345Sdim let Inst{5} = lane; 1920221345Sdim} 1921221345Sdim 1922223017Sdimclass N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1923223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1924223017Sdim string opc, string dt, string asm, string cstr, 1925223017Sdim list<dag> pattern> 1926221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1927221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1928221345Sdim 1929221345Sdim // Instruction operands. 1930221345Sdim bits<5> Vd; 1931221345Sdim bits<5> Vn; 1932221345Sdim bits<5> Vm; 1933221345Sdim bits<2> lane; 1934221345Sdim 1935221345Sdim let Inst{15-12} = Vd{3-0}; 1936221345Sdim let Inst{22} = Vd{4}; 1937221345Sdim let Inst{19-16} = Vn{3-0}; 1938221345Sdim let Inst{7} = Vn{4}; 1939221345Sdim let Inst{2-0} = Vm{2-0}; 1940221345Sdim let Inst{5} = lane{1}; 1941221345Sdim let Inst{3} = lane{0}; 1942221345Sdim} 1943221345Sdim 1944206083Srdivacky// Same as N3V except it doesn't have a data type suffix. 1945206083Srdivackyclass N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1946206083Srdivacky bit op4, 1947206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1948206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1949206083Srdivacky : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1950212904Sdim let Inst{24} = op24; 1951212904Sdim let Inst{23} = op23; 1952198396Srdivacky let Inst{21-20} = op21_20; 1953212904Sdim let Inst{11-8} = op11_8; 1954212904Sdim let Inst{6} = op6; 1955212904Sdim let Inst{4} = op4; 1956218893Sdim 1957218893Sdim // Instruction operands. 1958218893Sdim bits<5> Vd; 1959218893Sdim bits<5> Vn; 1960218893Sdim bits<5> Vm; 1961218893Sdim 1962218893Sdim let Inst{15-12} = Vd{3-0}; 1963218893Sdim let Inst{22} = Vd{4}; 1964218893Sdim let Inst{19-16} = Vn{3-0}; 1965218893Sdim let Inst{7} = Vn{4}; 1966218893Sdim let Inst{3-0} = Vm{3-0}; 1967218893Sdim let Inst{5} = Vm{4}; 1968198396Srdivacky} 1969198396Srdivacky 1970194710Sed// NEON VMOVs between scalar and core registers. 1971194710Sedclass NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1972198090Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1973199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1974224145Sdim : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain, 1975206083Srdivacky "", itin> { 1976194710Sed let Inst{27-20} = opcod1; 1977212904Sdim let Inst{11-8} = opcod2; 1978212904Sdim let Inst{6-5} = opcod3; 1979212904Sdim let Inst{4} = 1; 1980221345Sdim // A8.6.303, A8.6.328, A8.6.329 1981221345Sdim let Inst{3-0} = 0b0000; 1982199989Srdivacky 1983199989Srdivacky let OutOperandList = oops; 1984205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1985218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1986199989Srdivacky let Pattern = pattern; 1987194710Sed list<Predicate> Predicates = [HasNEON]; 1988218893Sdim 1989218893Sdim let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1990226633Sdim let DecoderNamespace = "NEONDup"; 1991218893Sdim 1992218893Sdim bits<5> V; 1993218893Sdim bits<4> R; 1994218893Sdim bits<4> p; 1995218893Sdim bits<4> lane; 1996218893Sdim 1997218893Sdim let Inst{31-28} = p{3-0}; 1998218893Sdim let Inst{7} = V{4}; 1999218893Sdim let Inst{19-16} = V{3-0}; 2000218893Sdim let Inst{15-12} = R{3-0}; 2001194710Sed} 2002194710Sedclass NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2003198090Srdivacky dag oops, dag iops, InstrItinClass itin, 2004199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 2005210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 2006199989Srdivacky opc, dt, asm, pattern>; 2007194710Sedclass NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2008198090Srdivacky dag oops, dag iops, InstrItinClass itin, 2009199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 2010210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 2011199989Srdivacky opc, dt, asm, pattern>; 2012194710Sedclass NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2013198090Srdivacky dag oops, dag iops, InstrItinClass itin, 2014199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 2015210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 2016199989Srdivacky opc, dt, asm, pattern>; 2017198090Srdivacky 2018206083Srdivacky// Vector Duplicate Lane (from scalar to all elements) 2019206083Srdivackyclass NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 2020206083Srdivacky InstrItinClass itin, string opc, string dt, string asm, 2021206083Srdivacky list<dag> pattern> 2022206083Srdivacky : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 2023206083Srdivacky let Inst{24-23} = 0b11; 2024206083Srdivacky let Inst{21-20} = 0b11; 2025206083Srdivacky let Inst{19-16} = op19_16; 2026212904Sdim let Inst{11-7} = 0b11000; 2027212904Sdim let Inst{6} = op6; 2028212904Sdim let Inst{4} = 0; 2029218893Sdim 2030218893Sdim bits<5> Vd; 2031218893Sdim bits<5> Vm; 2032218893Sdim 2033218893Sdim let Inst{22} = Vd{4}; 2034218893Sdim let Inst{15-12} = Vd{3-0}; 2035218893Sdim let Inst{5} = Vm{4}; 2036218893Sdim let Inst{3-0} = Vm{3-0}; 2037206083Srdivacky} 2038206083Srdivacky 2039198090Srdivacky// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 2040198090Srdivacky// for single-precision FP. 2041198090Srdivackyclass NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 2042198090Srdivacky list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 2043198090Srdivacky} 2044234353Sdim 2045234353Sdim// VFP/NEON Instruction aliases for type suffices. 2046234353Sdimclass VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> : 2047234353Sdim InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>; 2048234353Sdim 2049234353Sdimmulticlass VFPDTAnyInstAlias<string opc, string asm, dag Result> { 2050234353Sdim def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2051234353Sdim def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2052234353Sdim def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2053234353Sdim def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2054234353Sdim} 2055234353Sdim 2056234353Sdimmulticlass NEONDTAnyInstAlias<string opc, string asm, dag Result> { 2057234353Sdim let Predicates = [HasNEON] in { 2058234353Sdim def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2059234353Sdim def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2060234353Sdim def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2061234353Sdim def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2062234353Sdim} 2063234353Sdim} 2064234353Sdim 2065234353Sdim// The same alias classes using AsmPseudo instead, for the more complex 2066234353Sdim// stuff in NEON that InstAlias can't quite handle. 2067234353Sdim// Note that we can't use anonymous defm references here like we can 2068234353Sdim// above, as we care about the ultimate instruction enum names generated, unlike 2069234353Sdim// for instalias defs. 2070234353Sdimclass NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> : 2071234353Sdim AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>; 2072234353Sdim 2073234353Sdim// Data type suffix token aliases. Implements Table A7-3 in the ARM ARM. 2074234353Sdimdef : TokenAlias<".s8", ".i8">; 2075234353Sdimdef : TokenAlias<".u8", ".i8">; 2076234353Sdimdef : TokenAlias<".s16", ".i16">; 2077234353Sdimdef : TokenAlias<".u16", ".i16">; 2078234353Sdimdef : TokenAlias<".s32", ".i32">; 2079234353Sdimdef : TokenAlias<".u32", ".i32">; 2080234353Sdimdef : TokenAlias<".s64", ".i64">; 2081234353Sdimdef : TokenAlias<".u64", ".i64">; 2082234353Sdim 2083234353Sdimdef : TokenAlias<".i8", ".8">; 2084234353Sdimdef : TokenAlias<".i16", ".16">; 2085234353Sdimdef : TokenAlias<".i32", ".32">; 2086234353Sdimdef : TokenAlias<".i64", ".64">; 2087234353Sdim 2088234353Sdimdef : TokenAlias<".p8", ".8">; 2089234353Sdimdef : TokenAlias<".p16", ".16">; 2090234353Sdim 2091234353Sdimdef : TokenAlias<".f32", ".32">; 2092234353Sdimdef : TokenAlias<".f64", ".64">; 2093234353Sdimdef : TokenAlias<".f", ".f32">; 2094234353Sdimdef : TokenAlias<".d", ".f64">; 2095