ARMInstrFormats.td revision 243830
1//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<6> val> { 19 bits<6> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<11>; 37 38def ArithMiscFrm : Format<12>; 39def SatFrm : Format<13>; 40def ExtFrm : Format<14>; 41 42def VFPUnaryFrm : Format<15>; 43def VFPBinaryFrm : Format<16>; 44def VFPConv1Frm : Format<17>; 45def VFPConv2Frm : Format<18>; 46def VFPConv3Frm : Format<19>; 47def VFPConv4Frm : Format<20>; 48def VFPConv5Frm : Format<21>; 49def VFPLdStFrm : Format<22>; 50def VFPLdStMulFrm : Format<23>; 51def VFPMiscFrm : Format<24>; 52 53def ThumbFrm : Format<25>; 54def MiscFrm : Format<26>; 55 56def NGetLnFrm : Format<27>; 57def NSetLnFrm : Format<28>; 58def NDupFrm : Format<29>; 59def NLdStFrm : Format<30>; 60def N1RegModImmFrm: Format<31>; 61def N2RegFrm : Format<32>; 62def NVCVTFrm : Format<33>; 63def NVDupLnFrm : Format<34>; 64def N2RegVShLFrm : Format<35>; 65def N2RegVShRFrm : Format<36>; 66def N3RegFrm : Format<37>; 67def N3RegVShFrm : Format<38>; 68def NVExtFrm : Format<39>; 69def NVMulSLFrm : Format<40>; 70def NVTBLFrm : Format<41>; 71def DPSoRegImmFrm : Format<42>; 72 73// Misc flags. 74 75// The instruction has an Rn register operand. 76// UnaryDP - Indicates this is a unary data processing instruction, i.e. 77// it doesn't have a Rn operand. 78class UnaryDP { bit isUnaryDataProc = 1; } 79 80// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 81// a 16-bit Thumb instruction if certain conditions are met. 82class Xform16Bit { bit canXformTo16Bit = 1; } 83 84//===----------------------------------------------------------------------===// 85// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 86// 87 88// FIXME: Once the JIT is MC-ized, these can go away. 89// Addressing mode. 90class AddrMode<bits<5> val> { 91 bits<5> Value = val; 92} 93def AddrModeNone : AddrMode<0>; 94def AddrMode1 : AddrMode<1>; 95def AddrMode2 : AddrMode<2>; 96def AddrMode3 : AddrMode<3>; 97def AddrMode4 : AddrMode<4>; 98def AddrMode5 : AddrMode<5>; 99def AddrMode6 : AddrMode<6>; 100def AddrModeT1_1 : AddrMode<7>; 101def AddrModeT1_2 : AddrMode<8>; 102def AddrModeT1_4 : AddrMode<9>; 103def AddrModeT1_s : AddrMode<10>; 104def AddrModeT2_i12 : AddrMode<11>; 105def AddrModeT2_i8 : AddrMode<12>; 106def AddrModeT2_so : AddrMode<13>; 107def AddrModeT2_pc : AddrMode<14>; 108def AddrModeT2_i8s4 : AddrMode<15>; 109def AddrMode_i12 : AddrMode<16>; 110 111// Load / store index mode. 112class IndexMode<bits<2> val> { 113 bits<2> Value = val; 114} 115def IndexModeNone : IndexMode<0>; 116def IndexModePre : IndexMode<1>; 117def IndexModePost : IndexMode<2>; 118def IndexModeUpd : IndexMode<3>; 119 120// Instruction execution domain. 121class Domain<bits<3> val> { 122 bits<3> Value = val; 123} 124def GenericDomain : Domain<0>; 125def VFPDomain : Domain<1>; // Instructions in VFP domain only 126def NeonDomain : Domain<2>; // Instructions in Neon domain only 127def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 128def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 129 130//===----------------------------------------------------------------------===// 131// ARM special operands. 132// 133 134// ARM imod and iflag operands, used only by the CPS instruction. 135def imod_op : Operand<i32> { 136 let PrintMethod = "printCPSIMod"; 137} 138 139def ProcIFlagsOperand : AsmOperandClass { 140 let Name = "ProcIFlags"; 141 let ParserMethod = "parseProcIFlagsOperand"; 142} 143def iflags_op : Operand<i32> { 144 let PrintMethod = "printCPSIFlag"; 145 let ParserMatchClass = ProcIFlagsOperand; 146} 147 148// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 149// register whose default is 0 (no register). 150def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } 151def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), 152 (ops (i32 14), (i32 zero_reg))> { 153 let PrintMethod = "printPredicateOperand"; 154 let ParserMatchClass = CondCodeOperand; 155 let DecoderMethod = "DecodePredicateOperand"; 156} 157 158// Conditional code result for instructions whose 's' bit is set, e.g. subs. 159def CCOutOperand : AsmOperandClass { let Name = "CCOut"; } 160def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 161 let EncoderMethod = "getCCOutOpValue"; 162 let PrintMethod = "printSBitModifierOperand"; 163 let ParserMatchClass = CCOutOperand; 164 let DecoderMethod = "DecodeCCOutOperand"; 165} 166 167// Same as cc_out except it defaults to setting CPSR. 168def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 169 let EncoderMethod = "getCCOutOpValue"; 170 let PrintMethod = "printSBitModifierOperand"; 171 let ParserMatchClass = CCOutOperand; 172 let DecoderMethod = "DecodeCCOutOperand"; 173} 174 175// ARM special operands for disassembly only. 176// 177def SetEndAsmOperand : ImmAsmOperand { 178 let Name = "SetEndImm"; 179 let ParserMethod = "parseSetEndImm"; 180} 181def setend_op : Operand<i32> { 182 let PrintMethod = "printSetendOperand"; 183 let ParserMatchClass = SetEndAsmOperand; 184} 185 186def MSRMaskOperand : AsmOperandClass { 187 let Name = "MSRMask"; 188 let ParserMethod = "parseMSRMaskOperand"; 189} 190def msr_mask : Operand<i32> { 191 let PrintMethod = "printMSRMaskOperand"; 192 let DecoderMethod = "DecodeMSRMask"; 193 let ParserMatchClass = MSRMaskOperand; 194} 195 196// Shift Right Immediate - A shift right immediate is encoded differently from 197// other shift immediates. The imm6 field is encoded like so: 198// 199// Offset Encoding 200// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 201// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 202// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 203// 64 64 - <imm> is encoded in imm6<5:0> 204def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; } 205def shr_imm8 : Operand<i32> { 206 let EncoderMethod = "getShiftRight8Imm"; 207 let DecoderMethod = "DecodeShiftRight8Imm"; 208 let ParserMatchClass = shr_imm8_asm_operand; 209} 210def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; } 211def shr_imm16 : Operand<i32> { 212 let EncoderMethod = "getShiftRight16Imm"; 213 let DecoderMethod = "DecodeShiftRight16Imm"; 214 let ParserMatchClass = shr_imm16_asm_operand; 215} 216def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; } 217def shr_imm32 : Operand<i32> { 218 let EncoderMethod = "getShiftRight32Imm"; 219 let DecoderMethod = "DecodeShiftRight32Imm"; 220 let ParserMatchClass = shr_imm32_asm_operand; 221} 222def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; } 223def shr_imm64 : Operand<i32> { 224 let EncoderMethod = "getShiftRight64Imm"; 225 let DecoderMethod = "DecodeShiftRight64Imm"; 226 let ParserMatchClass = shr_imm64_asm_operand; 227} 228 229//===----------------------------------------------------------------------===// 230// ARM Assembler alias templates. 231// 232class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1> 233 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>; 234class tInstAlias<string Asm, dag Result, bit Emit = 0b1> 235 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>; 236class t2InstAlias<string Asm, dag Result, bit Emit = 0b1> 237 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>; 238class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1> 239 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>; 240class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1> 241 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>; 242class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1> 243 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>; 244 245 246class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 247 Requires<[HasVFP2]>; 248class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 249 Requires<[HasNEON]>; 250 251//===----------------------------------------------------------------------===// 252// ARM Instruction templates. 253// 254 255 256class InstTemplate<AddrMode am, int sz, IndexMode im, 257 Format f, Domain d, string cstr, InstrItinClass itin> 258 : Instruction { 259 let Namespace = "ARM"; 260 261 AddrMode AM = am; 262 int Size = sz; 263 IndexMode IM = im; 264 bits<2> IndexModeBits = IM.Value; 265 Format F = f; 266 bits<6> Form = F.Value; 267 Domain D = d; 268 bit isUnaryDataProc = 0; 269 bit canXformTo16Bit = 0; 270 // The instruction is a 16-bit flag setting Thumb instruction. Used 271 // by the parser to determine whether to require the 'S' suffix on the 272 // mnemonic (when not in an IT block) or preclude it (when in an IT block). 273 bit thumbArithFlagSetting = 0; 274 275 // If this is a pseudo instruction, mark it isCodeGenOnly. 276 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 277 278 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h. 279 let TSFlags{4-0} = AM.Value; 280 let TSFlags{6-5} = IndexModeBits; 281 let TSFlags{12-7} = Form; 282 let TSFlags{13} = isUnaryDataProc; 283 let TSFlags{14} = canXformTo16Bit; 284 let TSFlags{17-15} = D.Value; 285 let TSFlags{18} = thumbArithFlagSetting; 286 287 let Constraints = cstr; 288 let Itinerary = itin; 289} 290 291class Encoding { 292 field bits<32> Inst; 293 // Mask of bits that cause an encoding to be UNPREDICTABLE. 294 // If a bit is set, then if the corresponding bit in the 295 // target encoding differs from its value in the "Inst" field, 296 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance). 297 field bits<32> Unpredictable = 0; 298 // SoftFail is the generic name for this field, but we alias it so 299 // as to make it more obvious what it means in ARM-land. 300 field bits<32> SoftFail = Unpredictable; 301} 302 303class InstARM<AddrMode am, int sz, IndexMode im, 304 Format f, Domain d, string cstr, InstrItinClass itin> 305 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding { 306 let DecoderNamespace = "ARM"; 307} 308 309// This Encoding-less class is used by Thumb1 to specify the encoding bits later 310// on by adding flavors to specific instructions. 311class InstThumb<AddrMode am, int sz, IndexMode im, 312 Format f, Domain d, string cstr, InstrItinClass itin> 313 : InstTemplate<am, sz, im, f, d, cstr, itin> { 314 let DecoderNamespace = "Thumb"; 315} 316 317// Pseudo-instructions for alternate assembly syntax (never used by codegen). 318// These are aliases that require C++ handling to convert to the target 319// instruction, while InstAliases can be handled directly by tblgen. 320class AsmPseudoInst<string asm, dag iops> 321 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 322 "", NoItinerary> { 323 let OutOperandList = (outs); 324 let InOperandList = iops; 325 let Pattern = []; 326 let isCodeGenOnly = 0; // So we get asm matcher for it. 327 let AsmString = asm; 328 let isPseudo = 1; 329} 330 331class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 332 Requires<[IsARM]>; 333class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 334 Requires<[IsThumb]>; 335class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 336 Requires<[IsThumb2]>; 337class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 338 Requires<[HasVFP2]>; 339class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, 340 Requires<[HasNEON]>; 341 342// Pseudo instructions for the code generator. 343class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 344 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, 345 GenericDomain, "", itin> { 346 let OutOperandList = oops; 347 let InOperandList = iops; 348 let Pattern = pattern; 349 let isCodeGenOnly = 1; 350 let isPseudo = 1; 351} 352 353// PseudoInst that's ARM-mode only. 354class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 355 list<dag> pattern> 356 : PseudoInst<oops, iops, itin, pattern> { 357 let Size = sz; 358 list<Predicate> Predicates = [IsARM]; 359} 360 361// PseudoInst that's Thumb-mode only. 362class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 363 list<dag> pattern> 364 : PseudoInst<oops, iops, itin, pattern> { 365 let Size = sz; 366 list<Predicate> Predicates = [IsThumb]; 367} 368 369// PseudoInst that's Thumb2-mode only. 370class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 371 list<dag> pattern> 372 : PseudoInst<oops, iops, itin, pattern> { 373 let Size = sz; 374 list<Predicate> Predicates = [IsThumb2]; 375} 376 377class ARMPseudoExpand<dag oops, dag iops, int sz, 378 InstrItinClass itin, list<dag> pattern, 379 dag Result> 380 : ARMPseudoInst<oops, iops, sz, itin, pattern>, 381 PseudoInstExpansion<Result>; 382 383class tPseudoExpand<dag oops, dag iops, int sz, 384 InstrItinClass itin, list<dag> pattern, 385 dag Result> 386 : tPseudoInst<oops, iops, sz, itin, pattern>, 387 PseudoInstExpansion<Result>; 388 389class t2PseudoExpand<dag oops, dag iops, int sz, 390 InstrItinClass itin, list<dag> pattern, 391 dag Result> 392 : t2PseudoInst<oops, iops, sz, itin, pattern>, 393 PseudoInstExpansion<Result>; 394 395// Almost all ARM instructions are predicable. 396class I<dag oops, dag iops, AddrMode am, int sz, 397 IndexMode im, Format f, InstrItinClass itin, 398 string opc, string asm, string cstr, 399 list<dag> pattern> 400 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 401 bits<4> p; 402 let Inst{31-28} = p; 403 let OutOperandList = oops; 404 let InOperandList = !con(iops, (ins pred:$p)); 405 let AsmString = !strconcat(opc, "${p}", asm); 406 let Pattern = pattern; 407 list<Predicate> Predicates = [IsARM]; 408} 409 410// A few are not predicable 411class InoP<dag oops, dag iops, AddrMode am, int sz, 412 IndexMode im, Format f, InstrItinClass itin, 413 string opc, string asm, string cstr, 414 list<dag> pattern> 415 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 416 let OutOperandList = oops; 417 let InOperandList = iops; 418 let AsmString = !strconcat(opc, asm); 419 let Pattern = pattern; 420 let isPredicable = 0; 421 list<Predicate> Predicates = [IsARM]; 422} 423 424// Same as I except it can optionally modify CPSR. Note it's modeled as an input 425// operand since by default it's a zero register. It will become an implicit def 426// once it's "flipped". 427class sI<dag oops, dag iops, AddrMode am, int sz, 428 IndexMode im, Format f, InstrItinClass itin, 429 string opc, string asm, string cstr, 430 list<dag> pattern> 431 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 432 bits<4> p; // Predicate operand 433 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 434 let Inst{31-28} = p; 435 let Inst{20} = s; 436 437 let OutOperandList = oops; 438 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 439 let AsmString = !strconcat(opc, "${s}${p}", asm); 440 let Pattern = pattern; 441 list<Predicate> Predicates = [IsARM]; 442} 443 444// Special cases 445class XI<dag oops, dag iops, AddrMode am, int sz, 446 IndexMode im, Format f, InstrItinClass itin, 447 string asm, string cstr, list<dag> pattern> 448 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 449 let OutOperandList = oops; 450 let InOperandList = iops; 451 let AsmString = asm; 452 let Pattern = pattern; 453 list<Predicate> Predicates = [IsARM]; 454} 455 456class AI<dag oops, dag iops, Format f, InstrItinClass itin, 457 string opc, string asm, list<dag> pattern> 458 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 459 opc, asm, "", pattern>; 460class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 461 string opc, string asm, list<dag> pattern> 462 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 463 opc, asm, "", pattern>; 464class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 465 string asm, list<dag> pattern> 466 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 467 asm, "", pattern>; 468class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 469 string opc, string asm, list<dag> pattern> 470 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 471 opc, asm, "", pattern>; 472 473// Ctrl flow instructions 474class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 475 string opc, string asm, list<dag> pattern> 476 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 477 opc, asm, "", pattern> { 478 let Inst{27-24} = opcod; 479} 480class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 481 string asm, list<dag> pattern> 482 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 483 asm, "", pattern> { 484 let Inst{27-24} = opcod; 485} 486 487// BR_JT instructions 488class JTI<dag oops, dag iops, InstrItinClass itin, 489 string asm, list<dag> pattern> 490 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin, 491 asm, "", pattern>; 492 493// Atomic load/store instructions 494class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 495 string opc, string asm, list<dag> pattern> 496 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 497 opc, asm, "", pattern> { 498 bits<4> Rt; 499 bits<4> addr; 500 let Inst{27-23} = 0b00011; 501 let Inst{22-21} = opcod; 502 let Inst{20} = 1; 503 let Inst{19-16} = addr; 504 let Inst{15-12} = Rt; 505 let Inst{11-0} = 0b111110011111; 506} 507class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 508 string opc, string asm, list<dag> pattern> 509 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 510 opc, asm, "", pattern> { 511 bits<4> Rd; 512 bits<4> Rt; 513 bits<4> addr; 514 let Inst{27-23} = 0b00011; 515 let Inst{22-21} = opcod; 516 let Inst{20} = 0; 517 let Inst{19-16} = addr; 518 let Inst{15-12} = Rd; 519 let Inst{11-4} = 0b11111001; 520 let Inst{3-0} = Rt; 521} 522class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 523 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> { 524 bits<4> Rt; 525 bits<4> Rt2; 526 bits<4> addr; 527 let Inst{27-23} = 0b00010; 528 let Inst{22} = b; 529 let Inst{21-20} = 0b00; 530 let Inst{19-16} = addr; 531 let Inst{15-12} = Rt; 532 let Inst{11-4} = 0b00001001; 533 let Inst{3-0} = Rt2; 534 535 let Unpredictable{11-8} = 0b1111; 536 let DecoderMethod = "DecodeSwap"; 537} 538 539// addrmode1 instructions 540class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 541 string opc, string asm, list<dag> pattern> 542 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 543 opc, asm, "", pattern> { 544 let Inst{24-21} = opcod; 545 let Inst{27-26} = 0b00; 546} 547class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 548 string opc, string asm, list<dag> pattern> 549 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 550 opc, asm, "", pattern> { 551 let Inst{24-21} = opcod; 552 let Inst{27-26} = 0b00; 553} 554class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 555 string asm, list<dag> pattern> 556 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 557 asm, "", pattern> { 558 let Inst{24-21} = opcod; 559 let Inst{27-26} = 0b00; 560} 561 562// loads 563 564// LDR/LDRB/STR/STRB/... 565class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 566 Format f, InstrItinClass itin, string opc, string asm, 567 list<dag> pattern> 568 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm, 569 "", pattern> { 570 let Inst{27-25} = op; 571 let Inst{24} = 1; // 24 == P 572 // 23 == U 573 let Inst{22} = isByte; 574 let Inst{21} = 0; // 21 == W 575 let Inst{20} = isLd; 576} 577// Indexed load/stores 578class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 579 IndexMode im, Format f, InstrItinClass itin, string opc, 580 string asm, string cstr, list<dag> pattern> 581 : I<oops, iops, AddrMode2, 4, im, f, itin, 582 opc, asm, cstr, pattern> { 583 bits<4> Rt; 584 let Inst{27-26} = 0b01; 585 let Inst{24} = isPre; // P bit 586 let Inst{22} = isByte; // B bit 587 let Inst{21} = isPre; // W bit 588 let Inst{20} = isLd; // L bit 589 let Inst{15-12} = Rt; 590} 591class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops, 592 IndexMode im, Format f, InstrItinClass itin, string opc, 593 string asm, string cstr, list<dag> pattern> 594 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 595 pattern> { 596 // AM2 store w/ two operands: (GPR, am2offset) 597 // {12} isAdd 598 // {11-0} imm12/Rm 599 bits<14> offset; 600 bits<4> Rn; 601 let Inst{25} = 1; 602 let Inst{23} = offset{12}; 603 let Inst{19-16} = Rn; 604 let Inst{11-5} = offset{11-5}; 605 let Inst{4} = 0; 606 let Inst{3-0} = offset{3-0}; 607} 608 609class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops, 610 IndexMode im, Format f, InstrItinClass itin, string opc, 611 string asm, string cstr, list<dag> pattern> 612 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 613 pattern> { 614 // AM2 store w/ two operands: (GPR, am2offset) 615 // {12} isAdd 616 // {11-0} imm12/Rm 617 bits<14> offset; 618 bits<4> Rn; 619 let Inst{25} = 0; 620 let Inst{23} = offset{12}; 621 let Inst{19-16} = Rn; 622 let Inst{11-0} = offset{11-0}; 623} 624 625 626// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 627// but for now use this class for STRT and STRBT. 628class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 629 IndexMode im, Format f, InstrItinClass itin, string opc, 630 string asm, string cstr, list<dag> pattern> 631 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 632 pattern> { 633 // AM2 store w/ two operands: (GPR, am2offset) 634 // {17-14} Rn 635 // {13} 1 == Rm, 0 == imm12 636 // {12} isAdd 637 // {11-0} imm12/Rm 638 bits<18> addr; 639 let Inst{25} = addr{13}; 640 let Inst{23} = addr{12}; 641 let Inst{19-16} = addr{17-14}; 642 let Inst{11-0} = addr{11-0}; 643} 644 645// addrmode3 instructions 646class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 647 InstrItinClass itin, string opc, string asm, list<dag> pattern> 648 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 649 opc, asm, "", pattern> { 650 bits<14> addr; 651 bits<4> Rt; 652 let Inst{27-25} = 0b000; 653 let Inst{24} = 1; // P bit 654 let Inst{23} = addr{8}; // U bit 655 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 656 let Inst{21} = 0; // W bit 657 let Inst{20} = op20; // L bit 658 let Inst{19-16} = addr{12-9}; // Rn 659 let Inst{15-12} = Rt; // Rt 660 let Inst{11-8} = addr{7-4}; // imm7_4/zero 661 let Inst{7-4} = op; 662 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 663 664 let DecoderMethod = "DecodeAddrMode3Instruction"; 665} 666 667class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops, 668 IndexMode im, Format f, InstrItinClass itin, string opc, 669 string asm, string cstr, list<dag> pattern> 670 : I<oops, iops, AddrMode3, 4, im, f, itin, 671 opc, asm, cstr, pattern> { 672 bits<4> Rt; 673 let Inst{27-25} = 0b000; 674 let Inst{24} = isPre; // P bit 675 let Inst{21} = isPre; // W bit 676 let Inst{20} = op20; // L bit 677 let Inst{15-12} = Rt; // Rt 678 let Inst{7-4} = op; 679} 680 681// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 682// but for now use this class for LDRSBT, LDRHT, LDSHT. 683class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops, 684 IndexMode im, Format f, InstrItinClass itin, string opc, 685 string asm, string cstr, list<dag> pattern> 686 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> { 687 // {13} 1 == imm8, 0 == Rm 688 // {12-9} Rn 689 // {8} isAdd 690 // {7-4} imm7_4/zero 691 // {3-0} imm3_0/Rm 692 bits<4> addr; 693 bits<4> Rt; 694 let Inst{27-25} = 0b000; 695 let Inst{24} = 0; // P bit 696 let Inst{21} = 1; 697 let Inst{20} = isLoad; // L bit 698 let Inst{19-16} = addr; // Rn 699 let Inst{15-12} = Rt; // Rt 700 let Inst{7-4} = op; 701} 702 703// stores 704class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 705 string opc, string asm, list<dag> pattern> 706 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 707 opc, asm, "", pattern> { 708 bits<14> addr; 709 bits<4> Rt; 710 let Inst{27-25} = 0b000; 711 let Inst{24} = 1; // P bit 712 let Inst{23} = addr{8}; // U bit 713 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 714 let Inst{21} = 0; // W bit 715 let Inst{20} = 0; // L bit 716 let Inst{19-16} = addr{12-9}; // Rn 717 let Inst{15-12} = Rt; // Rt 718 let Inst{11-8} = addr{7-4}; // imm7_4/zero 719 let Inst{7-4} = op; 720 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 721 let DecoderMethod = "DecodeAddrMode3Instruction"; 722} 723 724// addrmode4 instructions 725class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 726 string asm, string cstr, list<dag> pattern> 727 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> { 728 bits<4> p; 729 bits<16> regs; 730 bits<4> Rn; 731 let Inst{31-28} = p; 732 let Inst{27-25} = 0b100; 733 let Inst{22} = 0; // S bit 734 let Inst{19-16} = Rn; 735 let Inst{15-0} = regs; 736} 737 738// Unsigned multiply, multiply-accumulate instructions. 739class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 740 string opc, string asm, list<dag> pattern> 741 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 742 opc, asm, "", pattern> { 743 let Inst{7-4} = 0b1001; 744 let Inst{20} = 0; // S bit 745 let Inst{27-21} = opcod; 746} 747class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 748 string opc, string asm, list<dag> pattern> 749 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 750 opc, asm, "", pattern> { 751 let Inst{7-4} = 0b1001; 752 let Inst{27-21} = opcod; 753} 754 755// Most significant word multiply 756class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 757 InstrItinClass itin, string opc, string asm, list<dag> pattern> 758 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 759 opc, asm, "", pattern> { 760 bits<4> Rd; 761 bits<4> Rn; 762 bits<4> Rm; 763 let Inst{7-4} = opc7_4; 764 let Inst{20} = 1; 765 let Inst{27-21} = opcod; 766 let Inst{19-16} = Rd; 767 let Inst{11-8} = Rm; 768 let Inst{3-0} = Rn; 769} 770// MSW multiple w/ Ra operand 771class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 772 InstrItinClass itin, string opc, string asm, list<dag> pattern> 773 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 774 bits<4> Ra; 775 let Inst{15-12} = Ra; 776} 777 778// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 779class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 780 InstrItinClass itin, string opc, string asm, list<dag> pattern> 781 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 782 opc, asm, "", pattern> { 783 bits<4> Rn; 784 bits<4> Rm; 785 let Inst{4} = 0; 786 let Inst{7} = 1; 787 let Inst{20} = 0; 788 let Inst{27-21} = opcod; 789 let Inst{6-5} = bit6_5; 790 let Inst{11-8} = Rm; 791 let Inst{3-0} = Rn; 792} 793class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 794 InstrItinClass itin, string opc, string asm, list<dag> pattern> 795 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 796 bits<4> Rd; 797 let Inst{19-16} = Rd; 798} 799 800// AMulxyI with Ra operand 801class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 802 InstrItinClass itin, string opc, string asm, list<dag> pattern> 803 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 804 bits<4> Ra; 805 let Inst{15-12} = Ra; 806} 807// SMLAL* 808class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 809 InstrItinClass itin, string opc, string asm, list<dag> pattern> 810 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 811 bits<4> RdLo; 812 bits<4> RdHi; 813 let Inst{19-16} = RdHi; 814 let Inst{15-12} = RdLo; 815} 816 817// Extend instructions. 818class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 819 string opc, string asm, list<dag> pattern> 820 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin, 821 opc, asm, "", pattern> { 822 // All AExtI instructions have Rd and Rm register operands. 823 bits<4> Rd; 824 bits<4> Rm; 825 let Inst{15-12} = Rd; 826 let Inst{3-0} = Rm; 827 let Inst{7-4} = 0b0111; 828 let Inst{9-8} = 0b00; 829 let Inst{27-20} = opcod; 830 831 let Unpredictable{9-8} = 0b11; 832} 833 834// Misc Arithmetic instructions. 835class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 836 InstrItinClass itin, string opc, string asm, list<dag> pattern> 837 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 838 opc, asm, "", pattern> { 839 bits<4> Rd; 840 bits<4> Rm; 841 let Inst{27-20} = opcod; 842 let Inst{19-16} = 0b1111; 843 let Inst{15-12} = Rd; 844 let Inst{11-8} = 0b1111; 845 let Inst{7-4} = opc7_4; 846 let Inst{3-0} = Rm; 847} 848 849// Division instructions. 850class ADivA1I<bits<3> opcod, dag oops, dag iops, 851 InstrItinClass itin, string opc, string asm, list<dag> pattern> 852 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 853 opc, asm, "", pattern> { 854 bits<4> Rd; 855 bits<4> Rn; 856 bits<4> Rm; 857 let Inst{27-23} = 0b01110; 858 let Inst{22-20} = opcod; 859 let Inst{19-16} = Rd; 860 let Inst{15-12} = 0b1111; 861 let Inst{11-8} = Rm; 862 let Inst{7-4} = 0b0001; 863 let Inst{3-0} = Rn; 864} 865 866// PKH instructions 867def PKHLSLAsmOperand : ImmAsmOperand { 868 let Name = "PKHLSLImm"; 869 let ParserMethod = "parsePKHLSLImm"; 870} 871def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{ 872 let PrintMethod = "printPKHLSLShiftImm"; 873 let ParserMatchClass = PKHLSLAsmOperand; 874} 875def PKHASRAsmOperand : AsmOperandClass { 876 let Name = "PKHASRImm"; 877 let ParserMethod = "parsePKHASRImm"; 878} 879def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{ 880 let PrintMethod = "printPKHASRShiftImm"; 881 let ParserMatchClass = PKHASRAsmOperand; 882} 883 884class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 885 string opc, string asm, list<dag> pattern> 886 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 887 opc, asm, "", pattern> { 888 bits<4> Rd; 889 bits<4> Rn; 890 bits<4> Rm; 891 bits<5> sh; 892 let Inst{27-20} = opcod; 893 let Inst{19-16} = Rn; 894 let Inst{15-12} = Rd; 895 let Inst{11-7} = sh; 896 let Inst{6} = tb; 897 let Inst{5-4} = 0b01; 898 let Inst{3-0} = Rm; 899} 900 901//===----------------------------------------------------------------------===// 902 903// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 904class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 905 list<Predicate> Predicates = [IsARM]; 906} 907class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { 908 list<Predicate> Predicates = [IsARM, HasV5T]; 909} 910class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 911 list<Predicate> Predicates = [IsARM, HasV5TE]; 912} 913// ARMV5MOPat - Same as ARMV5TEPat with UseMulOps. 914class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> { 915 list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps]; 916} 917class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 918 list<Predicate> Predicates = [IsARM, HasV6]; 919} 920 921//===----------------------------------------------------------------------===// 922// Thumb Instruction Format Definitions. 923// 924 925class ThumbI<dag oops, dag iops, AddrMode am, int sz, 926 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 927 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 928 let OutOperandList = oops; 929 let InOperandList = iops; 930 let AsmString = asm; 931 let Pattern = pattern; 932 list<Predicate> Predicates = [IsThumb]; 933} 934 935// TI - Thumb instruction. 936class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 937 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 938 939// Two-address instructions 940class TIt<dag oops, dag iops, InstrItinClass itin, string asm, 941 list<dag> pattern> 942 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst", 943 pattern>; 944 945// tBL, tBX 32-bit instructions 946class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 947 dag oops, dag iops, InstrItinClass itin, string asm, 948 list<dag> pattern> 949 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>, 950 Encoding { 951 let Inst{31-27} = opcod1; 952 let Inst{15-14} = opcod2; 953 let Inst{12} = opcod3; 954} 955 956// BR_JT instructions 957class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 958 list<dag> pattern> 959 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 960 961// Thumb1 only 962class Thumb1I<dag oops, dag iops, AddrMode am, int sz, 963 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 964 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 965 let OutOperandList = oops; 966 let InOperandList = iops; 967 let AsmString = asm; 968 let Pattern = pattern; 969 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 970} 971 972class T1I<dag oops, dag iops, InstrItinClass itin, 973 string asm, list<dag> pattern> 974 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 975class T1Ix2<dag oops, dag iops, InstrItinClass itin, 976 string asm, list<dag> pattern> 977 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 978 979// Two-address instructions 980class T1It<dag oops, dag iops, InstrItinClass itin, 981 string asm, string cstr, list<dag> pattern> 982 : Thumb1I<oops, iops, AddrModeNone, 2, itin, 983 asm, cstr, pattern>; 984 985// Thumb1 instruction that can either be predicated or set CPSR. 986class Thumb1sI<dag oops, dag iops, AddrMode am, int sz, 987 InstrItinClass itin, 988 string opc, string asm, string cstr, list<dag> pattern> 989 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 990 let OutOperandList = !con(oops, (outs s_cc_out:$s)); 991 let InOperandList = !con(iops, (ins pred:$p)); 992 let AsmString = !strconcat(opc, "${s}${p}", asm); 993 let Pattern = pattern; 994 let thumbArithFlagSetting = 1; 995 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 996 let DecoderNamespace = "ThumbSBit"; 997} 998 999class T1sI<dag oops, dag iops, InstrItinClass itin, 1000 string opc, string asm, list<dag> pattern> 1001 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1002 1003// Two-address instructions 1004class T1sIt<dag oops, dag iops, InstrItinClass itin, 1005 string opc, string asm, list<dag> pattern> 1006 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1007 "$Rn = $Rdn", pattern>; 1008 1009// Thumb1 instruction that can be predicated. 1010class Thumb1pI<dag oops, dag iops, AddrMode am, int sz, 1011 InstrItinClass itin, 1012 string opc, string asm, string cstr, list<dag> pattern> 1013 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1014 let OutOperandList = oops; 1015 let InOperandList = !con(iops, (ins pred:$p)); 1016 let AsmString = !strconcat(opc, "${p}", asm); 1017 let Pattern = pattern; 1018 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1019} 1020 1021class T1pI<dag oops, dag iops, InstrItinClass itin, 1022 string opc, string asm, list<dag> pattern> 1023 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1024 1025// Two-address instructions 1026class T1pIt<dag oops, dag iops, InstrItinClass itin, 1027 string opc, string asm, list<dag> pattern> 1028 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1029 "$Rn = $Rdn", pattern>; 1030 1031class T1pIs<dag oops, dag iops, 1032 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1033 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>; 1034 1035class Encoding16 : Encoding { 1036 let Inst{31-16} = 0x0000; 1037} 1038 1039// A6.2 16-bit Thumb instruction encoding 1040class T1Encoding<bits<6> opcode> : Encoding16 { 1041 let Inst{15-10} = opcode; 1042} 1043 1044// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1045class T1General<bits<5> opcode> : Encoding16 { 1046 let Inst{15-14} = 0b00; 1047 let Inst{13-9} = opcode; 1048} 1049 1050// A6.2.2 Data-processing encoding. 1051class T1DataProcessing<bits<4> opcode> : Encoding16 { 1052 let Inst{15-10} = 0b010000; 1053 let Inst{9-6} = opcode; 1054} 1055 1056// A6.2.3 Special data instructions and branch and exchange encoding. 1057class T1Special<bits<4> opcode> : Encoding16 { 1058 let Inst{15-10} = 0b010001; 1059 let Inst{9-6} = opcode; 1060} 1061 1062// A6.2.4 Load/store single data item encoding. 1063class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1064 let Inst{15-12} = opA; 1065 let Inst{11-9} = opB; 1066} 1067class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1068 1069class T1BranchCond<bits<4> opcode> : Encoding16 { 1070 let Inst{15-12} = opcode; 1071} 1072 1073// Helper classes to encode Thumb1 loads and stores. For immediates, the 1074// following bits are used for "opA" (see A6.2.4): 1075// 1076// 0b0110 => Immediate, 4 bytes 1077// 0b1000 => Immediate, 2 bytes 1078// 0b0111 => Immediate, 1 byte 1079class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1080 InstrItinClass itin, string opc, string asm, 1081 list<dag> pattern> 1082 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1083 T1LoadStore<0b0101, opcode> { 1084 bits<3> Rt; 1085 bits<8> addr; 1086 let Inst{8-6} = addr{5-3}; // Rm 1087 let Inst{5-3} = addr{2-0}; // Rn 1088 let Inst{2-0} = Rt; 1089} 1090class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1091 InstrItinClass itin, string opc, string asm, 1092 list<dag> pattern> 1093 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1094 T1LoadStore<opA, {opB,?,?}> { 1095 bits<3> Rt; 1096 bits<8> addr; 1097 let Inst{10-6} = addr{7-3}; // imm5 1098 let Inst{5-3} = addr{2-0}; // Rn 1099 let Inst{2-0} = Rt; 1100} 1101 1102// A6.2.5 Miscellaneous 16-bit instructions encoding. 1103class T1Misc<bits<7> opcode> : Encoding16 { 1104 let Inst{15-12} = 0b1011; 1105 let Inst{11-5} = opcode; 1106} 1107 1108// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1109class Thumb2I<dag oops, dag iops, AddrMode am, int sz, 1110 InstrItinClass itin, 1111 string opc, string asm, string cstr, list<dag> pattern> 1112 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1113 let OutOperandList = oops; 1114 let InOperandList = !con(iops, (ins pred:$p)); 1115 let AsmString = !strconcat(opc, "${p}", asm); 1116 let Pattern = pattern; 1117 list<Predicate> Predicates = [IsThumb2]; 1118 let DecoderNamespace = "Thumb2"; 1119} 1120 1121// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1122// input operand since by default it's a zero register. It will become an 1123// implicit def once it's "flipped". 1124// 1125// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1126// more consistent. 1127class Thumb2sI<dag oops, dag iops, AddrMode am, int sz, 1128 InstrItinClass itin, 1129 string opc, string asm, string cstr, list<dag> pattern> 1130 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1131 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1132 let Inst{20} = s; 1133 1134 let OutOperandList = oops; 1135 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1136 let AsmString = !strconcat(opc, "${s}${p}", asm); 1137 let Pattern = pattern; 1138 list<Predicate> Predicates = [IsThumb2]; 1139 let DecoderNamespace = "Thumb2"; 1140} 1141 1142// Special cases 1143class Thumb2XI<dag oops, dag iops, AddrMode am, int sz, 1144 InstrItinClass itin, 1145 string asm, string cstr, list<dag> pattern> 1146 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1147 let OutOperandList = oops; 1148 let InOperandList = iops; 1149 let AsmString = asm; 1150 let Pattern = pattern; 1151 list<Predicate> Predicates = [IsThumb2]; 1152 let DecoderNamespace = "Thumb2"; 1153} 1154 1155class ThumbXI<dag oops, dag iops, AddrMode am, int sz, 1156 InstrItinClass itin, 1157 string asm, string cstr, list<dag> pattern> 1158 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1159 let OutOperandList = oops; 1160 let InOperandList = iops; 1161 let AsmString = asm; 1162 let Pattern = pattern; 1163 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1164 let DecoderNamespace = "Thumb"; 1165} 1166 1167class T2I<dag oops, dag iops, InstrItinClass itin, 1168 string opc, string asm, list<dag> pattern> 1169 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1170class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1171 string opc, string asm, list<dag> pattern> 1172 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>; 1173class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1174 string opc, string asm, list<dag> pattern> 1175 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>; 1176class T2Iso<dag oops, dag iops, InstrItinClass itin, 1177 string opc, string asm, list<dag> pattern> 1178 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>; 1179class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1180 string opc, string asm, list<dag> pattern> 1181 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>; 1182class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1183 string opc, string asm, string cstr, list<dag> pattern> 1184 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1185 pattern> { 1186 bits<4> Rt; 1187 bits<4> Rt2; 1188 bits<13> addr; 1189 let Inst{31-25} = 0b1110100; 1190 let Inst{24} = P; 1191 let Inst{23} = addr{8}; 1192 let Inst{22} = 1; 1193 let Inst{21} = W; 1194 let Inst{20} = isLoad; 1195 let Inst{19-16} = addr{12-9}; 1196 let Inst{15-12} = Rt{3-0}; 1197 let Inst{11-8} = Rt2{3-0}; 1198 let Inst{7-0} = addr{7-0}; 1199} 1200class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops, 1201 InstrItinClass itin, string opc, string asm, string cstr, 1202 list<dag> pattern> 1203 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1204 pattern> { 1205 bits<4> Rt; 1206 bits<4> Rt2; 1207 bits<4> addr; 1208 bits<9> imm; 1209 let Inst{31-25} = 0b1110100; 1210 let Inst{24} = P; 1211 let Inst{23} = imm{8}; 1212 let Inst{22} = 1; 1213 let Inst{21} = W; 1214 let Inst{20} = isLoad; 1215 let Inst{19-16} = addr; 1216 let Inst{15-12} = Rt{3-0}; 1217 let Inst{11-8} = Rt2{3-0}; 1218 let Inst{7-0} = imm{7-0}; 1219} 1220 1221class T2sI<dag oops, dag iops, InstrItinClass itin, 1222 string opc, string asm, list<dag> pattern> 1223 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1224 1225class T2XI<dag oops, dag iops, InstrItinClass itin, 1226 string asm, list<dag> pattern> 1227 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1228class T2JTI<dag oops, dag iops, InstrItinClass itin, 1229 string asm, list<dag> pattern> 1230 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1231 1232// Move to/from coprocessor instructions 1233class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern> 1234 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> { 1235 let Inst{31-28} = opc; 1236} 1237 1238// Two-address instructions 1239class T2XIt<dag oops, dag iops, InstrItinClass itin, 1240 string asm, string cstr, list<dag> pattern> 1241 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>; 1242 1243// T2Ipreldst - Thumb2 pre-indexed load / store instructions. 1244class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre, 1245 dag oops, dag iops, 1246 AddrMode am, IndexMode im, InstrItinClass itin, 1247 string opc, string asm, string cstr, list<dag> pattern> 1248 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1249 let OutOperandList = oops; 1250 let InOperandList = !con(iops, (ins pred:$p)); 1251 let AsmString = !strconcat(opc, "${p}", asm); 1252 let Pattern = pattern; 1253 list<Predicate> Predicates = [IsThumb2]; 1254 let DecoderNamespace = "Thumb2"; 1255 1256 bits<4> Rt; 1257 bits<13> addr; 1258 let Inst{31-27} = 0b11111; 1259 let Inst{26-25} = 0b00; 1260 let Inst{24} = signed; 1261 let Inst{23} = 0; 1262 let Inst{22-21} = opcod; 1263 let Inst{20} = load; 1264 let Inst{19-16} = addr{12-9}; 1265 let Inst{15-12} = Rt{3-0}; 1266 let Inst{11} = 1; 1267 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1268 let Inst{10} = pre; // The P bit. 1269 let Inst{9} = addr{8}; // Sign bit 1270 let Inst{8} = 1; // The W bit. 1271 let Inst{7-0} = addr{7-0}; 1272 1273 let DecoderMethod = "DecodeT2LdStPre"; 1274} 1275 1276// T2Ipostldst - Thumb2 post-indexed load / store instructions. 1277class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre, 1278 dag oops, dag iops, 1279 AddrMode am, IndexMode im, InstrItinClass itin, 1280 string opc, string asm, string cstr, list<dag> pattern> 1281 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1282 let OutOperandList = oops; 1283 let InOperandList = !con(iops, (ins pred:$p)); 1284 let AsmString = !strconcat(opc, "${p}", asm); 1285 let Pattern = pattern; 1286 list<Predicate> Predicates = [IsThumb2]; 1287 let DecoderNamespace = "Thumb2"; 1288 1289 bits<4> Rt; 1290 bits<4> Rn; 1291 bits<9> offset; 1292 let Inst{31-27} = 0b11111; 1293 let Inst{26-25} = 0b00; 1294 let Inst{24} = signed; 1295 let Inst{23} = 0; 1296 let Inst{22-21} = opcod; 1297 let Inst{20} = load; 1298 let Inst{19-16} = Rn; 1299 let Inst{15-12} = Rt{3-0}; 1300 let Inst{11} = 1; 1301 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1302 let Inst{10} = pre; // The P bit. 1303 let Inst{9} = offset{8}; // Sign bit 1304 let Inst{8} = 1; // The W bit. 1305 let Inst{7-0} = offset{7-0}; 1306 1307 let DecoderMethod = "DecodeT2LdStPre"; 1308} 1309 1310// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1311class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1312 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1313} 1314 1315// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1316class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1317 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1318} 1319 1320// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. 1321class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { 1322 list<Predicate> Predicates = [IsThumb2, HasV6T2]; 1323} 1324 1325// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1326class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1327 list<Predicate> Predicates = [IsThumb2]; 1328} 1329 1330//===----------------------------------------------------------------------===// 1331 1332//===----------------------------------------------------------------------===// 1333// ARM VFP Instruction templates. 1334// 1335 1336// Almost all VFP instructions are predicable. 1337class VFPI<dag oops, dag iops, AddrMode am, int sz, 1338 IndexMode im, Format f, InstrItinClass itin, 1339 string opc, string asm, string cstr, list<dag> pattern> 1340 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1341 bits<4> p; 1342 let Inst{31-28} = p; 1343 let OutOperandList = oops; 1344 let InOperandList = !con(iops, (ins pred:$p)); 1345 let AsmString = !strconcat(opc, "${p}", asm); 1346 let Pattern = pattern; 1347 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1348 let DecoderNamespace = "VFP"; 1349 list<Predicate> Predicates = [HasVFP2]; 1350} 1351 1352// Special cases 1353class VFPXI<dag oops, dag iops, AddrMode am, int sz, 1354 IndexMode im, Format f, InstrItinClass itin, 1355 string asm, string cstr, list<dag> pattern> 1356 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1357 bits<4> p; 1358 let Inst{31-28} = p; 1359 let OutOperandList = oops; 1360 let InOperandList = iops; 1361 let AsmString = asm; 1362 let Pattern = pattern; 1363 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1364 let DecoderNamespace = "VFP"; 1365 list<Predicate> Predicates = [HasVFP2]; 1366} 1367 1368class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1369 string opc, string asm, list<dag> pattern> 1370 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 1371 opc, asm, "", pattern> { 1372 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1373} 1374 1375// ARM VFP addrmode5 loads and stores 1376class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1377 InstrItinClass itin, 1378 string opc, string asm, list<dag> pattern> 1379 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1380 VFPLdStFrm, itin, opc, asm, "", pattern> { 1381 // Instruction operands. 1382 bits<5> Dd; 1383 bits<13> addr; 1384 1385 // Encode instruction operands. 1386 let Inst{23} = addr{8}; // U (add = (U == '1')) 1387 let Inst{22} = Dd{4}; 1388 let Inst{19-16} = addr{12-9}; // Rn 1389 let Inst{15-12} = Dd{3-0}; 1390 let Inst{7-0} = addr{7-0}; // imm8 1391 1392 // TODO: Mark the instructions with the appropriate subtarget info. 1393 let Inst{27-24} = opcod1; 1394 let Inst{21-20} = opcod2; 1395 let Inst{11-9} = 0b101; 1396 let Inst{8} = 1; // Double precision 1397 1398 // Loads & stores operate on both NEON and VFP pipelines. 1399 let D = VFPNeonDomain; 1400} 1401 1402class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1403 InstrItinClass itin, 1404 string opc, string asm, list<dag> pattern> 1405 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1406 VFPLdStFrm, itin, opc, asm, "", pattern> { 1407 // Instruction operands. 1408 bits<5> Sd; 1409 bits<13> addr; 1410 1411 // Encode instruction operands. 1412 let Inst{23} = addr{8}; // U (add = (U == '1')) 1413 let Inst{22} = Sd{0}; 1414 let Inst{19-16} = addr{12-9}; // Rn 1415 let Inst{15-12} = Sd{4-1}; 1416 let Inst{7-0} = addr{7-0}; // imm8 1417 1418 // TODO: Mark the instructions with the appropriate subtarget info. 1419 let Inst{27-24} = opcod1; 1420 let Inst{21-20} = opcod2; 1421 let Inst{11-9} = 0b101; 1422 let Inst{8} = 0; // Single precision 1423 1424 // Loads & stores operate on both NEON and VFP pipelines. 1425 let D = VFPNeonDomain; 1426} 1427 1428// VFP Load / store multiple pseudo instructions. 1429class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1430 list<dag> pattern> 1431 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain, 1432 cstr, itin> { 1433 let OutOperandList = oops; 1434 let InOperandList = !con(iops, (ins pred:$p)); 1435 let Pattern = pattern; 1436 list<Predicate> Predicates = [HasVFP2]; 1437} 1438 1439// Load / store multiple 1440class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1441 string asm, string cstr, list<dag> pattern> 1442 : VFPXI<oops, iops, AddrMode4, 4, im, 1443 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1444 // Instruction operands. 1445 bits<4> Rn; 1446 bits<13> regs; 1447 1448 // Encode instruction operands. 1449 let Inst{19-16} = Rn; 1450 let Inst{22} = regs{12}; 1451 let Inst{15-12} = regs{11-8}; 1452 let Inst{7-0} = regs{7-0}; 1453 1454 // TODO: Mark the instructions with the appropriate subtarget info. 1455 let Inst{27-25} = 0b110; 1456 let Inst{11-9} = 0b101; 1457 let Inst{8} = 1; // Double precision 1458} 1459 1460class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1461 string asm, string cstr, list<dag> pattern> 1462 : VFPXI<oops, iops, AddrMode4, 4, im, 1463 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1464 // Instruction operands. 1465 bits<4> Rn; 1466 bits<13> regs; 1467 1468 // Encode instruction operands. 1469 let Inst{19-16} = Rn; 1470 let Inst{22} = regs{8}; 1471 let Inst{15-12} = regs{12-9}; 1472 let Inst{7-0} = regs{7-0}; 1473 1474 // TODO: Mark the instructions with the appropriate subtarget info. 1475 let Inst{27-25} = 0b110; 1476 let Inst{11-9} = 0b101; 1477 let Inst{8} = 0; // Single precision 1478} 1479 1480// Double precision, unary 1481class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1482 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1483 string asm, list<dag> pattern> 1484 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1485 // Instruction operands. 1486 bits<5> Dd; 1487 bits<5> Dm; 1488 1489 // Encode instruction operands. 1490 let Inst{3-0} = Dm{3-0}; 1491 let Inst{5} = Dm{4}; 1492 let Inst{15-12} = Dd{3-0}; 1493 let Inst{22} = Dd{4}; 1494 1495 let Inst{27-23} = opcod1; 1496 let Inst{21-20} = opcod2; 1497 let Inst{19-16} = opcod3; 1498 let Inst{11-9} = 0b101; 1499 let Inst{8} = 1; // Double precision 1500 let Inst{7-6} = opcod4; 1501 let Inst{4} = opcod5; 1502} 1503 1504// Double precision, binary 1505class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1506 dag iops, InstrItinClass itin, string opc, string asm, 1507 list<dag> pattern> 1508 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1509 // Instruction operands. 1510 bits<5> Dd; 1511 bits<5> Dn; 1512 bits<5> Dm; 1513 1514 // Encode instruction operands. 1515 let Inst{3-0} = Dm{3-0}; 1516 let Inst{5} = Dm{4}; 1517 let Inst{19-16} = Dn{3-0}; 1518 let Inst{7} = Dn{4}; 1519 let Inst{15-12} = Dd{3-0}; 1520 let Inst{22} = Dd{4}; 1521 1522 let Inst{27-23} = opcod1; 1523 let Inst{21-20} = opcod2; 1524 let Inst{11-9} = 0b101; 1525 let Inst{8} = 1; // Double precision 1526 let Inst{6} = op6; 1527 let Inst{4} = op4; 1528} 1529 1530// Single precision, unary 1531class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1532 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1533 string asm, list<dag> pattern> 1534 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1535 // Instruction operands. 1536 bits<5> Sd; 1537 bits<5> Sm; 1538 1539 // Encode instruction operands. 1540 let Inst{3-0} = Sm{4-1}; 1541 let Inst{5} = Sm{0}; 1542 let Inst{15-12} = Sd{4-1}; 1543 let Inst{22} = Sd{0}; 1544 1545 let Inst{27-23} = opcod1; 1546 let Inst{21-20} = opcod2; 1547 let Inst{19-16} = opcod3; 1548 let Inst{11-9} = 0b101; 1549 let Inst{8} = 0; // Single precision 1550 let Inst{7-6} = opcod4; 1551 let Inst{4} = opcod5; 1552} 1553 1554// Single precision unary, if no NEON. Same as ASuI except not available if 1555// NEON is enabled. 1556class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1557 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1558 string asm, list<dag> pattern> 1559 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1560 pattern> { 1561 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1562} 1563 1564// Single precision, binary 1565class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1566 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1567 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1568 // Instruction operands. 1569 bits<5> Sd; 1570 bits<5> Sn; 1571 bits<5> Sm; 1572 1573 // Encode instruction operands. 1574 let Inst{3-0} = Sm{4-1}; 1575 let Inst{5} = Sm{0}; 1576 let Inst{19-16} = Sn{4-1}; 1577 let Inst{7} = Sn{0}; 1578 let Inst{15-12} = Sd{4-1}; 1579 let Inst{22} = Sd{0}; 1580 1581 let Inst{27-23} = opcod1; 1582 let Inst{21-20} = opcod2; 1583 let Inst{11-9} = 0b101; 1584 let Inst{8} = 0; // Single precision 1585 let Inst{6} = op6; 1586 let Inst{4} = op4; 1587} 1588 1589// Single precision binary, if no NEON. Same as ASbI except not available if 1590// NEON is enabled. 1591class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1592 dag iops, InstrItinClass itin, string opc, string asm, 1593 list<dag> pattern> 1594 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1595 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1596 1597 // Instruction operands. 1598 bits<5> Sd; 1599 bits<5> Sn; 1600 bits<5> Sm; 1601 1602 // Encode instruction operands. 1603 let Inst{3-0} = Sm{4-1}; 1604 let Inst{5} = Sm{0}; 1605 let Inst{19-16} = Sn{4-1}; 1606 let Inst{7} = Sn{0}; 1607 let Inst{15-12} = Sd{4-1}; 1608 let Inst{22} = Sd{0}; 1609} 1610 1611// VFP conversion instructions 1612class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1613 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1614 list<dag> pattern> 1615 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1616 let Inst{27-23} = opcod1; 1617 let Inst{21-20} = opcod2; 1618 let Inst{19-16} = opcod3; 1619 let Inst{11-8} = opcod4; 1620 let Inst{6} = 1; 1621 let Inst{4} = 0; 1622} 1623 1624// VFP conversion between floating-point and fixed-point 1625class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1626 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1627 list<dag> pattern> 1628 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1629 bits<5> fbits; 1630 // size (fixed-point number): sx == 0 ? 16 : 32 1631 let Inst{7} = op5; // sx 1632 let Inst{5} = fbits{0}; 1633 let Inst{3-0} = fbits{4-1}; 1634} 1635 1636// VFP conversion instructions, if no NEON 1637class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1638 dag oops, dag iops, InstrItinClass itin, 1639 string opc, string asm, list<dag> pattern> 1640 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1641 pattern> { 1642 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1643} 1644 1645class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1646 InstrItinClass itin, 1647 string opc, string asm, list<dag> pattern> 1648 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1649 let Inst{27-20} = opcod1; 1650 let Inst{11-8} = opcod2; 1651 let Inst{4} = 1; 1652} 1653 1654class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1655 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1656 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1657 1658class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1659 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1660 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1661 1662class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1663 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1664 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1665 1666class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1667 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1668 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1669 1670//===----------------------------------------------------------------------===// 1671 1672//===----------------------------------------------------------------------===// 1673// ARM NEON Instruction templates. 1674// 1675 1676class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1677 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1678 list<dag> pattern> 1679 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1680 let OutOperandList = oops; 1681 let InOperandList = !con(iops, (ins pred:$p)); 1682 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1683 let Pattern = pattern; 1684 list<Predicate> Predicates = [HasNEON]; 1685 let DecoderNamespace = "NEON"; 1686} 1687 1688// Same as NeonI except it does not have a "data type" specifier. 1689class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1690 InstrItinClass itin, string opc, string asm, string cstr, 1691 list<dag> pattern> 1692 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1693 let OutOperandList = oops; 1694 let InOperandList = !con(iops, (ins pred:$p)); 1695 let AsmString = !strconcat(opc, "${p}", "\t", asm); 1696 let Pattern = pattern; 1697 list<Predicate> Predicates = [HasNEON]; 1698 let DecoderNamespace = "NEON"; 1699} 1700 1701class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1702 dag oops, dag iops, InstrItinClass itin, 1703 string opc, string dt, string asm, string cstr, list<dag> pattern> 1704 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1705 cstr, pattern> { 1706 let Inst{31-24} = 0b11110100; 1707 let Inst{23} = op23; 1708 let Inst{21-20} = op21_20; 1709 let Inst{11-8} = op11_8; 1710 let Inst{7-4} = op7_4; 1711 1712 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1713 let DecoderNamespace = "NEONLoadStore"; 1714 1715 bits<5> Vd; 1716 bits<6> Rn; 1717 bits<4> Rm; 1718 1719 let Inst{22} = Vd{4}; 1720 let Inst{15-12} = Vd{3-0}; 1721 let Inst{19-16} = Rn{3-0}; 1722 let Inst{3-0} = Rm{3-0}; 1723} 1724 1725class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1726 dag oops, dag iops, InstrItinClass itin, 1727 string opc, string dt, string asm, string cstr, list<dag> pattern> 1728 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1729 dt, asm, cstr, pattern> { 1730 bits<3> lane; 1731} 1732 1733class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1734 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1735 itin> { 1736 let OutOperandList = oops; 1737 let InOperandList = !con(iops, (ins pred:$p)); 1738 list<Predicate> Predicates = [HasNEON]; 1739} 1740 1741class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1742 list<dag> pattern> 1743 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1744 itin> { 1745 let OutOperandList = oops; 1746 let InOperandList = !con(iops, (ins pred:$p)); 1747 let Pattern = pattern; 1748 list<Predicate> Predicates = [HasNEON]; 1749} 1750 1751class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1752 string opc, string dt, string asm, string cstr, list<dag> pattern> 1753 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1754 pattern> { 1755 let Inst{31-25} = 0b1111001; 1756 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1757 let DecoderNamespace = "NEONData"; 1758} 1759 1760class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1761 string opc, string asm, string cstr, list<dag> pattern> 1762 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1763 cstr, pattern> { 1764 let Inst{31-25} = 0b1111001; 1765 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1766 let DecoderNamespace = "NEONData"; 1767} 1768 1769// NEON "one register and a modified immediate" format. 1770class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1771 bit op5, bit op4, 1772 dag oops, dag iops, InstrItinClass itin, 1773 string opc, string dt, string asm, string cstr, 1774 list<dag> pattern> 1775 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1776 let Inst{23} = op23; 1777 let Inst{21-19} = op21_19; 1778 let Inst{11-8} = op11_8; 1779 let Inst{7} = op7; 1780 let Inst{6} = op6; 1781 let Inst{5} = op5; 1782 let Inst{4} = op4; 1783 1784 // Instruction operands. 1785 bits<5> Vd; 1786 bits<13> SIMM; 1787 1788 let Inst{15-12} = Vd{3-0}; 1789 let Inst{22} = Vd{4}; 1790 let Inst{24} = SIMM{7}; 1791 let Inst{18-16} = SIMM{6-4}; 1792 let Inst{3-0} = SIMM{3-0}; 1793 let DecoderMethod = "DecodeNEONModImmInstruction"; 1794} 1795 1796// NEON 2 vector register format. 1797class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1798 bits<5> op11_7, bit op6, bit op4, 1799 dag oops, dag iops, InstrItinClass itin, 1800 string opc, string dt, string asm, string cstr, list<dag> pattern> 1801 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1802 let Inst{24-23} = op24_23; 1803 let Inst{21-20} = op21_20; 1804 let Inst{19-18} = op19_18; 1805 let Inst{17-16} = op17_16; 1806 let Inst{11-7} = op11_7; 1807 let Inst{6} = op6; 1808 let Inst{4} = op4; 1809 1810 // Instruction operands. 1811 bits<5> Vd; 1812 bits<5> Vm; 1813 1814 let Inst{15-12} = Vd{3-0}; 1815 let Inst{22} = Vd{4}; 1816 let Inst{3-0} = Vm{3-0}; 1817 let Inst{5} = Vm{4}; 1818} 1819 1820// Same as N2V except it doesn't have a datatype suffix. 1821class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1822 bits<5> op11_7, bit op6, bit op4, 1823 dag oops, dag iops, InstrItinClass itin, 1824 string opc, string asm, string cstr, list<dag> pattern> 1825 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1826 let Inst{24-23} = op24_23; 1827 let Inst{21-20} = op21_20; 1828 let Inst{19-18} = op19_18; 1829 let Inst{17-16} = op17_16; 1830 let Inst{11-7} = op11_7; 1831 let Inst{6} = op6; 1832 let Inst{4} = op4; 1833 1834 // Instruction operands. 1835 bits<5> Vd; 1836 bits<5> Vm; 1837 1838 let Inst{15-12} = Vd{3-0}; 1839 let Inst{22} = Vd{4}; 1840 let Inst{3-0} = Vm{3-0}; 1841 let Inst{5} = Vm{4}; 1842} 1843 1844// NEON 2 vector register with immediate. 1845class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1846 dag oops, dag iops, Format f, InstrItinClass itin, 1847 string opc, string dt, string asm, string cstr, list<dag> pattern> 1848 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1849 let Inst{24} = op24; 1850 let Inst{23} = op23; 1851 let Inst{11-8} = op11_8; 1852 let Inst{7} = op7; 1853 let Inst{6} = op6; 1854 let Inst{4} = op4; 1855 1856 // Instruction operands. 1857 bits<5> Vd; 1858 bits<5> Vm; 1859 bits<6> SIMM; 1860 1861 let Inst{15-12} = Vd{3-0}; 1862 let Inst{22} = Vd{4}; 1863 let Inst{3-0} = Vm{3-0}; 1864 let Inst{5} = Vm{4}; 1865 let Inst{21-16} = SIMM{5-0}; 1866} 1867 1868// NEON 3 vector register format. 1869 1870class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1871 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1872 string opc, string dt, string asm, string cstr, 1873 list<dag> pattern> 1874 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1875 let Inst{24} = op24; 1876 let Inst{23} = op23; 1877 let Inst{21-20} = op21_20; 1878 let Inst{11-8} = op11_8; 1879 let Inst{6} = op6; 1880 let Inst{4} = op4; 1881} 1882 1883class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1884 dag oops, dag iops, Format f, InstrItinClass itin, 1885 string opc, string dt, string asm, string cstr, list<dag> pattern> 1886 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1887 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1888 // Instruction operands. 1889 bits<5> Vd; 1890 bits<5> Vn; 1891 bits<5> Vm; 1892 1893 let Inst{15-12} = Vd{3-0}; 1894 let Inst{22} = Vd{4}; 1895 let Inst{19-16} = Vn{3-0}; 1896 let Inst{7} = Vn{4}; 1897 let Inst{3-0} = Vm{3-0}; 1898 let Inst{5} = Vm{4}; 1899} 1900 1901class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1902 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1903 string opc, string dt, string asm, string cstr, 1904 list<dag> pattern> 1905 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1906 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1907 1908 // Instruction operands. 1909 bits<5> Vd; 1910 bits<5> Vn; 1911 bits<5> Vm; 1912 bit lane; 1913 1914 let Inst{15-12} = Vd{3-0}; 1915 let Inst{22} = Vd{4}; 1916 let Inst{19-16} = Vn{3-0}; 1917 let Inst{7} = Vn{4}; 1918 let Inst{3-0} = Vm{3-0}; 1919 let Inst{5} = lane; 1920} 1921 1922class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1923 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1924 string opc, string dt, string asm, string cstr, 1925 list<dag> pattern> 1926 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1927 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1928 1929 // Instruction operands. 1930 bits<5> Vd; 1931 bits<5> Vn; 1932 bits<5> Vm; 1933 bits<2> lane; 1934 1935 let Inst{15-12} = Vd{3-0}; 1936 let Inst{22} = Vd{4}; 1937 let Inst{19-16} = Vn{3-0}; 1938 let Inst{7} = Vn{4}; 1939 let Inst{2-0} = Vm{2-0}; 1940 let Inst{5} = lane{1}; 1941 let Inst{3} = lane{0}; 1942} 1943 1944// Same as N3V except it doesn't have a data type suffix. 1945class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1946 bit op4, 1947 dag oops, dag iops, Format f, InstrItinClass itin, 1948 string opc, string asm, string cstr, list<dag> pattern> 1949 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1950 let Inst{24} = op24; 1951 let Inst{23} = op23; 1952 let Inst{21-20} = op21_20; 1953 let Inst{11-8} = op11_8; 1954 let Inst{6} = op6; 1955 let Inst{4} = op4; 1956 1957 // Instruction operands. 1958 bits<5> Vd; 1959 bits<5> Vn; 1960 bits<5> Vm; 1961 1962 let Inst{15-12} = Vd{3-0}; 1963 let Inst{22} = Vd{4}; 1964 let Inst{19-16} = Vn{3-0}; 1965 let Inst{7} = Vn{4}; 1966 let Inst{3-0} = Vm{3-0}; 1967 let Inst{5} = Vm{4}; 1968} 1969 1970// NEON VMOVs between scalar and core registers. 1971class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1972 dag oops, dag iops, Format f, InstrItinClass itin, 1973 string opc, string dt, string asm, list<dag> pattern> 1974 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain, 1975 "", itin> { 1976 let Inst{27-20} = opcod1; 1977 let Inst{11-8} = opcod2; 1978 let Inst{6-5} = opcod3; 1979 let Inst{4} = 1; 1980 // A8.6.303, A8.6.328, A8.6.329 1981 let Inst{3-0} = 0b0000; 1982 1983 let OutOperandList = oops; 1984 let InOperandList = !con(iops, (ins pred:$p)); 1985 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1986 let Pattern = pattern; 1987 list<Predicate> Predicates = [HasNEON]; 1988 1989 let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1990 let DecoderNamespace = "NEONDup"; 1991 1992 bits<5> V; 1993 bits<4> R; 1994 bits<4> p; 1995 bits<4> lane; 1996 1997 let Inst{31-28} = p{3-0}; 1998 let Inst{7} = V{4}; 1999 let Inst{19-16} = V{3-0}; 2000 let Inst{15-12} = R{3-0}; 2001} 2002class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2003 dag oops, dag iops, InstrItinClass itin, 2004 string opc, string dt, string asm, list<dag> pattern> 2005 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 2006 opc, dt, asm, pattern>; 2007class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2008 dag oops, dag iops, InstrItinClass itin, 2009 string opc, string dt, string asm, list<dag> pattern> 2010 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 2011 opc, dt, asm, pattern>; 2012class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2013 dag oops, dag iops, InstrItinClass itin, 2014 string opc, string dt, string asm, list<dag> pattern> 2015 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 2016 opc, dt, asm, pattern>; 2017 2018// Vector Duplicate Lane (from scalar to all elements) 2019class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 2020 InstrItinClass itin, string opc, string dt, string asm, 2021 list<dag> pattern> 2022 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 2023 let Inst{24-23} = 0b11; 2024 let Inst{21-20} = 0b11; 2025 let Inst{19-16} = op19_16; 2026 let Inst{11-7} = 0b11000; 2027 let Inst{6} = op6; 2028 let Inst{4} = 0; 2029 2030 bits<5> Vd; 2031 bits<5> Vm; 2032 2033 let Inst{22} = Vd{4}; 2034 let Inst{15-12} = Vd{3-0}; 2035 let Inst{5} = Vm{4}; 2036 let Inst{3-0} = Vm{3-0}; 2037} 2038 2039// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 2040// for single-precision FP. 2041class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 2042 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 2043} 2044 2045// VFP/NEON Instruction aliases for type suffices. 2046class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> : 2047 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>; 2048 2049multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> { 2050 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2051 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2052 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2053 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2054} 2055 2056multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result> { 2057 let Predicates = [HasNEON] in { 2058 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2059 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2060 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2061 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2062} 2063} 2064 2065// The same alias classes using AsmPseudo instead, for the more complex 2066// stuff in NEON that InstAlias can't quite handle. 2067// Note that we can't use anonymous defm references here like we can 2068// above, as we care about the ultimate instruction enum names generated, unlike 2069// for instalias defs. 2070class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> : 2071 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>; 2072 2073// Data type suffix token aliases. Implements Table A7-3 in the ARM ARM. 2074def : TokenAlias<".s8", ".i8">; 2075def : TokenAlias<".u8", ".i8">; 2076def : TokenAlias<".s16", ".i16">; 2077def : TokenAlias<".u16", ".i16">; 2078def : TokenAlias<".s32", ".i32">; 2079def : TokenAlias<".u32", ".i32">; 2080def : TokenAlias<".s64", ".i64">; 2081def : TokenAlias<".u64", ".i64">; 2082 2083def : TokenAlias<".i8", ".8">; 2084def : TokenAlias<".i16", ".16">; 2085def : TokenAlias<".i32", ".32">; 2086def : TokenAlias<".i64", ".64">; 2087 2088def : TokenAlias<".p8", ".8">; 2089def : TokenAlias<".p16", ".16">; 2090 2091def : TokenAlias<".f32", ".32">; 2092def : TokenAlias<".f64", ".64">; 2093def : TokenAlias<".f", ".f32">; 2094def : TokenAlias<".d", ".f64">; 2095