ARMInstrFormats.td revision 223017
1218893Sdim//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=// 2206083Srdivacky// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7206083Srdivacky// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// 12193323Sed// ARM Instruction Format Definitions. 13193323Sed// 14193323Sed 15193323Sed// Format specifies the encoding used by the instruction. This is part of the 16193323Sed// ad-hoc solution used to emit machine instruction encodings by our machine 17193323Sed// code emitter. 18205407Srdivackyclass Format<bits<6> val> { 19205407Srdivacky bits<6> Value = val; 20193323Sed} 21193323Sed 22193323Seddef Pseudo : Format<0>; 23193323Seddef MulFrm : Format<1>; 24193323Seddef BrFrm : Format<2>; 25193323Seddef BrMiscFrm : Format<3>; 26193323Sed 27193323Seddef DPFrm : Format<4>; 28193323Seddef DPSoRegFrm : Format<5>; 29193323Sed 30193323Seddef LdFrm : Format<6>; 31193323Seddef StFrm : Format<7>; 32193323Seddef LdMiscFrm : Format<8>; 33193323Seddef StMiscFrm : Format<9>; 34193323Seddef LdStMulFrm : Format<10>; 35193323Sed 36205407Srdivackydef LdStExFrm : Format<11>; 37200581Srdivacky 38205407Srdivackydef ArithMiscFrm : Format<12>; 39212904Sdimdef SatFrm : Format<13>; 40212904Sdimdef ExtFrm : Format<14>; 41193323Sed 42212904Sdimdef VFPUnaryFrm : Format<15>; 43212904Sdimdef VFPBinaryFrm : Format<16>; 44212904Sdimdef VFPConv1Frm : Format<17>; 45212904Sdimdef VFPConv2Frm : Format<18>; 46212904Sdimdef VFPConv3Frm : Format<19>; 47212904Sdimdef VFPConv4Frm : Format<20>; 48212904Sdimdef VFPConv5Frm : Format<21>; 49212904Sdimdef VFPLdStFrm : Format<22>; 50212904Sdimdef VFPLdStMulFrm : Format<23>; 51212904Sdimdef VFPMiscFrm : Format<24>; 52193323Sed 53212904Sdimdef ThumbFrm : Format<25>; 54212904Sdimdef MiscFrm : Format<26>; 55193323Sed 56212904Sdimdef NGetLnFrm : Format<27>; 57212904Sdimdef NSetLnFrm : Format<28>; 58212904Sdimdef NDupFrm : Format<29>; 59212904Sdimdef NLdStFrm : Format<30>; 60212904Sdimdef N1RegModImmFrm: Format<31>; 61212904Sdimdef N2RegFrm : Format<32>; 62212904Sdimdef NVCVTFrm : Format<33>; 63212904Sdimdef NVDupLnFrm : Format<34>; 64212904Sdimdef N2RegVShLFrm : Format<35>; 65212904Sdimdef N2RegVShRFrm : Format<36>; 66212904Sdimdef N3RegFrm : Format<37>; 67212904Sdimdef N3RegVShFrm : Format<38>; 68212904Sdimdef NVExtFrm : Format<39>; 69212904Sdimdef NVMulSLFrm : Format<40>; 70212904Sdimdef NVTBLFrm : Format<41>; 71194710Sed 72198090Srdivacky// Misc flags. 73198090Srdivacky 74218893Sdim// The instruction has an Rn register operand. 75198090Srdivacky// UnaryDP - Indicates this is a unary data processing instruction, i.e. 76198090Srdivacky// it doesn't have a Rn operand. 77198090Srdivackyclass UnaryDP { bit isUnaryDataProc = 1; } 78193323Sed 79198090Srdivacky// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 80198090Srdivacky// a 16-bit Thumb instruction if certain conditions are met. 81198090Srdivackyclass Xform16Bit { bit canXformTo16Bit = 1; } 82198090Srdivacky 83193323Sed//===----------------------------------------------------------------------===// 84205407Srdivacky// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 85195340Sed// 86193323Sed 87218893Sdim// FIXME: Once the JIT is MC-ized, these can go away. 88195340Sed// Addressing mode. 89218893Sdimclass AddrMode<bits<5> val> { 90218893Sdim bits<5> Value = val; 91195340Sed} 92212904Sdimdef AddrModeNone : AddrMode<0>; 93212904Sdimdef AddrMode1 : AddrMode<1>; 94212904Sdimdef AddrMode2 : AddrMode<2>; 95212904Sdimdef AddrMode3 : AddrMode<3>; 96212904Sdimdef AddrMode4 : AddrMode<4>; 97212904Sdimdef AddrMode5 : AddrMode<5>; 98212904Sdimdef AddrMode6 : AddrMode<6>; 99212904Sdimdef AddrModeT1_1 : AddrMode<7>; 100212904Sdimdef AddrModeT1_2 : AddrMode<8>; 101212904Sdimdef AddrModeT1_4 : AddrMode<9>; 102212904Sdimdef AddrModeT1_s : AddrMode<10>; 103212904Sdimdef AddrModeT2_i12 : AddrMode<11>; 104212904Sdimdef AddrModeT2_i8 : AddrMode<12>; 105212904Sdimdef AddrModeT2_so : AddrMode<13>; 106212904Sdimdef AddrModeT2_pc : AddrMode<14>; 107195340Seddef AddrModeT2_i8s4 : AddrMode<15>; 108218893Sdimdef AddrMode_i12 : AddrMode<16>; 109195340Sed 110195340Sed// Instruction size. 111195340Sedclass SizeFlagVal<bits<3> val> { 112195340Sed bits<3> Value = val; 113195340Sed} 114195340Seddef SizeInvalid : SizeFlagVal<0>; // Unset. 115195340Seddef SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 116195340Seddef Size8Bytes : SizeFlagVal<2>; 117195340Seddef Size4Bytes : SizeFlagVal<3>; 118195340Seddef Size2Bytes : SizeFlagVal<4>; 119195340Sed 120195340Sed// Load / store index mode. 121195340Sedclass IndexMode<bits<2> val> { 122195340Sed bits<2> Value = val; 123195340Sed} 124195340Seddef IndexModeNone : IndexMode<0>; 125195340Seddef IndexModePre : IndexMode<1>; 126195340Seddef IndexModePost : IndexMode<2>; 127205218Srdivackydef IndexModeUpd : IndexMode<3>; 128195340Sed 129198892Srdivacky// Instruction execution domain. 130219077Sdimclass Domain<bits<3> val> { 131219077Sdim bits<3> Value = val; 132198892Srdivacky} 133198892Srdivackydef GenericDomain : Domain<0>; 134198892Srdivackydef VFPDomain : Domain<1>; // Instructions in VFP domain only 135198892Srdivackydef NeonDomain : Domain<2>; // Instructions in Neon domain only 136198892Srdivackydef VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 137219077Sdimdef VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 138198892Srdivacky 139195340Sed//===----------------------------------------------------------------------===// 140198090Srdivacky// ARM special operands. 141198090Srdivacky// 142198090Srdivacky 143212904Sdimdef CondCodeOperand : AsmOperandClass { 144212904Sdim let Name = "CondCode"; 145212904Sdim let SuperClasses = []; 146212904Sdim} 147212904Sdim 148218893Sdimdef CCOutOperand : AsmOperandClass { 149218893Sdim let Name = "CCOut"; 150218893Sdim let SuperClasses = []; 151218893Sdim} 152218893Sdim 153218893Sdimdef MemBarrierOptOperand : AsmOperandClass { 154218893Sdim let Name = "MemBarrierOpt"; 155218893Sdim let SuperClasses = []; 156218893Sdim let ParserMethod = "tryParseMemBarrierOptOperand"; 157218893Sdim} 158218893Sdim 159218893Sdimdef ProcIFlagsOperand : AsmOperandClass { 160218893Sdim let Name = "ProcIFlags"; 161218893Sdim let SuperClasses = []; 162218893Sdim let ParserMethod = "tryParseProcIFlagsOperand"; 163218893Sdim} 164218893Sdim 165218893Sdimdef MSRMaskOperand : AsmOperandClass { 166218893Sdim let Name = "MSRMask"; 167218893Sdim let SuperClasses = []; 168218893Sdim let ParserMethod = "tryParseMSRMaskOperand"; 169218893Sdim} 170218893Sdim 171218893Sdim// ARM imod and iflag operands, used only by the CPS instruction. 172218893Sdimdef imod_op : Operand<i32> { 173218893Sdim let PrintMethod = "printCPSIMod"; 174218893Sdim} 175218893Sdim 176218893Sdimdef iflags_op : Operand<i32> { 177218893Sdim let PrintMethod = "printCPSIFlag"; 178218893Sdim let ParserMatchClass = ProcIFlagsOperand; 179218893Sdim} 180218893Sdim 181198090Srdivacky// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 182198090Srdivacky// register whose default is 0 (no register). 183198090Srdivackydef pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 184198090Srdivacky (ops (i32 14), (i32 zero_reg))> { 185198090Srdivacky let PrintMethod = "printPredicateOperand"; 186212904Sdim let ParserMatchClass = CondCodeOperand; 187198090Srdivacky} 188198090Srdivacky 189198090Srdivacky// Conditional code result for instructions whose 's' bit is set, e.g. subs. 190198090Srdivackydef cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 191218893Sdim let EncoderMethod = "getCCOutOpValue"; 192198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 193218893Sdim let ParserMatchClass = CCOutOperand; 194198090Srdivacky} 195198090Srdivacky 196198090Srdivacky// Same as cc_out except it defaults to setting CPSR. 197198090Srdivackydef s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 198218893Sdim let EncoderMethod = "getCCOutOpValue"; 199198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 200218893Sdim let ParserMatchClass = CCOutOperand; 201198090Srdivacky} 202198090Srdivacky 203205218Srdivacky// ARM special operands for disassembly only. 204205218Srdivacky// 205218893Sdimdef setend_op : Operand<i32> { 206218893Sdim let PrintMethod = "printSetendOperand"; 207218893Sdim} 208205218Srdivacky 209205218Srdivackydef msr_mask : Operand<i32> { 210205218Srdivacky let PrintMethod = "printMSRMaskOperand"; 211218893Sdim let ParserMatchClass = MSRMaskOperand; 212205218Srdivacky} 213205218Srdivacky 214221345Sdim// Shift Right Immediate - A shift right immediate is encoded differently from 215221345Sdim// other shift immediates. The imm6 field is encoded like so: 216221345Sdim// 217221345Sdim// Offset Encoding 218221345Sdim// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 219221345Sdim// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 220221345Sdim// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 221221345Sdim// 64 64 - <imm> is encoded in imm6<5:0> 222221345Sdimdef shr_imm8 : Operand<i32> { 223221345Sdim let EncoderMethod = "getShiftRight8Imm"; 224205218Srdivacky} 225221345Sdimdef shr_imm16 : Operand<i32> { 226221345Sdim let EncoderMethod = "getShiftRight16Imm"; 227221345Sdim} 228221345Sdimdef shr_imm32 : Operand<i32> { 229221345Sdim let EncoderMethod = "getShiftRight32Imm"; 230221345Sdim} 231221345Sdimdef shr_imm64 : Operand<i32> { 232221345Sdim let EncoderMethod = "getShiftRight64Imm"; 233221345Sdim} 234205218Srdivacky 235198090Srdivacky//===----------------------------------------------------------------------===// 236193323Sed// ARM Instruction templates. 237193323Sed// 238193323Sed 239201360Srdivackyclass InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 240201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 241193323Sed : Instruction { 242193323Sed let Namespace = "ARM"; 243193323Sed 244193323Sed AddrMode AM = am; 245193323Sed SizeFlagVal SZ = sz; 246193323Sed IndexMode IM = im; 247193323Sed bits<2> IndexModeBits = IM.Value; 248193323Sed Format F = f; 249205407Srdivacky bits<6> Form = F.Value; 250198892Srdivacky Domain D = d; 251193323Sed bit isUnaryDataProc = 0; 252198090Srdivacky bit canXformTo16Bit = 0; 253206083Srdivacky 254218893Sdim // If this is a pseudo instruction, mark it isCodeGenOnly. 255218893Sdim let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 256218893Sdim 257206274Srdivacky // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. 258218893Sdim let TSFlags{4-0} = AM.Value; 259218893Sdim let TSFlags{7-5} = SZ.Value; 260218893Sdim let TSFlags{9-8} = IndexModeBits; 261218893Sdim let TSFlags{15-10} = Form; 262218893Sdim let TSFlags{16} = isUnaryDataProc; 263218893Sdim let TSFlags{17} = canXformTo16Bit; 264219077Sdim let TSFlags{20-18} = D.Value; 265206274Srdivacky 266193323Sed let Constraints = cstr; 267198090Srdivacky let Itinerary = itin; 268193323Sed} 269193323Sed 270201360Srdivackyclass Encoding { 271201360Srdivacky field bits<32> Inst; 272201360Srdivacky} 273201360Srdivacky 274201360Srdivackyclass InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 275201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 276201360Srdivacky : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 277201360Srdivacky 278201360Srdivacky// This Encoding-less class is used by Thumb1 to specify the encoding bits later 279201360Srdivacky// on by adding flavors to specific instructions. 280201360Srdivackyclass InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 281201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 282201360Srdivacky : InstTemplate<am, sz, im, f, d, cstr, itin>; 283201360Srdivacky 284218893Sdimclass PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 285218893Sdim // FIXME: This really should derive from InstTemplate instead, as pseudos 286218893Sdim // don't need encoding information. TableGen doesn't like that 287218893Sdim // currently. Need to figure out why and fix it. 288206083Srdivacky : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 289198892Srdivacky "", itin> { 290193323Sed let OutOperandList = oops; 291193323Sed let InOperandList = iops; 292193323Sed let Pattern = pattern; 293221345Sdim let isCodeGenOnly = 1; 294193323Sed} 295193323Sed 296218893Sdim// PseudoInst that's ARM-mode only. 297218893Sdimclass ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 298218893Sdim list<dag> pattern> 299218893Sdim : PseudoInst<oops, iops, itin, pattern> { 300218893Sdim let SZ = sz; 301218893Sdim list<Predicate> Predicates = [IsARM]; 302218893Sdim} 303218893Sdim 304218893Sdim// PseudoInst that's Thumb-mode only. 305218893Sdimclass tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 306218893Sdim list<dag> pattern> 307218893Sdim : PseudoInst<oops, iops, itin, pattern> { 308218893Sdim let SZ = sz; 309218893Sdim list<Predicate> Predicates = [IsThumb]; 310218893Sdim} 311218893Sdim 312218893Sdim// PseudoInst that's Thumb2-mode only. 313218893Sdimclass t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 314218893Sdim list<dag> pattern> 315218893Sdim : PseudoInst<oops, iops, itin, pattern> { 316218893Sdim let SZ = sz; 317218893Sdim list<Predicate> Predicates = [IsThumb2]; 318218893Sdim} 319193323Sed// Almost all ARM instructions are predicable. 320193323Sedclass I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 321206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 322198090Srdivacky string opc, string asm, string cstr, 323193323Sed list<dag> pattern> 324198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 325218893Sdim bits<4> p; 326218893Sdim let Inst{31-28} = p; 327193323Sed let OutOperandList = oops; 328205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 329218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 330193323Sed let Pattern = pattern; 331193323Sed list<Predicate> Predicates = [IsARM]; 332193323Sed} 333212904Sdim 334200581Srdivacky// A few are not predicable 335200581Srdivackyclass InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 336206083Srdivacky IndexMode im, Format f, InstrItinClass itin, 337206083Srdivacky string opc, string asm, string cstr, 338206083Srdivacky list<dag> pattern> 339200581Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 340200581Srdivacky let OutOperandList = oops; 341200581Srdivacky let InOperandList = iops; 342208599Srdivacky let AsmString = !strconcat(opc, asm); 343200581Srdivacky let Pattern = pattern; 344200581Srdivacky let isPredicable = 0; 345200581Srdivacky list<Predicate> Predicates = [IsARM]; 346200581Srdivacky} 347193323Sed 348212904Sdim// Same as I except it can optionally modify CPSR. Note it's modeled as an input 349212904Sdim// operand since by default it's a zero register. It will become an implicit def 350212904Sdim// once it's "flipped". 351193323Sedclass sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 352198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 353198090Srdivacky string opc, string asm, string cstr, 354193323Sed list<dag> pattern> 355198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 356218893Sdim bits<4> p; // Predicate operand 357218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 358218893Sdim let Inst{31-28} = p; 359218893Sdim let Inst{20} = s; 360218893Sdim 361193323Sed let OutOperandList = oops; 362205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 363218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 364193323Sed let Pattern = pattern; 365193323Sed list<Predicate> Predicates = [IsARM]; 366193323Sed} 367193323Sed 368193323Sed// Special cases 369193323Sedclass XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 370198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 371198090Srdivacky string asm, string cstr, list<dag> pattern> 372198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 373193323Sed let OutOperandList = oops; 374193323Sed let InOperandList = iops; 375208599Srdivacky let AsmString = asm; 376193323Sed let Pattern = pattern; 377193323Sed list<Predicate> Predicates = [IsARM]; 378193323Sed} 379193323Sed 380198090Srdivackyclass AI<dag oops, dag iops, Format f, InstrItinClass itin, 381198090Srdivacky string opc, string asm, list<dag> pattern> 382198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 383198090Srdivacky opc, asm, "", pattern>; 384198090Srdivackyclass AsI<dag oops, dag iops, Format f, InstrItinClass itin, 385198090Srdivacky string opc, string asm, list<dag> pattern> 386198090Srdivacky : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 387198090Srdivacky opc, asm, "", pattern>; 388198090Srdivackyclass AXI<dag oops, dag iops, Format f, InstrItinClass itin, 389193323Sed string asm, list<dag> pattern> 390198090Srdivacky : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 391193323Sed asm, "", pattern>; 392200581Srdivackyclass AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 393206083Srdivacky string opc, string asm, list<dag> pattern> 394200581Srdivacky : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 395206083Srdivacky opc, asm, "", pattern>; 396193323Sed 397193323Sed// Ctrl flow instructions 398198090Srdivackyclass ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 399198090Srdivacky string opc, string asm, list<dag> pattern> 400198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 401198090Srdivacky opc, asm, "", pattern> { 402193323Sed let Inst{27-24} = opcod; 403193323Sed} 404198090Srdivackyclass ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 405198090Srdivacky string asm, list<dag> pattern> 406198090Srdivacky : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 407198090Srdivacky asm, "", pattern> { 408193323Sed let Inst{27-24} = opcod; 409193323Sed} 410193323Sed 411193323Sed// BR_JT instructions 412198090Srdivackyclass JTI<dag oops, dag iops, InstrItinClass itin, 413198090Srdivacky string asm, list<dag> pattern> 414198090Srdivacky : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 415193323Sed asm, "", pattern>; 416193323Sed 417200581Srdivacky// Atomic load/store instructions 418200581Srdivackyclass AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 419200581Srdivacky string opc, string asm, list<dag> pattern> 420200581Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 421200581Srdivacky opc, asm, "", pattern> { 422218893Sdim bits<4> Rt; 423218893Sdim bits<4> Rn; 424200581Srdivacky let Inst{27-23} = 0b00011; 425200581Srdivacky let Inst{22-21} = opcod; 426212904Sdim let Inst{20} = 1; 427218893Sdim let Inst{19-16} = Rn; 428218893Sdim let Inst{15-12} = Rt; 429200581Srdivacky let Inst{11-0} = 0b111110011111; 430200581Srdivacky} 431200581Srdivackyclass AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 432200581Srdivacky string opc, string asm, list<dag> pattern> 433200581Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 434200581Srdivacky opc, asm, "", pattern> { 435218893Sdim bits<4> Rd; 436218893Sdim bits<4> Rt; 437221345Sdim bits<4> addr; 438200581Srdivacky let Inst{27-23} = 0b00011; 439200581Srdivacky let Inst{22-21} = opcod; 440212904Sdim let Inst{20} = 0; 441221345Sdim let Inst{19-16} = addr; 442218893Sdim let Inst{15-12} = Rd; 443200581Srdivacky let Inst{11-4} = 0b11111001; 444218893Sdim let Inst{3-0} = Rt; 445200581Srdivacky} 446218893Sdimclass AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 447218893Sdim : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> { 448218893Sdim bits<4> Rt; 449218893Sdim bits<4> Rt2; 450218893Sdim bits<4> Rn; 451218893Sdim let Inst{27-23} = 0b00010; 452218893Sdim let Inst{22} = b; 453218893Sdim let Inst{21-20} = 0b00; 454218893Sdim let Inst{19-16} = Rn; 455218893Sdim let Inst{15-12} = Rt; 456218893Sdim let Inst{11-4} = 0b00001001; 457218893Sdim let Inst{3-0} = Rt2; 458218893Sdim} 459200581Srdivacky 460193323Sed// addrmode1 instructions 461198090Srdivackyclass AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 462198090Srdivacky string opc, string asm, list<dag> pattern> 463198090Srdivacky : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 464198090Srdivacky opc, asm, "", pattern> { 465193323Sed let Inst{24-21} = opcod; 466212904Sdim let Inst{27-26} = 0b00; 467193323Sed} 468198090Srdivackyclass AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 469198090Srdivacky string opc, string asm, list<dag> pattern> 470198090Srdivacky : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 471198090Srdivacky opc, asm, "", pattern> { 472193323Sed let Inst{24-21} = opcod; 473212904Sdim let Inst{27-26} = 0b00; 474193323Sed} 475198090Srdivackyclass AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 476198090Srdivacky string asm, list<dag> pattern> 477198090Srdivacky : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 478198090Srdivacky asm, "", pattern> { 479193323Sed let Inst{24-21} = opcod; 480212904Sdim let Inst{27-26} = 0b00; 481193323Sed} 482193323Sed 483193323Sed// loads 484193323Sed 485218893Sdim// LDR/LDRB/STR/STRB/... 486218893Sdimclass AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 487218893Sdim Format f, InstrItinClass itin, string opc, string asm, 488218893Sdim list<dag> pattern> 489218893Sdim : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm, 490218893Sdim "", pattern> { 491218893Sdim let Inst{27-25} = op; 492218893Sdim let Inst{24} = 1; // 24 == P 493218893Sdim // 23 == U 494218893Sdim let Inst{22} = isByte; 495218893Sdim let Inst{21} = 0; // 21 == W 496218893Sdim let Inst{20} = isLd; 497193323Sed} 498218893Sdim// Indexed load/stores 499218893Sdimclass AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 500218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 501218893Sdim string asm, string cstr, list<dag> pattern> 502218893Sdim : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin, 503198090Srdivacky opc, asm, cstr, pattern> { 504218893Sdim bits<4> Rt; 505212904Sdim let Inst{27-26} = 0b01; 506218893Sdim let Inst{24} = isPre; // P bit 507218893Sdim let Inst{22} = isByte; // B bit 508218893Sdim let Inst{21} = isPre; // W bit 509218893Sdim let Inst{20} = isLd; // L bit 510218893Sdim let Inst{15-12} = Rt; 511193323Sed} 512218893Sdimclass AI2stridx<bit isByte, bit isPre, dag oops, dag iops, 513218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 514218893Sdim string asm, string cstr, list<dag> pattern> 515218893Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 516218893Sdim pattern> { 517218893Sdim // AM2 store w/ two operands: (GPR, am2offset) 518218893Sdim // {13} 1 == Rm, 0 == imm12 519218893Sdim // {12} isAdd 520218893Sdim // {11-0} imm12/Rm 521218893Sdim bits<14> offset; 522218893Sdim bits<4> Rn; 523218893Sdim let Inst{25} = offset{13}; 524218893Sdim let Inst{23} = offset{12}; 525218893Sdim let Inst{19-16} = Rn; 526218893Sdim let Inst{11-0} = offset{11-0}; 527193323Sed} 528221345Sdim// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 529221345Sdim// but for now use this class for STRT and STRBT. 530221345Sdimclass AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 531221345Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 532221345Sdim string asm, string cstr, list<dag> pattern> 533221345Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 534221345Sdim pattern> { 535221345Sdim // AM2 store w/ two operands: (GPR, am2offset) 536221345Sdim // {17-14} Rn 537221345Sdim // {13} 1 == Rm, 0 == imm12 538221345Sdim // {12} isAdd 539221345Sdim // {11-0} imm12/Rm 540221345Sdim bits<18> addr; 541221345Sdim let Inst{25} = addr{13}; 542221345Sdim let Inst{23} = addr{12}; 543221345Sdim let Inst{19-16} = addr{17-14}; 544221345Sdim let Inst{11-0} = addr{11-0}; 545221345Sdim} 546193323Sed 547193323Sed// addrmode3 instructions 548218893Sdimclass AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 549218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 550198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 551198090Srdivacky opc, asm, "", pattern> { 552218893Sdim bits<14> addr; 553218893Sdim bits<4> Rt; 554198090Srdivacky let Inst{27-25} = 0b000; 555218893Sdim let Inst{24} = 1; // P bit 556218893Sdim let Inst{23} = addr{8}; // U bit 557218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 558218893Sdim let Inst{21} = 0; // W bit 559218893Sdim let Inst{20} = op20; // L bit 560218893Sdim let Inst{19-16} = addr{12-9}; // Rn 561218893Sdim let Inst{15-12} = Rt; // Rt 562218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 563218893Sdim let Inst{7-4} = op; 564218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 565193323Sed} 566218893Sdim 567218893Sdimclass AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 568218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 569218893Sdim string asm, string cstr, list<dag> pattern> 570218893Sdim : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin, 571218893Sdim opc, asm, cstr, pattern> { 572218893Sdim bits<4> Rt; 573198090Srdivacky let Inst{27-25} = 0b000; 574218893Sdim let Inst{24} = isPre; // P bit 575218893Sdim let Inst{21} = isPre; // W bit 576218893Sdim let Inst{20} = op20; // L bit 577218893Sdim let Inst{15-12} = Rt; // Rt 578218893Sdim let Inst{7-4} = op; 579193323Sed} 580221345Sdim 581221345Sdim// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 582221345Sdim// but for now use this class for LDRSBT, LDRHT, LDSHT. 583221345Sdimclass AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 584221345Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 585221345Sdim string asm, string cstr, list<dag> pattern> 586221345Sdim : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin, 587221345Sdim opc, asm, cstr, pattern> { 588221345Sdim // {13} 1 == imm8, 0 == Rm 589221345Sdim // {12-9} Rn 590221345Sdim // {8} isAdd 591221345Sdim // {7-4} imm7_4/zero 592221345Sdim // {3-0} imm3_0/Rm 593221345Sdim bits<14> addr; 594221345Sdim bits<4> Rt; 595221345Sdim let Inst{27-25} = 0b000; 596221345Sdim let Inst{24} = isPre; // P bit 597221345Sdim let Inst{23} = addr{8}; // U bit 598221345Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 599221345Sdim let Inst{20} = op20; // L bit 600221345Sdim let Inst{19-16} = addr{12-9}; // Rn 601221345Sdim let Inst{15-12} = Rt; // Rt 602221345Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 603221345Sdim let Inst{7-4} = op; 604221345Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 605221345Sdim let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3"; 606221345Sdim} 607221345Sdim 608218893Sdimclass AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops, 609218893Sdim IndexMode im, Format f, InstrItinClass itin, string opc, 610218893Sdim string asm, string cstr, list<dag> pattern> 611218893Sdim : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 612218893Sdim pattern> { 613218893Sdim // AM3 store w/ two operands: (GPR, am3offset) 614218893Sdim bits<14> offset; 615218893Sdim bits<4> Rt; 616218893Sdim bits<4> Rn; 617198090Srdivacky let Inst{27-25} = 0b000; 618218893Sdim let Inst{23} = offset{8}; 619218893Sdim let Inst{22} = offset{9}; 620218893Sdim let Inst{19-16} = Rn; 621218893Sdim let Inst{15-12} = Rt; // Rt 622218893Sdim let Inst{11-8} = offset{7-4}; // imm7_4/zero 623218893Sdim let Inst{7-4} = op; 624218893Sdim let Inst{3-0} = offset{3-0}; // imm3_0/Rm 625193323Sed} 626193323Sed 627193323Sed// stores 628218893Sdimclass AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 629198090Srdivacky string opc, string asm, list<dag> pattern> 630198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 631198090Srdivacky opc, asm, "", pattern> { 632218893Sdim bits<14> addr; 633218893Sdim bits<4> Rt; 634198090Srdivacky let Inst{27-25} = 0b000; 635218893Sdim let Inst{24} = 1; // P bit 636218893Sdim let Inst{23} = addr{8}; // U bit 637218893Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 638218893Sdim let Inst{21} = 0; // W bit 639218893Sdim let Inst{20} = 0; // L bit 640218893Sdim let Inst{19-16} = addr{12-9}; // Rn 641218893Sdim let Inst{15-12} = Rt; // Rt 642218893Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 643218893Sdim let Inst{7-4} = op; 644218893Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 645193323Sed} 646193323Sed 647193323Sed// Pre-indexed stores 648198090Srdivackyclass AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 649198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 650198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 651198090Srdivacky opc, asm, cstr, pattern> { 652193323Sed let Inst{4} = 1; 653193323Sed let Inst{5} = 1; // H bit 654193323Sed let Inst{6} = 0; // S bit 655193323Sed let Inst{7} = 1; 656193323Sed let Inst{20} = 0; // L bit 657193323Sed let Inst{21} = 1; // W bit 658193323Sed let Inst{24} = 1; // P bit 659198090Srdivacky let Inst{27-25} = 0b000; 660193323Sed} 661204642Srdivackyclass AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 662204642Srdivacky string opc, string asm, string cstr, list<dag> pattern> 663204642Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 664204642Srdivacky opc, asm, cstr, pattern> { 665204642Srdivacky let Inst{4} = 1; 666204642Srdivacky let Inst{5} = 1; // H bit 667204642Srdivacky let Inst{6} = 1; // S bit 668204642Srdivacky let Inst{7} = 1; 669204642Srdivacky let Inst{20} = 0; // L bit 670204642Srdivacky let Inst{21} = 1; // W bit 671204642Srdivacky let Inst{24} = 1; // P bit 672204642Srdivacky let Inst{27-25} = 0b000; 673204642Srdivacky} 674193323Sed 675193323Sed// Post-indexed stores 676198090Srdivackyclass AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 677198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 678198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 679198090Srdivacky opc, asm, cstr,pattern> { 680221345Sdim // {13} 1 == imm8, 0 == Rm 681221345Sdim // {12-9} Rn 682221345Sdim // {8} isAdd 683221345Sdim // {7-4} imm7_4/zero 684221345Sdim // {3-0} imm3_0/Rm 685221345Sdim bits<14> addr; 686221345Sdim bits<4> Rt; 687221345Sdim let Inst{3-0} = addr{3-0}; // imm3_0/Rm 688193323Sed let Inst{4} = 1; 689193323Sed let Inst{5} = 1; // H bit 690193323Sed let Inst{6} = 0; // S bit 691193323Sed let Inst{7} = 1; 692221345Sdim let Inst{11-8} = addr{7-4}; // imm7_4/zero 693221345Sdim let Inst{15-12} = Rt; // Rt 694221345Sdim let Inst{19-16} = addr{12-9}; // Rn 695193323Sed let Inst{20} = 0; // L bit 696204642Srdivacky let Inst{21} = 0; // W bit 697221345Sdim let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 698221345Sdim let Inst{23} = addr{8}; // U bit 699193323Sed let Inst{24} = 0; // P bit 700198090Srdivacky let Inst{27-25} = 0b000; 701193323Sed} 702204642Srdivackyclass AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 703204642Srdivacky string opc, string asm, string cstr, list<dag> pattern> 704204642Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 705204642Srdivacky opc, asm, cstr, pattern> { 706204642Srdivacky let Inst{4} = 1; 707204642Srdivacky let Inst{5} = 1; // H bit 708204642Srdivacky let Inst{6} = 1; // S bit 709204642Srdivacky let Inst{7} = 1; 710204642Srdivacky let Inst{20} = 0; // L bit 711204642Srdivacky let Inst{21} = 0; // W bit 712204642Srdivacky let Inst{24} = 0; // P bit 713204642Srdivacky let Inst{27-25} = 0b000; 714204642Srdivacky} 715193323Sed 716193323Sed// addrmode4 instructions 717218893Sdimclass AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 718218893Sdim string asm, string cstr, list<dag> pattern> 719218893Sdim : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> { 720218893Sdim bits<4> p; 721218893Sdim bits<16> regs; 722218893Sdim bits<4> Rn; 723218893Sdim let Inst{31-28} = p; 724193323Sed let Inst{27-25} = 0b100; 725193323Sed let Inst{22} = 0; // S bit 726218893Sdim let Inst{19-16} = Rn; 727218893Sdim let Inst{15-0} = regs; 728193323Sed} 729193323Sed 730193323Sed// Unsigned multiply, multiply-accumulate instructions. 731198090Srdivackyclass AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 732198090Srdivacky string opc, string asm, list<dag> pattern> 733198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 734198090Srdivacky opc, asm, "", pattern> { 735193323Sed let Inst{7-4} = 0b1001; 736193323Sed let Inst{20} = 0; // S bit 737193323Sed let Inst{27-21} = opcod; 738193323Sed} 739198090Srdivackyclass AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 740198090Srdivacky string opc, string asm, list<dag> pattern> 741198090Srdivacky : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 742198090Srdivacky opc, asm, "", pattern> { 743193323Sed let Inst{7-4} = 0b1001; 744193323Sed let Inst{27-21} = opcod; 745193323Sed} 746193323Sed 747193323Sed// Most significant word multiply 748218893Sdimclass AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 749218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 750198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 751198090Srdivacky opc, asm, "", pattern> { 752218893Sdim bits<4> Rd; 753218893Sdim bits<4> Rn; 754218893Sdim bits<4> Rm; 755218893Sdim let Inst{7-4} = opc7_4; 756193323Sed let Inst{20} = 1; 757193323Sed let Inst{27-21} = opcod; 758218893Sdim let Inst{19-16} = Rd; 759218893Sdim let Inst{11-8} = Rm; 760218893Sdim let Inst{3-0} = Rn; 761193323Sed} 762218893Sdim// MSW multiple w/ Ra operand 763218893Sdimclass AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 764218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 765218893Sdim : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 766218893Sdim bits<4> Ra; 767218893Sdim let Inst{15-12} = Ra; 768218893Sdim} 769193323Sed 770193323Sed// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 771218893Sdimclass AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 772218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 773198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 774198090Srdivacky opc, asm, "", pattern> { 775218893Sdim bits<4> Rn; 776218893Sdim bits<4> Rm; 777193323Sed let Inst{4} = 0; 778193323Sed let Inst{7} = 1; 779193323Sed let Inst{20} = 0; 780193323Sed let Inst{27-21} = opcod; 781218893Sdim let Inst{6-5} = bit6_5; 782218893Sdim let Inst{11-8} = Rm; 783218893Sdim let Inst{3-0} = Rn; 784193323Sed} 785218893Sdimclass AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 786218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 787218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 788218893Sdim bits<4> Rd; 789218893Sdim let Inst{19-16} = Rd; 790218893Sdim} 791193323Sed 792218893Sdim// AMulxyI with Ra operand 793218893Sdimclass AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 794218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 795218893Sdim : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 796218893Sdim bits<4> Ra; 797218893Sdim let Inst{15-12} = Ra; 798218893Sdim} 799218893Sdim// SMLAL* 800218893Sdimclass AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 801218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 802218893Sdim : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 803218893Sdim bits<4> RdLo; 804218893Sdim bits<4> RdHi; 805218893Sdim let Inst{19-16} = RdHi; 806218893Sdim let Inst{15-12} = RdLo; 807218893Sdim} 808218893Sdim 809193323Sed// Extend instructions. 810198090Srdivackyclass AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 811198090Srdivacky string opc, string asm, list<dag> pattern> 812198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 813198090Srdivacky opc, asm, "", pattern> { 814218893Sdim // All AExtI instructions have Rd and Rm register operands. 815218893Sdim bits<4> Rd; 816218893Sdim bits<4> Rm; 817218893Sdim let Inst{15-12} = Rd; 818218893Sdim let Inst{3-0} = Rm; 819193323Sed let Inst{7-4} = 0b0111; 820218893Sdim let Inst{9-8} = 0b00; 821193323Sed let Inst{27-20} = opcod; 822193323Sed} 823193323Sed 824193323Sed// Misc Arithmetic instructions. 825218893Sdimclass AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 826218893Sdim InstrItinClass itin, string opc, string asm, list<dag> pattern> 827198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 828198090Srdivacky opc, asm, "", pattern> { 829218893Sdim bits<4> Rd; 830218893Sdim bits<4> Rm; 831193323Sed let Inst{27-20} = opcod; 832218893Sdim let Inst{19-16} = 0b1111; 833218893Sdim let Inst{15-12} = Rd; 834218893Sdim let Inst{11-8} = 0b1111; 835218893Sdim let Inst{7-4} = opc7_4; 836218893Sdim let Inst{3-0} = Rm; 837193323Sed} 838193323Sed 839218893Sdim// PKH instructions 840218893Sdimclass APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 841218893Sdim string opc, string asm, list<dag> pattern> 842218893Sdim : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 843218893Sdim opc, asm, "", pattern> { 844218893Sdim bits<4> Rd; 845218893Sdim bits<4> Rn; 846218893Sdim bits<4> Rm; 847218893Sdim bits<8> sh; 848218893Sdim let Inst{27-20} = opcod; 849218893Sdim let Inst{19-16} = Rn; 850218893Sdim let Inst{15-12} = Rd; 851218893Sdim let Inst{11-7} = sh{7-3}; 852218893Sdim let Inst{6} = tb; 853218893Sdim let Inst{5-4} = 0b01; 854218893Sdim let Inst{3-0} = Rm; 855218893Sdim} 856218893Sdim 857193323Sed//===----------------------------------------------------------------------===// 858193323Sed 859193323Sed// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 860193323Sedclass ARMPat<dag pattern, dag result> : Pat<pattern, result> { 861193323Sed list<Predicate> Predicates = [IsARM]; 862193323Sed} 863223017Sdimclass ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { 864223017Sdim list<Predicate> Predicates = [IsARM, HasV5T]; 865223017Sdim} 866193323Sedclass ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 867193323Sed list<Predicate> Predicates = [IsARM, HasV5TE]; 868193323Sed} 869193323Sedclass ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 870193323Sed list<Predicate> Predicates = [IsARM, HasV6]; 871193323Sed} 872193323Sed 873193323Sed//===----------------------------------------------------------------------===// 874193323Sed// Thumb Instruction Format Definitions. 875193323Sed// 876193323Sed 877198090Srdivackyclass ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 878198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 879201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 880198090Srdivacky let OutOperandList = oops; 881198090Srdivacky let InOperandList = iops; 882208599Srdivacky let AsmString = asm; 883193323Sed let Pattern = pattern; 884193323Sed list<Predicate> Predicates = [IsThumb]; 885193323Sed} 886193323Sed 887218893Sdim// TI - Thumb instruction. 888198090Srdivackyclass TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 889198090Srdivacky : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 890193323Sed 891198090Srdivacky// Two-address instructions 892206083Srdivackyclass TIt<dag oops, dag iops, InstrItinClass itin, string asm, 893206083Srdivacky list<dag> pattern> 894206083Srdivacky : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", 895206083Srdivacky pattern>; 896193323Sed 897201360Srdivacky// tBL, tBX 32-bit instructions 898201360Srdivackyclass TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 899206083Srdivacky dag oops, dag iops, InstrItinClass itin, string asm, 900206083Srdivacky list<dag> pattern> 901206083Srdivacky : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, 902206083Srdivacky Encoding { 903201360Srdivacky let Inst{31-27} = opcod1; 904201360Srdivacky let Inst{15-14} = opcod2; 905212904Sdim let Inst{12} = opcod3; 906201360Srdivacky} 907198090Srdivacky 908218893Sdim// Move to/from coprocessor instructions 909218893Sdimclass T1Cop<dag oops, dag iops, string asm, list<dag> pattern> 910218893Sdim : ThumbI<oops, iops, AddrModeNone, Size4Bytes, NoItinerary, asm, "", pattern>, 911218893Sdim Encoding, Requires<[IsThumb, HasV6]> { 912218893Sdim let Inst{31-28} = 0b1110; 913218893Sdim} 914218893Sdim 915193323Sed// BR_JT instructions 916206083Srdivackyclass TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 917206083Srdivacky list<dag> pattern> 918198090Srdivacky : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 919193323Sed 920198090Srdivacky// Thumb1 only 921198090Srdivackyclass Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 922198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 923201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 924198090Srdivacky let OutOperandList = oops; 925198090Srdivacky let InOperandList = iops; 926208599Srdivacky let AsmString = asm; 927198090Srdivacky let Pattern = pattern; 928218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 929194710Sed} 930193323Sed 931198090Srdivackyclass T1I<dag oops, dag iops, InstrItinClass itin, 932198090Srdivacky string asm, list<dag> pattern> 933198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 934198090Srdivackyclass T1Ix2<dag oops, dag iops, InstrItinClass itin, 935198090Srdivacky string asm, list<dag> pattern> 936198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 937194710Sed 938198090Srdivacky// Two-address instructions 939198090Srdivackyclass T1It<dag oops, dag iops, InstrItinClass itin, 940205218Srdivacky string asm, string cstr, list<dag> pattern> 941206083Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 942205218Srdivacky asm, cstr, pattern>; 943198090Srdivacky 944198090Srdivacky// Thumb1 instruction that can either be predicated or set CPSR. 945198090Srdivackyclass Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 946198090Srdivacky InstrItinClass itin, 947198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 948201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 949205407Srdivacky let OutOperandList = !con(oops, (outs s_cc_out:$s)); 950205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 951218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 952194754Sed let Pattern = pattern; 953218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 954195098Sed} 955195098Sed 956198090Srdivackyclass T1sI<dag oops, dag iops, InstrItinClass itin, 957198090Srdivacky string opc, string asm, list<dag> pattern> 958198090Srdivacky : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 959195098Sed 960195098Sed// Two-address instructions 961198090Srdivackyclass T1sIt<dag oops, dag iops, InstrItinClass itin, 962198090Srdivacky string opc, string asm, list<dag> pattern> 963198090Srdivacky : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 964218893Sdim "$Rn = $Rdn", pattern>; 965195098Sed 966198090Srdivacky// Thumb1 instruction that can be predicated. 967198090Srdivackyclass Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 968198090Srdivacky InstrItinClass itin, 969198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 970201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 971198090Srdivacky let OutOperandList = oops; 972205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 973218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 974198090Srdivacky let Pattern = pattern; 975218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 976195098Sed} 977195098Sed 978198090Srdivackyclass T1pI<dag oops, dag iops, InstrItinClass itin, 979198090Srdivacky string opc, string asm, list<dag> pattern> 980198090Srdivacky : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 981198090Srdivacky 982198090Srdivacky// Two-address instructions 983198090Srdivackyclass T1pIt<dag oops, dag iops, InstrItinClass itin, 984198090Srdivacky string opc, string asm, list<dag> pattern> 985198090Srdivacky : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 986218893Sdim "$Rn = $Rdn", pattern>; 987198090Srdivacky 988206083Srdivackyclass T1pIs<dag oops, dag iops, 989198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 990198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 991198090Srdivacky 992201360Srdivackyclass Encoding16 : Encoding { 993201360Srdivacky let Inst{31-16} = 0x0000; 994201360Srdivacky} 995201360Srdivacky 996201360Srdivacky// A6.2 16-bit Thumb instruction encoding 997201360Srdivackyclass T1Encoding<bits<6> opcode> : Encoding16 { 998201360Srdivacky let Inst{15-10} = opcode; 999201360Srdivacky} 1000201360Srdivacky 1001201360Srdivacky// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1002201360Srdivackyclass T1General<bits<5> opcode> : Encoding16 { 1003201360Srdivacky let Inst{15-14} = 0b00; 1004201360Srdivacky let Inst{13-9} = opcode; 1005201360Srdivacky} 1006201360Srdivacky 1007201360Srdivacky// A6.2.2 Data-processing encoding. 1008201360Srdivackyclass T1DataProcessing<bits<4> opcode> : Encoding16 { 1009201360Srdivacky let Inst{15-10} = 0b010000; 1010201360Srdivacky let Inst{9-6} = opcode; 1011201360Srdivacky} 1012201360Srdivacky 1013201360Srdivacky// A6.2.3 Special data instructions and branch and exchange encoding. 1014201360Srdivackyclass T1Special<bits<4> opcode> : Encoding16 { 1015201360Srdivacky let Inst{15-10} = 0b010001; 1016218893Sdim let Inst{9-6} = opcode; 1017201360Srdivacky} 1018201360Srdivacky 1019201360Srdivacky// A6.2.4 Load/store single data item encoding. 1020201360Srdivackyclass T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1021201360Srdivacky let Inst{15-12} = opA; 1022212904Sdim let Inst{11-9} = opB; 1023201360Srdivacky} 1024212904Sdimclass T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1025201360Srdivacky 1026223017Sdimclass T1BranchCond<bits<4> opcode> : Encoding16 { 1027223017Sdim let Inst{15-12} = opcode; 1028223017Sdim} 1029223017Sdim 1030218893Sdim// Helper classes to encode Thumb1 loads and stores. For immediates, the 1031218893Sdim// following bits are used for "opA" (see A6.2.4): 1032218893Sdim// 1033218893Sdim// 0b0110 => Immediate, 4 bytes 1034218893Sdim// 0b1000 => Immediate, 2 bytes 1035218893Sdim// 0b0111 => Immediate, 1 byte 1036218893Sdimclass T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1037218893Sdim InstrItinClass itin, string opc, string asm, 1038218893Sdim list<dag> pattern> 1039218893Sdim : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 1040218893Sdim T1LoadStore<0b0101, opcode> { 1041218893Sdim bits<3> Rt; 1042218893Sdim bits<8> addr; 1043218893Sdim let Inst{8-6} = addr{5-3}; // Rm 1044218893Sdim let Inst{5-3} = addr{2-0}; // Rn 1045218893Sdim let Inst{2-0} = Rt; 1046218893Sdim} 1047218893Sdimclass T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1048218893Sdim InstrItinClass itin, string opc, string asm, 1049218893Sdim list<dag> pattern> 1050218893Sdim : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 1051218893Sdim T1LoadStore<opA, {opB,?,?}> { 1052218893Sdim bits<3> Rt; 1053218893Sdim bits<8> addr; 1054218893Sdim let Inst{10-6} = addr{7-3}; // imm5 1055218893Sdim let Inst{5-3} = addr{2-0}; // Rn 1056218893Sdim let Inst{2-0} = Rt; 1057218893Sdim} 1058218893Sdim 1059201360Srdivacky// A6.2.5 Miscellaneous 16-bit instructions encoding. 1060201360Srdivackyclass T1Misc<bits<7> opcode> : Encoding16 { 1061201360Srdivacky let Inst{15-12} = 0b1011; 1062201360Srdivacky let Inst{11-5} = opcode; 1063201360Srdivacky} 1064201360Srdivacky 1065195098Sed// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1066195098Sedclass Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1067198090Srdivacky InstrItinClass itin, 1068195098Sed string opc, string asm, string cstr, list<dag> pattern> 1069198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1070195098Sed let OutOperandList = oops; 1071205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1072218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1073195098Sed let Pattern = pattern; 1074195340Sed list<Predicate> Predicates = [IsThumb2]; 1075194754Sed} 1076194754Sed 1077212904Sdim// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1078212904Sdim// input operand since by default it's a zero register. It will become an 1079212904Sdim// implicit def once it's "flipped". 1080218893Sdim// 1081195098Sed// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1082195098Sed// more consistent. 1083195098Sedclass Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1084198090Srdivacky InstrItinClass itin, 1085195098Sed string opc, string asm, string cstr, list<dag> pattern> 1086198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1087218893Sdim bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1088218893Sdim let Inst{20} = s; 1089218893Sdim 1090195098Sed let OutOperandList = oops; 1091205407Srdivacky let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1092218893Sdim let AsmString = !strconcat(opc, "${s}${p}", asm); 1093195098Sed let Pattern = pattern; 1094195340Sed list<Predicate> Predicates = [IsThumb2]; 1095195098Sed} 1096194754Sed 1097195098Sed// Special cases 1098195098Sedclass Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1099198090Srdivacky InstrItinClass itin, 1100195098Sed string asm, string cstr, list<dag> pattern> 1101198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1102195098Sed let OutOperandList = oops; 1103195098Sed let InOperandList = iops; 1104208599Srdivacky let AsmString = asm; 1105195098Sed let Pattern = pattern; 1106195340Sed list<Predicate> Predicates = [IsThumb2]; 1107194754Sed} 1108194754Sed 1109200581Srdivackyclass ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1110206083Srdivacky InstrItinClass itin, 1111206083Srdivacky string asm, string cstr, list<dag> pattern> 1112200581Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1113200581Srdivacky let OutOperandList = oops; 1114200581Srdivacky let InOperandList = iops; 1115208599Srdivacky let AsmString = asm; 1116200581Srdivacky let Pattern = pattern; 1117218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1118200581Srdivacky} 1119200581Srdivacky 1120198090Srdivackyclass T2I<dag oops, dag iops, InstrItinClass itin, 1121198090Srdivacky string opc, string asm, list<dag> pattern> 1122198090Srdivacky : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1123198090Srdivackyclass T2Ii12<dag oops, dag iops, InstrItinClass itin, 1124198090Srdivacky string opc, string asm, list<dag> pattern> 1125206083Srdivacky : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>; 1126198090Srdivackyclass T2Ii8<dag oops, dag iops, InstrItinClass itin, 1127198090Srdivacky string opc, string asm, list<dag> pattern> 1128198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1129198090Srdivackyclass T2Iso<dag oops, dag iops, InstrItinClass itin, 1130198090Srdivacky string opc, string asm, list<dag> pattern> 1131198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1132198090Srdivackyclass T2Ipc<dag oops, dag iops, InstrItinClass itin, 1133198090Srdivacky string opc, string asm, list<dag> pattern> 1134198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1135218893Sdimclass T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1136198090Srdivacky string opc, string asm, list<dag> pattern> 1137201360Srdivacky : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1138201360Srdivacky pattern> { 1139218893Sdim bits<4> Rt; 1140218893Sdim bits<4> Rt2; 1141218893Sdim bits<13> addr; 1142218893Sdim let Inst{31-25} = 0b1110100; 1143212904Sdim let Inst{24} = P; 1144218893Sdim let Inst{23} = addr{8}; 1145212904Sdim let Inst{22} = 1; 1146212904Sdim let Inst{21} = W; 1147218893Sdim let Inst{20} = isLoad; 1148218893Sdim let Inst{19-16} = addr{12-9}; 1149218893Sdim let Inst{15-12} = Rt{3-0}; 1150218893Sdim let Inst{11-8} = Rt2{3-0}; 1151218893Sdim let Inst{7-0} = addr{7-0}; 1152201360Srdivacky} 1153195098Sed 1154198090Srdivackyclass T2sI<dag oops, dag iops, InstrItinClass itin, 1155198090Srdivacky string opc, string asm, list<dag> pattern> 1156198090Srdivacky : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1157195098Sed 1158198090Srdivackyclass T2XI<dag oops, dag iops, InstrItinClass itin, 1159198090Srdivacky string asm, list<dag> pattern> 1160198090Srdivacky : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1161198090Srdivackyclass T2JTI<dag oops, dag iops, InstrItinClass itin, 1162198090Srdivacky string asm, list<dag> pattern> 1163198090Srdivacky : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1164195098Sed 1165218893Sdim// Move to/from coprocessor instructions 1166218893Sdimclass T2Cop<dag oops, dag iops, string asm, list<dag> pattern> 1167218893Sdim : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> { 1168218893Sdim let Inst{31-28} = 0b1111; 1169218893Sdim} 1170198090Srdivacky 1171205218Srdivacky// Two-address instructions 1172205218Srdivackyclass T2XIt<dag oops, dag iops, InstrItinClass itin, 1173205218Srdivacky string asm, string cstr, list<dag> pattern> 1174205218Srdivacky : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>; 1175198090Srdivacky 1176195340Sed// T2Iidxldst - Thumb2 indexed load / store instructions. 1177201360Srdivackyclass T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1178201360Srdivacky dag oops, dag iops, 1179201360Srdivacky AddrMode am, IndexMode im, InstrItinClass itin, 1180195340Sed string opc, string asm, string cstr, list<dag> pattern> 1181198892Srdivacky : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1182195340Sed let OutOperandList = oops; 1183205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1184218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1185195340Sed let Pattern = pattern; 1186195340Sed list<Predicate> Predicates = [IsThumb2]; 1187201360Srdivacky let Inst{31-27} = 0b11111; 1188201360Srdivacky let Inst{26-25} = 0b00; 1189212904Sdim let Inst{24} = signed; 1190212904Sdim let Inst{23} = 0; 1191201360Srdivacky let Inst{22-21} = opcod; 1192212904Sdim let Inst{20} = load; 1193212904Sdim let Inst{11} = 1; 1194201360Srdivacky // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1195212904Sdim let Inst{10} = pre; // The P bit. 1196212904Sdim let Inst{8} = 1; // The W bit. 1197195340Sed 1198218893Sdim bits<9> addr; 1199218893Sdim let Inst{7-0} = addr{7-0}; 1200218893Sdim let Inst{9} = addr{8}; // Sign bit 1201218893Sdim 1202218893Sdim bits<4> Rt; 1203218893Sdim bits<4> Rn; 1204218893Sdim let Inst{15-12} = Rt{3-0}; 1205218893Sdim let Inst{19-16} = Rn{3-0}; 1206204642Srdivacky} 1207204642Srdivacky 1208198090Srdivacky// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1209198090Srdivackyclass Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1210218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1211198090Srdivacky} 1212195340Sed 1213198090Srdivacky// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1214198090Srdivackyclass T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1215218893Sdim list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1216198090Srdivacky} 1217198090Srdivacky 1218223017Sdim// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. 1219223017Sdimclass T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { 1220223017Sdim list<Predicate> Predicates = [IsThumb2, HasV6T2]; 1221223017Sdim} 1222223017Sdim 1223195098Sed// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1224195098Sedclass T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1225195340Sed list<Predicate> Predicates = [IsThumb2]; 1226195098Sed} 1227195098Sed 1228193323Sed//===----------------------------------------------------------------------===// 1229193323Sed 1230193323Sed//===----------------------------------------------------------------------===// 1231193323Sed// ARM VFP Instruction templates. 1232193323Sed// 1233193323Sed 1234198090Srdivacky// Almost all VFP instructions are predicable. 1235198090Srdivackyclass VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1236198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1237198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1238198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1239218893Sdim bits<4> p; 1240218893Sdim let Inst{31-28} = p; 1241198090Srdivacky let OutOperandList = oops; 1242205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1243218893Sdim let AsmString = !strconcat(opc, "${p}", asm); 1244198090Srdivacky let Pattern = pattern; 1245218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1246198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1247198090Srdivacky} 1248198090Srdivacky 1249198090Srdivacky// Special cases 1250198090Srdivackyclass VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1251198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1252198090Srdivacky string asm, string cstr, list<dag> pattern> 1253198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1254218893Sdim bits<4> p; 1255218893Sdim let Inst{31-28} = p; 1256198090Srdivacky let OutOperandList = oops; 1257198090Srdivacky let InOperandList = iops; 1258208599Srdivacky let AsmString = asm; 1259198090Srdivacky let Pattern = pattern; 1260218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1261198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1262198090Srdivacky} 1263198090Srdivacky 1264198090Srdivackyclass VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1265198090Srdivacky string opc, string asm, list<dag> pattern> 1266198090Srdivacky : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1267218893Sdim opc, asm, "", pattern> { 1268218893Sdim let PostEncoderMethod = "VFPThumb2PostEncoder"; 1269218893Sdim} 1270198090Srdivacky 1271193323Sed// ARM VFP addrmode5 loads and stores 1272193323Sedclass ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1273198090Srdivacky InstrItinClass itin, 1274193323Sed string opc, string asm, list<dag> pattern> 1275198090Srdivacky : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1276206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1277218893Sdim // Instruction operands. 1278218893Sdim bits<5> Dd; 1279218893Sdim bits<13> addr; 1280218893Sdim 1281218893Sdim // Encode instruction operands. 1282218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1283218893Sdim let Inst{22} = Dd{4}; 1284218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1285218893Sdim let Inst{15-12} = Dd{3-0}; 1286218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1287218893Sdim 1288193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1289193323Sed let Inst{27-24} = opcod1; 1290193323Sed let Inst{21-20} = opcod2; 1291218893Sdim let Inst{11-9} = 0b101; 1292218893Sdim let Inst{8} = 1; // Double precision 1293198892Srdivacky 1294218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1295206274Srdivacky let D = VFPNeonDomain; 1296193323Sed} 1297193323Sed 1298193323Sedclass ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1299198090Srdivacky InstrItinClass itin, 1300193323Sed string opc, string asm, list<dag> pattern> 1301198090Srdivacky : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1302206083Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1303218893Sdim // Instruction operands. 1304218893Sdim bits<5> Sd; 1305218893Sdim bits<13> addr; 1306218893Sdim 1307218893Sdim // Encode instruction operands. 1308218893Sdim let Inst{23} = addr{8}; // U (add = (U == '1')) 1309218893Sdim let Inst{22} = Sd{0}; 1310218893Sdim let Inst{19-16} = addr{12-9}; // Rn 1311218893Sdim let Inst{15-12} = Sd{4-1}; 1312218893Sdim let Inst{7-0} = addr{7-0}; // imm8 1313218893Sdim 1314193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1315193323Sed let Inst{27-24} = opcod1; 1316193323Sed let Inst{21-20} = opcod2; 1317218893Sdim let Inst{11-9} = 0b101; 1318218893Sdim let Inst{8} = 0; // Single precision 1319218893Sdim 1320218893Sdim // Loads & stores operate on both NEON and VFP pipelines. 1321218893Sdim let D = VFPNeonDomain; 1322193323Sed} 1323193323Sed 1324218893Sdim// VFP Load / store multiple pseudo instructions. 1325218893Sdimclass PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1326218893Sdim list<dag> pattern> 1327218893Sdim : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain, 1328218893Sdim cstr, itin> { 1329218893Sdim let OutOperandList = oops; 1330218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1331218893Sdim let Pattern = pattern; 1332218893Sdim list<Predicate> Predicates = [HasVFP2]; 1333218893Sdim} 1334218893Sdim 1335193323Sed// Load / store multiple 1336212904Sdimclass AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1337205218Srdivacky string asm, string cstr, list<dag> pattern> 1338212904Sdim : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1339206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1340218893Sdim // Instruction operands. 1341218893Sdim bits<4> Rn; 1342218893Sdim bits<13> regs; 1343218893Sdim 1344218893Sdim // Encode instruction operands. 1345218893Sdim let Inst{19-16} = Rn; 1346218893Sdim let Inst{22} = regs{12}; 1347218893Sdim let Inst{15-12} = regs{11-8}; 1348218893Sdim let Inst{7-0} = regs{7-0}; 1349218893Sdim 1350193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1351193323Sed let Inst{27-25} = 0b110; 1352218893Sdim let Inst{11-9} = 0b101; 1353218893Sdim let Inst{8} = 1; // Double precision 1354193323Sed} 1355193323Sed 1356212904Sdimclass AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1357205218Srdivacky string asm, string cstr, list<dag> pattern> 1358212904Sdim : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1359206083Srdivacky VFPLdStMulFrm, itin, asm, cstr, pattern> { 1360218893Sdim // Instruction operands. 1361218893Sdim bits<4> Rn; 1362218893Sdim bits<13> regs; 1363218893Sdim 1364218893Sdim // Encode instruction operands. 1365218893Sdim let Inst{19-16} = Rn; 1366218893Sdim let Inst{22} = regs{8}; 1367218893Sdim let Inst{15-12} = regs{12-9}; 1368218893Sdim let Inst{7-0} = regs{7-0}; 1369218893Sdim 1370193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1371193323Sed let Inst{27-25} = 0b110; 1372218893Sdim let Inst{11-9} = 0b101; 1373218893Sdim let Inst{8} = 0; // Single precision 1374193323Sed} 1375193323Sed 1376193323Sed// Double precision, unary 1377203954Srdivackyclass ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1378203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1379203954Srdivacky string asm, list<dag> pattern> 1380198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1381218893Sdim // Instruction operands. 1382218893Sdim bits<5> Dd; 1383218893Sdim bits<5> Dm; 1384218893Sdim 1385218893Sdim // Encode instruction operands. 1386218893Sdim let Inst{3-0} = Dm{3-0}; 1387218893Sdim let Inst{5} = Dm{4}; 1388218893Sdim let Inst{15-12} = Dd{3-0}; 1389218893Sdim let Inst{22} = Dd{4}; 1390218893Sdim 1391203954Srdivacky let Inst{27-23} = opcod1; 1392203954Srdivacky let Inst{21-20} = opcod2; 1393203954Srdivacky let Inst{19-16} = opcod3; 1394218893Sdim let Inst{11-9} = 0b101; 1395218893Sdim let Inst{8} = 1; // Double precision 1396203954Srdivacky let Inst{7-6} = opcod4; 1397203954Srdivacky let Inst{4} = opcod5; 1398193323Sed} 1399193323Sed 1400193323Sed// Double precision, binary 1401203954Srdivackyclass ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1402206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1403206083Srdivacky list<dag> pattern> 1404198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1405218893Sdim // Instruction operands. 1406218893Sdim bits<5> Dd; 1407218893Sdim bits<5> Dn; 1408218893Sdim bits<5> Dm; 1409193323Sed 1410218893Sdim // Encode instruction operands. 1411218893Sdim let Inst{3-0} = Dm{3-0}; 1412218893Sdim let Inst{5} = Dm{4}; 1413218893Sdim let Inst{19-16} = Dn{3-0}; 1414218893Sdim let Inst{7} = Dn{4}; 1415218893Sdim let Inst{15-12} = Dd{3-0}; 1416218893Sdim let Inst{22} = Dd{4}; 1417218893Sdim 1418206083Srdivacky let Inst{27-23} = opcod1; 1419206083Srdivacky let Inst{21-20} = opcod2; 1420218893Sdim let Inst{11-9} = 0b101; 1421218893Sdim let Inst{8} = 1; // Double precision 1422212904Sdim let Inst{6} = op6; 1423212904Sdim let Inst{4} = op4; 1424206083Srdivacky} 1425206083Srdivacky 1426193323Sed// Single precision, unary 1427203954Srdivackyclass ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1428203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1429203954Srdivacky string asm, list<dag> pattern> 1430198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1431218893Sdim // Instruction operands. 1432218893Sdim bits<5> Sd; 1433218893Sdim bits<5> Sm; 1434218893Sdim 1435218893Sdim // Encode instruction operands. 1436218893Sdim let Inst{3-0} = Sm{4-1}; 1437218893Sdim let Inst{5} = Sm{0}; 1438218893Sdim let Inst{15-12} = Sd{4-1}; 1439218893Sdim let Inst{22} = Sd{0}; 1440218893Sdim 1441203954Srdivacky let Inst{27-23} = opcod1; 1442203954Srdivacky let Inst{21-20} = opcod2; 1443203954Srdivacky let Inst{19-16} = opcod3; 1444218893Sdim let Inst{11-9} = 0b101; 1445218893Sdim let Inst{8} = 0; // Single precision 1446203954Srdivacky let Inst{7-6} = opcod4; 1447203954Srdivacky let Inst{4} = opcod5; 1448193323Sed} 1449193323Sed 1450218893Sdim// Single precision unary, if no NEON. Same as ASuI except not available if 1451218893Sdim// NEON is enabled. 1452203954Srdivackyclass ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1453203954Srdivacky bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1454203954Srdivacky string asm, list<dag> pattern> 1455203954Srdivacky : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1456203954Srdivacky pattern> { 1457198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1458198090Srdivacky} 1459198090Srdivacky 1460193323Sed// Single precision, binary 1461203954Srdivackyclass ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1462203954Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1463198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1464218893Sdim // Instruction operands. 1465218893Sdim bits<5> Sd; 1466218893Sdim bits<5> Sn; 1467218893Sdim bits<5> Sm; 1468218893Sdim 1469218893Sdim // Encode instruction operands. 1470218893Sdim let Inst{3-0} = Sm{4-1}; 1471218893Sdim let Inst{5} = Sm{0}; 1472218893Sdim let Inst{19-16} = Sn{4-1}; 1473218893Sdim let Inst{7} = Sn{0}; 1474218893Sdim let Inst{15-12} = Sd{4-1}; 1475218893Sdim let Inst{22} = Sd{0}; 1476218893Sdim 1477203954Srdivacky let Inst{27-23} = opcod1; 1478203954Srdivacky let Inst{21-20} = opcod2; 1479218893Sdim let Inst{11-9} = 0b101; 1480218893Sdim let Inst{8} = 0; // Single precision 1481212904Sdim let Inst{6} = op6; 1482212904Sdim let Inst{4} = op4; 1483193323Sed} 1484193323Sed 1485218893Sdim// Single precision binary, if no NEON. Same as ASbI except not available if 1486218893Sdim// NEON is enabled. 1487203954Srdivackyclass ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1488206083Srdivacky dag iops, InstrItinClass itin, string opc, string asm, 1489206083Srdivacky list<dag> pattern> 1490203954Srdivacky : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1491198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1492218893Sdim 1493218893Sdim // Instruction operands. 1494218893Sdim bits<5> Sd; 1495218893Sdim bits<5> Sn; 1496218893Sdim bits<5> Sm; 1497218893Sdim 1498218893Sdim // Encode instruction operands. 1499218893Sdim let Inst{3-0} = Sm{4-1}; 1500218893Sdim let Inst{5} = Sm{0}; 1501218893Sdim let Inst{19-16} = Sn{4-1}; 1502218893Sdim let Inst{7} = Sn{0}; 1503218893Sdim let Inst{15-12} = Sd{4-1}; 1504218893Sdim let Inst{22} = Sd{0}; 1505198090Srdivacky} 1506198090Srdivacky 1507193323Sed// VFP conversion instructions 1508203954Srdivackyclass AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1509203954Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1510203954Srdivacky list<dag> pattern> 1511198090Srdivacky : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1512203954Srdivacky let Inst{27-23} = opcod1; 1513203954Srdivacky let Inst{21-20} = opcod2; 1514203954Srdivacky let Inst{19-16} = opcod3; 1515203954Srdivacky let Inst{11-8} = opcod4; 1516193323Sed let Inst{6} = 1; 1517203954Srdivacky let Inst{4} = 0; 1518193323Sed} 1519193323Sed 1520203954Srdivacky// VFP conversion between floating-point and fixed-point 1521203954Srdivackyclass AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1522206083Srdivacky dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1523206083Srdivacky list<dag> pattern> 1524203954Srdivacky : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1525203954Srdivacky // size (fixed-point number): sx == 0 ? 16 : 32 1526203954Srdivacky let Inst{7} = op5; // sx 1527203954Srdivacky} 1528203954Srdivacky 1529198090Srdivacky// VFP conversion instructions, if no NEON 1530203954Srdivackyclass AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1531198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1532198090Srdivacky string opc, string asm, list<dag> pattern> 1533203954Srdivacky : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1534203954Srdivacky pattern> { 1535198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1536198090Srdivacky} 1537198090Srdivacky 1538193323Sedclass AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1539198090Srdivacky InstrItinClass itin, 1540198090Srdivacky string opc, string asm, list<dag> pattern> 1541198090Srdivacky : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1542193323Sed let Inst{27-20} = opcod1; 1543193323Sed let Inst{11-8} = opcod2; 1544193323Sed let Inst{4} = 1; 1545193323Sed} 1546193323Sed 1547198090Srdivackyclass AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1548198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1549198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1550193323Sed 1551206083Srdivackyclass AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1552198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1553198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1554193323Sed 1555198090Srdivackyclass AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1556198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1557198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1558193323Sed 1559198090Srdivackyclass AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1560198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1561198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1562193323Sed 1563193323Sed//===----------------------------------------------------------------------===// 1564193323Sed 1565194710Sed//===----------------------------------------------------------------------===// 1566194710Sed// ARM NEON Instruction templates. 1567194710Sed// 1568193323Sed 1569205407Srdivackyclass NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1570205407Srdivacky InstrItinClass itin, string opc, string dt, string asm, string cstr, 1571205407Srdivacky list<dag> pattern> 1572205407Srdivacky : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1573194710Sed let OutOperandList = oops; 1574205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1575218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1576194710Sed let Pattern = pattern; 1577194710Sed list<Predicate> Predicates = [HasNEON]; 1578193323Sed} 1579193323Sed 1580199989Srdivacky// Same as NeonI except it does not have a "data type" specifier. 1581206083Srdivackyclass NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1582206083Srdivacky InstrItinClass itin, string opc, string asm, string cstr, 1583206083Srdivacky list<dag> pattern> 1584206083Srdivacky : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1585199989Srdivacky let OutOperandList = oops; 1586205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1587218893Sdim let AsmString = !strconcat(opc, "${p}", "\t", asm); 1588199989Srdivacky let Pattern = pattern; 1589199989Srdivacky list<Predicate> Predicates = [HasNEON]; 1590193323Sed} 1591194710Sed 1592198090Srdivackyclass NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1593198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1594199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1595205407Srdivacky : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1596205407Srdivacky cstr, pattern> { 1597198090Srdivacky let Inst{31-24} = 0b11110100; 1598212904Sdim let Inst{23} = op23; 1599198396Srdivacky let Inst{21-20} = op21_20; 1600212904Sdim let Inst{11-8} = op11_8; 1601212904Sdim let Inst{7-4} = op7_4; 1602218893Sdim 1603218893Sdim let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1604218893Sdim 1605218893Sdim bits<5> Vd; 1606218893Sdim bits<6> Rn; 1607218893Sdim bits<4> Rm; 1608218893Sdim 1609218893Sdim let Inst{22} = Vd{4}; 1610218893Sdim let Inst{15-12} = Vd{3-0}; 1611218893Sdim let Inst{19-16} = Rn{3-0}; 1612218893Sdim let Inst{3-0} = Rm{3-0}; 1613198090Srdivacky} 1614198090Srdivacky 1615218893Sdimclass NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1616218893Sdim dag oops, dag iops, InstrItinClass itin, 1617218893Sdim string opc, string dt, string asm, string cstr, list<dag> pattern> 1618218893Sdim : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1619218893Sdim dt, asm, cstr, pattern> { 1620218893Sdim bits<3> lane; 1621218893Sdim} 1622218893Sdim 1623212904Sdimclass PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1624212904Sdim : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1625212904Sdim itin> { 1626212904Sdim let OutOperandList = oops; 1627212904Sdim let InOperandList = !con(iops, (ins pred:$p)); 1628212904Sdim list<Predicate> Predicates = [HasNEON]; 1629212904Sdim} 1630212904Sdim 1631218893Sdimclass PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1632218893Sdim list<dag> pattern> 1633218893Sdim : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1634218893Sdim itin> { 1635218893Sdim let OutOperandList = oops; 1636218893Sdim let InOperandList = !con(iops, (ins pred:$p)); 1637218893Sdim let Pattern = pattern; 1638218893Sdim list<Predicate> Predicates = [HasNEON]; 1639218893Sdim} 1640218893Sdim 1641206083Srdivackyclass NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1642199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1643206083Srdivacky : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1644206083Srdivacky pattern> { 1645194710Sed let Inst{31-25} = 0b1111001; 1646218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1647194710Sed} 1648194710Sed 1649206083Srdivackyclass NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1650206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1651206083Srdivacky : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1652206083Srdivacky cstr, pattern> { 1653199989Srdivacky let Inst{31-25} = 0b1111001; 1654218893Sdim let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1655199989Srdivacky} 1656199989Srdivacky 1657194710Sed// NEON "one register and a modified immediate" format. 1658194710Sedclass N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1659194710Sed bit op5, bit op4, 1660198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1661206083Srdivacky string opc, string dt, string asm, string cstr, 1662206083Srdivacky list<dag> pattern> 1663206083Srdivacky : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1664212904Sdim let Inst{23} = op23; 1665194710Sed let Inst{21-19} = op21_19; 1666212904Sdim let Inst{11-8} = op11_8; 1667212904Sdim let Inst{7} = op7; 1668212904Sdim let Inst{6} = op6; 1669212904Sdim let Inst{5} = op5; 1670212904Sdim let Inst{4} = op4; 1671218893Sdim 1672218893Sdim // Instruction operands. 1673218893Sdim bits<5> Vd; 1674218893Sdim bits<13> SIMM; 1675218893Sdim 1676218893Sdim let Inst{15-12} = Vd{3-0}; 1677218893Sdim let Inst{22} = Vd{4}; 1678218893Sdim let Inst{24} = SIMM{7}; 1679218893Sdim let Inst{18-16} = SIMM{6-4}; 1680218893Sdim let Inst{3-0} = SIMM{3-0}; 1681194710Sed} 1682194710Sed 1683194710Sed// NEON 2 vector register format. 1684194710Sedclass N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1685194710Sed bits<5> op11_7, bit op6, bit op4, 1686198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1687199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1688206083Srdivacky : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1689194710Sed let Inst{24-23} = op24_23; 1690194710Sed let Inst{21-20} = op21_20; 1691194710Sed let Inst{19-18} = op19_18; 1692194710Sed let Inst{17-16} = op17_16; 1693212904Sdim let Inst{11-7} = op11_7; 1694212904Sdim let Inst{6} = op6; 1695212904Sdim let Inst{4} = op4; 1696218893Sdim 1697218893Sdim // Instruction operands. 1698218893Sdim bits<5> Vd; 1699218893Sdim bits<5> Vm; 1700218893Sdim 1701218893Sdim let Inst{15-12} = Vd{3-0}; 1702218893Sdim let Inst{22} = Vd{4}; 1703218893Sdim let Inst{3-0} = Vm{3-0}; 1704218893Sdim let Inst{5} = Vm{4}; 1705194710Sed} 1706194710Sed 1707199989Srdivacky// Same as N2V except it doesn't have a datatype suffix. 1708199989Srdivackyclass N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1709206083Srdivacky bits<5> op11_7, bit op6, bit op4, 1710206083Srdivacky dag oops, dag iops, InstrItinClass itin, 1711206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1712206083Srdivacky : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1713198396Srdivacky let Inst{24-23} = op24_23; 1714198396Srdivacky let Inst{21-20} = op21_20; 1715199989Srdivacky let Inst{19-18} = op19_18; 1716199989Srdivacky let Inst{17-16} = op17_16; 1717212904Sdim let Inst{11-7} = op11_7; 1718212904Sdim let Inst{6} = op6; 1719212904Sdim let Inst{4} = op4; 1720218893Sdim 1721218893Sdim // Instruction operands. 1722218893Sdim bits<5> Vd; 1723218893Sdim bits<5> Vm; 1724218893Sdim 1725218893Sdim let Inst{15-12} = Vd{3-0}; 1726218893Sdim let Inst{22} = Vd{4}; 1727218893Sdim let Inst{3-0} = Vm{3-0}; 1728218893Sdim let Inst{5} = Vm{4}; 1729198396Srdivacky} 1730198396Srdivacky 1731194710Sed// NEON 2 vector register with immediate. 1732198396Srdivackyclass N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1733206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1734199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1735206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1736212904Sdim let Inst{24} = op24; 1737212904Sdim let Inst{23} = op23; 1738194710Sed let Inst{11-8} = op11_8; 1739212904Sdim let Inst{7} = op7; 1740212904Sdim let Inst{6} = op6; 1741212904Sdim let Inst{4} = op4; 1742218893Sdim 1743218893Sdim // Instruction operands. 1744218893Sdim bits<5> Vd; 1745218893Sdim bits<5> Vm; 1746218893Sdim bits<6> SIMM; 1747218893Sdim 1748218893Sdim let Inst{15-12} = Vd{3-0}; 1749218893Sdim let Inst{22} = Vd{4}; 1750218893Sdim let Inst{3-0} = Vm{3-0}; 1751218893Sdim let Inst{5} = Vm{4}; 1752218893Sdim let Inst{21-16} = SIMM{5-0}; 1753194710Sed} 1754194710Sed 1755194710Sed// NEON 3 vector register format. 1756221345Sdim 1757223017Sdimclass N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1758223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1759223017Sdim string opc, string dt, string asm, string cstr, 1760223017Sdim list<dag> pattern> 1761206083Srdivacky : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1762212904Sdim let Inst{24} = op24; 1763212904Sdim let Inst{23} = op23; 1764194710Sed let Inst{21-20} = op21_20; 1765212904Sdim let Inst{11-8} = op11_8; 1766212904Sdim let Inst{6} = op6; 1767212904Sdim let Inst{4} = op4; 1768221345Sdim} 1769218893Sdim 1770221345Sdimclass N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1771221345Sdim dag oops, dag iops, Format f, InstrItinClass itin, 1772221345Sdim string opc, string dt, string asm, string cstr, list<dag> pattern> 1773221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1774221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1775221345Sdim 1776218893Sdim // Instruction operands. 1777218893Sdim bits<5> Vd; 1778218893Sdim bits<5> Vn; 1779218893Sdim bits<5> Vm; 1780218893Sdim 1781218893Sdim let Inst{15-12} = Vd{3-0}; 1782218893Sdim let Inst{22} = Vd{4}; 1783218893Sdim let Inst{19-16} = Vn{3-0}; 1784218893Sdim let Inst{7} = Vn{4}; 1785218893Sdim let Inst{3-0} = Vm{3-0}; 1786218893Sdim let Inst{5} = Vm{4}; 1787194710Sed} 1788194710Sed 1789223017Sdimclass N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1790223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1791223017Sdim string opc, string dt, string asm, string cstr, 1792223017Sdim list<dag> pattern> 1793221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1794221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1795221345Sdim 1796221345Sdim // Instruction operands. 1797221345Sdim bits<5> Vd; 1798221345Sdim bits<5> Vn; 1799221345Sdim bits<5> Vm; 1800221345Sdim bit lane; 1801221345Sdim 1802221345Sdim let Inst{15-12} = Vd{3-0}; 1803221345Sdim let Inst{22} = Vd{4}; 1804221345Sdim let Inst{19-16} = Vn{3-0}; 1805221345Sdim let Inst{7} = Vn{4}; 1806221345Sdim let Inst{3-0} = Vm{3-0}; 1807221345Sdim let Inst{5} = lane; 1808221345Sdim} 1809221345Sdim 1810223017Sdimclass N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1811223017Sdim bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1812223017Sdim string opc, string dt, string asm, string cstr, 1813223017Sdim list<dag> pattern> 1814221345Sdim : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1815221345Sdim oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1816221345Sdim 1817221345Sdim // Instruction operands. 1818221345Sdim bits<5> Vd; 1819221345Sdim bits<5> Vn; 1820221345Sdim bits<5> Vm; 1821221345Sdim bits<2> lane; 1822221345Sdim 1823221345Sdim let Inst{15-12} = Vd{3-0}; 1824221345Sdim let Inst{22} = Vd{4}; 1825221345Sdim let Inst{19-16} = Vn{3-0}; 1826221345Sdim let Inst{7} = Vn{4}; 1827221345Sdim let Inst{2-0} = Vm{2-0}; 1828221345Sdim let Inst{5} = lane{1}; 1829221345Sdim let Inst{3} = lane{0}; 1830221345Sdim} 1831221345Sdim 1832206083Srdivacky// Same as N3V except it doesn't have a data type suffix. 1833206083Srdivackyclass N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1834206083Srdivacky bit op4, 1835206083Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1836206083Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1837206083Srdivacky : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1838212904Sdim let Inst{24} = op24; 1839212904Sdim let Inst{23} = op23; 1840198396Srdivacky let Inst{21-20} = op21_20; 1841212904Sdim let Inst{11-8} = op11_8; 1842212904Sdim let Inst{6} = op6; 1843212904Sdim let Inst{4} = op4; 1844218893Sdim 1845218893Sdim // Instruction operands. 1846218893Sdim bits<5> Vd; 1847218893Sdim bits<5> Vn; 1848218893Sdim bits<5> Vm; 1849218893Sdim 1850218893Sdim let Inst{15-12} = Vd{3-0}; 1851218893Sdim let Inst{22} = Vd{4}; 1852218893Sdim let Inst{19-16} = Vn{3-0}; 1853218893Sdim let Inst{7} = Vn{4}; 1854218893Sdim let Inst{3-0} = Vm{3-0}; 1855218893Sdim let Inst{5} = Vm{4}; 1856198396Srdivacky} 1857198396Srdivacky 1858194710Sed// NEON VMOVs between scalar and core registers. 1859194710Sedclass NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1860198090Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1861199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1862218893Sdim : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain, 1863206083Srdivacky "", itin> { 1864194710Sed let Inst{27-20} = opcod1; 1865212904Sdim let Inst{11-8} = opcod2; 1866212904Sdim let Inst{6-5} = opcod3; 1867212904Sdim let Inst{4} = 1; 1868221345Sdim // A8.6.303, A8.6.328, A8.6.329 1869221345Sdim let Inst{3-0} = 0b0000; 1870199989Srdivacky 1871199989Srdivacky let OutOperandList = oops; 1872205407Srdivacky let InOperandList = !con(iops, (ins pred:$p)); 1873218893Sdim let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1874199989Srdivacky let Pattern = pattern; 1875194710Sed list<Predicate> Predicates = [HasNEON]; 1876218893Sdim 1877218893Sdim let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1878218893Sdim 1879218893Sdim bits<5> V; 1880218893Sdim bits<4> R; 1881218893Sdim bits<4> p; 1882218893Sdim bits<4> lane; 1883218893Sdim 1884218893Sdim let Inst{31-28} = p{3-0}; 1885218893Sdim let Inst{7} = V{4}; 1886218893Sdim let Inst{19-16} = V{3-0}; 1887218893Sdim let Inst{15-12} = R{3-0}; 1888194710Sed} 1889194710Sedclass NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1890198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1891199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1892210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 1893199989Srdivacky opc, dt, asm, pattern>; 1894194710Sedclass NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1895198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1896199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1897210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 1898199989Srdivacky opc, dt, asm, pattern>; 1899194710Sedclass NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1900198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1901199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1902210299Sed : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 1903199989Srdivacky opc, dt, asm, pattern>; 1904198090Srdivacky 1905206083Srdivacky// Vector Duplicate Lane (from scalar to all elements) 1906206083Srdivackyclass NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 1907206083Srdivacky InstrItinClass itin, string opc, string dt, string asm, 1908206083Srdivacky list<dag> pattern> 1909206083Srdivacky : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 1910206083Srdivacky let Inst{24-23} = 0b11; 1911206083Srdivacky let Inst{21-20} = 0b11; 1912206083Srdivacky let Inst{19-16} = op19_16; 1913212904Sdim let Inst{11-7} = 0b11000; 1914212904Sdim let Inst{6} = op6; 1915212904Sdim let Inst{4} = 0; 1916218893Sdim 1917218893Sdim bits<5> Vd; 1918218893Sdim bits<5> Vm; 1919218893Sdim bits<4> lane; 1920218893Sdim 1921218893Sdim let Inst{22} = Vd{4}; 1922218893Sdim let Inst{15-12} = Vd{3-0}; 1923218893Sdim let Inst{5} = Vm{4}; 1924218893Sdim let Inst{3-0} = Vm{3-0}; 1925206083Srdivacky} 1926206083Srdivacky 1927198090Srdivacky// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1928198090Srdivacky// for single-precision FP. 1929198090Srdivackyclass NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1930198090Srdivacky list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1931198090Srdivacky} 1932