ARMInstrFormats.td revision 223017
1290494Sbapt//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=// 2290494Sbapt// 3290494Sbapt// The LLVM Compiler Infrastructure 4290494Sbapt// 5127474Stjr// This file is distributed under the University of Illinois Open Source 6174990Sache// License. See LICENSE.TXT for details. 7290494Sbapt// 8290494Sbapt//===----------------------------------------------------------------------===// 9290494Sbapt 10290494Sbapt//===----------------------------------------------------------------------===// 11127474Stjr// 12290494Sbapt// ARM Instruction Format Definitions. 13290494Sbapt// 14290494Sbapt 15290494Sbapt// Format specifies the encoding used by the instruction. This is part of the 16290494Sbapt// ad-hoc solution used to emit machine instruction encodings by our machine 17290494Sbapt// code emitter. 18290494Sbaptclass Format<bits<6> val> { 19127474Stjr bits<6> Value = val; 20174990Sache} 21127474Stjr 22127474Stjrdef Pseudo : Format<0>; 23127474Stjrdef MulFrm : Format<1>; 24127474Stjrdef BrFrm : Format<2>; 25127474Stjrdef BrMiscFrm : Format<3>; 26127474Stjr 27127474Stjrdef DPFrm : Format<4>; 28127474Stjrdef DPSoRegFrm : Format<5>; 29127474Stjr 30127474Stjrdef LdFrm : Format<6>; 31127474Stjrdef StFrm : Format<7>; 32127474Stjrdef LdMiscFrm : Format<8>; 33127474Stjrdef StMiscFrm : Format<9>; 34127474Stjrdef LdStMulFrm : Format<10>; 35290494Sbapt 36290494Sbaptdef LdStExFrm : Format<11>; 37290494Sbapt 38290494Sbaptdef ArithMiscFrm : Format<12>; 39290494Sbaptdef SatFrm : Format<13>; 40290494Sbaptdef ExtFrm : Format<14>; 41290494Sbapt 42127474Stjrdef VFPUnaryFrm : Format<15>; 43127474Stjrdef VFPBinaryFrm : Format<16>; 44127474Stjrdef VFPConv1Frm : Format<17>; 45127474Stjrdef VFPConv2Frm : Format<18>; 46127474Stjrdef VFPConv3Frm : Format<19>; 47127474Stjrdef VFPConv4Frm : Format<20>; 48127474Stjrdef VFPConv5Frm : Format<21>; 49127474Stjrdef VFPLdStFrm : Format<22>; 50127474Stjrdef VFPLdStMulFrm : Format<23>; 51127474Stjrdef VFPMiscFrm : Format<24>; 52127474Stjr 53127474Stjrdef ThumbFrm : Format<25>; 54127474Stjrdef MiscFrm : Format<26>; 55127474Stjr 56302016Sumedef NGetLnFrm : Format<27>; 57127474Stjrdef NSetLnFrm : Format<28>; 58127474Stjrdef NDupFrm : Format<29>; 59290494Sbaptdef NLdStFrm : Format<30>; 60127474Stjrdef N1RegModImmFrm: Format<31>; 61290494Sbaptdef N2RegFrm : Format<32>; 62290494Sbaptdef NVCVTFrm : Format<33>; 63290494Sbaptdef NVDupLnFrm : Format<34>; 64127474Stjrdef N2RegVShLFrm : Format<35>; 65127474Stjrdef N2RegVShRFrm : Format<36>; 66290494Sbaptdef N3RegFrm : Format<37>; 67127474Stjrdef N3RegVShFrm : Format<38>; 68174990Sachedef NVExtFrm : Format<39>; 69127474Stjrdef NVMulSLFrm : Format<40>; 70127474Stjrdef NVTBLFrm : Format<41>; 71127474Stjr 72127474Stjr// Misc flags. 73127474Stjr 74127474Stjr// The instruction has an Rn register operand. 75127474Stjr// UnaryDP - Indicates this is a unary data processing instruction, i.e. 76127474Stjr// it doesn't have a Rn operand. 77127474Stjrclass UnaryDP { bit isUnaryDataProc = 1; } 78127474Stjr 79127474Stjr// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 80127474Stjr// a 16-bit Thumb instruction if certain conditions are met. 81127474Stjrclass Xform16Bit { bit canXformTo16Bit = 1; } 82127474Stjr 83302016Sume//===----------------------------------------------------------------------===// 84127474Stjr// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 85127474Stjr// 86127474Stjr 87127474Stjr// FIXME: Once the JIT is MC-ized, these can go away. 88// Addressing mode. 89class AddrMode<bits<5> val> { 90 bits<5> Value = val; 91} 92def AddrModeNone : AddrMode<0>; 93def AddrMode1 : AddrMode<1>; 94def AddrMode2 : AddrMode<2>; 95def AddrMode3 : AddrMode<3>; 96def AddrMode4 : AddrMode<4>; 97def AddrMode5 : AddrMode<5>; 98def AddrMode6 : AddrMode<6>; 99def AddrModeT1_1 : AddrMode<7>; 100def AddrModeT1_2 : AddrMode<8>; 101def AddrModeT1_4 : AddrMode<9>; 102def AddrModeT1_s : AddrMode<10>; 103def AddrModeT2_i12 : AddrMode<11>; 104def AddrModeT2_i8 : AddrMode<12>; 105def AddrModeT2_so : AddrMode<13>; 106def AddrModeT2_pc : AddrMode<14>; 107def AddrModeT2_i8s4 : AddrMode<15>; 108def AddrMode_i12 : AddrMode<16>; 109 110// Instruction size. 111class SizeFlagVal<bits<3> val> { 112 bits<3> Value = val; 113} 114def SizeInvalid : SizeFlagVal<0>; // Unset. 115def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 116def Size8Bytes : SizeFlagVal<2>; 117def Size4Bytes : SizeFlagVal<3>; 118def Size2Bytes : SizeFlagVal<4>; 119 120// Load / store index mode. 121class IndexMode<bits<2> val> { 122 bits<2> Value = val; 123} 124def IndexModeNone : IndexMode<0>; 125def IndexModePre : IndexMode<1>; 126def IndexModePost : IndexMode<2>; 127def IndexModeUpd : IndexMode<3>; 128 129// Instruction execution domain. 130class Domain<bits<3> val> { 131 bits<3> Value = val; 132} 133def GenericDomain : Domain<0>; 134def VFPDomain : Domain<1>; // Instructions in VFP domain only 135def NeonDomain : Domain<2>; // Instructions in Neon domain only 136def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 137def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 138 139//===----------------------------------------------------------------------===// 140// ARM special operands. 141// 142 143def CondCodeOperand : AsmOperandClass { 144 let Name = "CondCode"; 145 let SuperClasses = []; 146} 147 148def CCOutOperand : AsmOperandClass { 149 let Name = "CCOut"; 150 let SuperClasses = []; 151} 152 153def MemBarrierOptOperand : AsmOperandClass { 154 let Name = "MemBarrierOpt"; 155 let SuperClasses = []; 156 let ParserMethod = "tryParseMemBarrierOptOperand"; 157} 158 159def ProcIFlagsOperand : AsmOperandClass { 160 let Name = "ProcIFlags"; 161 let SuperClasses = []; 162 let ParserMethod = "tryParseProcIFlagsOperand"; 163} 164 165def MSRMaskOperand : AsmOperandClass { 166 let Name = "MSRMask"; 167 let SuperClasses = []; 168 let ParserMethod = "tryParseMSRMaskOperand"; 169} 170 171// ARM imod and iflag operands, used only by the CPS instruction. 172def imod_op : Operand<i32> { 173 let PrintMethod = "printCPSIMod"; 174} 175 176def iflags_op : Operand<i32> { 177 let PrintMethod = "printCPSIFlag"; 178 let ParserMatchClass = ProcIFlagsOperand; 179} 180 181// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 182// register whose default is 0 (no register). 183def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 184 (ops (i32 14), (i32 zero_reg))> { 185 let PrintMethod = "printPredicateOperand"; 186 let ParserMatchClass = CondCodeOperand; 187} 188 189// Conditional code result for instructions whose 's' bit is set, e.g. subs. 190def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 191 let EncoderMethod = "getCCOutOpValue"; 192 let PrintMethod = "printSBitModifierOperand"; 193 let ParserMatchClass = CCOutOperand; 194} 195 196// Same as cc_out except it defaults to setting CPSR. 197def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 198 let EncoderMethod = "getCCOutOpValue"; 199 let PrintMethod = "printSBitModifierOperand"; 200 let ParserMatchClass = CCOutOperand; 201} 202 203// ARM special operands for disassembly only. 204// 205def setend_op : Operand<i32> { 206 let PrintMethod = "printSetendOperand"; 207} 208 209def msr_mask : Operand<i32> { 210 let PrintMethod = "printMSRMaskOperand"; 211 let ParserMatchClass = MSRMaskOperand; 212} 213 214// Shift Right Immediate - A shift right immediate is encoded differently from 215// other shift immediates. The imm6 field is encoded like so: 216// 217// Offset Encoding 218// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 219// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 220// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 221// 64 64 - <imm> is encoded in imm6<5:0> 222def shr_imm8 : Operand<i32> { 223 let EncoderMethod = "getShiftRight8Imm"; 224} 225def shr_imm16 : Operand<i32> { 226 let EncoderMethod = "getShiftRight16Imm"; 227} 228def shr_imm32 : Operand<i32> { 229 let EncoderMethod = "getShiftRight32Imm"; 230} 231def shr_imm64 : Operand<i32> { 232 let EncoderMethod = "getShiftRight64Imm"; 233} 234 235//===----------------------------------------------------------------------===// 236// ARM Instruction templates. 237// 238 239class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 240 Format f, Domain d, string cstr, InstrItinClass itin> 241 : Instruction { 242 let Namespace = "ARM"; 243 244 AddrMode AM = am; 245 SizeFlagVal SZ = sz; 246 IndexMode IM = im; 247 bits<2> IndexModeBits = IM.Value; 248 Format F = f; 249 bits<6> Form = F.Value; 250 Domain D = d; 251 bit isUnaryDataProc = 0; 252 bit canXformTo16Bit = 0; 253 254 // If this is a pseudo instruction, mark it isCodeGenOnly. 255 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 256 257 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. 258 let TSFlags{4-0} = AM.Value; 259 let TSFlags{7-5} = SZ.Value; 260 let TSFlags{9-8} = IndexModeBits; 261 let TSFlags{15-10} = Form; 262 let TSFlags{16} = isUnaryDataProc; 263 let TSFlags{17} = canXformTo16Bit; 264 let TSFlags{20-18} = D.Value; 265 266 let Constraints = cstr; 267 let Itinerary = itin; 268} 269 270class Encoding { 271 field bits<32> Inst; 272} 273 274class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 275 Format f, Domain d, string cstr, InstrItinClass itin> 276 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 277 278// This Encoding-less class is used by Thumb1 to specify the encoding bits later 279// on by adding flavors to specific instructions. 280class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 281 Format f, Domain d, string cstr, InstrItinClass itin> 282 : InstTemplate<am, sz, im, f, d, cstr, itin>; 283 284class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 285 // FIXME: This really should derive from InstTemplate instead, as pseudos 286 // don't need encoding information. TableGen doesn't like that 287 // currently. Need to figure out why and fix it. 288 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 289 "", itin> { 290 let OutOperandList = oops; 291 let InOperandList = iops; 292 let Pattern = pattern; 293 let isCodeGenOnly = 1; 294} 295 296// PseudoInst that's ARM-mode only. 297class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 298 list<dag> pattern> 299 : PseudoInst<oops, iops, itin, pattern> { 300 let SZ = sz; 301 list<Predicate> Predicates = [IsARM]; 302} 303 304// PseudoInst that's Thumb-mode only. 305class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 306 list<dag> pattern> 307 : PseudoInst<oops, iops, itin, pattern> { 308 let SZ = sz; 309 list<Predicate> Predicates = [IsThumb]; 310} 311 312// PseudoInst that's Thumb2-mode only. 313class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 314 list<dag> pattern> 315 : PseudoInst<oops, iops, itin, pattern> { 316 let SZ = sz; 317 list<Predicate> Predicates = [IsThumb2]; 318} 319// Almost all ARM instructions are predicable. 320class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 321 IndexMode im, Format f, InstrItinClass itin, 322 string opc, string asm, string cstr, 323 list<dag> pattern> 324 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 325 bits<4> p; 326 let Inst{31-28} = p; 327 let OutOperandList = oops; 328 let InOperandList = !con(iops, (ins pred:$p)); 329 let AsmString = !strconcat(opc, "${p}", asm); 330 let Pattern = pattern; 331 list<Predicate> Predicates = [IsARM]; 332} 333 334// A few are not predicable 335class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 336 IndexMode im, Format f, InstrItinClass itin, 337 string opc, string asm, string cstr, 338 list<dag> pattern> 339 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 340 let OutOperandList = oops; 341 let InOperandList = iops; 342 let AsmString = !strconcat(opc, asm); 343 let Pattern = pattern; 344 let isPredicable = 0; 345 list<Predicate> Predicates = [IsARM]; 346} 347 348// Same as I except it can optionally modify CPSR. Note it's modeled as an input 349// operand since by default it's a zero register. It will become an implicit def 350// once it's "flipped". 351class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 352 IndexMode im, Format f, InstrItinClass itin, 353 string opc, string asm, string cstr, 354 list<dag> pattern> 355 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 356 bits<4> p; // Predicate operand 357 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 358 let Inst{31-28} = p; 359 let Inst{20} = s; 360 361 let OutOperandList = oops; 362 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 363 let AsmString = !strconcat(opc, "${s}${p}", asm); 364 let Pattern = pattern; 365 list<Predicate> Predicates = [IsARM]; 366} 367 368// Special cases 369class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 370 IndexMode im, Format f, InstrItinClass itin, 371 string asm, string cstr, list<dag> pattern> 372 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 373 let OutOperandList = oops; 374 let InOperandList = iops; 375 let AsmString = asm; 376 let Pattern = pattern; 377 list<Predicate> Predicates = [IsARM]; 378} 379 380class AI<dag oops, dag iops, Format f, InstrItinClass itin, 381 string opc, string asm, list<dag> pattern> 382 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 383 opc, asm, "", pattern>; 384class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 385 string opc, string asm, list<dag> pattern> 386 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 387 opc, asm, "", pattern>; 388class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 389 string asm, list<dag> pattern> 390 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 391 asm, "", pattern>; 392class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 393 string opc, string asm, list<dag> pattern> 394 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 395 opc, asm, "", pattern>; 396 397// Ctrl flow instructions 398class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 399 string opc, string asm, list<dag> pattern> 400 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 401 opc, asm, "", pattern> { 402 let Inst{27-24} = opcod; 403} 404class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 405 string asm, list<dag> pattern> 406 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 407 asm, "", pattern> { 408 let Inst{27-24} = opcod; 409} 410 411// BR_JT instructions 412class JTI<dag oops, dag iops, InstrItinClass itin, 413 string asm, list<dag> pattern> 414 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 415 asm, "", pattern>; 416 417// Atomic load/store instructions 418class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 419 string opc, string asm, list<dag> pattern> 420 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 421 opc, asm, "", pattern> { 422 bits<4> Rt; 423 bits<4> Rn; 424 let Inst{27-23} = 0b00011; 425 let Inst{22-21} = opcod; 426 let Inst{20} = 1; 427 let Inst{19-16} = Rn; 428 let Inst{15-12} = Rt; 429 let Inst{11-0} = 0b111110011111; 430} 431class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 432 string opc, string asm, list<dag> pattern> 433 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 434 opc, asm, "", pattern> { 435 bits<4> Rd; 436 bits<4> Rt; 437 bits<4> addr; 438 let Inst{27-23} = 0b00011; 439 let Inst{22-21} = opcod; 440 let Inst{20} = 0; 441 let Inst{19-16} = addr; 442 let Inst{15-12} = Rd; 443 let Inst{11-4} = 0b11111001; 444 let Inst{3-0} = Rt; 445} 446class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 447 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> { 448 bits<4> Rt; 449 bits<4> Rt2; 450 bits<4> Rn; 451 let Inst{27-23} = 0b00010; 452 let Inst{22} = b; 453 let Inst{21-20} = 0b00; 454 let Inst{19-16} = Rn; 455 let Inst{15-12} = Rt; 456 let Inst{11-4} = 0b00001001; 457 let Inst{3-0} = Rt2; 458} 459 460// addrmode1 instructions 461class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 462 string opc, string asm, list<dag> pattern> 463 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 464 opc, asm, "", pattern> { 465 let Inst{24-21} = opcod; 466 let Inst{27-26} = 0b00; 467} 468class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 469 string opc, string asm, list<dag> pattern> 470 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 471 opc, asm, "", pattern> { 472 let Inst{24-21} = opcod; 473 let Inst{27-26} = 0b00; 474} 475class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 476 string asm, list<dag> pattern> 477 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 478 asm, "", pattern> { 479 let Inst{24-21} = opcod; 480 let Inst{27-26} = 0b00; 481} 482 483// loads 484 485// LDR/LDRB/STR/STRB/... 486class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 487 Format f, InstrItinClass itin, string opc, string asm, 488 list<dag> pattern> 489 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm, 490 "", pattern> { 491 let Inst{27-25} = op; 492 let Inst{24} = 1; // 24 == P 493 // 23 == U 494 let Inst{22} = isByte; 495 let Inst{21} = 0; // 21 == W 496 let Inst{20} = isLd; 497} 498// Indexed load/stores 499class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 500 IndexMode im, Format f, InstrItinClass itin, string opc, 501 string asm, string cstr, list<dag> pattern> 502 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin, 503 opc, asm, cstr, pattern> { 504 bits<4> Rt; 505 let Inst{27-26} = 0b01; 506 let Inst{24} = isPre; // P bit 507 let Inst{22} = isByte; // B bit 508 let Inst{21} = isPre; // W bit 509 let Inst{20} = isLd; // L bit 510 let Inst{15-12} = Rt; 511} 512class AI2stridx<bit isByte, bit isPre, dag oops, dag iops, 513 IndexMode im, Format f, InstrItinClass itin, string opc, 514 string asm, string cstr, list<dag> pattern> 515 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 516 pattern> { 517 // AM2 store w/ two operands: (GPR, am2offset) 518 // {13} 1 == Rm, 0 == imm12 519 // {12} isAdd 520 // {11-0} imm12/Rm 521 bits<14> offset; 522 bits<4> Rn; 523 let Inst{25} = offset{13}; 524 let Inst{23} = offset{12}; 525 let Inst{19-16} = Rn; 526 let Inst{11-0} = offset{11-0}; 527} 528// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 529// but for now use this class for STRT and STRBT. 530class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 531 IndexMode im, Format f, InstrItinClass itin, string opc, 532 string asm, string cstr, list<dag> pattern> 533 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 534 pattern> { 535 // AM2 store w/ two operands: (GPR, am2offset) 536 // {17-14} Rn 537 // {13} 1 == Rm, 0 == imm12 538 // {12} isAdd 539 // {11-0} imm12/Rm 540 bits<18> addr; 541 let Inst{25} = addr{13}; 542 let Inst{23} = addr{12}; 543 let Inst{19-16} = addr{17-14}; 544 let Inst{11-0} = addr{11-0}; 545} 546 547// addrmode3 instructions 548class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 549 InstrItinClass itin, string opc, string asm, list<dag> pattern> 550 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 551 opc, asm, "", pattern> { 552 bits<14> addr; 553 bits<4> Rt; 554 let Inst{27-25} = 0b000; 555 let Inst{24} = 1; // P bit 556 let Inst{23} = addr{8}; // U bit 557 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 558 let Inst{21} = 0; // W bit 559 let Inst{20} = op20; // L bit 560 let Inst{19-16} = addr{12-9}; // Rn 561 let Inst{15-12} = Rt; // Rt 562 let Inst{11-8} = addr{7-4}; // imm7_4/zero 563 let Inst{7-4} = op; 564 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 565} 566 567class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 568 IndexMode im, Format f, InstrItinClass itin, string opc, 569 string asm, string cstr, list<dag> pattern> 570 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin, 571 opc, asm, cstr, pattern> { 572 bits<4> Rt; 573 let Inst{27-25} = 0b000; 574 let Inst{24} = isPre; // P bit 575 let Inst{21} = isPre; // W bit 576 let Inst{20} = op20; // L bit 577 let Inst{15-12} = Rt; // Rt 578 let Inst{7-4} = op; 579} 580 581// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 582// but for now use this class for LDRSBT, LDRHT, LDSHT. 583class AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 584 IndexMode im, Format f, InstrItinClass itin, string opc, 585 string asm, string cstr, list<dag> pattern> 586 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin, 587 opc, asm, cstr, pattern> { 588 // {13} 1 == imm8, 0 == Rm 589 // {12-9} Rn 590 // {8} isAdd 591 // {7-4} imm7_4/zero 592 // {3-0} imm3_0/Rm 593 bits<14> addr; 594 bits<4> Rt; 595 let Inst{27-25} = 0b000; 596 let Inst{24} = isPre; // P bit 597 let Inst{23} = addr{8}; // U bit 598 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 599 let Inst{20} = op20; // L bit 600 let Inst{19-16} = addr{12-9}; // Rn 601 let Inst{15-12} = Rt; // Rt 602 let Inst{11-8} = addr{7-4}; // imm7_4/zero 603 let Inst{7-4} = op; 604 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 605 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3"; 606} 607 608class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops, 609 IndexMode im, Format f, InstrItinClass itin, string opc, 610 string asm, string cstr, list<dag> pattern> 611 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 612 pattern> { 613 // AM3 store w/ two operands: (GPR, am3offset) 614 bits<14> offset; 615 bits<4> Rt; 616 bits<4> Rn; 617 let Inst{27-25} = 0b000; 618 let Inst{23} = offset{8}; 619 let Inst{22} = offset{9}; 620 let Inst{19-16} = Rn; 621 let Inst{15-12} = Rt; // Rt 622 let Inst{11-8} = offset{7-4}; // imm7_4/zero 623 let Inst{7-4} = op; 624 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 625} 626 627// stores 628class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 629 string opc, string asm, list<dag> pattern> 630 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 631 opc, asm, "", pattern> { 632 bits<14> addr; 633 bits<4> Rt; 634 let Inst{27-25} = 0b000; 635 let Inst{24} = 1; // P bit 636 let Inst{23} = addr{8}; // U bit 637 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 638 let Inst{21} = 0; // W bit 639 let Inst{20} = 0; // L bit 640 let Inst{19-16} = addr{12-9}; // Rn 641 let Inst{15-12} = Rt; // Rt 642 let Inst{11-8} = addr{7-4}; // imm7_4/zero 643 let Inst{7-4} = op; 644 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 645} 646 647// Pre-indexed stores 648class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 649 string opc, string asm, string cstr, list<dag> pattern> 650 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 651 opc, asm, cstr, pattern> { 652 let Inst{4} = 1; 653 let Inst{5} = 1; // H bit 654 let Inst{6} = 0; // S bit 655 let Inst{7} = 1; 656 let Inst{20} = 0; // L bit 657 let Inst{21} = 1; // W bit 658 let Inst{24} = 1; // P bit 659 let Inst{27-25} = 0b000; 660} 661class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 662 string opc, string asm, string cstr, list<dag> pattern> 663 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 664 opc, asm, cstr, pattern> { 665 let Inst{4} = 1; 666 let Inst{5} = 1; // H bit 667 let Inst{6} = 1; // S bit 668 let Inst{7} = 1; 669 let Inst{20} = 0; // L bit 670 let Inst{21} = 1; // W bit 671 let Inst{24} = 1; // P bit 672 let Inst{27-25} = 0b000; 673} 674 675// Post-indexed stores 676class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 677 string opc, string asm, string cstr, list<dag> pattern> 678 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 679 opc, asm, cstr,pattern> { 680 // {13} 1 == imm8, 0 == Rm 681 // {12-9} Rn 682 // {8} isAdd 683 // {7-4} imm7_4/zero 684 // {3-0} imm3_0/Rm 685 bits<14> addr; 686 bits<4> Rt; 687 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 688 let Inst{4} = 1; 689 let Inst{5} = 1; // H bit 690 let Inst{6} = 0; // S bit 691 let Inst{7} = 1; 692 let Inst{11-8} = addr{7-4}; // imm7_4/zero 693 let Inst{15-12} = Rt; // Rt 694 let Inst{19-16} = addr{12-9}; // Rn 695 let Inst{20} = 0; // L bit 696 let Inst{21} = 0; // W bit 697 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 698 let Inst{23} = addr{8}; // U bit 699 let Inst{24} = 0; // P bit 700 let Inst{27-25} = 0b000; 701} 702class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 703 string opc, string asm, string cstr, list<dag> pattern> 704 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 705 opc, asm, cstr, pattern> { 706 let Inst{4} = 1; 707 let Inst{5} = 1; // H bit 708 let Inst{6} = 1; // S bit 709 let Inst{7} = 1; 710 let Inst{20} = 0; // L bit 711 let Inst{21} = 0; // W bit 712 let Inst{24} = 0; // P bit 713 let Inst{27-25} = 0b000; 714} 715 716// addrmode4 instructions 717class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 718 string asm, string cstr, list<dag> pattern> 719 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> { 720 bits<4> p; 721 bits<16> regs; 722 bits<4> Rn; 723 let Inst{31-28} = p; 724 let Inst{27-25} = 0b100; 725 let Inst{22} = 0; // S bit 726 let Inst{19-16} = Rn; 727 let Inst{15-0} = regs; 728} 729 730// Unsigned multiply, multiply-accumulate instructions. 731class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 732 string opc, string asm, list<dag> pattern> 733 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 734 opc, asm, "", pattern> { 735 let Inst{7-4} = 0b1001; 736 let Inst{20} = 0; // S bit 737 let Inst{27-21} = opcod; 738} 739class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 740 string opc, string asm, list<dag> pattern> 741 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 742 opc, asm, "", pattern> { 743 let Inst{7-4} = 0b1001; 744 let Inst{27-21} = opcod; 745} 746 747// Most significant word multiply 748class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 749 InstrItinClass itin, string opc, string asm, list<dag> pattern> 750 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 751 opc, asm, "", pattern> { 752 bits<4> Rd; 753 bits<4> Rn; 754 bits<4> Rm; 755 let Inst{7-4} = opc7_4; 756 let Inst{20} = 1; 757 let Inst{27-21} = opcod; 758 let Inst{19-16} = Rd; 759 let Inst{11-8} = Rm; 760 let Inst{3-0} = Rn; 761} 762// MSW multiple w/ Ra operand 763class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 764 InstrItinClass itin, string opc, string asm, list<dag> pattern> 765 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 766 bits<4> Ra; 767 let Inst{15-12} = Ra; 768} 769 770// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 771class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 772 InstrItinClass itin, string opc, string asm, list<dag> pattern> 773 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 774 opc, asm, "", pattern> { 775 bits<4> Rn; 776 bits<4> Rm; 777 let Inst{4} = 0; 778 let Inst{7} = 1; 779 let Inst{20} = 0; 780 let Inst{27-21} = opcod; 781 let Inst{6-5} = bit6_5; 782 let Inst{11-8} = Rm; 783 let Inst{3-0} = Rn; 784} 785class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 786 InstrItinClass itin, string opc, string asm, list<dag> pattern> 787 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 788 bits<4> Rd; 789 let Inst{19-16} = Rd; 790} 791 792// AMulxyI with Ra operand 793class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 794 InstrItinClass itin, string opc, string asm, list<dag> pattern> 795 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 796 bits<4> Ra; 797 let Inst{15-12} = Ra; 798} 799// SMLAL* 800class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 801 InstrItinClass itin, string opc, string asm, list<dag> pattern> 802 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 803 bits<4> RdLo; 804 bits<4> RdHi; 805 let Inst{19-16} = RdHi; 806 let Inst{15-12} = RdLo; 807} 808 809// Extend instructions. 810class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 811 string opc, string asm, list<dag> pattern> 812 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 813 opc, asm, "", pattern> { 814 // All AExtI instructions have Rd and Rm register operands. 815 bits<4> Rd; 816 bits<4> Rm; 817 let Inst{15-12} = Rd; 818 let Inst{3-0} = Rm; 819 let Inst{7-4} = 0b0111; 820 let Inst{9-8} = 0b00; 821 let Inst{27-20} = opcod; 822} 823 824// Misc Arithmetic instructions. 825class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 826 InstrItinClass itin, string opc, string asm, list<dag> pattern> 827 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 828 opc, asm, "", pattern> { 829 bits<4> Rd; 830 bits<4> Rm; 831 let Inst{27-20} = opcod; 832 let Inst{19-16} = 0b1111; 833 let Inst{15-12} = Rd; 834 let Inst{11-8} = 0b1111; 835 let Inst{7-4} = opc7_4; 836 let Inst{3-0} = Rm; 837} 838 839// PKH instructions 840class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 841 string opc, string asm, list<dag> pattern> 842 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 843 opc, asm, "", pattern> { 844 bits<4> Rd; 845 bits<4> Rn; 846 bits<4> Rm; 847 bits<8> sh; 848 let Inst{27-20} = opcod; 849 let Inst{19-16} = Rn; 850 let Inst{15-12} = Rd; 851 let Inst{11-7} = sh{7-3}; 852 let Inst{6} = tb; 853 let Inst{5-4} = 0b01; 854 let Inst{3-0} = Rm; 855} 856 857//===----------------------------------------------------------------------===// 858 859// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 860class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 861 list<Predicate> Predicates = [IsARM]; 862} 863class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { 864 list<Predicate> Predicates = [IsARM, HasV5T]; 865} 866class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 867 list<Predicate> Predicates = [IsARM, HasV5TE]; 868} 869class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 870 list<Predicate> Predicates = [IsARM, HasV6]; 871} 872 873//===----------------------------------------------------------------------===// 874// Thumb Instruction Format Definitions. 875// 876 877class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 878 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 879 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 880 let OutOperandList = oops; 881 let InOperandList = iops; 882 let AsmString = asm; 883 let Pattern = pattern; 884 list<Predicate> Predicates = [IsThumb]; 885} 886 887// TI - Thumb instruction. 888class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 889 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 890 891// Two-address instructions 892class TIt<dag oops, dag iops, InstrItinClass itin, string asm, 893 list<dag> pattern> 894 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", 895 pattern>; 896 897// tBL, tBX 32-bit instructions 898class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 899 dag oops, dag iops, InstrItinClass itin, string asm, 900 list<dag> pattern> 901 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, 902 Encoding { 903 let Inst{31-27} = opcod1; 904 let Inst{15-14} = opcod2; 905 let Inst{12} = opcod3; 906} 907 908// Move to/from coprocessor instructions 909class T1Cop<dag oops, dag iops, string asm, list<dag> pattern> 910 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, NoItinerary, asm, "", pattern>, 911 Encoding, Requires<[IsThumb, HasV6]> { 912 let Inst{31-28} = 0b1110; 913} 914 915// BR_JT instructions 916class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 917 list<dag> pattern> 918 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 919 920// Thumb1 only 921class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 922 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 923 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 924 let OutOperandList = oops; 925 let InOperandList = iops; 926 let AsmString = asm; 927 let Pattern = pattern; 928 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 929} 930 931class T1I<dag oops, dag iops, InstrItinClass itin, 932 string asm, list<dag> pattern> 933 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 934class T1Ix2<dag oops, dag iops, InstrItinClass itin, 935 string asm, list<dag> pattern> 936 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 937 938// Two-address instructions 939class T1It<dag oops, dag iops, InstrItinClass itin, 940 string asm, string cstr, list<dag> pattern> 941 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 942 asm, cstr, pattern>; 943 944// Thumb1 instruction that can either be predicated or set CPSR. 945class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 946 InstrItinClass itin, 947 string opc, string asm, string cstr, list<dag> pattern> 948 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 949 let OutOperandList = !con(oops, (outs s_cc_out:$s)); 950 let InOperandList = !con(iops, (ins pred:$p)); 951 let AsmString = !strconcat(opc, "${s}${p}", asm); 952 let Pattern = pattern; 953 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 954} 955 956class T1sI<dag oops, dag iops, InstrItinClass itin, 957 string opc, string asm, list<dag> pattern> 958 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 959 960// Two-address instructions 961class T1sIt<dag oops, dag iops, InstrItinClass itin, 962 string opc, string asm, list<dag> pattern> 963 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 964 "$Rn = $Rdn", pattern>; 965 966// Thumb1 instruction that can be predicated. 967class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 968 InstrItinClass itin, 969 string opc, string asm, string cstr, list<dag> pattern> 970 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 971 let OutOperandList = oops; 972 let InOperandList = !con(iops, (ins pred:$p)); 973 let AsmString = !strconcat(opc, "${p}", asm); 974 let Pattern = pattern; 975 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 976} 977 978class T1pI<dag oops, dag iops, InstrItinClass itin, 979 string opc, string asm, list<dag> pattern> 980 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 981 982// Two-address instructions 983class T1pIt<dag oops, dag iops, InstrItinClass itin, 984 string opc, string asm, list<dag> pattern> 985 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 986 "$Rn = $Rdn", pattern>; 987 988class T1pIs<dag oops, dag iops, 989 InstrItinClass itin, string opc, string asm, list<dag> pattern> 990 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 991 992class Encoding16 : Encoding { 993 let Inst{31-16} = 0x0000; 994} 995 996// A6.2 16-bit Thumb instruction encoding 997class T1Encoding<bits<6> opcode> : Encoding16 { 998 let Inst{15-10} = opcode; 999} 1000 1001// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1002class T1General<bits<5> opcode> : Encoding16 { 1003 let Inst{15-14} = 0b00; 1004 let Inst{13-9} = opcode; 1005} 1006 1007// A6.2.2 Data-processing encoding. 1008class T1DataProcessing<bits<4> opcode> : Encoding16 { 1009 let Inst{15-10} = 0b010000; 1010 let Inst{9-6} = opcode; 1011} 1012 1013// A6.2.3 Special data instructions and branch and exchange encoding. 1014class T1Special<bits<4> opcode> : Encoding16 { 1015 let Inst{15-10} = 0b010001; 1016 let Inst{9-6} = opcode; 1017} 1018 1019// A6.2.4 Load/store single data item encoding. 1020class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1021 let Inst{15-12} = opA; 1022 let Inst{11-9} = opB; 1023} 1024class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1025 1026class T1BranchCond<bits<4> opcode> : Encoding16 { 1027 let Inst{15-12} = opcode; 1028} 1029 1030// Helper classes to encode Thumb1 loads and stores. For immediates, the 1031// following bits are used for "opA" (see A6.2.4): 1032// 1033// 0b0110 => Immediate, 4 bytes 1034// 0b1000 => Immediate, 2 bytes 1035// 0b0111 => Immediate, 1 byte 1036class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1037 InstrItinClass itin, string opc, string asm, 1038 list<dag> pattern> 1039 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 1040 T1LoadStore<0b0101, opcode> { 1041 bits<3> Rt; 1042 bits<8> addr; 1043 let Inst{8-6} = addr{5-3}; // Rm 1044 let Inst{5-3} = addr{2-0}; // Rn 1045 let Inst{2-0} = Rt; 1046} 1047class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1048 InstrItinClass itin, string opc, string asm, 1049 list<dag> pattern> 1050 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 1051 T1LoadStore<opA, {opB,?,?}> { 1052 bits<3> Rt; 1053 bits<8> addr; 1054 let Inst{10-6} = addr{7-3}; // imm5 1055 let Inst{5-3} = addr{2-0}; // Rn 1056 let Inst{2-0} = Rt; 1057} 1058 1059// A6.2.5 Miscellaneous 16-bit instructions encoding. 1060class T1Misc<bits<7> opcode> : Encoding16 { 1061 let Inst{15-12} = 0b1011; 1062 let Inst{11-5} = opcode; 1063} 1064 1065// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1066class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1067 InstrItinClass itin, 1068 string opc, string asm, string cstr, list<dag> pattern> 1069 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1070 let OutOperandList = oops; 1071 let InOperandList = !con(iops, (ins pred:$p)); 1072 let AsmString = !strconcat(opc, "${p}", asm); 1073 let Pattern = pattern; 1074 list<Predicate> Predicates = [IsThumb2]; 1075} 1076 1077// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1078// input operand since by default it's a zero register. It will become an 1079// implicit def once it's "flipped". 1080// 1081// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1082// more consistent. 1083class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1084 InstrItinClass itin, 1085 string opc, string asm, string cstr, list<dag> pattern> 1086 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1087 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1088 let Inst{20} = s; 1089 1090 let OutOperandList = oops; 1091 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1092 let AsmString = !strconcat(opc, "${s}${p}", asm); 1093 let Pattern = pattern; 1094 list<Predicate> Predicates = [IsThumb2]; 1095} 1096 1097// Special cases 1098class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1099 InstrItinClass itin, 1100 string asm, string cstr, list<dag> pattern> 1101 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1102 let OutOperandList = oops; 1103 let InOperandList = iops; 1104 let AsmString = asm; 1105 let Pattern = pattern; 1106 list<Predicate> Predicates = [IsThumb2]; 1107} 1108 1109class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1110 InstrItinClass itin, 1111 string asm, string cstr, list<dag> pattern> 1112 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1113 let OutOperandList = oops; 1114 let InOperandList = iops; 1115 let AsmString = asm; 1116 let Pattern = pattern; 1117 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1118} 1119 1120class T2I<dag oops, dag iops, InstrItinClass itin, 1121 string opc, string asm, list<dag> pattern> 1122 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1123class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1124 string opc, string asm, list<dag> pattern> 1125 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>; 1126class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1127 string opc, string asm, list<dag> pattern> 1128 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1129class T2Iso<dag oops, dag iops, InstrItinClass itin, 1130 string opc, string asm, list<dag> pattern> 1131 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1132class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1133 string opc, string asm, list<dag> pattern> 1134 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1135class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1136 string opc, string asm, list<dag> pattern> 1137 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1138 pattern> { 1139 bits<4> Rt; 1140 bits<4> Rt2; 1141 bits<13> addr; 1142 let Inst{31-25} = 0b1110100; 1143 let Inst{24} = P; 1144 let Inst{23} = addr{8}; 1145 let Inst{22} = 1; 1146 let Inst{21} = W; 1147 let Inst{20} = isLoad; 1148 let Inst{19-16} = addr{12-9}; 1149 let Inst{15-12} = Rt{3-0}; 1150 let Inst{11-8} = Rt2{3-0}; 1151 let Inst{7-0} = addr{7-0}; 1152} 1153 1154class T2sI<dag oops, dag iops, InstrItinClass itin, 1155 string opc, string asm, list<dag> pattern> 1156 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1157 1158class T2XI<dag oops, dag iops, InstrItinClass itin, 1159 string asm, list<dag> pattern> 1160 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1161class T2JTI<dag oops, dag iops, InstrItinClass itin, 1162 string asm, list<dag> pattern> 1163 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1164 1165// Move to/from coprocessor instructions 1166class T2Cop<dag oops, dag iops, string asm, list<dag> pattern> 1167 : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> { 1168 let Inst{31-28} = 0b1111; 1169} 1170 1171// Two-address instructions 1172class T2XIt<dag oops, dag iops, InstrItinClass itin, 1173 string asm, string cstr, list<dag> pattern> 1174 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>; 1175 1176// T2Iidxldst - Thumb2 indexed load / store instructions. 1177class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1178 dag oops, dag iops, 1179 AddrMode am, IndexMode im, InstrItinClass itin, 1180 string opc, string asm, string cstr, list<dag> pattern> 1181 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1182 let OutOperandList = oops; 1183 let InOperandList = !con(iops, (ins pred:$p)); 1184 let AsmString = !strconcat(opc, "${p}", asm); 1185 let Pattern = pattern; 1186 list<Predicate> Predicates = [IsThumb2]; 1187 let Inst{31-27} = 0b11111; 1188 let Inst{26-25} = 0b00; 1189 let Inst{24} = signed; 1190 let Inst{23} = 0; 1191 let Inst{22-21} = opcod; 1192 let Inst{20} = load; 1193 let Inst{11} = 1; 1194 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1195 let Inst{10} = pre; // The P bit. 1196 let Inst{8} = 1; // The W bit. 1197 1198 bits<9> addr; 1199 let Inst{7-0} = addr{7-0}; 1200 let Inst{9} = addr{8}; // Sign bit 1201 1202 bits<4> Rt; 1203 bits<4> Rn; 1204 let Inst{15-12} = Rt{3-0}; 1205 let Inst{19-16} = Rn{3-0}; 1206} 1207 1208// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1209class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1210 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1211} 1212 1213// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1214class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1215 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1216} 1217 1218// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. 1219class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { 1220 list<Predicate> Predicates = [IsThumb2, HasV6T2]; 1221} 1222 1223// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1224class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1225 list<Predicate> Predicates = [IsThumb2]; 1226} 1227 1228//===----------------------------------------------------------------------===// 1229 1230//===----------------------------------------------------------------------===// 1231// ARM VFP Instruction templates. 1232// 1233 1234// Almost all VFP instructions are predicable. 1235class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1236 IndexMode im, Format f, InstrItinClass itin, 1237 string opc, string asm, string cstr, list<dag> pattern> 1238 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1239 bits<4> p; 1240 let Inst{31-28} = p; 1241 let OutOperandList = oops; 1242 let InOperandList = !con(iops, (ins pred:$p)); 1243 let AsmString = !strconcat(opc, "${p}", asm); 1244 let Pattern = pattern; 1245 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1246 list<Predicate> Predicates = [HasVFP2]; 1247} 1248 1249// Special cases 1250class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1251 IndexMode im, Format f, InstrItinClass itin, 1252 string asm, string cstr, list<dag> pattern> 1253 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1254 bits<4> p; 1255 let Inst{31-28} = p; 1256 let OutOperandList = oops; 1257 let InOperandList = iops; 1258 let AsmString = asm; 1259 let Pattern = pattern; 1260 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1261 list<Predicate> Predicates = [HasVFP2]; 1262} 1263 1264class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1265 string opc, string asm, list<dag> pattern> 1266 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1267 opc, asm, "", pattern> { 1268 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1269} 1270 1271// ARM VFP addrmode5 loads and stores 1272class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1273 InstrItinClass itin, 1274 string opc, string asm, list<dag> pattern> 1275 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1276 VFPLdStFrm, itin, opc, asm, "", pattern> { 1277 // Instruction operands. 1278 bits<5> Dd; 1279 bits<13> addr; 1280 1281 // Encode instruction operands. 1282 let Inst{23} = addr{8}; // U (add = (U == '1')) 1283 let Inst{22} = Dd{4}; 1284 let Inst{19-16} = addr{12-9}; // Rn 1285 let Inst{15-12} = Dd{3-0}; 1286 let Inst{7-0} = addr{7-0}; // imm8 1287 1288 // TODO: Mark the instructions with the appropriate subtarget info. 1289 let Inst{27-24} = opcod1; 1290 let Inst{21-20} = opcod2; 1291 let Inst{11-9} = 0b101; 1292 let Inst{8} = 1; // Double precision 1293 1294 // Loads & stores operate on both NEON and VFP pipelines. 1295 let D = VFPNeonDomain; 1296} 1297 1298class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1299 InstrItinClass itin, 1300 string opc, string asm, list<dag> pattern> 1301 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1302 VFPLdStFrm, itin, opc, asm, "", pattern> { 1303 // Instruction operands. 1304 bits<5> Sd; 1305 bits<13> addr; 1306 1307 // Encode instruction operands. 1308 let Inst{23} = addr{8}; // U (add = (U == '1')) 1309 let Inst{22} = Sd{0}; 1310 let Inst{19-16} = addr{12-9}; // Rn 1311 let Inst{15-12} = Sd{4-1}; 1312 let Inst{7-0} = addr{7-0}; // imm8 1313 1314 // TODO: Mark the instructions with the appropriate subtarget info. 1315 let Inst{27-24} = opcod1; 1316 let Inst{21-20} = opcod2; 1317 let Inst{11-9} = 0b101; 1318 let Inst{8} = 0; // Single precision 1319 1320 // Loads & stores operate on both NEON and VFP pipelines. 1321 let D = VFPNeonDomain; 1322} 1323 1324// VFP Load / store multiple pseudo instructions. 1325class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1326 list<dag> pattern> 1327 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain, 1328 cstr, itin> { 1329 let OutOperandList = oops; 1330 let InOperandList = !con(iops, (ins pred:$p)); 1331 let Pattern = pattern; 1332 list<Predicate> Predicates = [HasVFP2]; 1333} 1334 1335// Load / store multiple 1336class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1337 string asm, string cstr, list<dag> pattern> 1338 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1339 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1340 // Instruction operands. 1341 bits<4> Rn; 1342 bits<13> regs; 1343 1344 // Encode instruction operands. 1345 let Inst{19-16} = Rn; 1346 let Inst{22} = regs{12}; 1347 let Inst{15-12} = regs{11-8}; 1348 let Inst{7-0} = regs{7-0}; 1349 1350 // TODO: Mark the instructions with the appropriate subtarget info. 1351 let Inst{27-25} = 0b110; 1352 let Inst{11-9} = 0b101; 1353 let Inst{8} = 1; // Double precision 1354} 1355 1356class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1357 string asm, string cstr, list<dag> pattern> 1358 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1359 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1360 // Instruction operands. 1361 bits<4> Rn; 1362 bits<13> regs; 1363 1364 // Encode instruction operands. 1365 let Inst{19-16} = Rn; 1366 let Inst{22} = regs{8}; 1367 let Inst{15-12} = regs{12-9}; 1368 let Inst{7-0} = regs{7-0}; 1369 1370 // TODO: Mark the instructions with the appropriate subtarget info. 1371 let Inst{27-25} = 0b110; 1372 let Inst{11-9} = 0b101; 1373 let Inst{8} = 0; // Single precision 1374} 1375 1376// Double precision, unary 1377class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1378 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1379 string asm, list<dag> pattern> 1380 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1381 // Instruction operands. 1382 bits<5> Dd; 1383 bits<5> Dm; 1384 1385 // Encode instruction operands. 1386 let Inst{3-0} = Dm{3-0}; 1387 let Inst{5} = Dm{4}; 1388 let Inst{15-12} = Dd{3-0}; 1389 let Inst{22} = Dd{4}; 1390 1391 let Inst{27-23} = opcod1; 1392 let Inst{21-20} = opcod2; 1393 let Inst{19-16} = opcod3; 1394 let Inst{11-9} = 0b101; 1395 let Inst{8} = 1; // Double precision 1396 let Inst{7-6} = opcod4; 1397 let Inst{4} = opcod5; 1398} 1399 1400// Double precision, binary 1401class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1402 dag iops, InstrItinClass itin, string opc, string asm, 1403 list<dag> pattern> 1404 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1405 // Instruction operands. 1406 bits<5> Dd; 1407 bits<5> Dn; 1408 bits<5> Dm; 1409 1410 // Encode instruction operands. 1411 let Inst{3-0} = Dm{3-0}; 1412 let Inst{5} = Dm{4}; 1413 let Inst{19-16} = Dn{3-0}; 1414 let Inst{7} = Dn{4}; 1415 let Inst{15-12} = Dd{3-0}; 1416 let Inst{22} = Dd{4}; 1417 1418 let Inst{27-23} = opcod1; 1419 let Inst{21-20} = opcod2; 1420 let Inst{11-9} = 0b101; 1421 let Inst{8} = 1; // Double precision 1422 let Inst{6} = op6; 1423 let Inst{4} = op4; 1424} 1425 1426// Single precision, unary 1427class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1428 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1429 string asm, list<dag> pattern> 1430 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1431 // Instruction operands. 1432 bits<5> Sd; 1433 bits<5> Sm; 1434 1435 // Encode instruction operands. 1436 let Inst{3-0} = Sm{4-1}; 1437 let Inst{5} = Sm{0}; 1438 let Inst{15-12} = Sd{4-1}; 1439 let Inst{22} = Sd{0}; 1440 1441 let Inst{27-23} = opcod1; 1442 let Inst{21-20} = opcod2; 1443 let Inst{19-16} = opcod3; 1444 let Inst{11-9} = 0b101; 1445 let Inst{8} = 0; // Single precision 1446 let Inst{7-6} = opcod4; 1447 let Inst{4} = opcod5; 1448} 1449 1450// Single precision unary, if no NEON. Same as ASuI except not available if 1451// NEON is enabled. 1452class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1453 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1454 string asm, list<dag> pattern> 1455 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1456 pattern> { 1457 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1458} 1459 1460// Single precision, binary 1461class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1462 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1463 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1464 // Instruction operands. 1465 bits<5> Sd; 1466 bits<5> Sn; 1467 bits<5> Sm; 1468 1469 // Encode instruction operands. 1470 let Inst{3-0} = Sm{4-1}; 1471 let Inst{5} = Sm{0}; 1472 let Inst{19-16} = Sn{4-1}; 1473 let Inst{7} = Sn{0}; 1474 let Inst{15-12} = Sd{4-1}; 1475 let Inst{22} = Sd{0}; 1476 1477 let Inst{27-23} = opcod1; 1478 let Inst{21-20} = opcod2; 1479 let Inst{11-9} = 0b101; 1480 let Inst{8} = 0; // Single precision 1481 let Inst{6} = op6; 1482 let Inst{4} = op4; 1483} 1484 1485// Single precision binary, if no NEON. Same as ASbI except not available if 1486// NEON is enabled. 1487class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1488 dag iops, InstrItinClass itin, string opc, string asm, 1489 list<dag> pattern> 1490 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1491 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1492 1493 // Instruction operands. 1494 bits<5> Sd; 1495 bits<5> Sn; 1496 bits<5> Sm; 1497 1498 // Encode instruction operands. 1499 let Inst{3-0} = Sm{4-1}; 1500 let Inst{5} = Sm{0}; 1501 let Inst{19-16} = Sn{4-1}; 1502 let Inst{7} = Sn{0}; 1503 let Inst{15-12} = Sd{4-1}; 1504 let Inst{22} = Sd{0}; 1505} 1506 1507// VFP conversion instructions 1508class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1509 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1510 list<dag> pattern> 1511 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1512 let Inst{27-23} = opcod1; 1513 let Inst{21-20} = opcod2; 1514 let Inst{19-16} = opcod3; 1515 let Inst{11-8} = opcod4; 1516 let Inst{6} = 1; 1517 let Inst{4} = 0; 1518} 1519 1520// VFP conversion between floating-point and fixed-point 1521class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1522 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1523 list<dag> pattern> 1524 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1525 // size (fixed-point number): sx == 0 ? 16 : 32 1526 let Inst{7} = op5; // sx 1527} 1528 1529// VFP conversion instructions, if no NEON 1530class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1531 dag oops, dag iops, InstrItinClass itin, 1532 string opc, string asm, list<dag> pattern> 1533 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1534 pattern> { 1535 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1536} 1537 1538class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1539 InstrItinClass itin, 1540 string opc, string asm, list<dag> pattern> 1541 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1542 let Inst{27-20} = opcod1; 1543 let Inst{11-8} = opcod2; 1544 let Inst{4} = 1; 1545} 1546 1547class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1548 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1549 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1550 1551class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1552 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1553 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1554 1555class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1556 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1557 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1558 1559class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1560 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1561 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1562 1563//===----------------------------------------------------------------------===// 1564 1565//===----------------------------------------------------------------------===// 1566// ARM NEON Instruction templates. 1567// 1568 1569class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1570 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1571 list<dag> pattern> 1572 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1573 let OutOperandList = oops; 1574 let InOperandList = !con(iops, (ins pred:$p)); 1575 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1576 let Pattern = pattern; 1577 list<Predicate> Predicates = [HasNEON]; 1578} 1579 1580// Same as NeonI except it does not have a "data type" specifier. 1581class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1582 InstrItinClass itin, string opc, string asm, string cstr, 1583 list<dag> pattern> 1584 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1585 let OutOperandList = oops; 1586 let InOperandList = !con(iops, (ins pred:$p)); 1587 let AsmString = !strconcat(opc, "${p}", "\t", asm); 1588 let Pattern = pattern; 1589 list<Predicate> Predicates = [HasNEON]; 1590} 1591 1592class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1593 dag oops, dag iops, InstrItinClass itin, 1594 string opc, string dt, string asm, string cstr, list<dag> pattern> 1595 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1596 cstr, pattern> { 1597 let Inst{31-24} = 0b11110100; 1598 let Inst{23} = op23; 1599 let Inst{21-20} = op21_20; 1600 let Inst{11-8} = op11_8; 1601 let Inst{7-4} = op7_4; 1602 1603 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1604 1605 bits<5> Vd; 1606 bits<6> Rn; 1607 bits<4> Rm; 1608 1609 let Inst{22} = Vd{4}; 1610 let Inst{15-12} = Vd{3-0}; 1611 let Inst{19-16} = Rn{3-0}; 1612 let Inst{3-0} = Rm{3-0}; 1613} 1614 1615class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1616 dag oops, dag iops, InstrItinClass itin, 1617 string opc, string dt, string asm, string cstr, list<dag> pattern> 1618 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1619 dt, asm, cstr, pattern> { 1620 bits<3> lane; 1621} 1622 1623class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1624 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1625 itin> { 1626 let OutOperandList = oops; 1627 let InOperandList = !con(iops, (ins pred:$p)); 1628 list<Predicate> Predicates = [HasNEON]; 1629} 1630 1631class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1632 list<dag> pattern> 1633 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1634 itin> { 1635 let OutOperandList = oops; 1636 let InOperandList = !con(iops, (ins pred:$p)); 1637 let Pattern = pattern; 1638 list<Predicate> Predicates = [HasNEON]; 1639} 1640 1641class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1642 string opc, string dt, string asm, string cstr, list<dag> pattern> 1643 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1644 pattern> { 1645 let Inst{31-25} = 0b1111001; 1646 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1647} 1648 1649class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1650 string opc, string asm, string cstr, list<dag> pattern> 1651 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1652 cstr, pattern> { 1653 let Inst{31-25} = 0b1111001; 1654 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1655} 1656 1657// NEON "one register and a modified immediate" format. 1658class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1659 bit op5, bit op4, 1660 dag oops, dag iops, InstrItinClass itin, 1661 string opc, string dt, string asm, string cstr, 1662 list<dag> pattern> 1663 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1664 let Inst{23} = op23; 1665 let Inst{21-19} = op21_19; 1666 let Inst{11-8} = op11_8; 1667 let Inst{7} = op7; 1668 let Inst{6} = op6; 1669 let Inst{5} = op5; 1670 let Inst{4} = op4; 1671 1672 // Instruction operands. 1673 bits<5> Vd; 1674 bits<13> SIMM; 1675 1676 let Inst{15-12} = Vd{3-0}; 1677 let Inst{22} = Vd{4}; 1678 let Inst{24} = SIMM{7}; 1679 let Inst{18-16} = SIMM{6-4}; 1680 let Inst{3-0} = SIMM{3-0}; 1681} 1682 1683// NEON 2 vector register format. 1684class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1685 bits<5> op11_7, bit op6, bit op4, 1686 dag oops, dag iops, InstrItinClass itin, 1687 string opc, string dt, string asm, string cstr, list<dag> pattern> 1688 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1689 let Inst{24-23} = op24_23; 1690 let Inst{21-20} = op21_20; 1691 let Inst{19-18} = op19_18; 1692 let Inst{17-16} = op17_16; 1693 let Inst{11-7} = op11_7; 1694 let Inst{6} = op6; 1695 let Inst{4} = op4; 1696 1697 // Instruction operands. 1698 bits<5> Vd; 1699 bits<5> Vm; 1700 1701 let Inst{15-12} = Vd{3-0}; 1702 let Inst{22} = Vd{4}; 1703 let Inst{3-0} = Vm{3-0}; 1704 let Inst{5} = Vm{4}; 1705} 1706 1707// Same as N2V except it doesn't have a datatype suffix. 1708class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1709 bits<5> op11_7, bit op6, bit op4, 1710 dag oops, dag iops, InstrItinClass itin, 1711 string opc, string asm, string cstr, list<dag> pattern> 1712 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1713 let Inst{24-23} = op24_23; 1714 let Inst{21-20} = op21_20; 1715 let Inst{19-18} = op19_18; 1716 let Inst{17-16} = op17_16; 1717 let Inst{11-7} = op11_7; 1718 let Inst{6} = op6; 1719 let Inst{4} = op4; 1720 1721 // Instruction operands. 1722 bits<5> Vd; 1723 bits<5> Vm; 1724 1725 let Inst{15-12} = Vd{3-0}; 1726 let Inst{22} = Vd{4}; 1727 let Inst{3-0} = Vm{3-0}; 1728 let Inst{5} = Vm{4}; 1729} 1730 1731// NEON 2 vector register with immediate. 1732class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1733 dag oops, dag iops, Format f, InstrItinClass itin, 1734 string opc, string dt, string asm, string cstr, list<dag> pattern> 1735 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1736 let Inst{24} = op24; 1737 let Inst{23} = op23; 1738 let Inst{11-8} = op11_8; 1739 let Inst{7} = op7; 1740 let Inst{6} = op6; 1741 let Inst{4} = op4; 1742 1743 // Instruction operands. 1744 bits<5> Vd; 1745 bits<5> Vm; 1746 bits<6> SIMM; 1747 1748 let Inst{15-12} = Vd{3-0}; 1749 let Inst{22} = Vd{4}; 1750 let Inst{3-0} = Vm{3-0}; 1751 let Inst{5} = Vm{4}; 1752 let Inst{21-16} = SIMM{5-0}; 1753} 1754 1755// NEON 3 vector register format. 1756 1757class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1758 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1759 string opc, string dt, string asm, string cstr, 1760 list<dag> pattern> 1761 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1762 let Inst{24} = op24; 1763 let Inst{23} = op23; 1764 let Inst{21-20} = op21_20; 1765 let Inst{11-8} = op11_8; 1766 let Inst{6} = op6; 1767 let Inst{4} = op4; 1768} 1769 1770class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1771 dag oops, dag iops, Format f, InstrItinClass itin, 1772 string opc, string dt, string asm, string cstr, list<dag> pattern> 1773 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1774 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1775 1776 // Instruction operands. 1777 bits<5> Vd; 1778 bits<5> Vn; 1779 bits<5> Vm; 1780 1781 let Inst{15-12} = Vd{3-0}; 1782 let Inst{22} = Vd{4}; 1783 let Inst{19-16} = Vn{3-0}; 1784 let Inst{7} = Vn{4}; 1785 let Inst{3-0} = Vm{3-0}; 1786 let Inst{5} = Vm{4}; 1787} 1788 1789class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1790 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1791 string opc, string dt, string asm, string cstr, 1792 list<dag> pattern> 1793 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1794 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1795 1796 // Instruction operands. 1797 bits<5> Vd; 1798 bits<5> Vn; 1799 bits<5> Vm; 1800 bit lane; 1801 1802 let Inst{15-12} = Vd{3-0}; 1803 let Inst{22} = Vd{4}; 1804 let Inst{19-16} = Vn{3-0}; 1805 let Inst{7} = Vn{4}; 1806 let Inst{3-0} = Vm{3-0}; 1807 let Inst{5} = lane; 1808} 1809 1810class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1811 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1812 string opc, string dt, string asm, string cstr, 1813 list<dag> pattern> 1814 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1815 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1816 1817 // Instruction operands. 1818 bits<5> Vd; 1819 bits<5> Vn; 1820 bits<5> Vm; 1821 bits<2> lane; 1822 1823 let Inst{15-12} = Vd{3-0}; 1824 let Inst{22} = Vd{4}; 1825 let Inst{19-16} = Vn{3-0}; 1826 let Inst{7} = Vn{4}; 1827 let Inst{2-0} = Vm{2-0}; 1828 let Inst{5} = lane{1}; 1829 let Inst{3} = lane{0}; 1830} 1831 1832// Same as N3V except it doesn't have a data type suffix. 1833class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1834 bit op4, 1835 dag oops, dag iops, Format f, InstrItinClass itin, 1836 string opc, string asm, string cstr, list<dag> pattern> 1837 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1838 let Inst{24} = op24; 1839 let Inst{23} = op23; 1840 let Inst{21-20} = op21_20; 1841 let Inst{11-8} = op11_8; 1842 let Inst{6} = op6; 1843 let Inst{4} = op4; 1844 1845 // Instruction operands. 1846 bits<5> Vd; 1847 bits<5> Vn; 1848 bits<5> Vm; 1849 1850 let Inst{15-12} = Vd{3-0}; 1851 let Inst{22} = Vd{4}; 1852 let Inst{19-16} = Vn{3-0}; 1853 let Inst{7} = Vn{4}; 1854 let Inst{3-0} = Vm{3-0}; 1855 let Inst{5} = Vm{4}; 1856} 1857 1858// NEON VMOVs between scalar and core registers. 1859class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1860 dag oops, dag iops, Format f, InstrItinClass itin, 1861 string opc, string dt, string asm, list<dag> pattern> 1862 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain, 1863 "", itin> { 1864 let Inst{27-20} = opcod1; 1865 let Inst{11-8} = opcod2; 1866 let Inst{6-5} = opcod3; 1867 let Inst{4} = 1; 1868 // A8.6.303, A8.6.328, A8.6.329 1869 let Inst{3-0} = 0b0000; 1870 1871 let OutOperandList = oops; 1872 let InOperandList = !con(iops, (ins pred:$p)); 1873 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1874 let Pattern = pattern; 1875 list<Predicate> Predicates = [HasNEON]; 1876 1877 let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1878 1879 bits<5> V; 1880 bits<4> R; 1881 bits<4> p; 1882 bits<4> lane; 1883 1884 let Inst{31-28} = p{3-0}; 1885 let Inst{7} = V{4}; 1886 let Inst{19-16} = V{3-0}; 1887 let Inst{15-12} = R{3-0}; 1888} 1889class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1890 dag oops, dag iops, InstrItinClass itin, 1891 string opc, string dt, string asm, list<dag> pattern> 1892 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 1893 opc, dt, asm, pattern>; 1894class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1895 dag oops, dag iops, InstrItinClass itin, 1896 string opc, string dt, string asm, list<dag> pattern> 1897 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 1898 opc, dt, asm, pattern>; 1899class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1900 dag oops, dag iops, InstrItinClass itin, 1901 string opc, string dt, string asm, list<dag> pattern> 1902 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 1903 opc, dt, asm, pattern>; 1904 1905// Vector Duplicate Lane (from scalar to all elements) 1906class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 1907 InstrItinClass itin, string opc, string dt, string asm, 1908 list<dag> pattern> 1909 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 1910 let Inst{24-23} = 0b11; 1911 let Inst{21-20} = 0b11; 1912 let Inst{19-16} = op19_16; 1913 let Inst{11-7} = 0b11000; 1914 let Inst{6} = op6; 1915 let Inst{4} = 0; 1916 1917 bits<5> Vd; 1918 bits<5> Vm; 1919 bits<4> lane; 1920 1921 let Inst{22} = Vd{4}; 1922 let Inst{15-12} = Vd{3-0}; 1923 let Inst{5} = Vm{4}; 1924 let Inst{3-0} = Vm{3-0}; 1925} 1926 1927// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1928// for single-precision FP. 1929class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1930 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1931} 1932