ARMInstrFormats.td revision 201360
1193323Sed//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// 12193323Sed// ARM Instruction Format Definitions. 13193323Sed// 14193323Sed 15193323Sed// Format specifies the encoding used by the instruction. This is part of the 16193323Sed// ad-hoc solution used to emit machine instruction encodings by our machine 17193323Sed// code emitter. 18193323Sedclass Format<bits<5> val> { 19193323Sed bits<5> Value = val; 20193323Sed} 21193323Sed 22193323Seddef Pseudo : Format<0>; 23193323Seddef MulFrm : Format<1>; 24193323Seddef BrFrm : Format<2>; 25193323Seddef BrMiscFrm : Format<3>; 26193323Sed 27193323Seddef DPFrm : Format<4>; 28193323Seddef DPSoRegFrm : Format<5>; 29193323Sed 30193323Seddef LdFrm : Format<6>; 31193323Seddef StFrm : Format<7>; 32193323Seddef LdMiscFrm : Format<8>; 33193323Seddef StMiscFrm : Format<9>; 34193323Seddef LdStMulFrm : Format<10>; 35193323Sed 36200581Srdivackydef LdStExFrm : Format<28>; 37200581Srdivacky 38193323Seddef ArithMiscFrm : Format<11>; 39193323Seddef ExtFrm : Format<12>; 40193323Sed 41193323Seddef VFPUnaryFrm : Format<13>; 42193323Seddef VFPBinaryFrm : Format<14>; 43193323Seddef VFPConv1Frm : Format<15>; 44193323Seddef VFPConv2Frm : Format<16>; 45193323Seddef VFPConv3Frm : Format<17>; 46193323Seddef VFPConv4Frm : Format<18>; 47193323Seddef VFPConv5Frm : Format<19>; 48193323Seddef VFPLdStFrm : Format<20>; 49193323Seddef VFPLdStMulFrm : Format<21>; 50193323Seddef VFPMiscFrm : Format<22>; 51193323Sed 52193323Seddef ThumbFrm : Format<23>; 53193323Sed 54194710Seddef NEONFrm : Format<24>; 55194710Seddef NEONGetLnFrm : Format<25>; 56194710Seddef NEONSetLnFrm : Format<26>; 57194710Seddef NEONDupFrm : Format<27>; 58194710Sed 59198090Srdivacky// Misc flags. 60198090Srdivacky 61193323Sed// the instruction has a Rn register operand. 62198090Srdivacky// UnaryDP - Indicates this is a unary data processing instruction, i.e. 63198090Srdivacky// it doesn't have a Rn operand. 64198090Srdivackyclass UnaryDP { bit isUnaryDataProc = 1; } 65193323Sed 66198090Srdivacky// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 67198090Srdivacky// a 16-bit Thumb instruction if certain conditions are met. 68198090Srdivackyclass Xform16Bit { bit canXformTo16Bit = 1; } 69198090Srdivacky 70193323Sed//===----------------------------------------------------------------------===// 71195340Sed// ARM Instruction flags. These need to match ARMInstrInfo.h. 72195340Sed// 73193323Sed 74195340Sed// Addressing mode. 75195340Sedclass AddrMode<bits<4> val> { 76195340Sed bits<4> Value = val; 77195340Sed} 78195340Seddef AddrModeNone : AddrMode<0>; 79195340Seddef AddrMode1 : AddrMode<1>; 80195340Seddef AddrMode2 : AddrMode<2>; 81195340Seddef AddrMode3 : AddrMode<3>; 82195340Seddef AddrMode4 : AddrMode<4>; 83195340Seddef AddrMode5 : AddrMode<5>; 84195340Seddef AddrMode6 : AddrMode<6>; 85195340Seddef AddrModeT1_1 : AddrMode<7>; 86195340Seddef AddrModeT1_2 : AddrMode<8>; 87195340Seddef AddrModeT1_4 : AddrMode<9>; 88195340Seddef AddrModeT1_s : AddrMode<10>; 89198090Srdivackydef AddrModeT2_i12: AddrMode<11>; 90195340Seddef AddrModeT2_i8 : AddrMode<12>; 91195340Seddef AddrModeT2_so : AddrMode<13>; 92195340Seddef AddrModeT2_pc : AddrMode<14>; 93195340Seddef AddrModeT2_i8s4 : AddrMode<15>; 94195340Sed 95195340Sed// Instruction size. 96195340Sedclass SizeFlagVal<bits<3> val> { 97195340Sed bits<3> Value = val; 98195340Sed} 99195340Seddef SizeInvalid : SizeFlagVal<0>; // Unset. 100195340Seddef SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 101195340Seddef Size8Bytes : SizeFlagVal<2>; 102195340Seddef Size4Bytes : SizeFlagVal<3>; 103195340Seddef Size2Bytes : SizeFlagVal<4>; 104195340Sed 105195340Sed// Load / store index mode. 106195340Sedclass IndexMode<bits<2> val> { 107195340Sed bits<2> Value = val; 108195340Sed} 109195340Seddef IndexModeNone : IndexMode<0>; 110195340Seddef IndexModePre : IndexMode<1>; 111195340Seddef IndexModePost : IndexMode<2>; 112195340Sed 113198892Srdivacky// Instruction execution domain. 114198892Srdivackyclass Domain<bits<2> val> { 115198892Srdivacky bits<2> Value = val; 116198892Srdivacky} 117198892Srdivackydef GenericDomain : Domain<0>; 118198892Srdivackydef VFPDomain : Domain<1>; // Instructions in VFP domain only 119198892Srdivackydef NeonDomain : Domain<2>; // Instructions in Neon domain only 120198892Srdivackydef VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 121198892Srdivacky 122195340Sed//===----------------------------------------------------------------------===// 123195340Sed 124198090Srdivacky// ARM special operands. 125198090Srdivacky// 126198090Srdivacky 127198090Srdivacky// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 128198090Srdivacky// register whose default is 0 (no register). 129198090Srdivackydef pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 130198090Srdivacky (ops (i32 14), (i32 zero_reg))> { 131198090Srdivacky let PrintMethod = "printPredicateOperand"; 132198090Srdivacky} 133198090Srdivacky 134198090Srdivacky// Conditional code result for instructions whose 's' bit is set, e.g. subs. 135198090Srdivackydef cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 136198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 137198090Srdivacky} 138198090Srdivacky 139198090Srdivacky// Same as cc_out except it defaults to setting CPSR. 140198090Srdivackydef s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 141198090Srdivacky let PrintMethod = "printSBitModifierOperand"; 142198090Srdivacky} 143198090Srdivacky 144198090Srdivacky//===----------------------------------------------------------------------===// 145198090Srdivacky 146193323Sed// ARM Instruction templates. 147193323Sed// 148193323Sed 149201360Srdivackyclass InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 150201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 151193323Sed : Instruction { 152193323Sed let Namespace = "ARM"; 153193323Sed 154193323Sed // TSFlagsFields 155193323Sed AddrMode AM = am; 156193323Sed bits<4> AddrModeBits = AM.Value; 157193323Sed 158193323Sed SizeFlagVal SZ = sz; 159193323Sed bits<3> SizeFlag = SZ.Value; 160193323Sed 161193323Sed IndexMode IM = im; 162193323Sed bits<2> IndexModeBits = IM.Value; 163193323Sed 164193323Sed Format F = f; 165193323Sed bits<5> Form = F.Value; 166193323Sed 167198892Srdivacky Domain D = d; 168198892Srdivacky bits<2> Dom = D.Value; 169198892Srdivacky 170193323Sed // 171193323Sed // Attributes specific to ARM instructions... 172193323Sed // 173193323Sed bit isUnaryDataProc = 0; 174198090Srdivacky bit canXformTo16Bit = 0; 175193323Sed 176193323Sed let Constraints = cstr; 177198090Srdivacky let Itinerary = itin; 178193323Sed} 179193323Sed 180201360Srdivackyclass Encoding { 181201360Srdivacky field bits<32> Inst; 182201360Srdivacky} 183201360Srdivacky 184201360Srdivackyclass InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 185201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 186201360Srdivacky : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 187201360Srdivacky 188201360Srdivacky// This Encoding-less class is used by Thumb1 to specify the encoding bits later 189201360Srdivacky// on by adding flavors to specific instructions. 190201360Srdivackyclass InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 191201360Srdivacky Format f, Domain d, string cstr, InstrItinClass itin> 192201360Srdivacky : InstTemplate<am, sz, im, f, d, cstr, itin>; 193201360Srdivacky 194198090Srdivackyclass PseudoInst<dag oops, dag iops, InstrItinClass itin, 195198090Srdivacky string asm, list<dag> pattern> 196198892Srdivacky : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 197198892Srdivacky "", itin> { 198193323Sed let OutOperandList = oops; 199193323Sed let InOperandList = iops; 200193323Sed let AsmString = asm; 201193323Sed let Pattern = pattern; 202193323Sed} 203193323Sed 204193323Sed// Almost all ARM instructions are predicable. 205193323Sedclass I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 206198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 207198090Srdivacky string opc, string asm, string cstr, 208193323Sed list<dag> pattern> 209198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 210193323Sed let OutOperandList = oops; 211193323Sed let InOperandList = !con(iops, (ops pred:$p)); 212193323Sed let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 213193323Sed let Pattern = pattern; 214193323Sed list<Predicate> Predicates = [IsARM]; 215193323Sed} 216200581Srdivacky// A few are not predicable 217200581Srdivackyclass InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 218200581Srdivacky IndexMode im, Format f, InstrItinClass itin, 219200581Srdivacky string opc, string asm, string cstr, 220200581Srdivacky list<dag> pattern> 221200581Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 222200581Srdivacky let OutOperandList = oops; 223200581Srdivacky let InOperandList = iops; 224200581Srdivacky let AsmString = !strconcat(opc, asm); 225200581Srdivacky let Pattern = pattern; 226200581Srdivacky let isPredicable = 0; 227200581Srdivacky list<Predicate> Predicates = [IsARM]; 228200581Srdivacky} 229193323Sed 230193323Sed// Same as I except it can optionally modify CPSR. Note it's modeled as 231193323Sed// an input operand since by default it's a zero register. It will 232193323Sed// become an implicit def once it's "flipped". 233193323Sedclass sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 234198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 235198090Srdivacky string opc, string asm, string cstr, 236193323Sed list<dag> pattern> 237198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 238193323Sed let OutOperandList = oops; 239193323Sed let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 240193323Sed let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 241193323Sed let Pattern = pattern; 242193323Sed list<Predicate> Predicates = [IsARM]; 243193323Sed} 244193323Sed 245193323Sed// Special cases 246193323Sedclass XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 247198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 248198090Srdivacky string asm, string cstr, list<dag> pattern> 249198892Srdivacky : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 250193323Sed let OutOperandList = oops; 251193323Sed let InOperandList = iops; 252193323Sed let AsmString = asm; 253193323Sed let Pattern = pattern; 254193323Sed list<Predicate> Predicates = [IsARM]; 255193323Sed} 256193323Sed 257198090Srdivackyclass AI<dag oops, dag iops, Format f, InstrItinClass itin, 258198090Srdivacky string opc, string asm, list<dag> pattern> 259198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 260198090Srdivacky opc, asm, "", pattern>; 261198090Srdivackyclass AsI<dag oops, dag iops, Format f, InstrItinClass itin, 262198090Srdivacky string opc, string asm, list<dag> pattern> 263198090Srdivacky : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 264198090Srdivacky opc, asm, "", pattern>; 265198090Srdivackyclass AXI<dag oops, dag iops, Format f, InstrItinClass itin, 266193323Sed string asm, list<dag> pattern> 267198090Srdivacky : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 268193323Sed asm, "", pattern>; 269200581Srdivackyclass AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 270200581Srdivacky string opc, string asm, list<dag> pattern> 271200581Srdivacky : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 272200581Srdivacky opc, asm, "", pattern>; 273193323Sed 274193323Sed// Ctrl flow instructions 275198090Srdivackyclass ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 276198090Srdivacky string opc, string asm, list<dag> pattern> 277198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 278198090Srdivacky opc, asm, "", pattern> { 279193323Sed let Inst{27-24} = opcod; 280193323Sed} 281198090Srdivackyclass ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 282198090Srdivacky string asm, list<dag> pattern> 283198090Srdivacky : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 284198090Srdivacky asm, "", pattern> { 285193323Sed let Inst{27-24} = opcod; 286193323Sed} 287198090Srdivackyclass ABXIx2<dag oops, dag iops, InstrItinClass itin, 288198090Srdivacky string asm, list<dag> pattern> 289198090Srdivacky : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin, 290198090Srdivacky asm, "", pattern>; 291193323Sed 292193323Sed// BR_JT instructions 293198090Srdivackyclass JTI<dag oops, dag iops, InstrItinClass itin, 294198090Srdivacky string asm, list<dag> pattern> 295198090Srdivacky : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 296193323Sed asm, "", pattern>; 297193323Sed 298200581Srdivacky 299200581Srdivacky// Atomic load/store instructions 300200581Srdivacky 301200581Srdivackyclass AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 302200581Srdivacky string opc, string asm, list<dag> pattern> 303200581Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 304200581Srdivacky opc, asm, "", pattern> { 305200581Srdivacky let Inst{27-23} = 0b00011; 306200581Srdivacky let Inst{22-21} = opcod; 307200581Srdivacky let Inst{20} = 1; 308200581Srdivacky let Inst{11-0} = 0b111110011111; 309200581Srdivacky} 310200581Srdivackyclass AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 311200581Srdivacky string opc, string asm, list<dag> pattern> 312200581Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 313200581Srdivacky opc, asm, "", pattern> { 314200581Srdivacky let Inst{27-23} = 0b00011; 315200581Srdivacky let Inst{22-21} = opcod; 316200581Srdivacky let Inst{20} = 0; 317200581Srdivacky let Inst{11-4} = 0b11111001; 318200581Srdivacky} 319200581Srdivacky 320193323Sed// addrmode1 instructions 321198090Srdivackyclass AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 322198090Srdivacky string opc, string asm, list<dag> pattern> 323198090Srdivacky : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 324198090Srdivacky opc, asm, "", pattern> { 325193323Sed let Inst{24-21} = opcod; 326193323Sed let Inst{27-26} = {0,0}; 327193323Sed} 328198090Srdivackyclass AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 329198090Srdivacky string opc, string asm, list<dag> pattern> 330198090Srdivacky : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 331198090Srdivacky opc, asm, "", pattern> { 332193323Sed let Inst{24-21} = opcod; 333193323Sed let Inst{27-26} = {0,0}; 334193323Sed} 335198090Srdivackyclass AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 336198090Srdivacky string asm, list<dag> pattern> 337198090Srdivacky : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 338198090Srdivacky asm, "", pattern> { 339193323Sed let Inst{24-21} = opcod; 340193323Sed let Inst{27-26} = {0,0}; 341193323Sed} 342198090Srdivackyclass AI1x2<dag oops, dag iops, Format f, InstrItinClass itin, 343198090Srdivacky string opc, string asm, list<dag> pattern> 344198090Srdivacky : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin, 345198090Srdivacky opc, asm, "", pattern>; 346193323Sed 347193323Sed 348193323Sed// addrmode2 loads and stores 349198090Srdivackyclass AI2<dag oops, dag iops, Format f, InstrItinClass itin, 350198090Srdivacky string opc, string asm, list<dag> pattern> 351198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 352198090Srdivacky opc, asm, "", pattern> { 353193323Sed let Inst{27-26} = {0,1}; 354193323Sed} 355193323Sed 356193323Sed// loads 357198090Srdivackyclass AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 358198090Srdivacky string opc, string asm, list<dag> pattern> 359198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 360198090Srdivacky opc, asm, "", pattern> { 361193323Sed let Inst{20} = 1; // L bit 362193323Sed let Inst{21} = 0; // W bit 363193323Sed let Inst{22} = 0; // B bit 364193323Sed let Inst{24} = 1; // P bit 365193323Sed let Inst{27-26} = {0,1}; 366193323Sed} 367198090Srdivackyclass AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 368198090Srdivacky string asm, list<dag> pattern> 369198090Srdivacky : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 370193323Sed asm, "", pattern> { 371193323Sed let Inst{20} = 1; // L bit 372193323Sed let Inst{21} = 0; // W bit 373193323Sed let Inst{22} = 0; // B bit 374193323Sed let Inst{24} = 1; // P bit 375193323Sed let Inst{27-26} = {0,1}; 376193323Sed} 377198090Srdivackyclass AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 378198090Srdivacky string opc, string asm, list<dag> pattern> 379198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 380198090Srdivacky opc, asm, "", pattern> { 381193323Sed let Inst{20} = 1; // L bit 382193323Sed let Inst{21} = 0; // W bit 383193323Sed let Inst{22} = 1; // B bit 384193323Sed let Inst{24} = 1; // P bit 385193323Sed let Inst{27-26} = {0,1}; 386193323Sed} 387198090Srdivackyclass AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 388198090Srdivacky string asm, list<dag> pattern> 389198090Srdivacky : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 390193323Sed asm, "", pattern> { 391193323Sed let Inst{20} = 1; // L bit 392193323Sed let Inst{21} = 0; // W bit 393193323Sed let Inst{22} = 1; // B bit 394193323Sed let Inst{24} = 1; // P bit 395193323Sed let Inst{27-26} = {0,1}; 396193323Sed} 397193323Sed 398193323Sed// stores 399198090Srdivackyclass AI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 400198090Srdivacky string opc, string asm, list<dag> pattern> 401198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 402198090Srdivacky opc, asm, "", pattern> { 403193323Sed let Inst{20} = 0; // L bit 404193323Sed let Inst{21} = 0; // W bit 405193323Sed let Inst{22} = 0; // B bit 406193323Sed let Inst{24} = 1; // P bit 407193323Sed let Inst{27-26} = {0,1}; 408193323Sed} 409198090Srdivackyclass AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 410198090Srdivacky string asm, list<dag> pattern> 411198090Srdivacky : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 412193323Sed asm, "", pattern> { 413193323Sed let Inst{20} = 0; // L bit 414193323Sed let Inst{21} = 0; // W bit 415193323Sed let Inst{22} = 0; // B bit 416193323Sed let Inst{24} = 1; // P bit 417193323Sed let Inst{27-26} = {0,1}; 418193323Sed} 419198090Srdivackyclass AI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 420198090Srdivacky string opc, string asm, list<dag> pattern> 421198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 422198090Srdivacky opc, asm, "", pattern> { 423193323Sed let Inst{20} = 0; // L bit 424193323Sed let Inst{21} = 0; // W bit 425193323Sed let Inst{22} = 1; // B bit 426193323Sed let Inst{24} = 1; // P bit 427193323Sed let Inst{27-26} = {0,1}; 428193323Sed} 429198090Srdivackyclass AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 430198090Srdivacky string asm, list<dag> pattern> 431198090Srdivacky : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 432193323Sed asm, "", pattern> { 433193323Sed let Inst{20} = 0; // L bit 434193323Sed let Inst{21} = 0; // W bit 435193323Sed let Inst{22} = 1; // B bit 436193323Sed let Inst{24} = 1; // P bit 437193323Sed let Inst{27-26} = {0,1}; 438193323Sed} 439193323Sed 440193323Sed// Pre-indexed loads 441198090Srdivackyclass AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin, 442198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 443198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 444198090Srdivacky opc, asm, cstr, pattern> { 445193323Sed let Inst{20} = 1; // L bit 446193323Sed let Inst{21} = 1; // W bit 447193323Sed let Inst{22} = 0; // B bit 448193323Sed let Inst{24} = 1; // P bit 449193323Sed let Inst{27-26} = {0,1}; 450193323Sed} 451198090Srdivackyclass AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin, 452198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 453198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 454198090Srdivacky opc, asm, cstr, pattern> { 455193323Sed let Inst{20} = 1; // L bit 456193323Sed let Inst{21} = 1; // W bit 457193323Sed let Inst{22} = 1; // B bit 458193323Sed let Inst{24} = 1; // P bit 459193323Sed let Inst{27-26} = {0,1}; 460193323Sed} 461193323Sed 462193323Sed// Pre-indexed stores 463198090Srdivackyclass AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin, 464198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 465198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 466198090Srdivacky opc, asm, cstr, pattern> { 467193323Sed let Inst{20} = 0; // L bit 468193323Sed let Inst{21} = 1; // W bit 469193323Sed let Inst{22} = 0; // B bit 470193323Sed let Inst{24} = 1; // P bit 471193323Sed let Inst{27-26} = {0,1}; 472193323Sed} 473198090Srdivackyclass AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin, 474198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 475198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 476198090Srdivacky opc, asm, cstr, pattern> { 477193323Sed let Inst{20} = 0; // L bit 478193323Sed let Inst{21} = 1; // W bit 479193323Sed let Inst{22} = 1; // B bit 480193323Sed let Inst{24} = 1; // P bit 481193323Sed let Inst{27-26} = {0,1}; 482193323Sed} 483193323Sed 484193323Sed// Post-indexed loads 485198090Srdivackyclass AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin, 486198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 487198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 488198090Srdivacky opc, asm, cstr,pattern> { 489193323Sed let Inst{20} = 1; // L bit 490193323Sed let Inst{21} = 0; // W bit 491193323Sed let Inst{22} = 0; // B bit 492193323Sed let Inst{24} = 0; // P bit 493193323Sed let Inst{27-26} = {0,1}; 494193323Sed} 495198090Srdivackyclass AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin, 496198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 497198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 498198090Srdivacky opc, asm, cstr,pattern> { 499193323Sed let Inst{20} = 1; // L bit 500193323Sed let Inst{21} = 0; // W bit 501193323Sed let Inst{22} = 1; // B bit 502193323Sed let Inst{24} = 0; // P bit 503193323Sed let Inst{27-26} = {0,1}; 504193323Sed} 505193323Sed 506193323Sed// Post-indexed stores 507198090Srdivackyclass AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin, 508198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 509198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 510198090Srdivacky opc, asm, cstr,pattern> { 511193323Sed let Inst{20} = 0; // L bit 512193323Sed let Inst{21} = 0; // W bit 513193323Sed let Inst{22} = 0; // B bit 514193323Sed let Inst{24} = 0; // P bit 515193323Sed let Inst{27-26} = {0,1}; 516193323Sed} 517198090Srdivackyclass AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin, 518198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 519198090Srdivacky : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 520198090Srdivacky opc, asm, cstr,pattern> { 521193323Sed let Inst{20} = 0; // L bit 522193323Sed let Inst{21} = 0; // W bit 523193323Sed let Inst{22} = 1; // B bit 524193323Sed let Inst{24} = 0; // P bit 525193323Sed let Inst{27-26} = {0,1}; 526193323Sed} 527193323Sed 528193323Sed// addrmode3 instructions 529198090Srdivackyclass AI3<dag oops, dag iops, Format f, InstrItinClass itin, 530198090Srdivacky string opc, string asm, list<dag> pattern> 531198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 532198090Srdivacky opc, asm, "", pattern>; 533198090Srdivackyclass AXI3<dag oops, dag iops, Format f, InstrItinClass itin, 534198090Srdivacky string asm, list<dag> pattern> 535198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 536198090Srdivacky asm, "", pattern>; 537193323Sed 538193323Sed// loads 539198090Srdivackyclass AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 540198090Srdivacky string opc, string asm, list<dag> pattern> 541198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 542198090Srdivacky opc, asm, "", pattern> { 543193323Sed let Inst{4} = 1; 544193323Sed let Inst{5} = 1; // H bit 545193323Sed let Inst{6} = 0; // S bit 546193323Sed let Inst{7} = 1; 547193323Sed let Inst{20} = 1; // L bit 548193323Sed let Inst{21} = 0; // W bit 549193323Sed let Inst{24} = 1; // P bit 550198090Srdivacky let Inst{27-25} = 0b000; 551193323Sed} 552198090Srdivackyclass AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 553198090Srdivacky string asm, list<dag> pattern> 554198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 555193323Sed asm, "", pattern> { 556193323Sed let Inst{4} = 1; 557193323Sed let Inst{5} = 1; // H bit 558193323Sed let Inst{6} = 0; // S bit 559193323Sed let Inst{7} = 1; 560193323Sed let Inst{20} = 1; // L bit 561193323Sed let Inst{21} = 0; // W bit 562193323Sed let Inst{24} = 1; // P bit 563193323Sed} 564198090Srdivackyclass AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 565198090Srdivacky string opc, string asm, list<dag> pattern> 566198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 567198090Srdivacky opc, asm, "", pattern> { 568193323Sed let Inst{4} = 1; 569193323Sed let Inst{5} = 1; // H bit 570193323Sed let Inst{6} = 1; // S bit 571193323Sed let Inst{7} = 1; 572193323Sed let Inst{20} = 1; // L bit 573193323Sed let Inst{21} = 0; // W bit 574193323Sed let Inst{24} = 1; // P bit 575198090Srdivacky let Inst{27-25} = 0b000; 576193323Sed} 577198090Srdivackyclass AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 578198090Srdivacky string asm, list<dag> pattern> 579198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 580193323Sed asm, "", pattern> { 581193323Sed let Inst{4} = 1; 582193323Sed let Inst{5} = 1; // H bit 583193323Sed let Inst{6} = 1; // S bit 584193323Sed let Inst{7} = 1; 585193323Sed let Inst{20} = 1; // L bit 586193323Sed let Inst{21} = 0; // W bit 587193323Sed let Inst{24} = 1; // P bit 588193323Sed} 589198090Srdivackyclass AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 590198090Srdivacky string opc, string asm, list<dag> pattern> 591198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 592198090Srdivacky opc, asm, "", pattern> { 593193323Sed let Inst{4} = 1; 594193323Sed let Inst{5} = 0; // H bit 595193323Sed let Inst{6} = 1; // S bit 596193323Sed let Inst{7} = 1; 597193323Sed let Inst{20} = 1; // L bit 598193323Sed let Inst{21} = 0; // W bit 599193323Sed let Inst{24} = 1; // P bit 600198090Srdivacky let Inst{27-25} = 0b000; 601193323Sed} 602198090Srdivackyclass AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 603198090Srdivacky string asm, list<dag> pattern> 604198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 605193323Sed asm, "", pattern> { 606193323Sed let Inst{4} = 1; 607193323Sed let Inst{5} = 0; // H bit 608193323Sed let Inst{6} = 1; // S bit 609193323Sed let Inst{7} = 1; 610193323Sed let Inst{20} = 1; // L bit 611193323Sed let Inst{21} = 0; // W bit 612193323Sed let Inst{24} = 1; // P bit 613193323Sed} 614198090Srdivackyclass AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin, 615198090Srdivacky string opc, string asm, list<dag> pattern> 616198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 617198090Srdivacky opc, asm, "", pattern> { 618193323Sed let Inst{4} = 1; 619193323Sed let Inst{5} = 0; // H bit 620193323Sed let Inst{6} = 1; // S bit 621193323Sed let Inst{7} = 1; 622193323Sed let Inst{20} = 0; // L bit 623193323Sed let Inst{21} = 0; // W bit 624193323Sed let Inst{24} = 1; // P bit 625198090Srdivacky let Inst{27-25} = 0b000; 626193323Sed} 627193323Sed 628193323Sed// stores 629198090Srdivackyclass AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 630198090Srdivacky string opc, string asm, list<dag> pattern> 631198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 632198090Srdivacky opc, asm, "", pattern> { 633193323Sed let Inst{4} = 1; 634193323Sed let Inst{5} = 1; // H bit 635193323Sed let Inst{6} = 0; // S bit 636193323Sed let Inst{7} = 1; 637193323Sed let Inst{20} = 0; // L bit 638193323Sed let Inst{21} = 0; // W bit 639193323Sed let Inst{24} = 1; // P bit 640198090Srdivacky let Inst{27-25} = 0b000; 641193323Sed} 642198090Srdivackyclass AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 643198090Srdivacky string asm, list<dag> pattern> 644198090Srdivacky : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 645193323Sed asm, "", pattern> { 646193323Sed let Inst{4} = 1; 647193323Sed let Inst{5} = 1; // H bit 648193323Sed let Inst{6} = 0; // S bit 649193323Sed let Inst{7} = 1; 650193323Sed let Inst{20} = 0; // L bit 651193323Sed let Inst{21} = 0; // W bit 652193323Sed let Inst{24} = 1; // P bit 653193323Sed} 654198090Srdivackyclass AI3std<dag oops, dag iops, Format f, InstrItinClass itin, 655198090Srdivacky string opc, string asm, list<dag> pattern> 656198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 657198090Srdivacky opc, asm, "", pattern> { 658193323Sed let Inst{4} = 1; 659193323Sed let Inst{5} = 1; // H bit 660193323Sed let Inst{6} = 1; // S bit 661193323Sed let Inst{7} = 1; 662193323Sed let Inst{20} = 0; // L bit 663193323Sed let Inst{21} = 0; // W bit 664193323Sed let Inst{24} = 1; // P bit 665198090Srdivacky let Inst{27-25} = 0b000; 666193323Sed} 667193323Sed 668193323Sed// Pre-indexed loads 669198090Srdivackyclass AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin, 670198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 671198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 672198090Srdivacky opc, asm, cstr, pattern> { 673193323Sed let Inst{4} = 1; 674193323Sed let Inst{5} = 1; // H bit 675193323Sed let Inst{6} = 0; // S bit 676193323Sed let Inst{7} = 1; 677193323Sed let Inst{20} = 1; // L bit 678193323Sed let Inst{21} = 1; // W bit 679193323Sed let Inst{24} = 1; // P bit 680198090Srdivacky let Inst{27-25} = 0b000; 681193323Sed} 682198090Srdivackyclass AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin, 683198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 684198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 685198090Srdivacky opc, asm, cstr, pattern> { 686193323Sed let Inst{4} = 1; 687193323Sed let Inst{5} = 1; // H bit 688193323Sed let Inst{6} = 1; // S bit 689193323Sed let Inst{7} = 1; 690193323Sed let Inst{20} = 1; // L bit 691193323Sed let Inst{21} = 1; // W bit 692193323Sed let Inst{24} = 1; // P bit 693198090Srdivacky let Inst{27-25} = 0b000; 694193323Sed} 695198090Srdivackyclass AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin, 696198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 697198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 698198090Srdivacky opc, asm, cstr, pattern> { 699193323Sed let Inst{4} = 1; 700193323Sed let Inst{5} = 0; // H bit 701193323Sed let Inst{6} = 1; // S bit 702193323Sed let Inst{7} = 1; 703193323Sed let Inst{20} = 1; // L bit 704193323Sed let Inst{21} = 1; // W bit 705193323Sed let Inst{24} = 1; // P bit 706198090Srdivacky let Inst{27-25} = 0b000; 707193323Sed} 708193323Sed 709193323Sed// Pre-indexed stores 710198090Srdivackyclass AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 711198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 712198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 713198090Srdivacky opc, asm, cstr, pattern> { 714193323Sed let Inst{4} = 1; 715193323Sed let Inst{5} = 1; // H bit 716193323Sed let Inst{6} = 0; // S bit 717193323Sed let Inst{7} = 1; 718193323Sed let Inst{20} = 0; // L bit 719193323Sed let Inst{21} = 1; // W bit 720193323Sed let Inst{24} = 1; // P bit 721198090Srdivacky let Inst{27-25} = 0b000; 722193323Sed} 723193323Sed 724193323Sed// Post-indexed loads 725198090Srdivackyclass AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin, 726198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 727198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 728198090Srdivacky opc, asm, cstr,pattern> { 729193323Sed let Inst{4} = 1; 730193323Sed let Inst{5} = 1; // H bit 731193323Sed let Inst{6} = 0; // S bit 732193323Sed let Inst{7} = 1; 733193323Sed let Inst{20} = 1; // L bit 734193323Sed let Inst{21} = 1; // W bit 735193323Sed let Inst{24} = 0; // P bit 736198090Srdivacky let Inst{27-25} = 0b000; 737193323Sed} 738198090Srdivackyclass AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin, 739198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 740198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 741198090Srdivacky opc, asm, cstr,pattern> { 742193323Sed let Inst{4} = 1; 743193323Sed let Inst{5} = 1; // H bit 744193323Sed let Inst{6} = 1; // S bit 745193323Sed let Inst{7} = 1; 746193323Sed let Inst{20} = 1; // L bit 747193323Sed let Inst{21} = 1; // W bit 748193323Sed let Inst{24} = 0; // P bit 749198090Srdivacky let Inst{27-25} = 0b000; 750193323Sed} 751198090Srdivackyclass AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin, 752198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 753198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 754198090Srdivacky opc, asm, cstr,pattern> { 755193323Sed let Inst{4} = 1; 756193323Sed let Inst{5} = 0; // H bit 757193323Sed let Inst{6} = 1; // S bit 758193323Sed let Inst{7} = 1; 759193323Sed let Inst{20} = 1; // L bit 760193323Sed let Inst{21} = 1; // W bit 761193323Sed let Inst{24} = 0; // P bit 762198090Srdivacky let Inst{27-25} = 0b000; 763193323Sed} 764193323Sed 765193323Sed// Post-indexed stores 766198090Srdivackyclass AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 767198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 768198090Srdivacky : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 769198090Srdivacky opc, asm, cstr,pattern> { 770193323Sed let Inst{4} = 1; 771193323Sed let Inst{5} = 1; // H bit 772193323Sed let Inst{6} = 0; // S bit 773193323Sed let Inst{7} = 1; 774193323Sed let Inst{20} = 0; // L bit 775193323Sed let Inst{21} = 1; // W bit 776193323Sed let Inst{24} = 0; // P bit 777198090Srdivacky let Inst{27-25} = 0b000; 778193323Sed} 779193323Sed 780193323Sed 781193323Sed// addrmode4 instructions 782198090Srdivackyclass AXI4ld<dag oops, dag iops, Format f, InstrItinClass itin, 783198090Srdivacky string asm, list<dag> pattern> 784198090Srdivacky : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin, 785198090Srdivacky asm, "", pattern> { 786193323Sed let Inst{20} = 1; // L bit 787193323Sed let Inst{22} = 0; // S bit 788193323Sed let Inst{27-25} = 0b100; 789193323Sed} 790198090Srdivackyclass AXI4st<dag oops, dag iops, Format f, InstrItinClass itin, 791198090Srdivacky string asm, list<dag> pattern> 792198090Srdivacky : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin, 793198090Srdivacky asm, "", pattern> { 794193323Sed let Inst{20} = 0; // L bit 795193323Sed let Inst{22} = 0; // S bit 796193323Sed let Inst{27-25} = 0b100; 797193323Sed} 798193323Sed 799193323Sed// Unsigned multiply, multiply-accumulate instructions. 800198090Srdivackyclass AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 801198090Srdivacky string opc, string asm, list<dag> pattern> 802198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 803198090Srdivacky opc, asm, "", pattern> { 804193323Sed let Inst{7-4} = 0b1001; 805193323Sed let Inst{20} = 0; // S bit 806193323Sed let Inst{27-21} = opcod; 807193323Sed} 808198090Srdivackyclass AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 809198090Srdivacky string opc, string asm, list<dag> pattern> 810198090Srdivacky : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 811198090Srdivacky opc, asm, "", pattern> { 812193323Sed let Inst{7-4} = 0b1001; 813193323Sed let Inst{27-21} = opcod; 814193323Sed} 815193323Sed 816193323Sed// Most significant word multiply 817198090Srdivackyclass AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 818198090Srdivacky string opc, string asm, list<dag> pattern> 819198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 820198090Srdivacky opc, asm, "", pattern> { 821193323Sed let Inst{7-4} = 0b1001; 822193323Sed let Inst{20} = 1; 823193323Sed let Inst{27-21} = opcod; 824193323Sed} 825193323Sed 826193323Sed// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 827198090Srdivackyclass AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 828198090Srdivacky string opc, string asm, list<dag> pattern> 829198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 830198090Srdivacky opc, asm, "", pattern> { 831193323Sed let Inst{4} = 0; 832193323Sed let Inst{7} = 1; 833193323Sed let Inst{20} = 0; 834193323Sed let Inst{27-21} = opcod; 835193323Sed} 836193323Sed 837193323Sed// Extend instructions. 838198090Srdivackyclass AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 839198090Srdivacky string opc, string asm, list<dag> pattern> 840198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 841198090Srdivacky opc, asm, "", pattern> { 842193323Sed let Inst{7-4} = 0b0111; 843193323Sed let Inst{27-20} = opcod; 844193323Sed} 845193323Sed 846193323Sed// Misc Arithmetic instructions. 847198090Srdivackyclass AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 848198090Srdivacky string opc, string asm, list<dag> pattern> 849198090Srdivacky : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 850198090Srdivacky opc, asm, "", pattern> { 851193323Sed let Inst{27-20} = opcod; 852193323Sed} 853193323Sed 854193323Sed//===----------------------------------------------------------------------===// 855193323Sed 856193323Sed// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 857193323Sedclass ARMPat<dag pattern, dag result> : Pat<pattern, result> { 858193323Sed list<Predicate> Predicates = [IsARM]; 859193323Sed} 860193323Sedclass ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 861193323Sed list<Predicate> Predicates = [IsARM, HasV5TE]; 862193323Sed} 863193323Sedclass ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 864193323Sed list<Predicate> Predicates = [IsARM, HasV6]; 865193323Sed} 866193323Sed 867193323Sed//===----------------------------------------------------------------------===// 868193323Sed// 869193323Sed// Thumb Instruction Format Definitions. 870193323Sed// 871193323Sed 872193323Sed// TI - Thumb instruction. 873193323Sed 874198090Srdivackyclass ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 875198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 876201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 877198090Srdivacky let OutOperandList = oops; 878198090Srdivacky let InOperandList = iops; 879193323Sed let AsmString = asm; 880193323Sed let Pattern = pattern; 881193323Sed list<Predicate> Predicates = [IsThumb]; 882193323Sed} 883193323Sed 884198090Srdivackyclass TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 885198090Srdivacky : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 886193323Sed 887198090Srdivacky// Two-address instructions 888198090Srdivackyclass TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 889198090Srdivacky : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>; 890193323Sed 891201360Srdivacky// tBL, tBX 32-bit instructions 892201360Srdivackyclass TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 893201360Srdivacky dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 894201360Srdivacky : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding { 895201360Srdivacky let Inst{31-27} = opcod1; 896201360Srdivacky let Inst{15-14} = opcod2; 897201360Srdivacky let Inst{12} = opcod3; 898201360Srdivacky} 899198090Srdivacky 900193323Sed// BR_JT instructions 901198090Srdivackyclass TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 902198090Srdivacky : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 903193323Sed 904198090Srdivacky// Thumb1 only 905198090Srdivackyclass Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 906198090Srdivacky InstrItinClass itin, string asm, string cstr, list<dag> pattern> 907201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 908198090Srdivacky let OutOperandList = oops; 909198090Srdivacky let InOperandList = iops; 910198090Srdivacky let AsmString = asm; 911198090Srdivacky let Pattern = pattern; 912198090Srdivacky list<Predicate> Predicates = [IsThumb1Only]; 913194710Sed} 914193323Sed 915198090Srdivackyclass T1I<dag oops, dag iops, InstrItinClass itin, 916198090Srdivacky string asm, list<dag> pattern> 917198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 918198090Srdivackyclass T1Ix2<dag oops, dag iops, InstrItinClass itin, 919198090Srdivacky string asm, list<dag> pattern> 920198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 921198090Srdivackyclass T1JTI<dag oops, dag iops, InstrItinClass itin, 922198090Srdivacky string asm, list<dag> pattern> 923198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 924194710Sed 925198090Srdivacky// Two-address instructions 926198090Srdivackyclass T1It<dag oops, dag iops, InstrItinClass itin, 927198090Srdivacky string asm, list<dag> pattern> 928198090Srdivacky : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 929198090Srdivacky asm, "$lhs = $dst", pattern>; 930198090Srdivacky 931198090Srdivacky// Thumb1 instruction that can either be predicated or set CPSR. 932198090Srdivackyclass Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 933198090Srdivacky InstrItinClass itin, 934198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 935201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 936198090Srdivacky let OutOperandList = !con(oops, (ops s_cc_out:$s)); 937198090Srdivacky let InOperandList = !con(iops, (ops pred:$p)); 938198090Srdivacky let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 939194754Sed let Pattern = pattern; 940195098Sed list<Predicate> Predicates = [IsThumb1Only]; 941195098Sed} 942195098Sed 943198090Srdivackyclass T1sI<dag oops, dag iops, InstrItinClass itin, 944198090Srdivacky string opc, string asm, list<dag> pattern> 945198090Srdivacky : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 946195098Sed 947195098Sed// Two-address instructions 948198090Srdivackyclass T1sIt<dag oops, dag iops, InstrItinClass itin, 949198090Srdivacky string opc, string asm, list<dag> pattern> 950198090Srdivacky : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 951198090Srdivacky "$lhs = $dst", pattern>; 952195098Sed 953198090Srdivacky// Thumb1 instruction that can be predicated. 954198090Srdivackyclass Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 955198090Srdivacky InstrItinClass itin, 956198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 957201360Srdivacky : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 958198090Srdivacky let OutOperandList = oops; 959198090Srdivacky let InOperandList = !con(iops, (ops pred:$p)); 960198090Srdivacky let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 961198090Srdivacky let Pattern = pattern; 962195098Sed list<Predicate> Predicates = [IsThumb1Only]; 963195098Sed} 964195098Sed 965198090Srdivackyclass T1pI<dag oops, dag iops, InstrItinClass itin, 966198090Srdivacky string opc, string asm, list<dag> pattern> 967198090Srdivacky : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 968198090Srdivacky 969198090Srdivacky// Two-address instructions 970198090Srdivackyclass T1pIt<dag oops, dag iops, InstrItinClass itin, 971198090Srdivacky string opc, string asm, list<dag> pattern> 972198090Srdivacky : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 973198090Srdivacky "$lhs = $dst", pattern>; 974198090Srdivacky 975198090Srdivackyclass T1pI1<dag oops, dag iops, InstrItinClass itin, 976198090Srdivacky string opc, string asm, list<dag> pattern> 977198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>; 978198090Srdivackyclass T1pI2<dag oops, dag iops, InstrItinClass itin, 979198090Srdivacky string opc, string asm, list<dag> pattern> 980198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>; 981198090Srdivackyclass T1pI4<dag oops, dag iops, InstrItinClass itin, 982198090Srdivacky string opc, string asm, list<dag> pattern> 983198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>; 984198090Srdivackyclass T1pIs<dag oops, dag iops, 985198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 986198090Srdivacky : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 987198090Srdivacky 988201360Srdivackyclass Encoding16 : Encoding { 989201360Srdivacky let Inst{31-16} = 0x0000; 990201360Srdivacky} 991201360Srdivacky 992201360Srdivacky// A6.2 16-bit Thumb instruction encoding 993201360Srdivackyclass T1Encoding<bits<6> opcode> : Encoding16 { 994201360Srdivacky let Inst{15-10} = opcode; 995201360Srdivacky} 996201360Srdivacky 997201360Srdivacky// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 998201360Srdivackyclass T1General<bits<5> opcode> : Encoding16 { 999201360Srdivacky let Inst{15-14} = 0b00; 1000201360Srdivacky let Inst{13-9} = opcode; 1001201360Srdivacky} 1002201360Srdivacky 1003201360Srdivacky// A6.2.2 Data-processing encoding. 1004201360Srdivackyclass T1DataProcessing<bits<4> opcode> : Encoding16 { 1005201360Srdivacky let Inst{15-10} = 0b010000; 1006201360Srdivacky let Inst{9-6} = opcode; 1007201360Srdivacky} 1008201360Srdivacky 1009201360Srdivacky// A6.2.3 Special data instructions and branch and exchange encoding. 1010201360Srdivackyclass T1Special<bits<4> opcode> : Encoding16 { 1011201360Srdivacky let Inst{15-10} = 0b010001; 1012201360Srdivacky let Inst{9-6} = opcode; 1013201360Srdivacky} 1014201360Srdivacky 1015201360Srdivacky// A6.2.4 Load/store single data item encoding. 1016201360Srdivackyclass T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1017201360Srdivacky let Inst{15-12} = opA; 1018201360Srdivacky let Inst{11-9} = opB; 1019201360Srdivacky} 1020201360Srdivackyclass T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>; 1021201360Srdivackyclass T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes 1022201360Srdivackyclass T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte 1023201360Srdivackyclass T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes 1024201360Srdivackyclass T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1025201360Srdivacky 1026201360Srdivacky// A6.2.5 Miscellaneous 16-bit instructions encoding. 1027201360Srdivackyclass T1Misc<bits<7> opcode> : Encoding16 { 1028201360Srdivacky let Inst{15-12} = 0b1011; 1029201360Srdivacky let Inst{11-5} = opcode; 1030201360Srdivacky} 1031201360Srdivacky 1032195098Sed// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1033195098Sedclass Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1034198090Srdivacky InstrItinClass itin, 1035195098Sed string opc, string asm, string cstr, list<dag> pattern> 1036198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1037195098Sed let OutOperandList = oops; 1038195098Sed let InOperandList = !con(iops, (ops pred:$p)); 1039195098Sed let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1040195098Sed let Pattern = pattern; 1041195340Sed list<Predicate> Predicates = [IsThumb2]; 1042194754Sed} 1043194754Sed 1044195098Sed// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as 1045195098Sed// an input operand since by default it's a zero register. It will 1046195098Sed// become an implicit def once it's "flipped". 1047195098Sed// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1048195098Sed// more consistent. 1049195098Sedclass Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1050198090Srdivacky InstrItinClass itin, 1051195098Sed string opc, string asm, string cstr, list<dag> pattern> 1052198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1053195098Sed let OutOperandList = oops; 1054195098Sed let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 1055195098Sed let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 1056195098Sed let Pattern = pattern; 1057195340Sed list<Predicate> Predicates = [IsThumb2]; 1058195098Sed} 1059194754Sed 1060195098Sed// Special cases 1061195098Sedclass Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1062198090Srdivacky InstrItinClass itin, 1063195098Sed string asm, string cstr, list<dag> pattern> 1064198892Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1065195098Sed let OutOperandList = oops; 1066195098Sed let InOperandList = iops; 1067195098Sed let AsmString = asm; 1068195098Sed let Pattern = pattern; 1069195340Sed list<Predicate> Predicates = [IsThumb2]; 1070194754Sed} 1071194754Sed 1072200581Srdivackyclass ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1073200581Srdivacky InstrItinClass itin, 1074200581Srdivacky string asm, string cstr, list<dag> pattern> 1075200581Srdivacky : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1076200581Srdivacky let OutOperandList = oops; 1077200581Srdivacky let InOperandList = iops; 1078200581Srdivacky let AsmString = asm; 1079200581Srdivacky let Pattern = pattern; 1080200581Srdivacky list<Predicate> Predicates = [IsThumb1Only]; 1081200581Srdivacky} 1082200581Srdivacky 1083198090Srdivackyclass T2I<dag oops, dag iops, InstrItinClass itin, 1084198090Srdivacky string opc, string asm, list<dag> pattern> 1085198090Srdivacky : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1086198090Srdivackyclass T2Ii12<dag oops, dag iops, InstrItinClass itin, 1087198090Srdivacky string opc, string asm, list<dag> pattern> 1088198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>; 1089198090Srdivackyclass T2Ii8<dag oops, dag iops, InstrItinClass itin, 1090198090Srdivacky string opc, string asm, list<dag> pattern> 1091198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1092198090Srdivackyclass T2Iso<dag oops, dag iops, InstrItinClass itin, 1093198090Srdivacky string opc, string asm, list<dag> pattern> 1094198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1095198090Srdivackyclass T2Ipc<dag oops, dag iops, InstrItinClass itin, 1096198090Srdivacky string opc, string asm, list<dag> pattern> 1097198090Srdivacky : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1098201360Srdivackyclass T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin, 1099198090Srdivacky string opc, string asm, list<dag> pattern> 1100201360Srdivacky : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1101201360Srdivacky pattern> { 1102201360Srdivacky let Inst{31-27} = 0b11101; 1103201360Srdivacky let Inst{26-25} = 0b00; 1104201360Srdivacky let Inst{24} = P; 1105201360Srdivacky let Inst{23} = ?; // The U bit. 1106201360Srdivacky let Inst{22} = 1; 1107201360Srdivacky let Inst{21} = W; 1108201360Srdivacky let Inst{20} = load; 1109201360Srdivacky} 1110195098Sed 1111198090Srdivackyclass T2sI<dag oops, dag iops, InstrItinClass itin, 1112198090Srdivacky string opc, string asm, list<dag> pattern> 1113198090Srdivacky : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1114195098Sed 1115198090Srdivackyclass T2XI<dag oops, dag iops, InstrItinClass itin, 1116198090Srdivacky string asm, list<dag> pattern> 1117198090Srdivacky : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1118198090Srdivackyclass T2JTI<dag oops, dag iops, InstrItinClass itin, 1119198090Srdivacky string asm, list<dag> pattern> 1120198090Srdivacky : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1121195098Sed 1122198090Srdivackyclass T2Ix2<dag oops, dag iops, InstrItinClass itin, 1123198090Srdivacky string opc, string asm, list<dag> pattern> 1124198090Srdivacky : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>; 1125198090Srdivacky 1126198090Srdivacky 1127195340Sed// T2Iidxldst - Thumb2 indexed load / store instructions. 1128201360Srdivackyclass T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1129201360Srdivacky dag oops, dag iops, 1130201360Srdivacky AddrMode am, IndexMode im, InstrItinClass itin, 1131195340Sed string opc, string asm, string cstr, list<dag> pattern> 1132198892Srdivacky : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1133195340Sed let OutOperandList = oops; 1134195340Sed let InOperandList = !con(iops, (ops pred:$p)); 1135195340Sed let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1136195340Sed let Pattern = pattern; 1137195340Sed list<Predicate> Predicates = [IsThumb2]; 1138201360Srdivacky let Inst{31-27} = 0b11111; 1139201360Srdivacky let Inst{26-25} = 0b00; 1140201360Srdivacky let Inst{24} = signed; 1141201360Srdivacky let Inst{23} = 0; 1142201360Srdivacky let Inst{22-21} = opcod; 1143201360Srdivacky let Inst{20} = load; 1144201360Srdivacky let Inst{11} = 1; 1145201360Srdivacky // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1146201360Srdivacky let Inst{10} = pre; // The P bit. 1147201360Srdivacky let Inst{8} = 1; // The W bit. 1148195340Sed} 1149195340Sed 1150198090Srdivacky// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1151198090Srdivackyclass Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1152198090Srdivacky list<Predicate> Predicates = [IsThumb1Only, HasV5T]; 1153198090Srdivacky} 1154195340Sed 1155198090Srdivacky// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1156198090Srdivackyclass T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1157198090Srdivacky list<Predicate> Predicates = [IsThumb1Only]; 1158198090Srdivacky} 1159198090Srdivacky 1160195098Sed// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1161195098Sedclass T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1162195340Sed list<Predicate> Predicates = [IsThumb2]; 1163195098Sed} 1164195098Sed 1165193323Sed//===----------------------------------------------------------------------===// 1166193323Sed 1167193323Sed//===----------------------------------------------------------------------===// 1168193323Sed// ARM VFP Instruction templates. 1169193323Sed// 1170193323Sed 1171198090Srdivacky// Almost all VFP instructions are predicable. 1172198090Srdivackyclass VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1173198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1174198090Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1175198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1176198090Srdivacky let OutOperandList = oops; 1177198090Srdivacky let InOperandList = !con(iops, (ops pred:$p)); 1178198090Srdivacky let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1179198090Srdivacky let Pattern = pattern; 1180198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1181198090Srdivacky} 1182198090Srdivacky 1183198090Srdivacky// Special cases 1184198090Srdivackyclass VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1185198090Srdivacky IndexMode im, Format f, InstrItinClass itin, 1186198090Srdivacky string asm, string cstr, list<dag> pattern> 1187198892Srdivacky : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1188198090Srdivacky let OutOperandList = oops; 1189198090Srdivacky let InOperandList = iops; 1190198090Srdivacky let AsmString = asm; 1191198090Srdivacky let Pattern = pattern; 1192198090Srdivacky list<Predicate> Predicates = [HasVFP2]; 1193198090Srdivacky} 1194198090Srdivacky 1195198090Srdivackyclass VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1196198090Srdivacky string opc, string asm, list<dag> pattern> 1197198090Srdivacky : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1198198090Srdivacky opc, asm, "", pattern>; 1199198090Srdivacky 1200193323Sed// ARM VFP addrmode5 loads and stores 1201193323Sedclass ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1202198090Srdivacky InstrItinClass itin, 1203193323Sed string opc, string asm, list<dag> pattern> 1204198090Srdivacky : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1205198090Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1206193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1207193323Sed let Inst{27-24} = opcod1; 1208193323Sed let Inst{21-20} = opcod2; 1209193323Sed let Inst{11-8} = 0b1011; 1210198892Srdivacky 1211198892Srdivacky // 64-bit loads & stores operate on both NEON and VFP pipelines. 1212198892Srdivacky let Dom = VFPNeonDomain.Value; 1213193323Sed} 1214193323Sed 1215193323Sedclass ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1216198090Srdivacky InstrItinClass itin, 1217193323Sed string opc, string asm, list<dag> pattern> 1218198090Srdivacky : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1219198090Srdivacky VFPLdStFrm, itin, opc, asm, "", pattern> { 1220193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1221193323Sed let Inst{27-24} = opcod1; 1222193323Sed let Inst{21-20} = opcod2; 1223193323Sed let Inst{11-8} = 0b1010; 1224193323Sed} 1225193323Sed 1226193323Sed// Load / store multiple 1227198090Srdivackyclass AXDI5<dag oops, dag iops, InstrItinClass itin, 1228198090Srdivacky string asm, list<dag> pattern> 1229198090Srdivacky : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1230198090Srdivacky VFPLdStMulFrm, itin, asm, "", pattern> { 1231193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1232193323Sed let Inst{27-25} = 0b110; 1233193323Sed let Inst{11-8} = 0b1011; 1234198892Srdivacky 1235198892Srdivacky // 64-bit loads & stores operate on both NEON and VFP pipelines. 1236198892Srdivacky let Dom = VFPNeonDomain.Value; 1237193323Sed} 1238193323Sed 1239198090Srdivackyclass AXSI5<dag oops, dag iops, InstrItinClass itin, 1240198090Srdivacky string asm, list<dag> pattern> 1241198090Srdivacky : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1242198090Srdivacky VFPLdStMulFrm, itin, asm, "", pattern> { 1243193323Sed // TODO: Mark the instructions with the appropriate subtarget info. 1244193323Sed let Inst{27-25} = 0b110; 1245193323Sed let Inst{11-8} = 0b1010; 1246193323Sed} 1247193323Sed 1248193323Sed// Double precision, unary 1249193323Sedclass ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 1250198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1251198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1252193323Sed let Inst{27-20} = opcod1; 1253193323Sed let Inst{19-16} = opcod2; 1254193323Sed let Inst{11-8} = 0b1011; 1255193323Sed let Inst{7-4} = opcod3; 1256193323Sed} 1257193323Sed 1258193323Sed// Double precision, binary 1259198090Srdivackyclass ADbI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 1260198090Srdivacky string opc, string asm, list<dag> pattern> 1261198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1262193323Sed let Inst{27-20} = opcod; 1263193323Sed let Inst{11-8} = 0b1011; 1264193323Sed} 1265193323Sed 1266193323Sed// Single precision, unary 1267193323Sedclass ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 1268198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1269198090Srdivacky : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1270193323Sed // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding. 1271193323Sed let Inst{27-20} = opcod1; 1272193323Sed let Inst{19-16} = opcod2; 1273193323Sed let Inst{11-8} = 0b1010; 1274193323Sed let Inst{7-4} = opcod3; 1275193323Sed} 1276193323Sed 1277198090Srdivacky// Single precision unary, if no NEON 1278198090Srdivacky// Same as ASuI except not available if NEON is enabled 1279198090Srdivackyclass ASuIn<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 1280198892Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1281198892Srdivacky : ASuI<opcod1, opcod2, opcod3, oops, iops, itin, opc, asm, pattern> { 1282198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1283198090Srdivacky} 1284198090Srdivacky 1285193323Sed// Single precision, binary 1286198090Srdivackyclass ASbI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 1287198090Srdivacky string opc, string asm, list<dag> pattern> 1288198090Srdivacky : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1289193323Sed // Bit 22 (D bit) can be changed during instruction encoding. 1290193323Sed let Inst{27-20} = opcod; 1291193323Sed let Inst{11-8} = 0b1010; 1292193323Sed} 1293193323Sed 1294198090Srdivacky// Single precision binary, if no NEON 1295198090Srdivacky// Same as ASbI except not available if NEON is enabled 1296198090Srdivackyclass ASbIn<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 1297198090Srdivacky string opc, string asm, list<dag> pattern> 1298198090Srdivacky : ASbI<opcod, oops, iops, itin, opc, asm, pattern> { 1299198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1300198090Srdivacky} 1301198090Srdivacky 1302193323Sed// VFP conversion instructions 1303193323Sedclass AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, 1304198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1305198090Srdivacky string opc, string asm, list<dag> pattern> 1306198090Srdivacky : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1307193323Sed let Inst{27-20} = opcod1; 1308193323Sed let Inst{19-16} = opcod2; 1309193323Sed let Inst{11-8} = opcod3; 1310193323Sed let Inst{6} = 1; 1311193323Sed} 1312193323Sed 1313198090Srdivacky// VFP conversion instructions, if no NEON 1314198090Srdivackyclass AVConv1In<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, 1315198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1316198090Srdivacky string opc, string asm, list<dag> pattern> 1317198090Srdivacky : AVConv1I<opcod1, opcod2, opcod3, oops, iops, itin, opc, asm, pattern> { 1318198090Srdivacky list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1319198090Srdivacky} 1320198090Srdivacky 1321193323Sedclass AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1322198090Srdivacky InstrItinClass itin, 1323198090Srdivacky string opc, string asm, list<dag> pattern> 1324198090Srdivacky : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1325193323Sed let Inst{27-20} = opcod1; 1326193323Sed let Inst{11-8} = opcod2; 1327193323Sed let Inst{4} = 1; 1328193323Sed} 1329193323Sed 1330198090Srdivackyclass AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1331198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1332198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1333193323Sed 1334198090Srdivackyclass AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1335198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1336198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1337193323Sed 1338198090Srdivackyclass AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1339198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1340198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1341193323Sed 1342198090Srdivackyclass AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1343198090Srdivacky InstrItinClass itin, string opc, string asm, list<dag> pattern> 1344198090Srdivacky : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1345193323Sed 1346193323Sed//===----------------------------------------------------------------------===// 1347193323Sed 1348194710Sed//===----------------------------------------------------------------------===// 1349194710Sed// ARM NEON Instruction templates. 1350194710Sed// 1351193323Sed 1352198090Srdivackyclass NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1353199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1354198892Srdivacky : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1355194710Sed let OutOperandList = oops; 1356199989Srdivacky let InOperandList = !con(iops, (ops pred:$p)); 1357199989Srdivacky let AsmString = !strconcat( 1358199989Srdivacky !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1359199989Srdivacky !strconcat("\t", asm)); 1360194710Sed let Pattern = pattern; 1361194710Sed list<Predicate> Predicates = [HasNEON]; 1362193323Sed} 1363193323Sed 1364199989Srdivacky// Same as NeonI except it does not have a "data type" specifier. 1365199989Srdivackyclass NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1366199989Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1367199989Srdivacky : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1368199989Srdivacky let OutOperandList = oops; 1369199989Srdivacky let InOperandList = !con(iops, (ops pred:$p)); 1370199989Srdivacky let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm)); 1371199989Srdivacky let Pattern = pattern; 1372199989Srdivacky list<Predicate> Predicates = [HasNEON]; 1373193323Sed} 1374194710Sed 1375199989Srdivackyclass NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1376199989Srdivacky list<dag> pattern> 1377199989Srdivacky : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "", 1378199989Srdivacky pattern> { 1379198090Srdivacky} 1380198090Srdivacky 1381199989Srdivackyclass NI4<dag oops, dag iops, InstrItinClass itin, string opc, 1382199989Srdivacky string asm, list<dag> pattern> 1383199989Srdivacky : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "", 1384199989Srdivacky pattern> { 1385199989Srdivacky} 1386199989Srdivacky 1387198090Srdivackyclass NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1388198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1389199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1390199989Srdivacky : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr, 1391199989Srdivacky pattern> { 1392198090Srdivacky let Inst{31-24} = 0b11110100; 1393198396Srdivacky let Inst{23} = op23; 1394198396Srdivacky let Inst{21-20} = op21_20; 1395198396Srdivacky let Inst{11-8} = op11_8; 1396198396Srdivacky let Inst{7-4} = op7_4; 1397198090Srdivacky} 1398198090Srdivacky 1399198090Srdivackyclass NDataI<dag oops, dag iops, InstrItinClass itin, 1400199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1401199989Srdivacky : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm, 1402199989Srdivacky cstr, pattern> { 1403194710Sed let Inst{31-25} = 0b1111001; 1404194710Sed} 1405194710Sed 1406199989Srdivackyclass NDataXI<dag oops, dag iops, InstrItinClass itin, 1407199989Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1408199989Srdivacky : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, 1409199989Srdivacky cstr, pattern> { 1410199989Srdivacky let Inst{31-25} = 0b1111001; 1411199989Srdivacky} 1412199989Srdivacky 1413194710Sed// NEON "one register and a modified immediate" format. 1414194710Sedclass N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1415194710Sed bit op5, bit op4, 1416198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1417199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1418199989Srdivacky : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1419194710Sed let Inst{23} = op23; 1420194710Sed let Inst{21-19} = op21_19; 1421194710Sed let Inst{11-8} = op11_8; 1422194710Sed let Inst{7} = op7; 1423194710Sed let Inst{6} = op6; 1424194710Sed let Inst{5} = op5; 1425194710Sed let Inst{4} = op4; 1426194710Sed} 1427194710Sed 1428194710Sed// NEON 2 vector register format. 1429194710Sedclass N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1430194710Sed bits<5> op11_7, bit op6, bit op4, 1431198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1432199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1433199989Srdivacky : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1434194710Sed let Inst{24-23} = op24_23; 1435194710Sed let Inst{21-20} = op21_20; 1436194710Sed let Inst{19-18} = op19_18; 1437194710Sed let Inst{17-16} = op17_16; 1438194710Sed let Inst{11-7} = op11_7; 1439194710Sed let Inst{6} = op6; 1440194710Sed let Inst{4} = op4; 1441194710Sed} 1442194710Sed 1443199989Srdivacky// Same as N2V except it doesn't have a datatype suffix. 1444199989Srdivackyclass N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1445199989Srdivacky bits<5> op11_7, bit op6, bit op4, 1446199989Srdivacky dag oops, dag iops, InstrItinClass itin, 1447199989Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1448199989Srdivacky : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1449198396Srdivacky let Inst{24-23} = op24_23; 1450198396Srdivacky let Inst{21-20} = op21_20; 1451199989Srdivacky let Inst{19-18} = op19_18; 1452199989Srdivacky let Inst{17-16} = op17_16; 1453198396Srdivacky let Inst{11-7} = op11_7; 1454198396Srdivacky let Inst{6} = op6; 1455198396Srdivacky let Inst{4} = op4; 1456198396Srdivacky} 1457198396Srdivacky 1458194710Sed// NEON 2 vector register with immediate. 1459198396Srdivackyclass N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1460198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1461199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1462199989Srdivacky : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1463194710Sed let Inst{24} = op24; 1464194710Sed let Inst{23} = op23; 1465194710Sed let Inst{11-8} = op11_8; 1466194710Sed let Inst{7} = op7; 1467194710Sed let Inst{6} = op6; 1468194710Sed let Inst{4} = op4; 1469194710Sed} 1470194710Sed 1471194710Sed// NEON 3 vector register format. 1472194710Sedclass N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1473198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1474199989Srdivacky string opc, string dt, string asm, string cstr, list<dag> pattern> 1475199989Srdivacky : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1476194710Sed let Inst{24} = op24; 1477194710Sed let Inst{23} = op23; 1478194710Sed let Inst{21-20} = op21_20; 1479194710Sed let Inst{11-8} = op11_8; 1480194710Sed let Inst{6} = op6; 1481194710Sed let Inst{4} = op4; 1482194710Sed} 1483194710Sed 1484199989Srdivacky// Same as N3VX except it doesn't have a data type suffix. 1485199989Srdivackyclass N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1486199989Srdivacky dag oops, dag iops, InstrItinClass itin, 1487199989Srdivacky string opc, string asm, string cstr, list<dag> pattern> 1488199989Srdivacky : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1489198396Srdivacky let Inst{24} = op24; 1490198396Srdivacky let Inst{23} = op23; 1491198396Srdivacky let Inst{21-20} = op21_20; 1492199989Srdivacky let Inst{11-8} = op11_8; 1493198396Srdivacky let Inst{6} = op6; 1494198396Srdivacky let Inst{4} = op4; 1495198396Srdivacky} 1496198396Srdivacky 1497194710Sed// NEON VMOVs between scalar and core registers. 1498194710Sedclass NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1499198090Srdivacky dag oops, dag iops, Format f, InstrItinClass itin, 1500199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1501199989Srdivacky : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain, 1502199989Srdivacky "", itin> { 1503194710Sed let Inst{27-20} = opcod1; 1504194710Sed let Inst{11-8} = opcod2; 1505194710Sed let Inst{6-5} = opcod3; 1506194710Sed let Inst{4} = 1; 1507199989Srdivacky 1508199989Srdivacky let OutOperandList = oops; 1509199989Srdivacky let InOperandList = !con(iops, (ops pred:$p)); 1510199989Srdivacky let AsmString = !strconcat( 1511199989Srdivacky !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1512199989Srdivacky !strconcat("\t", asm)); 1513199989Srdivacky let Pattern = pattern; 1514194710Sed list<Predicate> Predicates = [HasNEON]; 1515194710Sed} 1516194710Sedclass NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1517198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1518199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1519198090Srdivacky : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin, 1520199989Srdivacky opc, dt, asm, pattern>; 1521194710Sedclass NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1522198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1523199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1524198090Srdivacky : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin, 1525199989Srdivacky opc, dt, asm, pattern>; 1526194710Sedclass NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1527198090Srdivacky dag oops, dag iops, InstrItinClass itin, 1528199989Srdivacky string opc, string dt, string asm, list<dag> pattern> 1529198090Srdivacky : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin, 1530199989Srdivacky opc, dt, asm, pattern>; 1531198090Srdivacky 1532198090Srdivacky// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1533198090Srdivacky// for single-precision FP. 1534198090Srdivackyclass NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1535198090Srdivacky list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1536198090Srdivacky} 1537