ARMInstrFormats.td revision 201360
1//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<5> val> { 19 bits<5> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<28>; 37 38def ArithMiscFrm : Format<11>; 39def ExtFrm : Format<12>; 40 41def VFPUnaryFrm : Format<13>; 42def VFPBinaryFrm : Format<14>; 43def VFPConv1Frm : Format<15>; 44def VFPConv2Frm : Format<16>; 45def VFPConv3Frm : Format<17>; 46def VFPConv4Frm : Format<18>; 47def VFPConv5Frm : Format<19>; 48def VFPLdStFrm : Format<20>; 49def VFPLdStMulFrm : Format<21>; 50def VFPMiscFrm : Format<22>; 51 52def ThumbFrm : Format<23>; 53 54def NEONFrm : Format<24>; 55def NEONGetLnFrm : Format<25>; 56def NEONSetLnFrm : Format<26>; 57def NEONDupFrm : Format<27>; 58 59// Misc flags. 60 61// the instruction has a Rn register operand. 62// UnaryDP - Indicates this is a unary data processing instruction, i.e. 63// it doesn't have a Rn operand. 64class UnaryDP { bit isUnaryDataProc = 1; } 65 66// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 67// a 16-bit Thumb instruction if certain conditions are met. 68class Xform16Bit { bit canXformTo16Bit = 1; } 69 70//===----------------------------------------------------------------------===// 71// ARM Instruction flags. These need to match ARMInstrInfo.h. 72// 73 74// Addressing mode. 75class AddrMode<bits<4> val> { 76 bits<4> Value = val; 77} 78def AddrModeNone : AddrMode<0>; 79def AddrMode1 : AddrMode<1>; 80def AddrMode2 : AddrMode<2>; 81def AddrMode3 : AddrMode<3>; 82def AddrMode4 : AddrMode<4>; 83def AddrMode5 : AddrMode<5>; 84def AddrMode6 : AddrMode<6>; 85def AddrModeT1_1 : AddrMode<7>; 86def AddrModeT1_2 : AddrMode<8>; 87def AddrModeT1_4 : AddrMode<9>; 88def AddrModeT1_s : AddrMode<10>; 89def AddrModeT2_i12: AddrMode<11>; 90def AddrModeT2_i8 : AddrMode<12>; 91def AddrModeT2_so : AddrMode<13>; 92def AddrModeT2_pc : AddrMode<14>; 93def AddrModeT2_i8s4 : AddrMode<15>; 94 95// Instruction size. 96class SizeFlagVal<bits<3> val> { 97 bits<3> Value = val; 98} 99def SizeInvalid : SizeFlagVal<0>; // Unset. 100def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 101def Size8Bytes : SizeFlagVal<2>; 102def Size4Bytes : SizeFlagVal<3>; 103def Size2Bytes : SizeFlagVal<4>; 104 105// Load / store index mode. 106class IndexMode<bits<2> val> { 107 bits<2> Value = val; 108} 109def IndexModeNone : IndexMode<0>; 110def IndexModePre : IndexMode<1>; 111def IndexModePost : IndexMode<2>; 112 113// Instruction execution domain. 114class Domain<bits<2> val> { 115 bits<2> Value = val; 116} 117def GenericDomain : Domain<0>; 118def VFPDomain : Domain<1>; // Instructions in VFP domain only 119def NeonDomain : Domain<2>; // Instructions in Neon domain only 120def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 121 122//===----------------------------------------------------------------------===// 123 124// ARM special operands. 125// 126 127// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 128// register whose default is 0 (no register). 129def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 130 (ops (i32 14), (i32 zero_reg))> { 131 let PrintMethod = "printPredicateOperand"; 132} 133 134// Conditional code result for instructions whose 's' bit is set, e.g. subs. 135def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 136 let PrintMethod = "printSBitModifierOperand"; 137} 138 139// Same as cc_out except it defaults to setting CPSR. 140def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 141 let PrintMethod = "printSBitModifierOperand"; 142} 143 144//===----------------------------------------------------------------------===// 145 146// ARM Instruction templates. 147// 148 149class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 150 Format f, Domain d, string cstr, InstrItinClass itin> 151 : Instruction { 152 let Namespace = "ARM"; 153 154 // TSFlagsFields 155 AddrMode AM = am; 156 bits<4> AddrModeBits = AM.Value; 157 158 SizeFlagVal SZ = sz; 159 bits<3> SizeFlag = SZ.Value; 160 161 IndexMode IM = im; 162 bits<2> IndexModeBits = IM.Value; 163 164 Format F = f; 165 bits<5> Form = F.Value; 166 167 Domain D = d; 168 bits<2> Dom = D.Value; 169 170 // 171 // Attributes specific to ARM instructions... 172 // 173 bit isUnaryDataProc = 0; 174 bit canXformTo16Bit = 0; 175 176 let Constraints = cstr; 177 let Itinerary = itin; 178} 179 180class Encoding { 181 field bits<32> Inst; 182} 183 184class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 185 Format f, Domain d, string cstr, InstrItinClass itin> 186 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 187 188// This Encoding-less class is used by Thumb1 to specify the encoding bits later 189// on by adding flavors to specific instructions. 190class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 191 Format f, Domain d, string cstr, InstrItinClass itin> 192 : InstTemplate<am, sz, im, f, d, cstr, itin>; 193 194class PseudoInst<dag oops, dag iops, InstrItinClass itin, 195 string asm, list<dag> pattern> 196 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 197 "", itin> { 198 let OutOperandList = oops; 199 let InOperandList = iops; 200 let AsmString = asm; 201 let Pattern = pattern; 202} 203 204// Almost all ARM instructions are predicable. 205class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 206 IndexMode im, Format f, InstrItinClass itin, 207 string opc, string asm, string cstr, 208 list<dag> pattern> 209 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 210 let OutOperandList = oops; 211 let InOperandList = !con(iops, (ops pred:$p)); 212 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 213 let Pattern = pattern; 214 list<Predicate> Predicates = [IsARM]; 215} 216// A few are not predicable 217class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 218 IndexMode im, Format f, InstrItinClass itin, 219 string opc, string asm, string cstr, 220 list<dag> pattern> 221 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 222 let OutOperandList = oops; 223 let InOperandList = iops; 224 let AsmString = !strconcat(opc, asm); 225 let Pattern = pattern; 226 let isPredicable = 0; 227 list<Predicate> Predicates = [IsARM]; 228} 229 230// Same as I except it can optionally modify CPSR. Note it's modeled as 231// an input operand since by default it's a zero register. It will 232// become an implicit def once it's "flipped". 233class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 234 IndexMode im, Format f, InstrItinClass itin, 235 string opc, string asm, string cstr, 236 list<dag> pattern> 237 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 238 let OutOperandList = oops; 239 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 240 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 241 let Pattern = pattern; 242 list<Predicate> Predicates = [IsARM]; 243} 244 245// Special cases 246class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 247 IndexMode im, Format f, InstrItinClass itin, 248 string asm, string cstr, list<dag> pattern> 249 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 250 let OutOperandList = oops; 251 let InOperandList = iops; 252 let AsmString = asm; 253 let Pattern = pattern; 254 list<Predicate> Predicates = [IsARM]; 255} 256 257class AI<dag oops, dag iops, Format f, InstrItinClass itin, 258 string opc, string asm, list<dag> pattern> 259 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 260 opc, asm, "", pattern>; 261class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 262 string opc, string asm, list<dag> pattern> 263 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 264 opc, asm, "", pattern>; 265class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 266 string asm, list<dag> pattern> 267 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 268 asm, "", pattern>; 269class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 270 string opc, string asm, list<dag> pattern> 271 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 272 opc, asm, "", pattern>; 273 274// Ctrl flow instructions 275class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 276 string opc, string asm, list<dag> pattern> 277 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 278 opc, asm, "", pattern> { 279 let Inst{27-24} = opcod; 280} 281class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 282 string asm, list<dag> pattern> 283 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 284 asm, "", pattern> { 285 let Inst{27-24} = opcod; 286} 287class ABXIx2<dag oops, dag iops, InstrItinClass itin, 288 string asm, list<dag> pattern> 289 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin, 290 asm, "", pattern>; 291 292// BR_JT instructions 293class JTI<dag oops, dag iops, InstrItinClass itin, 294 string asm, list<dag> pattern> 295 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 296 asm, "", pattern>; 297 298 299// Atomic load/store instructions 300 301class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 302 string opc, string asm, list<dag> pattern> 303 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 304 opc, asm, "", pattern> { 305 let Inst{27-23} = 0b00011; 306 let Inst{22-21} = opcod; 307 let Inst{20} = 1; 308 let Inst{11-0} = 0b111110011111; 309} 310class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 311 string opc, string asm, list<dag> pattern> 312 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 313 opc, asm, "", pattern> { 314 let Inst{27-23} = 0b00011; 315 let Inst{22-21} = opcod; 316 let Inst{20} = 0; 317 let Inst{11-4} = 0b11111001; 318} 319 320// addrmode1 instructions 321class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 322 string opc, string asm, list<dag> pattern> 323 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 324 opc, asm, "", pattern> { 325 let Inst{24-21} = opcod; 326 let Inst{27-26} = {0,0}; 327} 328class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 329 string opc, string asm, list<dag> pattern> 330 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 331 opc, asm, "", pattern> { 332 let Inst{24-21} = opcod; 333 let Inst{27-26} = {0,0}; 334} 335class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 336 string asm, list<dag> pattern> 337 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 338 asm, "", pattern> { 339 let Inst{24-21} = opcod; 340 let Inst{27-26} = {0,0}; 341} 342class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin, 343 string opc, string asm, list<dag> pattern> 344 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin, 345 opc, asm, "", pattern>; 346 347 348// addrmode2 loads and stores 349class AI2<dag oops, dag iops, Format f, InstrItinClass itin, 350 string opc, string asm, list<dag> pattern> 351 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 352 opc, asm, "", pattern> { 353 let Inst{27-26} = {0,1}; 354} 355 356// loads 357class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 358 string opc, string asm, list<dag> pattern> 359 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 360 opc, asm, "", pattern> { 361 let Inst{20} = 1; // L bit 362 let Inst{21} = 0; // W bit 363 let Inst{22} = 0; // B bit 364 let Inst{24} = 1; // P bit 365 let Inst{27-26} = {0,1}; 366} 367class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 368 string asm, list<dag> pattern> 369 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 370 asm, "", pattern> { 371 let Inst{20} = 1; // L bit 372 let Inst{21} = 0; // W bit 373 let Inst{22} = 0; // B bit 374 let Inst{24} = 1; // P bit 375 let Inst{27-26} = {0,1}; 376} 377class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 378 string opc, string asm, list<dag> pattern> 379 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 380 opc, asm, "", pattern> { 381 let Inst{20} = 1; // L bit 382 let Inst{21} = 0; // W bit 383 let Inst{22} = 1; // B bit 384 let Inst{24} = 1; // P bit 385 let Inst{27-26} = {0,1}; 386} 387class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 388 string asm, list<dag> pattern> 389 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 390 asm, "", pattern> { 391 let Inst{20} = 1; // L bit 392 let Inst{21} = 0; // W bit 393 let Inst{22} = 1; // B bit 394 let Inst{24} = 1; // P bit 395 let Inst{27-26} = {0,1}; 396} 397 398// stores 399class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 400 string opc, string asm, list<dag> pattern> 401 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 402 opc, asm, "", pattern> { 403 let Inst{20} = 0; // L bit 404 let Inst{21} = 0; // W bit 405 let Inst{22} = 0; // B bit 406 let Inst{24} = 1; // P bit 407 let Inst{27-26} = {0,1}; 408} 409class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 410 string asm, list<dag> pattern> 411 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 412 asm, "", pattern> { 413 let Inst{20} = 0; // L bit 414 let Inst{21} = 0; // W bit 415 let Inst{22} = 0; // B bit 416 let Inst{24} = 1; // P bit 417 let Inst{27-26} = {0,1}; 418} 419class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 420 string opc, string asm, list<dag> pattern> 421 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 422 opc, asm, "", pattern> { 423 let Inst{20} = 0; // L bit 424 let Inst{21} = 0; // W bit 425 let Inst{22} = 1; // B bit 426 let Inst{24} = 1; // P bit 427 let Inst{27-26} = {0,1}; 428} 429class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 430 string asm, list<dag> pattern> 431 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 432 asm, "", pattern> { 433 let Inst{20} = 0; // L bit 434 let Inst{21} = 0; // W bit 435 let Inst{22} = 1; // B bit 436 let Inst{24} = 1; // P bit 437 let Inst{27-26} = {0,1}; 438} 439 440// Pre-indexed loads 441class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin, 442 string opc, string asm, string cstr, list<dag> pattern> 443 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 444 opc, asm, cstr, pattern> { 445 let Inst{20} = 1; // L bit 446 let Inst{21} = 1; // W bit 447 let Inst{22} = 0; // B bit 448 let Inst{24} = 1; // P bit 449 let Inst{27-26} = {0,1}; 450} 451class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin, 452 string opc, string asm, string cstr, list<dag> pattern> 453 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 454 opc, asm, cstr, pattern> { 455 let Inst{20} = 1; // L bit 456 let Inst{21} = 1; // W bit 457 let Inst{22} = 1; // B bit 458 let Inst{24} = 1; // P bit 459 let Inst{27-26} = {0,1}; 460} 461 462// Pre-indexed stores 463class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin, 464 string opc, string asm, string cstr, list<dag> pattern> 465 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 466 opc, asm, cstr, pattern> { 467 let Inst{20} = 0; // L bit 468 let Inst{21} = 1; // W bit 469 let Inst{22} = 0; // B bit 470 let Inst{24} = 1; // P bit 471 let Inst{27-26} = {0,1}; 472} 473class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin, 474 string opc, string asm, string cstr, list<dag> pattern> 475 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 476 opc, asm, cstr, pattern> { 477 let Inst{20} = 0; // L bit 478 let Inst{21} = 1; // W bit 479 let Inst{22} = 1; // B bit 480 let Inst{24} = 1; // P bit 481 let Inst{27-26} = {0,1}; 482} 483 484// Post-indexed loads 485class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin, 486 string opc, string asm, string cstr, list<dag> pattern> 487 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 488 opc, asm, cstr,pattern> { 489 let Inst{20} = 1; // L bit 490 let Inst{21} = 0; // W bit 491 let Inst{22} = 0; // B bit 492 let Inst{24} = 0; // P bit 493 let Inst{27-26} = {0,1}; 494} 495class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin, 496 string opc, string asm, string cstr, list<dag> pattern> 497 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 498 opc, asm, cstr,pattern> { 499 let Inst{20} = 1; // L bit 500 let Inst{21} = 0; // W bit 501 let Inst{22} = 1; // B bit 502 let Inst{24} = 0; // P bit 503 let Inst{27-26} = {0,1}; 504} 505 506// Post-indexed stores 507class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin, 508 string opc, string asm, string cstr, list<dag> pattern> 509 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 510 opc, asm, cstr,pattern> { 511 let Inst{20} = 0; // L bit 512 let Inst{21} = 0; // W bit 513 let Inst{22} = 0; // B bit 514 let Inst{24} = 0; // P bit 515 let Inst{27-26} = {0,1}; 516} 517class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin, 518 string opc, string asm, string cstr, list<dag> pattern> 519 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 520 opc, asm, cstr,pattern> { 521 let Inst{20} = 0; // L bit 522 let Inst{21} = 0; // W bit 523 let Inst{22} = 1; // B bit 524 let Inst{24} = 0; // P bit 525 let Inst{27-26} = {0,1}; 526} 527 528// addrmode3 instructions 529class AI3<dag oops, dag iops, Format f, InstrItinClass itin, 530 string opc, string asm, list<dag> pattern> 531 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 532 opc, asm, "", pattern>; 533class AXI3<dag oops, dag iops, Format f, InstrItinClass itin, 534 string asm, list<dag> pattern> 535 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 536 asm, "", pattern>; 537 538// loads 539class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 540 string opc, string asm, list<dag> pattern> 541 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 542 opc, asm, "", pattern> { 543 let Inst{4} = 1; 544 let Inst{5} = 1; // H bit 545 let Inst{6} = 0; // S bit 546 let Inst{7} = 1; 547 let Inst{20} = 1; // L bit 548 let Inst{21} = 0; // W bit 549 let Inst{24} = 1; // P bit 550 let Inst{27-25} = 0b000; 551} 552class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 553 string asm, list<dag> pattern> 554 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 555 asm, "", pattern> { 556 let Inst{4} = 1; 557 let Inst{5} = 1; // H bit 558 let Inst{6} = 0; // S bit 559 let Inst{7} = 1; 560 let Inst{20} = 1; // L bit 561 let Inst{21} = 0; // W bit 562 let Inst{24} = 1; // P bit 563} 564class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 565 string opc, string asm, list<dag> pattern> 566 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 567 opc, asm, "", pattern> { 568 let Inst{4} = 1; 569 let Inst{5} = 1; // H bit 570 let Inst{6} = 1; // S bit 571 let Inst{7} = 1; 572 let Inst{20} = 1; // L bit 573 let Inst{21} = 0; // W bit 574 let Inst{24} = 1; // P bit 575 let Inst{27-25} = 0b000; 576} 577class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 578 string asm, list<dag> pattern> 579 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 580 asm, "", pattern> { 581 let Inst{4} = 1; 582 let Inst{5} = 1; // H bit 583 let Inst{6} = 1; // S bit 584 let Inst{7} = 1; 585 let Inst{20} = 1; // L bit 586 let Inst{21} = 0; // W bit 587 let Inst{24} = 1; // P bit 588} 589class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 590 string opc, string asm, list<dag> pattern> 591 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 592 opc, asm, "", pattern> { 593 let Inst{4} = 1; 594 let Inst{5} = 0; // H bit 595 let Inst{6} = 1; // S bit 596 let Inst{7} = 1; 597 let Inst{20} = 1; // L bit 598 let Inst{21} = 0; // W bit 599 let Inst{24} = 1; // P bit 600 let Inst{27-25} = 0b000; 601} 602class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 603 string asm, list<dag> pattern> 604 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 605 asm, "", pattern> { 606 let Inst{4} = 1; 607 let Inst{5} = 0; // H bit 608 let Inst{6} = 1; // S bit 609 let Inst{7} = 1; 610 let Inst{20} = 1; // L bit 611 let Inst{21} = 0; // W bit 612 let Inst{24} = 1; // P bit 613} 614class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin, 615 string opc, string asm, list<dag> pattern> 616 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 617 opc, asm, "", pattern> { 618 let Inst{4} = 1; 619 let Inst{5} = 0; // H bit 620 let Inst{6} = 1; // S bit 621 let Inst{7} = 1; 622 let Inst{20} = 0; // L bit 623 let Inst{21} = 0; // W bit 624 let Inst{24} = 1; // P bit 625 let Inst{27-25} = 0b000; 626} 627 628// stores 629class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 630 string opc, string asm, list<dag> pattern> 631 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 632 opc, asm, "", pattern> { 633 let Inst{4} = 1; 634 let Inst{5} = 1; // H bit 635 let Inst{6} = 0; // S bit 636 let Inst{7} = 1; 637 let Inst{20} = 0; // L bit 638 let Inst{21} = 0; // W bit 639 let Inst{24} = 1; // P bit 640 let Inst{27-25} = 0b000; 641} 642class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 643 string asm, list<dag> pattern> 644 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 645 asm, "", pattern> { 646 let Inst{4} = 1; 647 let Inst{5} = 1; // H bit 648 let Inst{6} = 0; // S bit 649 let Inst{7} = 1; 650 let Inst{20} = 0; // L bit 651 let Inst{21} = 0; // W bit 652 let Inst{24} = 1; // P bit 653} 654class AI3std<dag oops, dag iops, Format f, InstrItinClass itin, 655 string opc, string asm, list<dag> pattern> 656 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 657 opc, asm, "", pattern> { 658 let Inst{4} = 1; 659 let Inst{5} = 1; // H bit 660 let Inst{6} = 1; // S bit 661 let Inst{7} = 1; 662 let Inst{20} = 0; // L bit 663 let Inst{21} = 0; // W bit 664 let Inst{24} = 1; // P bit 665 let Inst{27-25} = 0b000; 666} 667 668// Pre-indexed loads 669class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin, 670 string opc, string asm, string cstr, list<dag> pattern> 671 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 672 opc, asm, cstr, pattern> { 673 let Inst{4} = 1; 674 let Inst{5} = 1; // H bit 675 let Inst{6} = 0; // S bit 676 let Inst{7} = 1; 677 let Inst{20} = 1; // L bit 678 let Inst{21} = 1; // W bit 679 let Inst{24} = 1; // P bit 680 let Inst{27-25} = 0b000; 681} 682class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin, 683 string opc, string asm, string cstr, list<dag> pattern> 684 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 685 opc, asm, cstr, pattern> { 686 let Inst{4} = 1; 687 let Inst{5} = 1; // H bit 688 let Inst{6} = 1; // S bit 689 let Inst{7} = 1; 690 let Inst{20} = 1; // L bit 691 let Inst{21} = 1; // W bit 692 let Inst{24} = 1; // P bit 693 let Inst{27-25} = 0b000; 694} 695class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin, 696 string opc, string asm, string cstr, list<dag> pattern> 697 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 698 opc, asm, cstr, pattern> { 699 let Inst{4} = 1; 700 let Inst{5} = 0; // H bit 701 let Inst{6} = 1; // S bit 702 let Inst{7} = 1; 703 let Inst{20} = 1; // L bit 704 let Inst{21} = 1; // W bit 705 let Inst{24} = 1; // P bit 706 let Inst{27-25} = 0b000; 707} 708 709// Pre-indexed stores 710class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 711 string opc, string asm, string cstr, list<dag> pattern> 712 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 713 opc, asm, cstr, pattern> { 714 let Inst{4} = 1; 715 let Inst{5} = 1; // H bit 716 let Inst{6} = 0; // S bit 717 let Inst{7} = 1; 718 let Inst{20} = 0; // L bit 719 let Inst{21} = 1; // W bit 720 let Inst{24} = 1; // P bit 721 let Inst{27-25} = 0b000; 722} 723 724// Post-indexed loads 725class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin, 726 string opc, string asm, string cstr, list<dag> pattern> 727 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 728 opc, asm, cstr,pattern> { 729 let Inst{4} = 1; 730 let Inst{5} = 1; // H bit 731 let Inst{6} = 0; // S bit 732 let Inst{7} = 1; 733 let Inst{20} = 1; // L bit 734 let Inst{21} = 1; // W bit 735 let Inst{24} = 0; // P bit 736 let Inst{27-25} = 0b000; 737} 738class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin, 739 string opc, string asm, string cstr, list<dag> pattern> 740 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 741 opc, asm, cstr,pattern> { 742 let Inst{4} = 1; 743 let Inst{5} = 1; // H bit 744 let Inst{6} = 1; // S bit 745 let Inst{7} = 1; 746 let Inst{20} = 1; // L bit 747 let Inst{21} = 1; // W bit 748 let Inst{24} = 0; // P bit 749 let Inst{27-25} = 0b000; 750} 751class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin, 752 string opc, string asm, string cstr, list<dag> pattern> 753 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 754 opc, asm, cstr,pattern> { 755 let Inst{4} = 1; 756 let Inst{5} = 0; // H bit 757 let Inst{6} = 1; // S bit 758 let Inst{7} = 1; 759 let Inst{20} = 1; // L bit 760 let Inst{21} = 1; // W bit 761 let Inst{24} = 0; // P bit 762 let Inst{27-25} = 0b000; 763} 764 765// Post-indexed stores 766class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 767 string opc, string asm, string cstr, list<dag> pattern> 768 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 769 opc, asm, cstr,pattern> { 770 let Inst{4} = 1; 771 let Inst{5} = 1; // H bit 772 let Inst{6} = 0; // S bit 773 let Inst{7} = 1; 774 let Inst{20} = 0; // L bit 775 let Inst{21} = 1; // W bit 776 let Inst{24} = 0; // P bit 777 let Inst{27-25} = 0b000; 778} 779 780 781// addrmode4 instructions 782class AXI4ld<dag oops, dag iops, Format f, InstrItinClass itin, 783 string asm, list<dag> pattern> 784 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin, 785 asm, "", pattern> { 786 let Inst{20} = 1; // L bit 787 let Inst{22} = 0; // S bit 788 let Inst{27-25} = 0b100; 789} 790class AXI4st<dag oops, dag iops, Format f, InstrItinClass itin, 791 string asm, list<dag> pattern> 792 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin, 793 asm, "", pattern> { 794 let Inst{20} = 0; // L bit 795 let Inst{22} = 0; // S bit 796 let Inst{27-25} = 0b100; 797} 798 799// Unsigned multiply, multiply-accumulate instructions. 800class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 801 string opc, string asm, list<dag> pattern> 802 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 803 opc, asm, "", pattern> { 804 let Inst{7-4} = 0b1001; 805 let Inst{20} = 0; // S bit 806 let Inst{27-21} = opcod; 807} 808class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 809 string opc, string asm, list<dag> pattern> 810 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 811 opc, asm, "", pattern> { 812 let Inst{7-4} = 0b1001; 813 let Inst{27-21} = opcod; 814} 815 816// Most significant word multiply 817class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 818 string opc, string asm, list<dag> pattern> 819 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 820 opc, asm, "", pattern> { 821 let Inst{7-4} = 0b1001; 822 let Inst{20} = 1; 823 let Inst{27-21} = opcod; 824} 825 826// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 827class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 828 string opc, string asm, list<dag> pattern> 829 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 830 opc, asm, "", pattern> { 831 let Inst{4} = 0; 832 let Inst{7} = 1; 833 let Inst{20} = 0; 834 let Inst{27-21} = opcod; 835} 836 837// Extend instructions. 838class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 839 string opc, string asm, list<dag> pattern> 840 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 841 opc, asm, "", pattern> { 842 let Inst{7-4} = 0b0111; 843 let Inst{27-20} = opcod; 844} 845 846// Misc Arithmetic instructions. 847class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 848 string opc, string asm, list<dag> pattern> 849 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 850 opc, asm, "", pattern> { 851 let Inst{27-20} = opcod; 852} 853 854//===----------------------------------------------------------------------===// 855 856// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 857class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 858 list<Predicate> Predicates = [IsARM]; 859} 860class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 861 list<Predicate> Predicates = [IsARM, HasV5TE]; 862} 863class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 864 list<Predicate> Predicates = [IsARM, HasV6]; 865} 866 867//===----------------------------------------------------------------------===// 868// 869// Thumb Instruction Format Definitions. 870// 871 872// TI - Thumb instruction. 873 874class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 875 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 876 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 877 let OutOperandList = oops; 878 let InOperandList = iops; 879 let AsmString = asm; 880 let Pattern = pattern; 881 list<Predicate> Predicates = [IsThumb]; 882} 883 884class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 885 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 886 887// Two-address instructions 888class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 889 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>; 890 891// tBL, tBX 32-bit instructions 892class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 893 dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 894 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding { 895 let Inst{31-27} = opcod1; 896 let Inst{15-14} = opcod2; 897 let Inst{12} = opcod3; 898} 899 900// BR_JT instructions 901class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 902 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 903 904// Thumb1 only 905class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 906 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 907 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 908 let OutOperandList = oops; 909 let InOperandList = iops; 910 let AsmString = asm; 911 let Pattern = pattern; 912 list<Predicate> Predicates = [IsThumb1Only]; 913} 914 915class T1I<dag oops, dag iops, InstrItinClass itin, 916 string asm, list<dag> pattern> 917 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 918class T1Ix2<dag oops, dag iops, InstrItinClass itin, 919 string asm, list<dag> pattern> 920 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 921class T1JTI<dag oops, dag iops, InstrItinClass itin, 922 string asm, list<dag> pattern> 923 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 924 925// Two-address instructions 926class T1It<dag oops, dag iops, InstrItinClass itin, 927 string asm, list<dag> pattern> 928 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 929 asm, "$lhs = $dst", pattern>; 930 931// Thumb1 instruction that can either be predicated or set CPSR. 932class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 933 InstrItinClass itin, 934 string opc, string asm, string cstr, list<dag> pattern> 935 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 936 let OutOperandList = !con(oops, (ops s_cc_out:$s)); 937 let InOperandList = !con(iops, (ops pred:$p)); 938 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 939 let Pattern = pattern; 940 list<Predicate> Predicates = [IsThumb1Only]; 941} 942 943class T1sI<dag oops, dag iops, InstrItinClass itin, 944 string opc, string asm, list<dag> pattern> 945 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 946 947// Two-address instructions 948class T1sIt<dag oops, dag iops, InstrItinClass itin, 949 string opc, string asm, list<dag> pattern> 950 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 951 "$lhs = $dst", pattern>; 952 953// Thumb1 instruction that can be predicated. 954class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 955 InstrItinClass itin, 956 string opc, string asm, string cstr, list<dag> pattern> 957 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 958 let OutOperandList = oops; 959 let InOperandList = !con(iops, (ops pred:$p)); 960 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 961 let Pattern = pattern; 962 list<Predicate> Predicates = [IsThumb1Only]; 963} 964 965class T1pI<dag oops, dag iops, InstrItinClass itin, 966 string opc, string asm, list<dag> pattern> 967 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 968 969// Two-address instructions 970class T1pIt<dag oops, dag iops, InstrItinClass itin, 971 string opc, string asm, list<dag> pattern> 972 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 973 "$lhs = $dst", pattern>; 974 975class T1pI1<dag oops, dag iops, InstrItinClass itin, 976 string opc, string asm, list<dag> pattern> 977 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>; 978class T1pI2<dag oops, dag iops, InstrItinClass itin, 979 string opc, string asm, list<dag> pattern> 980 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>; 981class T1pI4<dag oops, dag iops, InstrItinClass itin, 982 string opc, string asm, list<dag> pattern> 983 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>; 984class T1pIs<dag oops, dag iops, 985 InstrItinClass itin, string opc, string asm, list<dag> pattern> 986 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 987 988class Encoding16 : Encoding { 989 let Inst{31-16} = 0x0000; 990} 991 992// A6.2 16-bit Thumb instruction encoding 993class T1Encoding<bits<6> opcode> : Encoding16 { 994 let Inst{15-10} = opcode; 995} 996 997// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 998class T1General<bits<5> opcode> : Encoding16 { 999 let Inst{15-14} = 0b00; 1000 let Inst{13-9} = opcode; 1001} 1002 1003// A6.2.2 Data-processing encoding. 1004class T1DataProcessing<bits<4> opcode> : Encoding16 { 1005 let Inst{15-10} = 0b010000; 1006 let Inst{9-6} = opcode; 1007} 1008 1009// A6.2.3 Special data instructions and branch and exchange encoding. 1010class T1Special<bits<4> opcode> : Encoding16 { 1011 let Inst{15-10} = 0b010001; 1012 let Inst{9-6} = opcode; 1013} 1014 1015// A6.2.4 Load/store single data item encoding. 1016class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1017 let Inst{15-12} = opA; 1018 let Inst{11-9} = opB; 1019} 1020class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>; 1021class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes 1022class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte 1023class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes 1024class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1025 1026// A6.2.5 Miscellaneous 16-bit instructions encoding. 1027class T1Misc<bits<7> opcode> : Encoding16 { 1028 let Inst{15-12} = 0b1011; 1029 let Inst{11-5} = opcode; 1030} 1031 1032// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1033class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1034 InstrItinClass itin, 1035 string opc, string asm, string cstr, list<dag> pattern> 1036 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1037 let OutOperandList = oops; 1038 let InOperandList = !con(iops, (ops pred:$p)); 1039 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1040 let Pattern = pattern; 1041 list<Predicate> Predicates = [IsThumb2]; 1042} 1043 1044// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as 1045// an input operand since by default it's a zero register. It will 1046// become an implicit def once it's "flipped". 1047// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1048// more consistent. 1049class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1050 InstrItinClass itin, 1051 string opc, string asm, string cstr, list<dag> pattern> 1052 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1053 let OutOperandList = oops; 1054 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 1055 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 1056 let Pattern = pattern; 1057 list<Predicate> Predicates = [IsThumb2]; 1058} 1059 1060// Special cases 1061class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1062 InstrItinClass itin, 1063 string asm, string cstr, list<dag> pattern> 1064 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1065 let OutOperandList = oops; 1066 let InOperandList = iops; 1067 let AsmString = asm; 1068 let Pattern = pattern; 1069 list<Predicate> Predicates = [IsThumb2]; 1070} 1071 1072class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1073 InstrItinClass itin, 1074 string asm, string cstr, list<dag> pattern> 1075 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1076 let OutOperandList = oops; 1077 let InOperandList = iops; 1078 let AsmString = asm; 1079 let Pattern = pattern; 1080 list<Predicate> Predicates = [IsThumb1Only]; 1081} 1082 1083class T2I<dag oops, dag iops, InstrItinClass itin, 1084 string opc, string asm, list<dag> pattern> 1085 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1086class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1087 string opc, string asm, list<dag> pattern> 1088 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>; 1089class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1090 string opc, string asm, list<dag> pattern> 1091 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1092class T2Iso<dag oops, dag iops, InstrItinClass itin, 1093 string opc, string asm, list<dag> pattern> 1094 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1095class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1096 string opc, string asm, list<dag> pattern> 1097 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1098class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin, 1099 string opc, string asm, list<dag> pattern> 1100 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1101 pattern> { 1102 let Inst{31-27} = 0b11101; 1103 let Inst{26-25} = 0b00; 1104 let Inst{24} = P; 1105 let Inst{23} = ?; // The U bit. 1106 let Inst{22} = 1; 1107 let Inst{21} = W; 1108 let Inst{20} = load; 1109} 1110 1111class T2sI<dag oops, dag iops, InstrItinClass itin, 1112 string opc, string asm, list<dag> pattern> 1113 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1114 1115class T2XI<dag oops, dag iops, InstrItinClass itin, 1116 string asm, list<dag> pattern> 1117 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1118class T2JTI<dag oops, dag iops, InstrItinClass itin, 1119 string asm, list<dag> pattern> 1120 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1121 1122class T2Ix2<dag oops, dag iops, InstrItinClass itin, 1123 string opc, string asm, list<dag> pattern> 1124 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>; 1125 1126 1127// T2Iidxldst - Thumb2 indexed load / store instructions. 1128class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1129 dag oops, dag iops, 1130 AddrMode am, IndexMode im, InstrItinClass itin, 1131 string opc, string asm, string cstr, list<dag> pattern> 1132 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1133 let OutOperandList = oops; 1134 let InOperandList = !con(iops, (ops pred:$p)); 1135 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1136 let Pattern = pattern; 1137 list<Predicate> Predicates = [IsThumb2]; 1138 let Inst{31-27} = 0b11111; 1139 let Inst{26-25} = 0b00; 1140 let Inst{24} = signed; 1141 let Inst{23} = 0; 1142 let Inst{22-21} = opcod; 1143 let Inst{20} = load; 1144 let Inst{11} = 1; 1145 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1146 let Inst{10} = pre; // The P bit. 1147 let Inst{8} = 1; // The W bit. 1148} 1149 1150// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1151class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1152 list<Predicate> Predicates = [IsThumb1Only, HasV5T]; 1153} 1154 1155// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1156class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1157 list<Predicate> Predicates = [IsThumb1Only]; 1158} 1159 1160// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1161class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1162 list<Predicate> Predicates = [IsThumb2]; 1163} 1164 1165//===----------------------------------------------------------------------===// 1166 1167//===----------------------------------------------------------------------===// 1168// ARM VFP Instruction templates. 1169// 1170 1171// Almost all VFP instructions are predicable. 1172class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1173 IndexMode im, Format f, InstrItinClass itin, 1174 string opc, string asm, string cstr, list<dag> pattern> 1175 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1176 let OutOperandList = oops; 1177 let InOperandList = !con(iops, (ops pred:$p)); 1178 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 1179 let Pattern = pattern; 1180 list<Predicate> Predicates = [HasVFP2]; 1181} 1182 1183// Special cases 1184class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1185 IndexMode im, Format f, InstrItinClass itin, 1186 string asm, string cstr, list<dag> pattern> 1187 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1188 let OutOperandList = oops; 1189 let InOperandList = iops; 1190 let AsmString = asm; 1191 let Pattern = pattern; 1192 list<Predicate> Predicates = [HasVFP2]; 1193} 1194 1195class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1196 string opc, string asm, list<dag> pattern> 1197 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1198 opc, asm, "", pattern>; 1199 1200// ARM VFP addrmode5 loads and stores 1201class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1202 InstrItinClass itin, 1203 string opc, string asm, list<dag> pattern> 1204 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1205 VFPLdStFrm, itin, opc, asm, "", pattern> { 1206 // TODO: Mark the instructions with the appropriate subtarget info. 1207 let Inst{27-24} = opcod1; 1208 let Inst{21-20} = opcod2; 1209 let Inst{11-8} = 0b1011; 1210 1211 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1212 let Dom = VFPNeonDomain.Value; 1213} 1214 1215class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1216 InstrItinClass itin, 1217 string opc, string asm, list<dag> pattern> 1218 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1219 VFPLdStFrm, itin, opc, asm, "", pattern> { 1220 // TODO: Mark the instructions with the appropriate subtarget info. 1221 let Inst{27-24} = opcod1; 1222 let Inst{21-20} = opcod2; 1223 let Inst{11-8} = 0b1010; 1224} 1225 1226// Load / store multiple 1227class AXDI5<dag oops, dag iops, InstrItinClass itin, 1228 string asm, list<dag> pattern> 1229 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1230 VFPLdStMulFrm, itin, asm, "", pattern> { 1231 // TODO: Mark the instructions with the appropriate subtarget info. 1232 let Inst{27-25} = 0b110; 1233 let Inst{11-8} = 0b1011; 1234 1235 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1236 let Dom = VFPNeonDomain.Value; 1237} 1238 1239class AXSI5<dag oops, dag iops, InstrItinClass itin, 1240 string asm, list<dag> pattern> 1241 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1242 VFPLdStMulFrm, itin, asm, "", pattern> { 1243 // TODO: Mark the instructions with the appropriate subtarget info. 1244 let Inst{27-25} = 0b110; 1245 let Inst{11-8} = 0b1010; 1246} 1247 1248// Double precision, unary 1249class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 1250 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1251 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1252 let Inst{27-20} = opcod1; 1253 let Inst{19-16} = opcod2; 1254 let Inst{11-8} = 0b1011; 1255 let Inst{7-4} = opcod3; 1256} 1257 1258// Double precision, binary 1259class ADbI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 1260 string opc, string asm, list<dag> pattern> 1261 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1262 let Inst{27-20} = opcod; 1263 let Inst{11-8} = 0b1011; 1264} 1265 1266// Single precision, unary 1267class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 1268 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1269 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1270 // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding. 1271 let Inst{27-20} = opcod1; 1272 let Inst{19-16} = opcod2; 1273 let Inst{11-8} = 0b1010; 1274 let Inst{7-4} = opcod3; 1275} 1276 1277// Single precision unary, if no NEON 1278// Same as ASuI except not available if NEON is enabled 1279class ASuIn<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 1280 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1281 : ASuI<opcod1, opcod2, opcod3, oops, iops, itin, opc, asm, pattern> { 1282 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1283} 1284 1285// Single precision, binary 1286class ASbI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 1287 string opc, string asm, list<dag> pattern> 1288 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1289 // Bit 22 (D bit) can be changed during instruction encoding. 1290 let Inst{27-20} = opcod; 1291 let Inst{11-8} = 0b1010; 1292} 1293 1294// Single precision binary, if no NEON 1295// Same as ASbI except not available if NEON is enabled 1296class ASbIn<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 1297 string opc, string asm, list<dag> pattern> 1298 : ASbI<opcod, oops, iops, itin, opc, asm, pattern> { 1299 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1300} 1301 1302// VFP conversion instructions 1303class AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, 1304 dag oops, dag iops, InstrItinClass itin, 1305 string opc, string asm, list<dag> pattern> 1306 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1307 let Inst{27-20} = opcod1; 1308 let Inst{19-16} = opcod2; 1309 let Inst{11-8} = opcod3; 1310 let Inst{6} = 1; 1311} 1312 1313// VFP conversion instructions, if no NEON 1314class AVConv1In<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, 1315 dag oops, dag iops, InstrItinClass itin, 1316 string opc, string asm, list<dag> pattern> 1317 : AVConv1I<opcod1, opcod2, opcod3, oops, iops, itin, opc, asm, pattern> { 1318 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1319} 1320 1321class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1322 InstrItinClass itin, 1323 string opc, string asm, list<dag> pattern> 1324 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1325 let Inst{27-20} = opcod1; 1326 let Inst{11-8} = opcod2; 1327 let Inst{4} = 1; 1328} 1329 1330class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1331 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1332 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1333 1334class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1335 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1336 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1337 1338class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1339 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1340 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1341 1342class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1343 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1344 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1345 1346//===----------------------------------------------------------------------===// 1347 1348//===----------------------------------------------------------------------===// 1349// ARM NEON Instruction templates. 1350// 1351 1352class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1353 string opc, string dt, string asm, string cstr, list<dag> pattern> 1354 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1355 let OutOperandList = oops; 1356 let InOperandList = !con(iops, (ops pred:$p)); 1357 let AsmString = !strconcat( 1358 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1359 !strconcat("\t", asm)); 1360 let Pattern = pattern; 1361 list<Predicate> Predicates = [HasNEON]; 1362} 1363 1364// Same as NeonI except it does not have a "data type" specifier. 1365class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, 1366 string opc, string asm, string cstr, list<dag> pattern> 1367 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> { 1368 let OutOperandList = oops; 1369 let InOperandList = !con(iops, (ops pred:$p)); 1370 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm)); 1371 let Pattern = pattern; 1372 list<Predicate> Predicates = [HasNEON]; 1373} 1374 1375class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1376 list<dag> pattern> 1377 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "", 1378 pattern> { 1379} 1380 1381class NI4<dag oops, dag iops, InstrItinClass itin, string opc, 1382 string asm, list<dag> pattern> 1383 : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "", 1384 pattern> { 1385} 1386 1387class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1388 dag oops, dag iops, InstrItinClass itin, 1389 string opc, string dt, string asm, string cstr, list<dag> pattern> 1390 : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr, 1391 pattern> { 1392 let Inst{31-24} = 0b11110100; 1393 let Inst{23} = op23; 1394 let Inst{21-20} = op21_20; 1395 let Inst{11-8} = op11_8; 1396 let Inst{7-4} = op7_4; 1397} 1398 1399class NDataI<dag oops, dag iops, InstrItinClass itin, 1400 string opc, string dt, string asm, string cstr, list<dag> pattern> 1401 : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm, 1402 cstr, pattern> { 1403 let Inst{31-25} = 0b1111001; 1404} 1405 1406class NDataXI<dag oops, dag iops, InstrItinClass itin, 1407 string opc, string asm, string cstr, list<dag> pattern> 1408 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, 1409 cstr, pattern> { 1410 let Inst{31-25} = 0b1111001; 1411} 1412 1413// NEON "one register and a modified immediate" format. 1414class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1415 bit op5, bit op4, 1416 dag oops, dag iops, InstrItinClass itin, 1417 string opc, string dt, string asm, string cstr, list<dag> pattern> 1418 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1419 let Inst{23} = op23; 1420 let Inst{21-19} = op21_19; 1421 let Inst{11-8} = op11_8; 1422 let Inst{7} = op7; 1423 let Inst{6} = op6; 1424 let Inst{5} = op5; 1425 let Inst{4} = op4; 1426} 1427 1428// NEON 2 vector register format. 1429class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1430 bits<5> op11_7, bit op6, bit op4, 1431 dag oops, dag iops, InstrItinClass itin, 1432 string opc, string dt, string asm, string cstr, list<dag> pattern> 1433 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1434 let Inst{24-23} = op24_23; 1435 let Inst{21-20} = op21_20; 1436 let Inst{19-18} = op19_18; 1437 let Inst{17-16} = op17_16; 1438 let Inst{11-7} = op11_7; 1439 let Inst{6} = op6; 1440 let Inst{4} = op4; 1441} 1442 1443// Same as N2V except it doesn't have a datatype suffix. 1444class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1445 bits<5> op11_7, bit op6, bit op4, 1446 dag oops, dag iops, InstrItinClass itin, 1447 string opc, string asm, string cstr, list<dag> pattern> 1448 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1449 let Inst{24-23} = op24_23; 1450 let Inst{21-20} = op21_20; 1451 let Inst{19-18} = op19_18; 1452 let Inst{17-16} = op17_16; 1453 let Inst{11-7} = op11_7; 1454 let Inst{6} = op6; 1455 let Inst{4} = op4; 1456} 1457 1458// NEON 2 vector register with immediate. 1459class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1460 dag oops, dag iops, InstrItinClass itin, 1461 string opc, string dt, string asm, string cstr, list<dag> pattern> 1462 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1463 let Inst{24} = op24; 1464 let Inst{23} = op23; 1465 let Inst{11-8} = op11_8; 1466 let Inst{7} = op7; 1467 let Inst{6} = op6; 1468 let Inst{4} = op4; 1469} 1470 1471// NEON 3 vector register format. 1472class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1473 dag oops, dag iops, InstrItinClass itin, 1474 string opc, string dt, string asm, string cstr, list<dag> pattern> 1475 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> { 1476 let Inst{24} = op24; 1477 let Inst{23} = op23; 1478 let Inst{21-20} = op21_20; 1479 let Inst{11-8} = op11_8; 1480 let Inst{6} = op6; 1481 let Inst{4} = op4; 1482} 1483 1484// Same as N3VX except it doesn't have a data type suffix. 1485class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1486 dag oops, dag iops, InstrItinClass itin, 1487 string opc, string asm, string cstr, list<dag> pattern> 1488 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> { 1489 let Inst{24} = op24; 1490 let Inst{23} = op23; 1491 let Inst{21-20} = op21_20; 1492 let Inst{11-8} = op11_8; 1493 let Inst{6} = op6; 1494 let Inst{4} = op4; 1495} 1496 1497// NEON VMOVs between scalar and core registers. 1498class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1499 dag oops, dag iops, Format f, InstrItinClass itin, 1500 string opc, string dt, string asm, list<dag> pattern> 1501 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain, 1502 "", itin> { 1503 let Inst{27-20} = opcod1; 1504 let Inst{11-8} = opcod2; 1505 let Inst{6-5} = opcod3; 1506 let Inst{4} = 1; 1507 1508 let OutOperandList = oops; 1509 let InOperandList = !con(iops, (ops pred:$p)); 1510 let AsmString = !strconcat( 1511 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), 1512 !strconcat("\t", asm)); 1513 let Pattern = pattern; 1514 list<Predicate> Predicates = [HasNEON]; 1515} 1516class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1517 dag oops, dag iops, InstrItinClass itin, 1518 string opc, string dt, string asm, list<dag> pattern> 1519 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin, 1520 opc, dt, asm, pattern>; 1521class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1522 dag oops, dag iops, InstrItinClass itin, 1523 string opc, string dt, string asm, list<dag> pattern> 1524 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin, 1525 opc, dt, asm, pattern>; 1526class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1527 dag oops, dag iops, InstrItinClass itin, 1528 string opc, string dt, string asm, list<dag> pattern> 1529 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin, 1530 opc, dt, asm, pattern>; 1531 1532// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1533// for single-precision FP. 1534class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1535 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1536} 1537