ARMBaseRegisterInfo.cpp revision 280031
1139743Simp//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2123474Swpaul// 3123474Swpaul// The LLVM Compiler Infrastructure 4123474Swpaul// 5123474Swpaul// This file is distributed under the University of Illinois Open Source 6123474Swpaul// License. See LICENSE.TXT for details. 7123474Swpaul// 8123474Swpaul//===----------------------------------------------------------------------===// 9123474Swpaul// 10123474Swpaul// This file contains the base ARM implementation of TargetRegisterInfo class. 11123474Swpaul// 12123474Swpaul//===----------------------------------------------------------------------===// 13123474Swpaul 14123474Swpaul#include "ARMBaseRegisterInfo.h" 15123474Swpaul#include "ARM.h" 16123474Swpaul#include "ARMBaseInstrInfo.h" 17123474Swpaul#include "ARMFrameLowering.h" 18123474Swpaul#include "ARMMachineFunctionInfo.h" 19123474Swpaul#include "ARMSubtarget.h" 20123474Swpaul#include "MCTargetDesc/ARMAddressingModes.h" 21123474Swpaul#include "llvm/ADT/BitVector.h" 22123474Swpaul#include "llvm/ADT/SmallVector.h" 23123474Swpaul#include "llvm/CodeGen/MachineConstantPool.h" 24123474Swpaul#include "llvm/CodeGen/MachineFrameInfo.h" 25123474Swpaul#include "llvm/CodeGen/MachineFunction.h" 26123474Swpaul#include "llvm/CodeGen/MachineInstrBuilder.h" 27123474Swpaul#include "llvm/CodeGen/MachineRegisterInfo.h" 28123474Swpaul#include "llvm/CodeGen/RegisterScavenging.h" 29123474Swpaul#include "llvm/CodeGen/VirtRegMap.h" 30123474Swpaul#include "llvm/IR/Constants.h" 31123474Swpaul#include "llvm/IR/DerivedTypes.h" 32123474Swpaul#include "llvm/IR/Function.h" 33123474Swpaul#include "llvm/IR/LLVMContext.h" 34123474Swpaul#include "llvm/Support/Debug.h" 35123474Swpaul#include "llvm/Support/ErrorHandling.h" 36123474Swpaul#include "llvm/Support/raw_ostream.h" 37123474Swpaul#include "llvm/Target/TargetFrameLowering.h" 38140751Swpaul#include "llvm/Target/TargetMachine.h" 39140751Swpaul#include "llvm/Target/TargetOptions.h" 40140751Swpaul 41140751Swpaul#define DEBUG_TYPE "arm-register-info" 42140751Swpaul 43140751Swpaul#define GET_REGINFO_TARGET_DESC 44140751Swpaul#include "ARMGenRegisterInfo.inc" 45140751Swpaul 46140751Swpaulusing namespace llvm; 47140751Swpaul 48140751SwpaulARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti) 49140751Swpaul : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), BasePtr(ARM::R6) { 50140751Swpaul if (STI.isTargetMachO()) { 51140751Swpaul if (STI.isTargetDarwin() || STI.isThumb1Only()) 52140751Swpaul FramePtr = ARM::R7; 53140751Swpaul else 54140751Swpaul FramePtr = ARM::R11; 55140751Swpaul } else if (STI.isTargetWindows()) 56140751Swpaul FramePtr = ARM::R11; 57140751Swpaul else // ARM EABI 58140751Swpaul FramePtr = STI.isThumb() ? ARM::R7 : ARM::R11; 59140751Swpaul} 60140751Swpaul 61140751Swpaulconst MCPhysReg* 62140751SwpaulARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 63140751Swpaul const MCPhysReg *RegList = 64140751Swpaul STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 65140751Swpaul 66140751Swpaul if (!MF) return RegList; 67140751Swpaul 68140751Swpaul const Function *F = MF->getFunction(); 69140751Swpaul if (F->getCallingConv() == CallingConv::GHC) { 70140751Swpaul // GHC set of callee saved regs is empty as all those regs are 71140751Swpaul // used for passing STG regs around 72140751Swpaul return CSR_NoRegs_SaveList; 73140751Swpaul } else if (F->hasFnAttribute("interrupt")) { 74140751Swpaul if (STI.isMClass()) { 75140751Swpaul // M-class CPUs have hardware which saves the registers needed to allow a 76140751Swpaul // function conforming to the AAPCS to function as a handler. 77140751Swpaul return CSR_AAPCS_SaveList; 78140751Swpaul } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") { 79140751Swpaul // Fast interrupt mode gives the handler a private copy of R8-R14, so less 80140751Swpaul // need to be saved to restore user-mode state. 81140751Swpaul return CSR_FIQ_SaveList; 82140751Swpaul } else { 83140751Swpaul // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by 84140751Swpaul // exception handling. 85140751Swpaul return CSR_GenericInt_SaveList; 86140751Swpaul } 87140751Swpaul } 88140751Swpaul 89140751Swpaul return RegList; 90140751Swpaul} 91140751Swpaul 92140751Swpaulconst uint32_t* 93140751SwpaulARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 94140751Swpaul if (CC == CallingConv::GHC) 95140751Swpaul // This is academic becase all GHC calls are (supposed to be) tail calls 96140751Swpaul return CSR_NoRegs_RegMask; 97140751Swpaul return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 98140751Swpaul} 99140751Swpaul 100140751Swpaulconst uint32_t* 101140751SwpaulARMBaseRegisterInfo::getNoPreservedMask() const { 102140751Swpaul return CSR_NoRegs_RegMask; 103140751Swpaul} 104123512Swpaul 105140751Swpaulconst uint32_t* 106140751SwpaulARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const { 107123512Swpaul // This should return a register mask that is the same as that returned by 108140751Swpaul // getCallPreservedMask but that additionally preserves the register used for 109140751Swpaul // the first i32 argument (which must also be the register used to return a 110140751Swpaul // single i32 return value) 111140751Swpaul // 112140751Swpaul // In case that the calling convention does not use the same register for 113140751Swpaul // both or otherwise does not want to enable this optimization, the function 114123512Swpaul // should return NULL 115140751Swpaul if (CC == CallingConv::GHC) 116123512Swpaul // This is academic becase all GHC calls are (supposed to be) tail calls 117140751Swpaul return nullptr; 118123757Swpaul return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask 119123757Swpaul : CSR_AAPCS_ThisReturn_RegMask; 120140751Swpaul} 121123757Swpaul 122123757SwpaulBitVector ARMBaseRegisterInfo:: 123140751SwpaulgetReservedRegs(const MachineFunction &MF) const { 124140751Swpaul const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 125140751Swpaul 126140751Swpaul // FIXME: avoid re-calculating this every time. 127140751Swpaul BitVector Reserved(getNumRegs()); 128140751Swpaul Reserved.set(ARM::SP); 129123757Swpaul Reserved.set(ARM::PC); 130140751Swpaul Reserved.set(ARM::FPSCR); 131140751Swpaul Reserved.set(ARM::APSR_NZCV); 132140751Swpaul if (TFI->hasFP(MF)) 133140751Swpaul Reserved.set(FramePtr); 134123512Swpaul if (hasBasePointer(MF)) 135140751Swpaul Reserved.set(BasePtr); 136140751Swpaul // Some targets reserve R9. 137140751Swpaul if (STI.isR9Reserved()) 138140751Swpaul Reserved.set(ARM::R9); 139140751Swpaul // Reserve D16-D31 if the subtarget doesn't support them. 140140751Swpaul if (!STI.hasVFP3() || STI.hasD16()) { 141140751Swpaul assert(ARM::D31 == ARM::D16 + 15); 142124729Swpaul for (unsigned i = 0; i != 16; ++i) 143124729Swpaul Reserved.set(ARM::D16 + i); 144124729Swpaul } 145124729Swpaul const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 146124729Swpaul for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 147124729Swpaul for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 148124729Swpaul if (Reserved.test(*SI)) Reserved.set(*I); 149124582Sobrien 150124582Sobrien return Reserved; 151124582Sobrien} 152124582Sobrien 153124582Sobrienconst TargetRegisterClass* 154124582SobrienARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 155124582Sobrien const { 156124582Sobrien const TargetRegisterClass *Super = RC; 157124582Sobrien TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 158124582Sobrien do { 159124582Sobrien switch (Super->getID()) { 160124582Sobrien case ARM::GPRRegClassID: 161124582Sobrien case ARM::SPRRegClassID: 162124582Sobrien case ARM::DPRRegClassID: 163124582Sobrien case ARM::QPRRegClassID: 164124582Sobrien case ARM::QQPRRegClassID: 165124582Sobrien case ARM::QQQQPRRegClassID: 166124582Sobrien case ARM::GPRPairRegClassID: 167124582Sobrien return Super; 168124582Sobrien } 169123474Swpaul Super = *I++; 170124582Sobrien } while (Super); 171124582Sobrien return RC; 172123474Swpaul} 173123474Swpaul 174123474Swpaulconst TargetRegisterClass * 175123474SwpaulARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 176123474Swpaul const { 177123474Swpaul return &ARM::GPRRegClass; 178123474Swpaul} 179123474Swpaul 180123474Swpaulconst TargetRegisterClass * 181123474SwpaulARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 182123474Swpaul if (RC == &ARM::CCRRegClass) 183123474Swpaul return &ARM::rGPRRegClass; // Can't copy CCR registers. 184123474Swpaul return RC; 185123474Swpaul} 186123474Swpaul 187123474Swpaulunsigned 188123474SwpaulARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 189123507Swpaul MachineFunction &MF) const { 190123507Swpaul const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 191123507Swpaul 192123507Swpaul switch (RC->getID()) { 193123507Swpaul default: 194123507Swpaul return 0; 195123507Swpaul case ARM::tGPRRegClassID: 196125551Swpaul return TFI->hasFP(MF) ? 4 : 5; 197141524Swpaul case ARM::GPRRegClassID: { 198125551Swpaul unsigned FP = TFI->hasFP(MF) ? 1 : 0; 199125551Swpaul return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 200125551Swpaul } 201125551Swpaul case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 202125551Swpaul case ARM::DPRRegClassID: 203125551Swpaul return 32 - 10; 204125551Swpaul } 205125551Swpaul} 206125551Swpaul 207125551Swpaul// Get the other register in a GPRPair. 208125551Swpaulstatic unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 209125551Swpaul for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 210125551Swpaul if (ARM::GPRPairRegClass.contains(*Supers)) 211125551Swpaul return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 212125551Swpaul return 0; 213125551Swpaul} 214125551Swpaul 215125551Swpaul// Resolve the RegPairEven / RegPairOdd register allocator hints. 216125551Swpaulvoid 217125551SwpaulARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 218125551Swpaul ArrayRef<MCPhysReg> Order, 219125551Swpaul SmallVectorImpl<MCPhysReg> &Hints, 220125551Swpaul const MachineFunction &MF, 221125551Swpaul const VirtRegMap *VRM) const { 222125551Swpaul const MachineRegisterInfo &MRI = MF.getRegInfo(); 223125551Swpaul std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 224125551Swpaul 225125551Swpaul unsigned Odd; 226125551Swpaul switch (Hint.first) { 227125551Swpaul case ARMRI::RegPairEven: 228125551Swpaul Odd = 0; 229125551Swpaul break; 230125551Swpaul case ARMRI::RegPairOdd: 231125551Swpaul Odd = 1; 232125551Swpaul break; 233125551Swpaul default: 234125551Swpaul TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 235125551Swpaul return; 236125551Swpaul } 237125860Swpaul 238125551Swpaul // This register should preferably be even (Odd == 0) or odd (Odd == 1). 239141524Swpaul // Check if the other part of the pair has already been assigned, and provide 240141524Swpaul // the paired register as the first hint. 241125551Swpaul unsigned PairedPhys = 0; 242125551Swpaul if (VRM && VRM->hasPhys(Hint.second)) { 243125551Swpaul PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 244125551Swpaul if (PairedPhys && MRI.isReserved(PairedPhys)) 245125551Swpaul PairedPhys = 0; 246125551Swpaul } 247125551Swpaul 248125551Swpaul // First prefer the paired physreg. 249125551Swpaul if (PairedPhys && 250125551Swpaul std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 251125551Swpaul Hints.push_back(PairedPhys); 252125551Swpaul 253125551Swpaul // Then prefer even or odd registers. 254125551Swpaul for (unsigned I = 0, E = Order.size(); I != E; ++I) { 255125551Swpaul unsigned Reg = Order[I]; 256125551Swpaul if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 257125551Swpaul continue; 258125551Swpaul // Don't provide hints that are paired to a reserved register. 259125551Swpaul unsigned Paired = getPairedGPR(Reg, !Odd, this); 260125551Swpaul if (!Paired || MRI.isReserved(Paired)) 261125551Swpaul continue; 262125551Swpaul Hints.push_back(Reg); 263125551Swpaul } 264125551Swpaul} 265125551Swpaul 266125551Swpaulvoid 267125551SwpaulARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 268125551Swpaul MachineFunction &MF) const { 269125551Swpaul MachineRegisterInfo *MRI = &MF.getRegInfo(); 270125551Swpaul std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 271125551Swpaul if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 272125551Swpaul Hint.first == (unsigned)ARMRI::RegPairEven) && 273125551Swpaul TargetRegisterInfo::isVirtualRegister(Hint.second)) { 274125551Swpaul // If 'Reg' is one of the even / odd register pair and it's now changed 275125551Swpaul // (e.g. coalesced) into a different register. The other register of the 276128229Swpaul // pair allocation hint must be updated to reflect the relationship 277125551Swpaul // change. 278125551Swpaul unsigned OtherReg = Hint.second; 279125551Swpaul Hint = MRI->getRegAllocationHint(OtherReg); 280125551Swpaul if (Hint.second == Reg) 281125551Swpaul // Make sure the pair has not already divorced. 282125551Swpaul MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 283125551Swpaul } 284125551Swpaul} 285125551Swpaul 286125551Swpaulbool 287128229SwpaulARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 288128229Swpaul // CortexA9 has a Write-after-write hazard for NEON registers. 289128229Swpaul if (!STI.isLikeA9()) 290128229Swpaul return false; 291128449Swpaul 292128229Swpaul switch (RC->getID()) { 293128229Swpaul case ARM::DPRRegClassID: 294128295Swpaul case ARM::DPR_8RegClassID: 295128229Swpaul case ARM::DPR_VFP2RegClassID: 296128229Swpaul case ARM::QPRRegClassID: 297128229Swpaul case ARM::QPR_8RegClassID: 298128229Swpaul case ARM::QPR_VFP2RegClassID: 299125551Swpaul case ARM::SPRRegClassID: 300125551Swpaul case ARM::SPR_8RegClassID: 301125551Swpaul // Avoid reusing S, D, and Q registers. 302125551Swpaul // Don't increase register pressure for QQ and QQQQ. 303125551Swpaul return true; 304125551Swpaul default: 305125551Swpaul return false; 306125551Swpaul } 307125551Swpaul} 308125551Swpaul 309125551Swpaulbool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 310125551Swpaul const MachineFrameInfo *MFI = MF.getFrameInfo(); 311125551Swpaul const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 312126620Swpaul const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 313126620Swpaul 314126620Swpaul // When outgoing call frames are so large that we adjust the stack pointer 315126620Swpaul // around the call, we can no longer use the stack pointer to reach the 316126620Swpaul // emergency spill slot. 317126620Swpaul if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 318126620Swpaul return true; 319126620Swpaul 320126620Swpaul // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 321126620Swpaul // negative range for ldr/str (255), and thumb1 is positive offsets only. 322126620Swpaul // It's going to be better to use the SP or Base Pointer instead. When there 323126620Swpaul // are variable sized objects, we can't reference off of the SP, so we 324126620Swpaul // reserve a Base Pointer. 325125551Swpaul if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 326125551Swpaul // Conservatively estimate whether the negative offset from the frame 327125551Swpaul // pointer will be sufficient to reach. If a function has a smallish 328126620Swpaul // frame, it's less likely to have lots of spills and callee saved 329126620Swpaul // space, so it's all more likely to be within range of the frame pointer. 330126620Swpaul // If it's wrong, the scavenger will still enable access to work, it just 331126620Swpaul // won't be optimal. 332125551Swpaul if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 333125551Swpaul return false; 334125551Swpaul return true; 335125551Swpaul } 336126620Swpaul 337126620Swpaul return false; 338126620Swpaul} 339126620Swpaul 340126620Swpaulbool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 341125551Swpaul const MachineRegisterInfo *MRI = &MF.getRegInfo(); 342125551Swpaul const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 343125551Swpaul // We can't realign the stack if: 344125551Swpaul // 1. Dynamic stack realignment is explicitly disabled, 345125551Swpaul // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 346125551Swpaul // 3. There are VLAs in the function and the base pointer is disabled. 347125551Swpaul if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 348125551Swpaul return false; 349125551Swpaul if (AFI->isThumb1OnlyFunction()) 350125551Swpaul return false; 351125551Swpaul // Stack realignment requires a frame pointer. If we already started 352125551Swpaul // register allocation with frame pointer elimination, it is too late now. 353125551Swpaul if (!MRI->canReserveReg(FramePtr)) 354125551Swpaul return false; 355125551Swpaul // We may also need a base pointer if there are dynamic allocas or stack 356125551Swpaul // pointer adjustments around calls. 357140827Swpaul if (MF.getTarget() 358125551Swpaul .getSubtargetImpl() 359125551Swpaul ->getFrameLowering() 360125551Swpaul ->hasReservedCallFrame(MF)) 361127552Swpaul return true; 362125551Swpaul // A base pointer is required and allowed. Check that it isn't too late to 363125551Swpaul // reserve it. 364126620Swpaul return MRI->canReserveReg(BasePtr); 365126620Swpaul} 366125551Swpaul 367125551Swpaulbool ARMBaseRegisterInfo:: 368125551SwpaulneedsStackRealignment(const MachineFunction &MF) const { 369125551Swpaul const MachineFrameInfo *MFI = MF.getFrameInfo(); 370125551Swpaul const Function *F = MF.getFunction(); 371125551Swpaul unsigned StackAlign = MF.getTarget() 372125551Swpaul .getSubtargetImpl() 373125551Swpaul ->getFrameLowering() 374125551Swpaul ->getStackAlignment(); 375125551Swpaul bool requiresRealignment = 376125551Swpaul ((MFI->getMaxAlignment() > StackAlign) || 377125551Swpaul F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 378125551Swpaul Attribute::StackAlignment)); 379126620Swpaul 380126620Swpaul return requiresRealignment && canRealignStack(MF); 381126620Swpaul} 382126620Swpaul 383125551Swpaulbool ARMBaseRegisterInfo:: 384125551SwpaulcannotEliminateFrame(const MachineFunction &MF) const { 385125551Swpaul const MachineFrameInfo *MFI = MF.getFrameInfo(); 386125551Swpaul if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 387125551Swpaul return true; 388126620Swpaul return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 389126620Swpaul || needsStackRealignment(MF); 390126620Swpaul} 391125551Swpaul 392125551Swpaulunsigned 393125860SwpaulARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 394125860Swpaul const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 395123474Swpaul 396123474Swpaul if (TFI->hasFP(MF)) 397123474Swpaul return FramePtr; 398123474Swpaul return ARM::SP; 399123474Swpaul} 400123474Swpaul 401123474Swpaul/// emitLoadConstPool - Emits a load from constpool to materialize the 402123474Swpaul/// specified immediate. 403123474Swpaulvoid ARMBaseRegisterInfo:: 404123474SwpaulemitLoadConstPool(MachineBasicBlock &MBB, 405123474Swpaul MachineBasicBlock::iterator &MBBI, 406123474Swpaul DebugLoc dl, 407123474Swpaul unsigned DestReg, unsigned SubIdx, int Val, 408123474Swpaul ARMCC::CondCodes Pred, 409123474Swpaul unsigned PredReg, unsigned MIFlags) const { 410123474Swpaul MachineFunction &MF = *MBB.getParent(); 411123474Swpaul const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 412123474Swpaul MachineConstantPool *ConstantPool = MF.getConstantPool(); 413123474Swpaul const Constant *C = 414123507Swpaul ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 415123474Swpaul unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 416123474Swpaul 417123474Swpaul BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 418123474Swpaul .addReg(DestReg, getDefRegState(true), SubIdx) 419123474Swpaul .addConstantPoolIndex(Idx) 420123474Swpaul .addImm(0).addImm(Pred).addReg(PredReg) 421123474Swpaul .setMIFlags(MIFlags); 422123474Swpaul} 423123474Swpaul 424123474Swpaulbool ARMBaseRegisterInfo:: 425123474SwpaulrequiresRegisterScavenging(const MachineFunction &MF) const { 426123474Swpaul return true; 427123474Swpaul} 428123474Swpaul 429123474Swpaulbool ARMBaseRegisterInfo:: 430123474SwpaultrackLivenessAfterRegAlloc(const MachineFunction &MF) const { 431123474Swpaul return true; 432123474Swpaul} 433123474Swpaul 434123474Swpaulbool ARMBaseRegisterInfo:: 435123474SwpaulrequiresFrameIndexScavenging(const MachineFunction &MF) const { 436125551Swpaul return true; 437123474Swpaul} 438125551Swpaul 439125551Swpaulbool ARMBaseRegisterInfo:: 440125551SwpaulrequiresVirtualBaseRegisters(const MachineFunction &MF) const { 441125551Swpaul return true; 442125551Swpaul} 443125551Swpaul 444125551Swpaulint64_t ARMBaseRegisterInfo:: 445125551SwpaulgetFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 446125551Swpaul const MCInstrDesc &Desc = MI->getDesc(); 447125551Swpaul unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 448125551Swpaul int64_t InstrOffs = 0; 449125551Swpaul int Scale = 1; 450125551Swpaul unsigned ImmIdx = 0; 451125551Swpaul switch (AddrMode) { 452125551Swpaul case ARMII::AddrModeT2_i8: 453125551Swpaul case ARMII::AddrModeT2_i12: 454125551Swpaul case ARMII::AddrMode_i12: 455125551Swpaul InstrOffs = MI->getOperand(Idx+1).getImm(); 456125551Swpaul Scale = 1; 457125551Swpaul break; 458125551Swpaul case ARMII::AddrMode5: { 459125551Swpaul // VFP address mode. 460125551Swpaul const MachineOperand &OffOp = MI->getOperand(Idx+1); 461125551Swpaul InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 462125551Swpaul if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 463125551Swpaul InstrOffs = -InstrOffs; 464125551Swpaul Scale = 4; 465125551Swpaul break; 466125551Swpaul } 467125551Swpaul case ARMII::AddrMode2: { 468125551Swpaul ImmIdx = Idx+2; 469125551Swpaul InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 470125551Swpaul if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 471125551Swpaul InstrOffs = -InstrOffs; 472125551Swpaul break; 473125551Swpaul } 474125551Swpaul case ARMII::AddrMode3: { 475125551Swpaul ImmIdx = Idx+2; 476125551Swpaul InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 477125551Swpaul if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 478125551Swpaul InstrOffs = -InstrOffs; 479125551Swpaul break; 480125551Swpaul } 481125551Swpaul case ARMII::AddrModeT1_s: { 482125551Swpaul ImmIdx = Idx+1; 483125551Swpaul InstrOffs = MI->getOperand(ImmIdx).getImm(); 484125551Swpaul Scale = 4; 485125551Swpaul break; 486125551Swpaul } 487125551Swpaul default: 488125551Swpaul llvm_unreachable("Unsupported addressing mode!"); 489125551Swpaul } 490125551Swpaul 491125551Swpaul return InstrOffs * Scale; 492140751Swpaul} 493140751Swpaul 494140751Swpaul/// needsFrameBaseReg - Returns true if the instruction's frame index 495140751Swpaul/// reference would be better served by a base register other than FP 496140751Swpaul/// or SP. Used by LocalStackFrameAllocation to determine which frame index 497140751Swpaul/// references it should create new base registers for. 498140751Swpaulbool ARMBaseRegisterInfo:: 499140751SwpaulneedsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 500140751Swpaul for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 501141524Swpaul assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 502141524Swpaul } 503141524Swpaul 504141524Swpaul // It's the load/store FI references that cause issues, as it can be difficult 505141524Swpaul // to materialize the offset if it won't fit in the literal field. Estimate 506141524Swpaul // based on the size of the local frame and some conservative assumptions 507141524Swpaul // about the rest of the stack frame (note, this is pre-regalloc, so 508141524Swpaul // we don't know everything for certain yet) whether this offset is likely 509140751Swpaul // to be out of range of the immediate. Return true if so. 510140751Swpaul 511140751Swpaul // We only generate virtual base registers for loads and stores, so 512140751Swpaul // return false for everything else. 513141524Swpaul unsigned Opc = MI->getOpcode(); 514141524Swpaul switch (Opc) { 515141524Swpaul case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 516141524Swpaul case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 517141524Swpaul case ARM::t2LDRi12: case ARM::t2LDRi8: 518141524Swpaul case ARM::t2STRi12: case ARM::t2STRi8: 519141524Swpaul case ARM::VLDRS: case ARM::VLDRD: 520140751Swpaul case ARM::VSTRS: case ARM::VSTRD: 521140751Swpaul case ARM::tSTRspi: case ARM::tLDRspi: 522140751Swpaul break; 523140751Swpaul default: 524140751Swpaul return false; 525140751Swpaul } 526140751Swpaul 527140751Swpaul // Without a virtual base register, if the function has variable sized 528140751Swpaul // objects, all fixed-size local references will be via the frame pointer, 529140751Swpaul // Approximate the offset and see if it's legal for the instruction. 530140751Swpaul // Note that the incoming offset is based on the SP value at function entry, 531140751Swpaul // so it'll be negative. 532140751Swpaul MachineFunction &MF = *MI->getParent()->getParent(); 533140751Swpaul const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 534140751Swpaul MachineFrameInfo *MFI = MF.getFrameInfo(); 535140751Swpaul ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 536125551Swpaul 537125551Swpaul // Estimate an offset from the frame pointer. 538125551Swpaul // Conservatively assume all callee-saved registers get pushed. R4-R6 539125551Swpaul // will be earlier than the FP, so we ignore those. 540141524Swpaul // R7, LR 541125551Swpaul int64_t FPOffset = Offset - 8; 542125551Swpaul // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 543125551Swpaul if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 544125551Swpaul FPOffset -= 80; 545125551Swpaul // Estimate an offset from the stack pointer. 546125551Swpaul // The incoming offset is relating to the SP at the start of the function, 547125551Swpaul // but when we access the local it'll be relative to the SP after local 548125551Swpaul // allocation, so adjust our SP-relative offset by that allocation size. 549141524Swpaul Offset = -Offset; 550125551Swpaul Offset += MFI->getLocalFrameSize(); 551125551Swpaul // Assume that we'll have at least some spill slots allocated. 552125551Swpaul // FIXME: This is a total SWAG number. We should run some statistics 553125551Swpaul // and pick a real one. 554125551Swpaul Offset += 128; // 128 bytes of spill slots 555125551Swpaul 556125551Swpaul // If there is a frame pointer, try using it. 557125551Swpaul // The FP is only available if there is no dynamic realignment. We 558125551Swpaul // don't know for sure yet whether we'll need that, so we guess based 559125551Swpaul // on whether there are any local variables that would trigger it. 560125551Swpaul unsigned StackAlign = TFI->getStackAlignment(); 561125551Swpaul if (TFI->hasFP(MF) && 562125551Swpaul !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 563140751Swpaul if (isFrameOffsetLegal(MI, FPOffset)) 564125551Swpaul return false; 565125551Swpaul } 566125551Swpaul // If we can reference via the stack pointer, try that. 567125551Swpaul // FIXME: This (and the code that resolves the references) can be improved 568125551Swpaul // to only disallow SP relative references in the live range of 569140751Swpaul // the VLA(s). In practice, it's unclear how much difference that 570140751Swpaul // would make, but it may be worth doing. 571140751Swpaul if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 572140751Swpaul return false; 573140751Swpaul 574140751Swpaul // The offset likely isn't legal, we want to allocate a virtual base register. 575140751Swpaul return true; 576140751Swpaul} 577140751Swpaul 578140751Swpaul/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 579140751Swpaul/// be a pointer to FrameIdx at the beginning of the basic block. 580140751Swpaulvoid ARMBaseRegisterInfo:: 581140751SwpaulmaterializeFrameBaseRegister(MachineBasicBlock *MBB, 582140751Swpaul unsigned BaseReg, int FrameIdx, 583140751Swpaul int64_t Offset) const { 584140751Swpaul ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 585140751Swpaul unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 586140751Swpaul (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); 587140751Swpaul 588140751Swpaul MachineBasicBlock::iterator Ins = MBB->begin(); 589140751Swpaul DebugLoc DL; // Defaults to "unknown" 590140751Swpaul if (Ins != MBB->end()) 591140751Swpaul DL = Ins->getDebugLoc(); 592140751Swpaul 593140751Swpaul const MachineFunction &MF = *MBB->getParent(); 594140751Swpaul MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 595140751Swpaul const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 596140751Swpaul const MCInstrDesc &MCID = TII.get(ADDriOpc); 597140751Swpaul MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 598140751Swpaul 599140751Swpaul MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) 600140751Swpaul .addFrameIndex(FrameIdx).addImm(Offset); 601140751Swpaul 602140751Swpaul if (!AFI->isThumb1OnlyFunction()) 603140751Swpaul AddDefaultCC(AddDefaultPred(MIB)); 604140751Swpaul} 605140751Swpaul 606140751Swpaulvoid ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 607140751Swpaul int64_t Offset) const { 608140751Swpaul MachineBasicBlock &MBB = *MI.getParent(); 609140751Swpaul MachineFunction &MF = *MBB.getParent(); 610140751Swpaul const ARMBaseInstrInfo &TII = 611140751Swpaul *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 612140751Swpaul ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 613140751Swpaul int Off = Offset; // ARM doesn't need the general 64-bit offsets 614140751Swpaul unsigned i = 0; 615140751Swpaul 616140751Swpaul assert(!AFI->isThumb1OnlyFunction() && 617140751Swpaul "This resolveFrameIndex does not support Thumb1!"); 618140751Swpaul 619140751Swpaul while (!MI.getOperand(i).isFI()) { 620140751Swpaul ++i; 621140751Swpaul assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 622140751Swpaul } 623140751Swpaul bool Done = false; 624140751Swpaul if (!AFI->isThumbFunction()) 625140751Swpaul Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 626140751Swpaul else { 627140751Swpaul assert(AFI->isThumb2Function()); 628140751Swpaul Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 629140751Swpaul } 630140751Swpaul assert (Done && "Unable to resolve frame index!"); 631140751Swpaul (void)Done; 632140751Swpaul} 633140751Swpaul 634140751Swpaulbool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 635140751Swpaul int64_t Offset) const { 636140751Swpaul const MCInstrDesc &Desc = MI->getDesc(); 637140751Swpaul unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 638140751Swpaul unsigned i = 0; 639140751Swpaul 640140751Swpaul while (!MI->getOperand(i).isFI()) { 641140751Swpaul ++i; 642140751Swpaul assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 643140751Swpaul } 644140751Swpaul 645140751Swpaul // AddrMode4 and AddrMode6 cannot handle any offset. 646140751Swpaul if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 647140751Swpaul return Offset == 0; 648140751Swpaul 649140751Swpaul unsigned NumBits = 0; 650140751Swpaul unsigned Scale = 1; 651140751Swpaul bool isSigned = true; 652140751Swpaul switch (AddrMode) { 653140751Swpaul case ARMII::AddrModeT2_i8: 654140751Swpaul case ARMII::AddrModeT2_i12: 655140751Swpaul // i8 supports only negative, and i12 supports only positive, so 656140751Swpaul // based on Offset sign, consider the appropriate instruction 657140751Swpaul Scale = 1; 658140751Swpaul if (Offset < 0) { 659140751Swpaul NumBits = 8; 660140751Swpaul Offset = -Offset; 661140751Swpaul } else { 662140751Swpaul NumBits = 12; 663140751Swpaul } 664140751Swpaul break; 665140751Swpaul case ARMII::AddrMode5: 666140751Swpaul // VFP address mode. 667140751Swpaul NumBits = 8; 668140751Swpaul Scale = 4; 669140751Swpaul break; 670140751Swpaul case ARMII::AddrMode_i12: 671140751Swpaul case ARMII::AddrMode2: 672140751Swpaul NumBits = 12; 673140751Swpaul break; 674140751Swpaul case ARMII::AddrMode3: 675140751Swpaul NumBits = 8; 676140751Swpaul break; 677140751Swpaul case ARMII::AddrModeT1_s: 678140751Swpaul NumBits = 5; 679140751Swpaul Scale = 4; 680140751Swpaul isSigned = false; 681140751Swpaul break; 682140751Swpaul default: 683140751Swpaul llvm_unreachable("Unsupported addressing mode!"); 684140751Swpaul } 685140751Swpaul 686140751Swpaul Offset += getFrameIndexInstrOffset(MI, i); 687140751Swpaul // Make sure the offset is encodable for instructions that scale the 688140751Swpaul // immediate. 689140751Swpaul if ((Offset & (Scale-1)) != 0) 690140751Swpaul return false; 691140751Swpaul 692140751Swpaul if (isSigned && Offset < 0) 693140751Swpaul Offset = -Offset; 694140751Swpaul 695140751Swpaul unsigned Mask = (1 << NumBits) - 1; 696140751Swpaul if ((unsigned)Offset <= Mask * Scale) 697140751Swpaul return true; 698140751Swpaul 699140751Swpaul return false; 700140751Swpaul} 701140751Swpaul 702140751Swpaulvoid 703140751SwpaulARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 704140751Swpaul int SPAdj, unsigned FIOperandNum, 705140751Swpaul RegScavenger *RS) const { 706140751Swpaul MachineInstr &MI = *II; 707140751Swpaul MachineBasicBlock &MBB = *MI.getParent(); 708140751Swpaul MachineFunction &MF = *MBB.getParent(); 709140751Swpaul const ARMBaseInstrInfo &TII = 710140751Swpaul *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 711140751Swpaul const ARMFrameLowering *TFI = static_cast<const ARMFrameLowering *>( 712140751Swpaul MF.getSubtarget().getFrameLowering()); 713140751Swpaul ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 714140751Swpaul assert(!AFI->isThumb1OnlyFunction() && 715140751Swpaul "This eliminateFrameIndex does not support Thumb1!"); 716140751Swpaul int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 717140751Swpaul unsigned FrameReg; 718140751Swpaul 719140751Swpaul int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 720140751Swpaul 721140751Swpaul // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 722140751Swpaul // call frame setup/destroy instructions have already been eliminated. That 723140751Swpaul // means the stack pointer cannot be used to access the emergency spill slot 724140751Swpaul // when !hasReservedCallFrame(). 725140751Swpaul#ifndef NDEBUG 726140751Swpaul if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 727140751Swpaul assert(TFI->hasReservedCallFrame(MF) && 728140751Swpaul "Cannot use SP to access the emergency spill slot in " 729140751Swpaul "functions without a reserved call frame"); 730140751Swpaul assert(!MF.getFrameInfo()->hasVarSizedObjects() && 731140751Swpaul "Cannot use SP to access the emergency spill slot in " 732140751Swpaul "functions with variable sized frame objects"); 733141524Swpaul } 734141524Swpaul#endif // NDEBUG 735140751Swpaul 736140751Swpaul assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 737140751Swpaul 738140751Swpaul // Modify MI as necessary to handle as much of 'Offset' as possible 739140751Swpaul bool Done = false; 740140751Swpaul if (!AFI->isThumbFunction()) 741140751Swpaul Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 742140751Swpaul else { 743140751Swpaul assert(AFI->isThumb2Function()); 744140751Swpaul Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 745140751Swpaul } 746140751Swpaul if (Done) 747140751Swpaul return; 748140751Swpaul 749140751Swpaul // If we get here, the immediate doesn't fit into the instruction. We folded 750140751Swpaul // as much as possible above, handle the rest, providing a register that is 751140751Swpaul // SP+LargeImm. 752140751Swpaul assert((Offset || 753140751Swpaul (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 754140751Swpaul (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 755140751Swpaul "This code isn't needed if offset already handled!"); 756140751Swpaul 757141524Swpaul unsigned ScratchReg = 0; 758141524Swpaul int PIdx = MI.findFirstPredOperandIdx(); 759141524Swpaul ARMCC::CondCodes Pred = (PIdx == -1) 760140751Swpaul ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 761140751Swpaul unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 762140751Swpaul if (Offset == 0) 763140751Swpaul // Must be addrmode4/6. 764140751Swpaul MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 765140751Swpaul else { 766140751Swpaul ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 767140751Swpaul if (!AFI->isThumbFunction()) 768140751Swpaul emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 769140751Swpaul Offset, Pred, PredReg, TII); 770140751Swpaul else { 771140751Swpaul assert(AFI->isThumb2Function()); 772140751Swpaul emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 773140751Swpaul Offset, Pred, PredReg, TII); 774140751Swpaul } 775140751Swpaul // Update the original instruction to use the scratch register. 776140751Swpaul MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 777140751Swpaul } 778140751Swpaul} 779140751Swpaul 780140751Swpaulbool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI, 781140751Swpaul const TargetRegisterClass *SrcRC, 782140751Swpaul unsigned SubReg, 783140751Swpaul const TargetRegisterClass *DstRC, 784140751Swpaul unsigned DstSubReg, 785140751Swpaul const TargetRegisterClass *NewRC) const { 786140751Swpaul auto MBB = MI->getParent(); 787141524Swpaul auto MF = MBB->getParent(); 788140751Swpaul const MachineRegisterInfo &MRI = MF->getRegInfo(); 789140751Swpaul // If not copying into a sub-register this should be ok because we shouldn't 790140751Swpaul // need to split the reg. 791140751Swpaul if (!DstSubReg) 792140751Swpaul return true; 793140751Swpaul // Small registers don't frequently cause a problem, so we can coalesce them. 794140751Swpaul if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) 795140751Swpaul return true; 796140751Swpaul 797140751Swpaul auto NewRCWeight = 798140751Swpaul MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); 799140751Swpaul auto SrcRCWeight = 800125551Swpaul MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); 801140751Swpaul auto DstRCWeight = 802140751Swpaul MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); 803140751Swpaul // If the source register class is more expensive than the destination, the 804140751Swpaul // coalescing is probably profitable. 805140751Swpaul if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight) 806140751Swpaul return true; 807140751Swpaul if (DstRCWeight.RegWeight > NewRCWeight.RegWeight) 808140751Swpaul return true; 809140751Swpaul 810140751Swpaul // If the register allocator isn't constrained, we can always allow coalescing 811140751Swpaul // unfortunately we don't know yet if we will be constrained. 812140751Swpaul // The goal of this heuristic is to restrict how many expensive registers 813140751Swpaul // we allow to coalesce in a given basic block. 814140751Swpaul auto AFI = MF->getInfo<ARMFunctionInfo>(); 815140751Swpaul auto It = AFI->getCoalescedWeight(MBB); 816140751Swpaul 817140751Swpaul DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " 818140751Swpaul << It->second << "\n"); 819140751Swpaul DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " 820140751Swpaul << NewRCWeight.RegWeight << "\n"); 821141524Swpaul 822140751Swpaul // This number is the largest round number that which meets the criteria: 823140751Swpaul // (1) addresses PR18825 824140751Swpaul // (2) generates better code in some test cases (like vldm-shed-a9.ll) 825140751Swpaul // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC) 826140751Swpaul // In practice the SizeMultiplier will only factor in for straight line code 827140751Swpaul // that uses a lot of NEON vectors, which isn't terribly common. 828140751Swpaul unsigned SizeMultiplier = MBB->size()/100; 829140751Swpaul SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1; 830140751Swpaul if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { 831140751Swpaul It->second += NewRCWeight.RegWeight; 832140751Swpaul return true; 833140751Swpaul } 834140751Swpaul return false; 835140751Swpaul} 836140751Swpaul