ARMBaseRegisterInfo.cpp revision 208599
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMBaseRegisterInfo.h" 18#include "ARMInstrInfo.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMSubtarget.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineLocation.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/RegisterScavenging.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetFrameInfo.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/BitVector.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/Support/CommandLine.h" 41 42namespace llvm { 43cl::opt<bool> 44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true), 45 cl::desc("Reuse repeated frame index values")); 46} 47 48using namespace llvm; 49 50unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 51 bool *isSPVFP) { 52 if (isSPVFP) 53 *isSPVFP = false; 54 55 using namespace ARM; 56 switch (RegEnum) { 57 default: 58 llvm_unreachable("Unknown ARM register!"); 59 case R0: case D0: case Q0: return 0; 60 case R1: case D1: case Q1: return 1; 61 case R2: case D2: case Q2: return 2; 62 case R3: case D3: case Q3: return 3; 63 case R4: case D4: case Q4: return 4; 64 case R5: case D5: case Q5: return 5; 65 case R6: case D6: case Q6: return 6; 66 case R7: case D7: case Q7: return 7; 67 case R8: case D8: case Q8: return 8; 68 case R9: case D9: case Q9: return 9; 69 case R10: case D10: case Q10: return 10; 70 case R11: case D11: case Q11: return 11; 71 case R12: case D12: case Q12: return 12; 72 case SP: case D13: case Q13: return 13; 73 case LR: case D14: case Q14: return 14; 74 case PC: case D15: case Q15: return 15; 75 76 case D16: return 16; 77 case D17: return 17; 78 case D18: return 18; 79 case D19: return 19; 80 case D20: return 20; 81 case D21: return 21; 82 case D22: return 22; 83 case D23: return 23; 84 case D24: return 24; 85 case D25: return 25; 86 case D26: return 26; 87 case D27: return 27; 88 case D28: return 28; 89 case D29: return 29; 90 case D30: return 30; 91 case D31: return 31; 92 93 case S0: case S1: case S2: case S3: 94 case S4: case S5: case S6: case S7: 95 case S8: case S9: case S10: case S11: 96 case S12: case S13: case S14: case S15: 97 case S16: case S17: case S18: case S19: 98 case S20: case S21: case S22: case S23: 99 case S24: case S25: case S26: case S27: 100 case S28: case S29: case S30: case S31: { 101 if (isSPVFP) 102 *isSPVFP = true; 103 switch (RegEnum) { 104 default: return 0; // Avoid compile time warning. 105 case S0: return 0; 106 case S1: return 1; 107 case S2: return 2; 108 case S3: return 3; 109 case S4: return 4; 110 case S5: return 5; 111 case S6: return 6; 112 case S7: return 7; 113 case S8: return 8; 114 case S9: return 9; 115 case S10: return 10; 116 case S11: return 11; 117 case S12: return 12; 118 case S13: return 13; 119 case S14: return 14; 120 case S15: return 15; 121 case S16: return 16; 122 case S17: return 17; 123 case S18: return 18; 124 case S19: return 19; 125 case S20: return 20; 126 case S21: return 21; 127 case S22: return 22; 128 case S23: return 23; 129 case S24: return 24; 130 case S25: return 25; 131 case S26: return 26; 132 case S27: return 27; 133 case S28: return 28; 134 case S29: return 29; 135 case S30: return 30; 136 case S31: return 31; 137 } 138 } 139 } 140} 141 142ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 143 const ARMSubtarget &sti) 144 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 145 TII(tii), STI(sti), 146 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 147} 148 149const unsigned* 150ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 151 static const unsigned CalleeSavedRegs[] = { 152 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 153 ARM::R7, ARM::R6, ARM::R5, ARM::R4, 154 155 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 156 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 157 0 158 }; 159 160 static const unsigned DarwinCalleeSavedRegs[] = { 161 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 162 // register. 163 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 164 ARM::R11, ARM::R10, ARM::R8, 165 166 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 167 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 168 0 169 }; 170 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 171} 172 173const TargetRegisterClass* const * 174ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 175 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 176 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 177 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 178 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 179 180 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 181 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 182 0 183 }; 184 185 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { 186 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 187 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, 188 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, 189 190 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 191 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 192 0 193 }; 194 195 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { 196 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 197 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 198 &ARM::GPRRegClass, &ARM::GPRRegClass, 199 200 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 201 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 202 0 203 }; 204 205 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ 206 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, 207 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, 208 &ARM::GPRRegClass, &ARM::GPRRegClass, 209 210 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 211 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 212 0 213 }; 214 215 if (STI.isThumb1Only()) { 216 return STI.isTargetDarwin() 217 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; 218 } 219 return STI.isTargetDarwin() 220 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; 221} 222 223BitVector ARMBaseRegisterInfo:: 224getReservedRegs(const MachineFunction &MF) const { 225 // FIXME: avoid re-calculating this everytime. 226 BitVector Reserved(getNumRegs()); 227 Reserved.set(ARM::SP); 228 Reserved.set(ARM::PC); 229 if (STI.isTargetDarwin() || hasFP(MF)) 230 Reserved.set(FramePtr); 231 // Some targets reserve R9. 232 if (STI.isR9Reserved()) 233 Reserved.set(ARM::R9); 234 return Reserved; 235} 236 237bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 238 unsigned Reg) const { 239 switch (Reg) { 240 default: break; 241 case ARM::SP: 242 case ARM::PC: 243 return true; 244 case ARM::R7: 245 case ARM::R11: 246 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 247 return true; 248 break; 249 case ARM::R9: 250 return STI.isR9Reserved(); 251 } 252 253 return false; 254} 255 256const TargetRegisterClass * 257ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 258 const TargetRegisterClass *B, 259 unsigned SubIdx) const { 260 switch (SubIdx) { 261 default: return 0; 262 case ARM::ssub_0: 263 case ARM::ssub_1: 264 case ARM::ssub_2: 265 case ARM::ssub_3: { 266 // S sub-registers. 267 if (A->getSize() == 8) { 268 if (B == &ARM::SPR_8RegClass) 269 return &ARM::DPR_8RegClass; 270 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); 271 if (A == &ARM::DPR_8RegClass) 272 return A; 273 return &ARM::DPR_VFP2RegClass; 274 } 275 276 if (A->getSize() == 16) { 277 if (B == &ARM::SPR_8RegClass) 278 return &ARM::QPR_8RegClass; 279 return &ARM::QPR_VFP2RegClass; 280 } 281 282 if (A->getSize() == 32) { 283 if (B == &ARM::SPR_8RegClass) 284 return 0; // Do not allow coalescing! 285 return &ARM::QQPR_VFP2RegClass; 286 } 287 288 assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 289 return 0; // Do not allow coalescing! 290 } 291 case ARM::dsub_0: 292 case ARM::dsub_1: 293 case ARM::dsub_2: 294 case ARM::dsub_3: { 295 // D sub-registers. 296 if (A->getSize() == 16) { 297 if (B == &ARM::DPR_VFP2RegClass) 298 return &ARM::QPR_VFP2RegClass; 299 if (B == &ARM::DPR_8RegClass) 300 return 0; // Do not allow coalescing! 301 return A; 302 } 303 304 if (A->getSize() == 32) { 305 if (B == &ARM::DPR_VFP2RegClass) 306 return &ARM::QQPR_VFP2RegClass; 307 if (B == &ARM::DPR_8RegClass) 308 return 0; // Do not allow coalescing! 309 return A; 310 } 311 312 assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 313 if (B != &ARM::DPRRegClass) 314 return 0; // Do not allow coalescing! 315 return A; 316 } 317 case ARM::dsub_4: 318 case ARM::dsub_5: 319 case ARM::dsub_6: 320 case ARM::dsub_7: { 321 // D sub-registers of QQQQ registers. 322 if (A->getSize() == 64 && B == &ARM::DPRRegClass) 323 return A; 324 return 0; // Do not allow coalescing! 325 } 326 327 case ARM::qsub_0: 328 case ARM::qsub_1: { 329 // Q sub-registers. 330 if (A->getSize() == 32) { 331 if (B == &ARM::QPR_VFP2RegClass) 332 return &ARM::QQPR_VFP2RegClass; 333 if (B == &ARM::QPR_8RegClass) 334 return 0; // Do not allow coalescing! 335 return A; 336 } 337 338 assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 339 if (B == &ARM::QPRRegClass) 340 return A; 341 return 0; // Do not allow coalescing! 342 } 343 case ARM::qsub_2: 344 case ARM::qsub_3: { 345 // Q sub-registers of QQQQ registers. 346 if (A->getSize() == 64 && B == &ARM::QPRRegClass) 347 return A; 348 return 0; // Do not allow coalescing! 349 } 350 } 351 return 0; 352} 353 354bool 355ARMBaseRegisterInfo::canCombinedSubRegIndex(const TargetRegisterClass *RC, 356 SmallVectorImpl<unsigned> &SubIndices, 357 unsigned &NewSubIdx) const { 358 359 unsigned Size = RC->getSize() * 8; 360 if (Size < 6) 361 return 0; 362 363 NewSubIdx = 0; // Whole register. 364 unsigned NumRegs = SubIndices.size(); 365 if (NumRegs == 8) { 366 // 8 D registers -> 1 QQQQ register. 367 return (Size == 512 && 368 SubIndices[0] == ARM::dsub_0 && 369 SubIndices[1] == ARM::dsub_1 && 370 SubIndices[2] == ARM::dsub_2 && 371 SubIndices[3] == ARM::dsub_3 && 372 SubIndices[4] == ARM::dsub_4 && 373 SubIndices[5] == ARM::dsub_5 && 374 SubIndices[6] == ARM::dsub_6 && 375 SubIndices[7] == ARM::dsub_7); 376 } else if (NumRegs == 4) { 377 if (SubIndices[0] == ARM::qsub_0) { 378 // 4 Q registers -> 1 QQQQ register. 379 return (Size == 512 && 380 SubIndices[1] == ARM::qsub_1 && 381 SubIndices[2] == ARM::qsub_2 && 382 SubIndices[3] == ARM::qsub_3); 383 } else if (SubIndices[0] == ARM::dsub_0) { 384 // 4 D registers -> 1 QQ register. 385 if (Size >= 256 && 386 SubIndices[1] == ARM::dsub_1 && 387 SubIndices[2] == ARM::dsub_2 && 388 SubIndices[3] == ARM::dsub_3) { 389 if (Size == 512) 390 NewSubIdx = ARM::qqsub_0; 391 return true; 392 } 393 } else if (SubIndices[0] == ARM::dsub_4) { 394 // 4 D registers -> 1 QQ register (2nd). 395 if (Size == 512 && 396 SubIndices[1] == ARM::dsub_5 && 397 SubIndices[2] == ARM::dsub_6 && 398 SubIndices[3] == ARM::dsub_7) { 399 NewSubIdx = ARM::qqsub_1; 400 return true; 401 } 402 } else if (SubIndices[0] == ARM::ssub_0) { 403 // 4 S registers -> 1 Q register. 404 if (Size >= 128 && 405 SubIndices[1] == ARM::ssub_1 && 406 SubIndices[2] == ARM::ssub_2 && 407 SubIndices[3] == ARM::ssub_3) { 408 if (Size >= 256) 409 NewSubIdx = ARM::qsub_0; 410 return true; 411 } 412 } 413 } else if (NumRegs == 2) { 414 if (SubIndices[0] == ARM::qsub_0) { 415 // 2 Q registers -> 1 QQ register. 416 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) { 417 if (Size == 512) 418 NewSubIdx = ARM::qqsub_0; 419 return true; 420 } 421 } else if (SubIndices[0] == ARM::qsub_2) { 422 // 2 Q registers -> 1 QQ register (2nd). 423 if (Size == 512 && SubIndices[1] == ARM::qsub_3) { 424 NewSubIdx = ARM::qqsub_1; 425 return true; 426 } 427 } else if (SubIndices[0] == ARM::dsub_0) { 428 // 2 D registers -> 1 Q register. 429 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) { 430 if (Size >= 256) 431 NewSubIdx = ARM::qsub_0; 432 return true; 433 } 434 } else if (SubIndices[0] == ARM::dsub_2) { 435 // 2 D registers -> 1 Q register (2nd). 436 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) { 437 NewSubIdx = ARM::qsub_1; 438 return true; 439 } 440 } else if (SubIndices[0] == ARM::dsub_4) { 441 // 2 D registers -> 1 Q register (3rd). 442 if (Size == 512 && SubIndices[1] == ARM::dsub_5) { 443 NewSubIdx = ARM::qsub_2; 444 return true; 445 } 446 } else if (SubIndices[0] == ARM::dsub_6) { 447 // 2 D registers -> 1 Q register (3rd). 448 if (Size == 512 && SubIndices[1] == ARM::dsub_7) { 449 NewSubIdx = ARM::qsub_3; 450 return true; 451 } 452 } else if (SubIndices[0] == ARM::ssub_0) { 453 // 2 S registers -> 1 D register. 454 if (SubIndices[1] == ARM::ssub_1) { 455 if (Size >= 128) 456 NewSubIdx = ARM::dsub_0; 457 return true; 458 } 459 } else if (SubIndices[0] == ARM::ssub_2) { 460 // 2 S registers -> 1 D register (2nd). 461 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) { 462 NewSubIdx = ARM::dsub_1; 463 return true; 464 } 465 } 466 } 467 return false; 468} 469 470 471const TargetRegisterClass * 472ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 473 return ARM::GPRRegisterClass; 474} 475 476/// getAllocationOrder - Returns the register allocation order for a specified 477/// register class in the form of a pair of TargetRegisterClass iterators. 478std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 479ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 480 unsigned HintType, unsigned HintReg, 481 const MachineFunction &MF) const { 482 // Alternative register allocation orders when favoring even / odd registers 483 // of register pairs. 484 485 // No FP, R9 is available. 486 static const unsigned GPREven1[] = { 487 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 488 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 489 ARM::R9, ARM::R11 490 }; 491 static const unsigned GPROdd1[] = { 492 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 493 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 494 ARM::R8, ARM::R10 495 }; 496 497 // FP is R7, R9 is available. 498 static const unsigned GPREven2[] = { 499 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 500 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 501 ARM::R9, ARM::R11 502 }; 503 static const unsigned GPROdd2[] = { 504 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 505 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 506 ARM::R8, ARM::R10 507 }; 508 509 // FP is R11, R9 is available. 510 static const unsigned GPREven3[] = { 511 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 512 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 513 ARM::R9 514 }; 515 static const unsigned GPROdd3[] = { 516 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 517 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 518 ARM::R8 519 }; 520 521 // No FP, R9 is not available. 522 static const unsigned GPREven4[] = { 523 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 524 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 525 ARM::R11 526 }; 527 static const unsigned GPROdd4[] = { 528 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 529 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 530 ARM::R10 531 }; 532 533 // FP is R7, R9 is not available. 534 static const unsigned GPREven5[] = { 535 ARM::R0, ARM::R2, ARM::R4, ARM::R10, 536 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 537 ARM::R11 538 }; 539 static const unsigned GPROdd5[] = { 540 ARM::R1, ARM::R3, ARM::R5, ARM::R11, 541 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 542 ARM::R10 543 }; 544 545 // FP is R11, R9 is not available. 546 static const unsigned GPREven6[] = { 547 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 548 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 549 }; 550 static const unsigned GPROdd6[] = { 551 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 552 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 553 }; 554 555 556 if (HintType == ARMRI::RegPairEven) { 557 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 558 // It's no longer possible to fulfill this hint. Return the default 559 // allocation order. 560 return std::make_pair(RC->allocation_order_begin(MF), 561 RC->allocation_order_end(MF)); 562 563 if (!STI.isTargetDarwin() && !hasFP(MF)) { 564 if (!STI.isR9Reserved()) 565 return std::make_pair(GPREven1, 566 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 567 else 568 return std::make_pair(GPREven4, 569 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 570 } else if (FramePtr == ARM::R7) { 571 if (!STI.isR9Reserved()) 572 return std::make_pair(GPREven2, 573 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 574 else 575 return std::make_pair(GPREven5, 576 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 577 } else { // FramePtr == ARM::R11 578 if (!STI.isR9Reserved()) 579 return std::make_pair(GPREven3, 580 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 581 else 582 return std::make_pair(GPREven6, 583 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 584 } 585 } else if (HintType == ARMRI::RegPairOdd) { 586 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 587 // It's no longer possible to fulfill this hint. Return the default 588 // allocation order. 589 return std::make_pair(RC->allocation_order_begin(MF), 590 RC->allocation_order_end(MF)); 591 592 if (!STI.isTargetDarwin() && !hasFP(MF)) { 593 if (!STI.isR9Reserved()) 594 return std::make_pair(GPROdd1, 595 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 596 else 597 return std::make_pair(GPROdd4, 598 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 599 } else if (FramePtr == ARM::R7) { 600 if (!STI.isR9Reserved()) 601 return std::make_pair(GPROdd2, 602 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 603 else 604 return std::make_pair(GPROdd5, 605 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 606 } else { // FramePtr == ARM::R11 607 if (!STI.isR9Reserved()) 608 return std::make_pair(GPROdd3, 609 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 610 else 611 return std::make_pair(GPROdd6, 612 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 613 } 614 } 615 return std::make_pair(RC->allocation_order_begin(MF), 616 RC->allocation_order_end(MF)); 617} 618 619/// ResolveRegAllocHint - Resolves the specified register allocation hint 620/// to a physical register. Returns the physical register if it is successful. 621unsigned 622ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 623 const MachineFunction &MF) const { 624 if (Reg == 0 || !isPhysicalRegister(Reg)) 625 return 0; 626 if (Type == 0) 627 return Reg; 628 else if (Type == (unsigned)ARMRI::RegPairOdd) 629 // Odd register. 630 return getRegisterPairOdd(Reg, MF); 631 else if (Type == (unsigned)ARMRI::RegPairEven) 632 // Even register. 633 return getRegisterPairEven(Reg, MF); 634 return 0; 635} 636 637void 638ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 639 MachineFunction &MF) const { 640 MachineRegisterInfo *MRI = &MF.getRegInfo(); 641 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 642 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 643 Hint.first == (unsigned)ARMRI::RegPairEven) && 644 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 645 // If 'Reg' is one of the even / odd register pair and it's now changed 646 // (e.g. coalesced) into a different register. The other register of the 647 // pair allocation hint must be updated to reflect the relationship 648 // change. 649 unsigned OtherReg = Hint.second; 650 Hint = MRI->getRegAllocationHint(OtherReg); 651 if (Hint.second == Reg) 652 // Make sure the pair has not already divorced. 653 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 654 } 655} 656 657/// hasFP - Return true if the specified function should have a dedicated frame 658/// pointer register. This is true if the function has variable sized allocas 659/// or if frame pointer elimination is disabled. 660/// 661bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 662 const MachineFrameInfo *MFI = MF.getFrameInfo(); 663 return ((DisableFramePointerElim(MF) && MFI->adjustsStack())|| 664 needsStackRealignment(MF) || 665 MFI->hasVarSizedObjects() || 666 MFI->isFrameAddressTaken()); 667} 668 669bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 670 const MachineFrameInfo *MFI = MF.getFrameInfo(); 671 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 672 return (RealignStack && 673 !AFI->isThumb1OnlyFunction() && 674 !MFI->hasVarSizedObjects()); 675} 676 677bool ARMBaseRegisterInfo:: 678needsStackRealignment(const MachineFunction &MF) const { 679 const MachineFrameInfo *MFI = MF.getFrameInfo(); 680 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 681 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 682 return (RealignStack && 683 !AFI->isThumb1OnlyFunction() && 684 (MFI->getMaxAlignment() > StackAlign) && 685 !MFI->hasVarSizedObjects()); 686} 687 688bool ARMBaseRegisterInfo:: 689cannotEliminateFrame(const MachineFunction &MF) const { 690 const MachineFrameInfo *MFI = MF.getFrameInfo(); 691 if (DisableFramePointerElim(MF) && MFI->adjustsStack()) 692 return true; 693 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 694 || needsStackRealignment(MF); 695} 696 697/// estimateStackSize - Estimate and return the size of the frame. 698static unsigned estimateStackSize(MachineFunction &MF) { 699 const MachineFrameInfo *FFI = MF.getFrameInfo(); 700 int Offset = 0; 701 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 702 int FixedOff = -FFI->getObjectOffset(i); 703 if (FixedOff > Offset) Offset = FixedOff; 704 } 705 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 706 if (FFI->isDeadObjectIndex(i)) 707 continue; 708 Offset += FFI->getObjectSize(i); 709 unsigned Align = FFI->getObjectAlignment(i); 710 // Adjust to alignment boundary 711 Offset = (Offset+Align-1)/Align*Align; 712 } 713 return (unsigned)Offset; 714} 715 716/// estimateRSStackSizeLimit - Look at each instruction that references stack 717/// frames and return the stack size limit beyond which some of these 718/// instructions will require a scratch register during their expansion later. 719unsigned 720ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 721 unsigned Limit = (1 << 12) - 1; 722 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 723 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 724 I != E; ++I) { 725 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 726 if (!I->getOperand(i).isFI()) continue; 727 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { 728 case ARMII::AddrMode3: 729 case ARMII::AddrModeT2_i8: 730 Limit = std::min(Limit, (1U << 8) - 1); 731 break; 732 case ARMII::AddrMode5: 733 case ARMII::AddrModeT2_i8s4: 734 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 735 break; 736 case ARMII::AddrModeT2_i12: 737 if (hasFP(MF)) Limit = std::min(Limit, (1U << 8) - 1); 738 break; 739 case ARMII::AddrMode6: 740 // Addressing mode 6 (load/store) instructions can't encode an 741 // immediate offset for stack references. 742 return 0; 743 default: 744 break; 745 } 746 break; // At most one FI per instruction 747 } 748 } 749 } 750 751 return Limit; 752} 753 754void 755ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 756 RegScavenger *RS) const { 757 // This tells PEI to spill the FP as if it is any other callee-save register 758 // to take advantage the eliminateFrameIndex machinery. This also ensures it 759 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 760 // to combine multiple loads / stores. 761 bool CanEliminateFrame = true; 762 bool CS1Spilled = false; 763 bool LRSpilled = false; 764 unsigned NumGPRSpills = 0; 765 SmallVector<unsigned, 4> UnspilledCS1GPRs; 766 SmallVector<unsigned, 4> UnspilledCS2GPRs; 767 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 768 769 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 770 // scratch register. 771 // FIXME: It will be better just to find spare register here. 772 if (needsStackRealignment(MF) && 773 AFI->isThumb2Function()) 774 MF.getRegInfo().setPhysRegUsed(ARM::R4); 775 776 // Spill LR if Thumb1 function uses variable length argument lists. 777 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0) 778 MF.getRegInfo().setPhysRegUsed(ARM::LR); 779 780 // Don't spill FP if the frame can be eliminated. This is determined 781 // by scanning the callee-save registers to see if any is used. 782 const unsigned *CSRegs = getCalleeSavedRegs(); 783 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 784 for (unsigned i = 0; CSRegs[i]; ++i) { 785 unsigned Reg = CSRegs[i]; 786 bool Spilled = false; 787 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 788 AFI->setCSRegisterIsSpilled(Reg); 789 Spilled = true; 790 CanEliminateFrame = false; 791 } else { 792 // Check alias registers too. 793 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 794 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 795 Spilled = true; 796 CanEliminateFrame = false; 797 } 798 } 799 } 800 801 if (CSRegClasses[i] == ARM::GPRRegisterClass || 802 CSRegClasses[i] == ARM::tGPRRegisterClass) { 803 if (Spilled) { 804 NumGPRSpills++; 805 806 if (!STI.isTargetDarwin()) { 807 if (Reg == ARM::LR) 808 LRSpilled = true; 809 CS1Spilled = true; 810 continue; 811 } 812 813 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 814 switch (Reg) { 815 case ARM::LR: 816 LRSpilled = true; 817 // Fallthrough 818 case ARM::R4: 819 case ARM::R5: 820 case ARM::R6: 821 case ARM::R7: 822 CS1Spilled = true; 823 break; 824 default: 825 break; 826 } 827 } else { 828 if (!STI.isTargetDarwin()) { 829 UnspilledCS1GPRs.push_back(Reg); 830 continue; 831 } 832 833 switch (Reg) { 834 case ARM::R4: 835 case ARM::R5: 836 case ARM::R6: 837 case ARM::R7: 838 case ARM::LR: 839 UnspilledCS1GPRs.push_back(Reg); 840 break; 841 default: 842 UnspilledCS2GPRs.push_back(Reg); 843 break; 844 } 845 } 846 } 847 } 848 849 bool ForceLRSpill = false; 850 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 851 unsigned FnSize = TII.GetFunctionSizeInBytes(MF); 852 // Force LR to be spilled if the Thumb function size is > 2048. This enables 853 // use of BL to implement far jump. If it turns out that it's not needed 854 // then the branch fix up path will undo it. 855 if (FnSize >= (1 << 11)) { 856 CanEliminateFrame = false; 857 ForceLRSpill = true; 858 } 859 } 860 861 // If any of the stack slot references may be out of range of an immediate 862 // offset, make sure a register (or a spill slot) is available for the 863 // register scavenger. Note that if we're indexing off the frame pointer, the 864 // effective stack size is 4 bytes larger since the FP points to the stack 865 // slot of the previous FP. 866 bool BigStack = RS && 867 estimateStackSize(MF) + (hasFP(MF) ? 4 : 0) >= estimateRSStackSizeLimit(MF); 868 869 bool ExtraCSSpill = false; 870 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) { 871 AFI->setHasStackFrame(true); 872 873 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 874 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 875 if (!LRSpilled && CS1Spilled) { 876 MF.getRegInfo().setPhysRegUsed(ARM::LR); 877 AFI->setCSRegisterIsSpilled(ARM::LR); 878 NumGPRSpills++; 879 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 880 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 881 ForceLRSpill = false; 882 ExtraCSSpill = true; 883 } 884 885 // Darwin ABI requires FP to point to the stack slot that contains the 886 // previous FP. 887 if (STI.isTargetDarwin() || hasFP(MF)) { 888 MF.getRegInfo().setPhysRegUsed(FramePtr); 889 NumGPRSpills++; 890 } 891 892 // If stack and double are 8-byte aligned and we are spilling an odd number 893 // of GPRs. Spill one extra callee save GPR so we won't have to pad between 894 // the integer and double callee save areas. 895 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 896 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 897 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 898 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 899 unsigned Reg = UnspilledCS1GPRs[i]; 900 // Don't spill high register if the function is thumb1 901 if (!AFI->isThumb1OnlyFunction() || 902 isARMLowRegister(Reg) || Reg == ARM::LR) { 903 MF.getRegInfo().setPhysRegUsed(Reg); 904 AFI->setCSRegisterIsSpilled(Reg); 905 if (!isReservedReg(MF, Reg)) 906 ExtraCSSpill = true; 907 break; 908 } 909 } 910 } else if (!UnspilledCS2GPRs.empty() && 911 !AFI->isThumb1OnlyFunction()) { 912 unsigned Reg = UnspilledCS2GPRs.front(); 913 MF.getRegInfo().setPhysRegUsed(Reg); 914 AFI->setCSRegisterIsSpilled(Reg); 915 if (!isReservedReg(MF, Reg)) 916 ExtraCSSpill = true; 917 } 918 } 919 920 // Estimate if we might need to scavenge a register at some point in order 921 // to materialize a stack offset. If so, either spill one additional 922 // callee-saved register or reserve a special spill slot to facilitate 923 // register scavenging. Thumb1 needs a spill slot for stack pointer 924 // adjustments also, even when the frame itself is small. 925 if (BigStack && !ExtraCSSpill) { 926 // If any non-reserved CS register isn't spilled, just spill one or two 927 // extra. That should take care of it! 928 unsigned NumExtras = TargetAlign / 4; 929 SmallVector<unsigned, 2> Extras; 930 while (NumExtras && !UnspilledCS1GPRs.empty()) { 931 unsigned Reg = UnspilledCS1GPRs.back(); 932 UnspilledCS1GPRs.pop_back(); 933 if (!isReservedReg(MF, Reg) && 934 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 935 Reg == ARM::LR)) { 936 Extras.push_back(Reg); 937 NumExtras--; 938 } 939 } 940 // For non-Thumb1 functions, also check for hi-reg CS registers 941 if (!AFI->isThumb1OnlyFunction()) { 942 while (NumExtras && !UnspilledCS2GPRs.empty()) { 943 unsigned Reg = UnspilledCS2GPRs.back(); 944 UnspilledCS2GPRs.pop_back(); 945 if (!isReservedReg(MF, Reg)) { 946 Extras.push_back(Reg); 947 NumExtras--; 948 } 949 } 950 } 951 if (Extras.size() && NumExtras == 0) { 952 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 953 MF.getRegInfo().setPhysRegUsed(Extras[i]); 954 AFI->setCSRegisterIsSpilled(Extras[i]); 955 } 956 } else if (!AFI->isThumb1OnlyFunction()) { 957 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 958 // closest to SP or frame pointer. 959 const TargetRegisterClass *RC = ARM::GPRRegisterClass; 960 MachineFrameInfo *MFI = MF.getFrameInfo(); 961 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 962 RC->getAlignment(), 963 false)); 964 } 965 } 966 } 967 968 if (ForceLRSpill) { 969 MF.getRegInfo().setPhysRegUsed(ARM::LR); 970 AFI->setCSRegisterIsSpilled(ARM::LR); 971 AFI->setLRIsSpilledForFarJump(true); 972 } 973} 974 975unsigned ARMBaseRegisterInfo::getRARegister() const { 976 return ARM::LR; 977} 978 979unsigned 980ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 981 if (STI.isTargetDarwin() || hasFP(MF)) 982 return FramePtr; 983 return ARM::SP; 984} 985 986int 987ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI, 988 unsigned &FrameReg) const { 989 const MachineFrameInfo *MFI = MF.getFrameInfo(); 990 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 991 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 992 bool isFixed = MFI->isFixedObjectIndex(FI); 993 994 FrameReg = ARM::SP; 995 if (AFI->isGPRCalleeSavedArea1Frame(FI)) 996 Offset -= AFI->getGPRCalleeSavedArea1Offset(); 997 else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 998 Offset -= AFI->getGPRCalleeSavedArea2Offset(); 999 else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 1000 Offset -= AFI->getDPRCalleeSavedAreaOffset(); 1001 else if (needsStackRealignment(MF)) { 1002 // When dynamically realigning the stack, use the frame pointer for 1003 // parameters, and the stack pointer for locals. 1004 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 1005 if (isFixed) { 1006 FrameReg = getFrameRegister(MF); 1007 Offset -= AFI->getFramePtrSpillOffset(); 1008 } 1009 } else if (hasFP(MF) && AFI->hasStackFrame()) { 1010 if (isFixed || MFI->hasVarSizedObjects()) { 1011 // Use frame pointer to reference fixed objects unless this is a 1012 // frameless function. 1013 FrameReg = getFrameRegister(MF); 1014 Offset -= AFI->getFramePtrSpillOffset(); 1015 } else if (AFI->isThumb2Function()) { 1016 // In Thumb2 mode, the negative offset is very limited. 1017 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 1018 if (FPOffset >= -255 && FPOffset < 0) { 1019 FrameReg = getFrameRegister(MF); 1020 Offset = FPOffset; 1021 } 1022 } 1023 } 1024 return Offset; 1025} 1026 1027 1028int 1029ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF, 1030 int FI) const { 1031 unsigned FrameReg; 1032 return getFrameIndexReference(MF, FI, FrameReg); 1033} 1034 1035unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 1036 llvm_unreachable("What is the exception register"); 1037 return 0; 1038} 1039 1040unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 1041 llvm_unreachable("What is the exception handler register"); 1042 return 0; 1043} 1044 1045int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1046 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1047} 1048 1049unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 1050 const MachineFunction &MF) const { 1051 switch (Reg) { 1052 default: break; 1053 // Return 0 if either register of the pair is a special register. 1054 // So no R12, etc. 1055 case ARM::R1: 1056 return ARM::R0; 1057 case ARM::R3: 1058 return ARM::R2; 1059 case ARM::R5: 1060 return ARM::R4; 1061 case ARM::R7: 1062 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 1063 case ARM::R9: 1064 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 1065 case ARM::R11: 1066 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 1067 1068 case ARM::S1: 1069 return ARM::S0; 1070 case ARM::S3: 1071 return ARM::S2; 1072 case ARM::S5: 1073 return ARM::S4; 1074 case ARM::S7: 1075 return ARM::S6; 1076 case ARM::S9: 1077 return ARM::S8; 1078 case ARM::S11: 1079 return ARM::S10; 1080 case ARM::S13: 1081 return ARM::S12; 1082 case ARM::S15: 1083 return ARM::S14; 1084 case ARM::S17: 1085 return ARM::S16; 1086 case ARM::S19: 1087 return ARM::S18; 1088 case ARM::S21: 1089 return ARM::S20; 1090 case ARM::S23: 1091 return ARM::S22; 1092 case ARM::S25: 1093 return ARM::S24; 1094 case ARM::S27: 1095 return ARM::S26; 1096 case ARM::S29: 1097 return ARM::S28; 1098 case ARM::S31: 1099 return ARM::S30; 1100 1101 case ARM::D1: 1102 return ARM::D0; 1103 case ARM::D3: 1104 return ARM::D2; 1105 case ARM::D5: 1106 return ARM::D4; 1107 case ARM::D7: 1108 return ARM::D6; 1109 case ARM::D9: 1110 return ARM::D8; 1111 case ARM::D11: 1112 return ARM::D10; 1113 case ARM::D13: 1114 return ARM::D12; 1115 case ARM::D15: 1116 return ARM::D14; 1117 case ARM::D17: 1118 return ARM::D16; 1119 case ARM::D19: 1120 return ARM::D18; 1121 case ARM::D21: 1122 return ARM::D20; 1123 case ARM::D23: 1124 return ARM::D22; 1125 case ARM::D25: 1126 return ARM::D24; 1127 case ARM::D27: 1128 return ARM::D26; 1129 case ARM::D29: 1130 return ARM::D28; 1131 case ARM::D31: 1132 return ARM::D30; 1133 } 1134 1135 return 0; 1136} 1137 1138unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 1139 const MachineFunction &MF) const { 1140 switch (Reg) { 1141 default: break; 1142 // Return 0 if either register of the pair is a special register. 1143 // So no R12, etc. 1144 case ARM::R0: 1145 return ARM::R1; 1146 case ARM::R2: 1147 return ARM::R3; 1148 case ARM::R4: 1149 return ARM::R5; 1150 case ARM::R6: 1151 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 1152 case ARM::R8: 1153 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 1154 case ARM::R10: 1155 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 1156 1157 case ARM::S0: 1158 return ARM::S1; 1159 case ARM::S2: 1160 return ARM::S3; 1161 case ARM::S4: 1162 return ARM::S5; 1163 case ARM::S6: 1164 return ARM::S7; 1165 case ARM::S8: 1166 return ARM::S9; 1167 case ARM::S10: 1168 return ARM::S11; 1169 case ARM::S12: 1170 return ARM::S13; 1171 case ARM::S14: 1172 return ARM::S15; 1173 case ARM::S16: 1174 return ARM::S17; 1175 case ARM::S18: 1176 return ARM::S19; 1177 case ARM::S20: 1178 return ARM::S21; 1179 case ARM::S22: 1180 return ARM::S23; 1181 case ARM::S24: 1182 return ARM::S25; 1183 case ARM::S26: 1184 return ARM::S27; 1185 case ARM::S28: 1186 return ARM::S29; 1187 case ARM::S30: 1188 return ARM::S31; 1189 1190 case ARM::D0: 1191 return ARM::D1; 1192 case ARM::D2: 1193 return ARM::D3; 1194 case ARM::D4: 1195 return ARM::D5; 1196 case ARM::D6: 1197 return ARM::D7; 1198 case ARM::D8: 1199 return ARM::D9; 1200 case ARM::D10: 1201 return ARM::D11; 1202 case ARM::D12: 1203 return ARM::D13; 1204 case ARM::D14: 1205 return ARM::D15; 1206 case ARM::D16: 1207 return ARM::D17; 1208 case ARM::D18: 1209 return ARM::D19; 1210 case ARM::D20: 1211 return ARM::D21; 1212 case ARM::D22: 1213 return ARM::D23; 1214 case ARM::D24: 1215 return ARM::D25; 1216 case ARM::D26: 1217 return ARM::D27; 1218 case ARM::D28: 1219 return ARM::D29; 1220 case ARM::D30: 1221 return ARM::D31; 1222 } 1223 1224 return 0; 1225} 1226 1227/// emitLoadConstPool - Emits a load from constpool to materialize the 1228/// specified immediate. 1229void ARMBaseRegisterInfo:: 1230emitLoadConstPool(MachineBasicBlock &MBB, 1231 MachineBasicBlock::iterator &MBBI, 1232 DebugLoc dl, 1233 unsigned DestReg, unsigned SubIdx, int Val, 1234 ARMCC::CondCodes Pred, 1235 unsigned PredReg) const { 1236 MachineFunction &MF = *MBB.getParent(); 1237 MachineConstantPool *ConstantPool = MF.getConstantPool(); 1238 const Constant *C = 1239 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 1240 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 1241 1242 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 1243 .addReg(DestReg, getDefRegState(true), SubIdx) 1244 .addConstantPoolIndex(Idx) 1245 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 1246} 1247 1248bool ARMBaseRegisterInfo:: 1249requiresRegisterScavenging(const MachineFunction &MF) const { 1250 return true; 1251} 1252 1253bool ARMBaseRegisterInfo:: 1254requiresFrameIndexScavenging(const MachineFunction &MF) const { 1255 return true; 1256} 1257 1258// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 1259// not required, we reserve argument space for call sites in the function 1260// immediately on entry to the current function. This eliminates the need for 1261// add/sub sp brackets around call sites. Returns true if the call frame is 1262// included as part of the stack frame. 1263bool ARMBaseRegisterInfo:: 1264hasReservedCallFrame(MachineFunction &MF) const { 1265 const MachineFrameInfo *FFI = MF.getFrameInfo(); 1266 unsigned CFSize = FFI->getMaxCallFrameSize(); 1267 // It's not always a good idea to include the call frame as part of the 1268 // stack frame. ARM (especially Thumb) has small immediate offset to 1269 // address the stack frame. So a large call frame can cause poor codegen 1270 // and may even makes it impossible to scavenge a register. 1271 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 1272 return false; 1273 1274 return !MF.getFrameInfo()->hasVarSizedObjects(); 1275} 1276 1277// canSimplifyCallFramePseudos - If there is a reserved call frame, the 1278// call frame pseudos can be simplified. Unlike most targets, having a FP 1279// is not sufficient here since we still may reference some objects via SP 1280// even when FP is available in Thumb2 mode. 1281bool ARMBaseRegisterInfo:: 1282canSimplifyCallFramePseudos(MachineFunction &MF) const { 1283 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 1284} 1285 1286static void 1287emitSPUpdate(bool isARM, 1288 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 1289 DebugLoc dl, const ARMBaseInstrInfo &TII, 1290 int NumBytes, 1291 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 1292 if (isARM) 1293 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1294 Pred, PredReg, TII); 1295 else 1296 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1297 Pred, PredReg, TII); 1298} 1299 1300 1301void ARMBaseRegisterInfo:: 1302eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1303 MachineBasicBlock::iterator I) const { 1304 if (!hasReservedCallFrame(MF)) { 1305 // If we have alloca, convert as follows: 1306 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1307 // ADJCALLSTACKUP -> add, sp, sp, amount 1308 MachineInstr *Old = I; 1309 DebugLoc dl = Old->getDebugLoc(); 1310 unsigned Amount = Old->getOperand(0).getImm(); 1311 if (Amount != 0) { 1312 // We need to keep the stack aligned properly. To do this, we round the 1313 // amount of space needed for the outgoing arguments up to the next 1314 // alignment boundary. 1315 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1316 Amount = (Amount+Align-1)/Align*Align; 1317 1318 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1319 assert(!AFI->isThumb1OnlyFunction() && 1320 "This eliminateCallFramePseudoInstr does not support Thumb1!"); 1321 bool isARM = !AFI->isThumbFunction(); 1322 1323 // Replace the pseudo instruction with a new instruction... 1324 unsigned Opc = Old->getOpcode(); 1325 int PIdx = Old->findFirstPredOperandIdx(); 1326 ARMCC::CondCodes Pred = (PIdx == -1) 1327 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 1328 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1329 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1330 unsigned PredReg = Old->getOperand(2).getReg(); 1331 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 1332 } else { 1333 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1334 unsigned PredReg = Old->getOperand(3).getReg(); 1335 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 1336 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 1337 } 1338 } 1339 } 1340 MBB.erase(I); 1341} 1342 1343unsigned 1344ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1345 int SPAdj, FrameIndexValue *Value, 1346 RegScavenger *RS) const { 1347 unsigned i = 0; 1348 MachineInstr &MI = *II; 1349 MachineBasicBlock &MBB = *MI.getParent(); 1350 MachineFunction &MF = *MBB.getParent(); 1351 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1352 assert(!AFI->isThumb1OnlyFunction() && 1353 "This eliminateFrameIndex does not support Thumb1!"); 1354 1355 while (!MI.getOperand(i).isFI()) { 1356 ++i; 1357 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1358 } 1359 1360 int FrameIndex = MI.getOperand(i).getIndex(); 1361 unsigned FrameReg; 1362 1363 int Offset = getFrameIndexReference(MF, FrameIndex, FrameReg); 1364 if (FrameReg != ARM::SP) 1365 SPAdj = 0; 1366 Offset += SPAdj; 1367 1368 // Special handling of dbg_value instructions. 1369 if (MI.isDebugValue()) { 1370 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); 1371 MI.getOperand(i+1).ChangeToImmediate(Offset); 1372 return 0; 1373 } 1374 1375 // Modify MI as necessary to handle as much of 'Offset' as possible 1376 bool Done = false; 1377 if (!AFI->isThumbFunction()) 1378 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 1379 else { 1380 assert(AFI->isThumb2Function()); 1381 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 1382 } 1383 if (Done) 1384 return 0; 1385 1386 // If we get here, the immediate doesn't fit into the instruction. We folded 1387 // as much as possible above, handle the rest, providing a register that is 1388 // SP+LargeImm. 1389 assert((Offset || 1390 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 1391 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 1392 "This code isn't needed if offset already handled!"); 1393 1394 unsigned ScratchReg = 0; 1395 int PIdx = MI.findFirstPredOperandIdx(); 1396 ARMCC::CondCodes Pred = (PIdx == -1) 1397 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1398 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1399 if (Offset == 0) 1400 // Must be addrmode4/6. 1401 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 1402 else { 1403 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); 1404 if (Value) { 1405 Value->first = FrameReg; // use the frame register as a kind indicator 1406 Value->second = Offset; 1407 } 1408 if (!AFI->isThumbFunction()) 1409 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1410 Offset, Pred, PredReg, TII); 1411 else { 1412 assert(AFI->isThumb2Function()); 1413 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1414 Offset, Pred, PredReg, TII); 1415 } 1416 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1417 if (!ReuseFrameIndexVals) 1418 ScratchReg = 0; 1419 } 1420 return ScratchReg; 1421} 1422 1423/// Move iterator past the next bunch of callee save load / store ops for 1424/// the particular spill area (1: integer area 1, 2: integer area 2, 1425/// 3: fp area, 0: don't care). 1426static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1427 MachineBasicBlock::iterator &MBBI, 1428 int Opc1, int Opc2, unsigned Area, 1429 const ARMSubtarget &STI) { 1430 while (MBBI != MBB.end() && 1431 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 1432 MBBI->getOperand(1).isFI()) { 1433 if (Area != 0) { 1434 bool Done = false; 1435 unsigned Category = 0; 1436 switch (MBBI->getOperand(0).getReg()) { 1437 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1438 case ARM::LR: 1439 Category = 1; 1440 break; 1441 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1442 Category = STI.isTargetDarwin() ? 2 : 1; 1443 break; 1444 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1445 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1446 Category = 3; 1447 break; 1448 default: 1449 Done = true; 1450 break; 1451 } 1452 if (Done || Category != Area) 1453 break; 1454 } 1455 1456 ++MBBI; 1457 } 1458} 1459 1460void ARMBaseRegisterInfo:: 1461emitPrologue(MachineFunction &MF) const { 1462 MachineBasicBlock &MBB = MF.front(); 1463 MachineBasicBlock::iterator MBBI = MBB.begin(); 1464 MachineFrameInfo *MFI = MF.getFrameInfo(); 1465 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1466 assert(!AFI->isThumb1OnlyFunction() && 1467 "This emitPrologue does not support Thumb1!"); 1468 bool isARM = !AFI->isThumbFunction(); 1469 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1470 unsigned NumBytes = MFI->getStackSize(); 1471 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1472 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 1473 1474 // Determine the sizes of each callee-save spill areas and record which frame 1475 // belongs to which callee-save spill areas. 1476 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1477 int FramePtrSpillFI = 0; 1478 1479 // Allocate the vararg register save area. This is not counted in NumBytes. 1480 if (VARegSaveSize) 1481 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1482 1483 if (!AFI->hasStackFrame()) { 1484 if (NumBytes != 0) 1485 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1486 return; 1487 } 1488 1489 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1490 unsigned Reg = CSI[i].getReg(); 1491 int FI = CSI[i].getFrameIdx(); 1492 switch (Reg) { 1493 case ARM::R4: 1494 case ARM::R5: 1495 case ARM::R6: 1496 case ARM::R7: 1497 case ARM::LR: 1498 if (Reg == FramePtr) 1499 FramePtrSpillFI = FI; 1500 AFI->addGPRCalleeSavedArea1Frame(FI); 1501 GPRCS1Size += 4; 1502 break; 1503 case ARM::R8: 1504 case ARM::R9: 1505 case ARM::R10: 1506 case ARM::R11: 1507 if (Reg == FramePtr) 1508 FramePtrSpillFI = FI; 1509 if (STI.isTargetDarwin()) { 1510 AFI->addGPRCalleeSavedArea2Frame(FI); 1511 GPRCS2Size += 4; 1512 } else { 1513 AFI->addGPRCalleeSavedArea1Frame(FI); 1514 GPRCS1Size += 4; 1515 } 1516 break; 1517 default: 1518 AFI->addDPRCalleeSavedAreaFrame(FI); 1519 DPRCSSize += 8; 1520 } 1521 } 1522 1523 // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1524 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 1525 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1526 1527 // Set FP to point to the stack slot that contains the previous FP. 1528 // For Darwin, FP is R7, which has now been stored in spill area 1. 1529 // Otherwise, if this is not Darwin, all the callee-saved registers go 1530 // into spill area 1, including the FP in R11. In either case, it is 1531 // now safe to emit this assignment. 1532 if (STI.isTargetDarwin() || hasFP(MF)) { 1533 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1534 MachineInstrBuilder MIB = 1535 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1536 .addFrameIndex(FramePtrSpillFI).addImm(0); 1537 AddDefaultCC(AddDefaultPred(MIB)); 1538 } 1539 1540 // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1541 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1542 1543 // Build the new SUBri to adjust SP for FP callee-save spill area. 1544 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 1545 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1546 1547 // Determine starting offsets of spill areas. 1548 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1549 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1550 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1551 if (STI.isTargetDarwin() || hasFP(MF)) 1552 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 1553 NumBytes); 1554 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1555 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1556 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1557 1558 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); 1559 NumBytes = DPRCSOffset; 1560 if (NumBytes) { 1561 // Adjust SP after all the callee-save spills. 1562 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1563 } 1564 1565 if (STI.isTargetELF() && hasFP(MF)) { 1566 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1567 AFI->getFramePtrSpillOffset()); 1568 } 1569 1570 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1571 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1572 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1573 1574 // If we need dynamic stack realignment, do it here. 1575 if (needsStackRealignment(MF)) { 1576 unsigned MaxAlign = MFI->getMaxAlignment(); 1577 assert (!AFI->isThumb1OnlyFunction()); 1578 if (!AFI->isThumbFunction()) { 1579 // Emit bic sp, sp, MaxAlign 1580 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 1581 TII.get(ARM::BICri), ARM::SP) 1582 .addReg(ARM::SP, RegState::Kill) 1583 .addImm(MaxAlign-1))); 1584 } else { 1585 // We cannot use sp as source/dest register here, thus we're emitting the 1586 // following sequence: 1587 // mov r4, sp 1588 // bic r4, r4, MaxAlign 1589 // mov sp, r4 1590 // FIXME: It will be better just to find spare register here. 1591 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4) 1592 .addReg(ARM::SP, RegState::Kill); 1593 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 1594 TII.get(ARM::t2BICri), ARM::R4) 1595 .addReg(ARM::R4, RegState::Kill) 1596 .addImm(MaxAlign-1))); 1597 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) 1598 .addReg(ARM::R4, RegState::Kill); 1599 } 1600 } 1601} 1602 1603static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1604 for (unsigned i = 0; CSRegs[i]; ++i) 1605 if (Reg == CSRegs[i]) 1606 return true; 1607 return false; 1608} 1609 1610static bool isCSRestore(MachineInstr *MI, 1611 const ARMBaseInstrInfo &TII, 1612 const unsigned *CSRegs) { 1613 return ((MI->getOpcode() == (int)ARM::VLDRD || 1614 MI->getOpcode() == (int)ARM::LDR || 1615 MI->getOpcode() == (int)ARM::t2LDRi12) && 1616 MI->getOperand(1).isFI() && 1617 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1618} 1619 1620void ARMBaseRegisterInfo:: 1621emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1622 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1623 assert(MBBI->getDesc().isReturn() && 1624 "Can only insert epilog into returning blocks"); 1625 DebugLoc dl = MBBI->getDebugLoc(); 1626 MachineFrameInfo *MFI = MF.getFrameInfo(); 1627 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1628 assert(!AFI->isThumb1OnlyFunction() && 1629 "This emitEpilogue does not support Thumb1!"); 1630 bool isARM = !AFI->isThumbFunction(); 1631 1632 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1633 int NumBytes = (int)MFI->getStackSize(); 1634 1635 if (!AFI->hasStackFrame()) { 1636 if (NumBytes != 0) 1637 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1638 } else { 1639 // Unwind MBBI to point to first LDR / VLDRD. 1640 const unsigned *CSRegs = getCalleeSavedRegs(); 1641 if (MBBI != MBB.begin()) { 1642 do 1643 --MBBI; 1644 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 1645 if (!isCSRestore(MBBI, TII, CSRegs)) 1646 ++MBBI; 1647 } 1648 1649 // Move SP to start of FP callee save spill area. 1650 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1651 AFI->getGPRCalleeSavedArea2Size() + 1652 AFI->getDPRCalleeSavedAreaSize()); 1653 1654 // Darwin ABI requires FP to point to the stack slot that contains the 1655 // previous FP. 1656 bool HasFP = hasFP(MF); 1657 if ((STI.isTargetDarwin() && NumBytes) || HasFP) { 1658 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1659 // Reset SP based on frame pointer only if the stack frame extends beyond 1660 // frame pointer stack slot or target is ELF and the function has FP. 1661 if (HasFP || 1662 AFI->getGPRCalleeSavedArea2Size() || 1663 AFI->getDPRCalleeSavedAreaSize() || 1664 AFI->getDPRCalleeSavedAreaOffset()) { 1665 if (NumBytes) { 1666 if (isARM) 1667 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1668 ARMCC::AL, 0, TII); 1669 else 1670 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1671 ARMCC::AL, 0, TII); 1672 } else { 1673 // Thumb2 or ARM. 1674 if (isARM) 1675 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1676 .addReg(FramePtr) 1677 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1678 else 1679 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1680 .addReg(FramePtr); 1681 } 1682 } 1683 } else if (NumBytes) 1684 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1685 1686 // Move SP to start of integer callee save spill area 2. 1687 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); 1688 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1689 1690 // Move SP to start of integer callee save spill area 1. 1691 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 1692 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1693 1694 // Move SP to SP upon entry to the function. 1695 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 1696 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1697 } 1698 1699 if (VARegSaveSize) 1700 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 1701} 1702 1703#include "ARMGenRegisterInfo.inc" 1704