ARMBaseRegisterInfo.cpp revision 207618 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42namespace llvm {
43cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46}
47
48using namespace llvm;
49
50unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
51                                                   bool *isSPVFP) {
52  if (isSPVFP)
53    *isSPVFP = false;
54
55  using namespace ARM;
56  switch (RegEnum) {
57  default:
58    llvm_unreachable("Unknown ARM register!");
59  case R0:  case D0:  case Q0:  return 0;
60  case R1:  case D1:  case Q1:  return 1;
61  case R2:  case D2:  case Q2:  return 2;
62  case R3:  case D3:  case Q3:  return 3;
63  case R4:  case D4:  case Q4:  return 4;
64  case R5:  case D5:  case Q5:  return 5;
65  case R6:  case D6:  case Q6:  return 6;
66  case R7:  case D7:  case Q7:  return 7;
67  case R8:  case D8:  case Q8:  return 8;
68  case R9:  case D9:  case Q9:  return 9;
69  case R10: case D10: case Q10: return 10;
70  case R11: case D11: case Q11: return 11;
71  case R12: case D12: case Q12: return 12;
72  case SP:  case D13: case Q13: return 13;
73  case LR:  case D14: case Q14: return 14;
74  case PC:  case D15: case Q15: return 15;
75
76  case D16: return 16;
77  case D17: return 17;
78  case D18: return 18;
79  case D19: return 19;
80  case D20: return 20;
81  case D21: return 21;
82  case D22: return 22;
83  case D23: return 23;
84  case D24: return 24;
85  case D25: return 25;
86  case D26: return 26;
87  case D27: return 27;
88  case D28: return 28;
89  case D29: return 29;
90  case D30: return 30;
91  case D31: return 31;
92
93  case S0: case S1: case S2: case S3:
94  case S4: case S5: case S6: case S7:
95  case S8: case S9: case S10: case S11:
96  case S12: case S13: case S14: case S15:
97  case S16: case S17: case S18: case S19:
98  case S20: case S21: case S22: case S23:
99  case S24: case S25: case S26: case S27:
100  case S28: case S29: case S30: case S31: {
101    if (isSPVFP)
102      *isSPVFP = true;
103    switch (RegEnum) {
104    default: return 0; // Avoid compile time warning.
105    case S0: return 0;
106    case S1: return 1;
107    case S2: return 2;
108    case S3: return 3;
109    case S4: return 4;
110    case S5: return 5;
111    case S6: return 6;
112    case S7: return 7;
113    case S8: return 8;
114    case S9: return 9;
115    case S10: return 10;
116    case S11: return 11;
117    case S12: return 12;
118    case S13: return 13;
119    case S14: return 14;
120    case S15: return 15;
121    case S16: return 16;
122    case S17: return 17;
123    case S18: return 18;
124    case S19: return 19;
125    case S20: return 20;
126    case S21: return 21;
127    case S22: return 22;
128    case S23: return 23;
129    case S24: return 24;
130    case S25: return 25;
131    case S26: return 26;
132    case S27: return 27;
133    case S28: return 28;
134    case S29: return 29;
135    case S30: return 30;
136    case S31: return 31;
137    }
138  }
139  }
140}
141
142ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
143                                         const ARMSubtarget &sti)
144  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
145    TII(tii), STI(sti),
146    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
147}
148
149const unsigned*
150ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151  static const unsigned CalleeSavedRegs[] = {
152    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
153    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
154
155    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
156    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
157    0
158  };
159
160  static const unsigned DarwinCalleeSavedRegs[] = {
161    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
162    // register.
163    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
164    ARM::R11, ARM::R10, ARM::R8,
165
166    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
167    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
168    0
169  };
170  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
171}
172
173const TargetRegisterClass* const *
174ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
175  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
176    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
177    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
179
180    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
181    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182    0
183  };
184
185  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
186    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
187    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
188    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
189
190    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
191    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192    0
193  };
194
195  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
196    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
197    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198    &ARM::GPRRegClass, &ARM::GPRRegClass,
199
200    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
201    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202    0
203  };
204
205  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
206    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
207    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
208    &ARM::GPRRegClass,  &ARM::GPRRegClass,
209
210    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
211    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212    0
213  };
214
215  if (STI.isThumb1Only()) {
216    return STI.isTargetDarwin()
217      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
218  }
219  return STI.isTargetDarwin()
220    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
221}
222
223BitVector ARMBaseRegisterInfo::
224getReservedRegs(const MachineFunction &MF) const {
225  // FIXME: avoid re-calculating this everytime.
226  BitVector Reserved(getNumRegs());
227  Reserved.set(ARM::SP);
228  Reserved.set(ARM::PC);
229  if (STI.isTargetDarwin() || hasFP(MF))
230    Reserved.set(FramePtr);
231  // Some targets reserve R9.
232  if (STI.isR9Reserved())
233    Reserved.set(ARM::R9);
234  return Reserved;
235}
236
237bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238                                        unsigned Reg) const {
239  switch (Reg) {
240  default: break;
241  case ARM::SP:
242  case ARM::PC:
243    return true;
244  case ARM::R7:
245  case ARM::R11:
246    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
247      return true;
248    break;
249  case ARM::R9:
250    return STI.isR9Reserved();
251  }
252
253  return false;
254}
255
256const TargetRegisterClass *
257ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
258                                              const TargetRegisterClass *B,
259                                              unsigned SubIdx) const {
260  switch (SubIdx) {
261  default: return 0;
262  case 1:
263  case 2:
264  case 3:
265  case 4:
266    // S sub-registers.
267    if (A->getSize() == 8) {
268      if (B == &ARM::SPR_8RegClass)
269        return &ARM::DPR_8RegClass;
270      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
271      if (A == &ARM::DPR_8RegClass)
272        return A;
273      return &ARM::DPR_VFP2RegClass;
274    }
275
276    assert(A->getSize() == 16 && "Expecting a Q register class!");
277    if (B == &ARM::SPR_8RegClass)
278      return &ARM::QPR_8RegClass;
279    return &ARM::QPR_VFP2RegClass;
280  case 5:
281  case 6:
282    // D sub-registers.
283    if (B == &ARM::DPR_VFP2RegClass)
284      return &ARM::QPR_VFP2RegClass;
285    if (B == &ARM::DPR_8RegClass)
286      return &ARM::QPR_8RegClass;
287    return A;
288  }
289  return 0;
290}
291
292const TargetRegisterClass *
293ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
294  return ARM::GPRRegisterClass;
295}
296
297/// getAllocationOrder - Returns the register allocation order for a specified
298/// register class in the form of a pair of TargetRegisterClass iterators.
299std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
300ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
301                                        unsigned HintType, unsigned HintReg,
302                                        const MachineFunction &MF) const {
303  // Alternative register allocation orders when favoring even / odd registers
304  // of register pairs.
305
306  // No FP, R9 is available.
307  static const unsigned GPREven1[] = {
308    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
309    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
310    ARM::R9, ARM::R11
311  };
312  static const unsigned GPROdd1[] = {
313    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
314    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
315    ARM::R8, ARM::R10
316  };
317
318  // FP is R7, R9 is available.
319  static const unsigned GPREven2[] = {
320    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
321    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
322    ARM::R9, ARM::R11
323  };
324  static const unsigned GPROdd2[] = {
325    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
326    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
327    ARM::R8, ARM::R10
328  };
329
330  // FP is R11, R9 is available.
331  static const unsigned GPREven3[] = {
332    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
333    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
334    ARM::R9
335  };
336  static const unsigned GPROdd3[] = {
337    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
338    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
339    ARM::R8
340  };
341
342  // No FP, R9 is not available.
343  static const unsigned GPREven4[] = {
344    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
345    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
346    ARM::R11
347  };
348  static const unsigned GPROdd4[] = {
349    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
350    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
351    ARM::R10
352  };
353
354  // FP is R7, R9 is not available.
355  static const unsigned GPREven5[] = {
356    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
357    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
358    ARM::R11
359  };
360  static const unsigned GPROdd5[] = {
361    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
362    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
363    ARM::R10
364  };
365
366  // FP is R11, R9 is not available.
367  static const unsigned GPREven6[] = {
368    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
369    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
370  };
371  static const unsigned GPROdd6[] = {
372    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
373    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
374  };
375
376
377  if (HintType == ARMRI::RegPairEven) {
378    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
379      // It's no longer possible to fulfill this hint. Return the default
380      // allocation order.
381      return std::make_pair(RC->allocation_order_begin(MF),
382                            RC->allocation_order_end(MF));
383
384    if (!STI.isTargetDarwin() && !hasFP(MF)) {
385      if (!STI.isR9Reserved())
386        return std::make_pair(GPREven1,
387                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
388      else
389        return std::make_pair(GPREven4,
390                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
391    } else if (FramePtr == ARM::R7) {
392      if (!STI.isR9Reserved())
393        return std::make_pair(GPREven2,
394                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
395      else
396        return std::make_pair(GPREven5,
397                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
398    } else { // FramePtr == ARM::R11
399      if (!STI.isR9Reserved())
400        return std::make_pair(GPREven3,
401                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
402      else
403        return std::make_pair(GPREven6,
404                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
405    }
406  } else if (HintType == ARMRI::RegPairOdd) {
407    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
408      // It's no longer possible to fulfill this hint. Return the default
409      // allocation order.
410      return std::make_pair(RC->allocation_order_begin(MF),
411                            RC->allocation_order_end(MF));
412
413    if (!STI.isTargetDarwin() && !hasFP(MF)) {
414      if (!STI.isR9Reserved())
415        return std::make_pair(GPROdd1,
416                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
417      else
418        return std::make_pair(GPROdd4,
419                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
420    } else if (FramePtr == ARM::R7) {
421      if (!STI.isR9Reserved())
422        return std::make_pair(GPROdd2,
423                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
424      else
425        return std::make_pair(GPROdd5,
426                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
427    } else { // FramePtr == ARM::R11
428      if (!STI.isR9Reserved())
429        return std::make_pair(GPROdd3,
430                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
431      else
432        return std::make_pair(GPROdd6,
433                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
434    }
435  }
436  return std::make_pair(RC->allocation_order_begin(MF),
437                        RC->allocation_order_end(MF));
438}
439
440/// ResolveRegAllocHint - Resolves the specified register allocation hint
441/// to a physical register. Returns the physical register if it is successful.
442unsigned
443ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
444                                         const MachineFunction &MF) const {
445  if (Reg == 0 || !isPhysicalRegister(Reg))
446    return 0;
447  if (Type == 0)
448    return Reg;
449  else if (Type == (unsigned)ARMRI::RegPairOdd)
450    // Odd register.
451    return getRegisterPairOdd(Reg, MF);
452  else if (Type == (unsigned)ARMRI::RegPairEven)
453    // Even register.
454    return getRegisterPairEven(Reg, MF);
455  return 0;
456}
457
458void
459ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
460                                        MachineFunction &MF) const {
461  MachineRegisterInfo *MRI = &MF.getRegInfo();
462  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
463  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
464       Hint.first == (unsigned)ARMRI::RegPairEven) &&
465      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
466    // If 'Reg' is one of the even / odd register pair and it's now changed
467    // (e.g. coalesced) into a different register. The other register of the
468    // pair allocation hint must be updated to reflect the relationship
469    // change.
470    unsigned OtherReg = Hint.second;
471    Hint = MRI->getRegAllocationHint(OtherReg);
472    if (Hint.second == Reg)
473      // Make sure the pair has not already divorced.
474      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
475  }
476}
477
478/// hasFP - Return true if the specified function should have a dedicated frame
479/// pointer register.  This is true if the function has variable sized allocas
480/// or if frame pointer elimination is disabled.
481///
482bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
483  const MachineFrameInfo *MFI = MF.getFrameInfo();
484  return ((DisableFramePointerElim(MF) && MFI->hasCalls())||
485          needsStackRealignment(MF) ||
486          MFI->hasVarSizedObjects() ||
487          MFI->isFrameAddressTaken());
488}
489
490bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
491  const MachineFrameInfo *MFI = MF.getFrameInfo();
492  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
493  return (RealignStack &&
494          !AFI->isThumb1OnlyFunction() &&
495          !MFI->hasVarSizedObjects());
496}
497
498bool ARMBaseRegisterInfo::
499needsStackRealignment(const MachineFunction &MF) const {
500  const MachineFrameInfo *MFI = MF.getFrameInfo();
501  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
502  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
503  return (RealignStack &&
504          !AFI->isThumb1OnlyFunction() &&
505          (MFI->getMaxAlignment() > StackAlign) &&
506          !MFI->hasVarSizedObjects());
507}
508
509bool ARMBaseRegisterInfo::
510cannotEliminateFrame(const MachineFunction &MF) const {
511  const MachineFrameInfo *MFI = MF.getFrameInfo();
512  if (DisableFramePointerElim(MF) && MFI->hasCalls())
513    return true;
514  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
515    || needsStackRealignment(MF);
516}
517
518/// estimateStackSize - Estimate and return the size of the frame.
519static unsigned estimateStackSize(MachineFunction &MF) {
520  const MachineFrameInfo *FFI = MF.getFrameInfo();
521  int Offset = 0;
522  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
523    int FixedOff = -FFI->getObjectOffset(i);
524    if (FixedOff > Offset) Offset = FixedOff;
525  }
526  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
527    if (FFI->isDeadObjectIndex(i))
528      continue;
529    Offset += FFI->getObjectSize(i);
530    unsigned Align = FFI->getObjectAlignment(i);
531    // Adjust to alignment boundary
532    Offset = (Offset+Align-1)/Align*Align;
533  }
534  return (unsigned)Offset;
535}
536
537/// estimateRSStackSizeLimit - Look at each instruction that references stack
538/// frames and return the stack size limit beyond which some of these
539/// instructions will require a scratch register during their expansion later.
540unsigned
541ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
542  unsigned Limit = (1 << 12) - 1;
543  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
544    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
545         I != E; ++I) {
546      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
547        if (!I->getOperand(i).isFI()) continue;
548
549        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
550        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
551        if (AddrMode == ARMII::AddrMode3 ||
552            AddrMode == ARMII::AddrModeT2_i8)
553          return (1 << 8) - 1;
554
555        if (AddrMode == ARMII::AddrMode5 ||
556            AddrMode == ARMII::AddrModeT2_i8s4)
557          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
558
559        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
560          // When the stack offset is negative, we will end up using
561          // the i8 instructions instead.
562          return (1 << 8) - 1;
563
564        if (AddrMode == ARMII::AddrMode6)
565          return 0;
566        break; // At most one FI per instruction
567      }
568    }
569  }
570
571  return Limit;
572}
573
574void
575ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
576                                                       RegScavenger *RS) const {
577  // This tells PEI to spill the FP as if it is any other callee-save register
578  // to take advantage the eliminateFrameIndex machinery. This also ensures it
579  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
580  // to combine multiple loads / stores.
581  bool CanEliminateFrame = true;
582  bool CS1Spilled = false;
583  bool LRSpilled = false;
584  unsigned NumGPRSpills = 0;
585  SmallVector<unsigned, 4> UnspilledCS1GPRs;
586  SmallVector<unsigned, 4> UnspilledCS2GPRs;
587  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
588
589  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
590  // scratch register.
591  // FIXME: It will be better just to find spare register here.
592  if (needsStackRealignment(MF) &&
593      AFI->isThumb2Function())
594    MF.getRegInfo().setPhysRegUsed(ARM::R4);
595
596  // Spill LR if Thumb1 function uses variable length argument lists.
597  if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
598    MF.getRegInfo().setPhysRegUsed(ARM::LR);
599
600  // Don't spill FP if the frame can be eliminated. This is determined
601  // by scanning the callee-save registers to see if any is used.
602  const unsigned *CSRegs = getCalleeSavedRegs();
603  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
604  for (unsigned i = 0; CSRegs[i]; ++i) {
605    unsigned Reg = CSRegs[i];
606    bool Spilled = false;
607    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
608      AFI->setCSRegisterIsSpilled(Reg);
609      Spilled = true;
610      CanEliminateFrame = false;
611    } else {
612      // Check alias registers too.
613      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
614        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
615          Spilled = true;
616          CanEliminateFrame = false;
617        }
618      }
619    }
620
621    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
622        CSRegClasses[i] == ARM::tGPRRegisterClass) {
623      if (Spilled) {
624        NumGPRSpills++;
625
626        if (!STI.isTargetDarwin()) {
627          if (Reg == ARM::LR)
628            LRSpilled = true;
629          CS1Spilled = true;
630          continue;
631        }
632
633        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
634        switch (Reg) {
635        case ARM::LR:
636          LRSpilled = true;
637          // Fallthrough
638        case ARM::R4:
639        case ARM::R5:
640        case ARM::R6:
641        case ARM::R7:
642          CS1Spilled = true;
643          break;
644        default:
645          break;
646        }
647      } else {
648        if (!STI.isTargetDarwin()) {
649          UnspilledCS1GPRs.push_back(Reg);
650          continue;
651        }
652
653        switch (Reg) {
654        case ARM::R4:
655        case ARM::R5:
656        case ARM::R6:
657        case ARM::R7:
658        case ARM::LR:
659          UnspilledCS1GPRs.push_back(Reg);
660          break;
661        default:
662          UnspilledCS2GPRs.push_back(Reg);
663          break;
664        }
665      }
666    }
667  }
668
669  bool ForceLRSpill = false;
670  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
671    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
672    // Force LR to be spilled if the Thumb function size is > 2048. This enables
673    // use of BL to implement far jump. If it turns out that it's not needed
674    // then the branch fix up path will undo it.
675    if (FnSize >= (1 << 11)) {
676      CanEliminateFrame = false;
677      ForceLRSpill = true;
678    }
679  }
680
681  // If any of the stack slot references may be out of range of an immediate
682  // offset, make sure a register (or a spill slot) is available for the
683  // register scavenger. Note that if we're indexing off the frame pointer, the
684  // effective stack size is 4 bytes larger since the FP points to the stack
685  // slot of the previous FP.
686  bool BigStack = RS &&
687    estimateStackSize(MF) + (hasFP(MF) ? 4 : 0) >= estimateRSStackSizeLimit(MF);
688
689  bool ExtraCSSpill = false;
690  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
691    AFI->setHasStackFrame(true);
692
693    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
694    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
695    if (!LRSpilled && CS1Spilled) {
696      MF.getRegInfo().setPhysRegUsed(ARM::LR);
697      AFI->setCSRegisterIsSpilled(ARM::LR);
698      NumGPRSpills++;
699      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
700                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
701      ForceLRSpill = false;
702      ExtraCSSpill = true;
703    }
704
705    // Darwin ABI requires FP to point to the stack slot that contains the
706    // previous FP.
707    if (STI.isTargetDarwin() || hasFP(MF)) {
708      MF.getRegInfo().setPhysRegUsed(FramePtr);
709      NumGPRSpills++;
710    }
711
712    // If stack and double are 8-byte aligned and we are spilling an odd number
713    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
714    // the integer and double callee save areas.
715    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
716    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
717      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
718        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
719          unsigned Reg = UnspilledCS1GPRs[i];
720          // Don't spill high register if the function is thumb1
721          if (!AFI->isThumb1OnlyFunction() ||
722              isARMLowRegister(Reg) || Reg == ARM::LR) {
723            MF.getRegInfo().setPhysRegUsed(Reg);
724            AFI->setCSRegisterIsSpilled(Reg);
725            if (!isReservedReg(MF, Reg))
726              ExtraCSSpill = true;
727            break;
728          }
729        }
730      } else if (!UnspilledCS2GPRs.empty() &&
731                 !AFI->isThumb1OnlyFunction()) {
732        unsigned Reg = UnspilledCS2GPRs.front();
733        MF.getRegInfo().setPhysRegUsed(Reg);
734        AFI->setCSRegisterIsSpilled(Reg);
735        if (!isReservedReg(MF, Reg))
736          ExtraCSSpill = true;
737      }
738    }
739
740    // Estimate if we might need to scavenge a register at some point in order
741    // to materialize a stack offset. If so, either spill one additional
742    // callee-saved register or reserve a special spill slot to facilitate
743    // register scavenging. Thumb1 needs a spill slot for stack pointer
744    // adjustments also, even when the frame itself is small.
745    if (BigStack && !ExtraCSSpill) {
746      // If any non-reserved CS register isn't spilled, just spill one or two
747      // extra. That should take care of it!
748      unsigned NumExtras = TargetAlign / 4;
749      SmallVector<unsigned, 2> Extras;
750      while (NumExtras && !UnspilledCS1GPRs.empty()) {
751        unsigned Reg = UnspilledCS1GPRs.back();
752        UnspilledCS1GPRs.pop_back();
753        if (!isReservedReg(MF, Reg)) {
754          Extras.push_back(Reg);
755          NumExtras--;
756        }
757      }
758      // For non-Thumb1 functions, also check for hi-reg CS registers
759      if (!AFI->isThumb1OnlyFunction()) {
760        while (NumExtras && !UnspilledCS2GPRs.empty()) {
761          unsigned Reg = UnspilledCS2GPRs.back();
762          UnspilledCS2GPRs.pop_back();
763          if (!isReservedReg(MF, Reg)) {
764            Extras.push_back(Reg);
765            NumExtras--;
766          }
767        }
768      }
769      if (Extras.size() && NumExtras == 0) {
770        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
771          MF.getRegInfo().setPhysRegUsed(Extras[i]);
772          AFI->setCSRegisterIsSpilled(Extras[i]);
773        }
774      } else if (!AFI->isThumb1OnlyFunction()) {
775        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
776        // closest to SP or frame pointer.
777        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
778        MachineFrameInfo *MFI = MF.getFrameInfo();
779        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
780                                                           RC->getAlignment(),
781                                                           false));
782      }
783    }
784  }
785
786  if (ForceLRSpill) {
787    MF.getRegInfo().setPhysRegUsed(ARM::LR);
788    AFI->setCSRegisterIsSpilled(ARM::LR);
789    AFI->setLRIsSpilledForFarJump(true);
790  }
791}
792
793unsigned ARMBaseRegisterInfo::getRARegister() const {
794  return ARM::LR;
795}
796
797unsigned
798ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
799  if (STI.isTargetDarwin() || hasFP(MF))
800    return FramePtr;
801  return ARM::SP;
802}
803
804int
805ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
806                                            unsigned &FrameReg) const {
807  const MachineFrameInfo *MFI = MF.getFrameInfo();
808  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
809  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
810  bool isFixed = MFI->isFixedObjectIndex(FI);
811
812  FrameReg = ARM::SP;
813  if (AFI->isGPRCalleeSavedArea1Frame(FI))
814    Offset -= AFI->getGPRCalleeSavedArea1Offset();
815  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
816    Offset -= AFI->getGPRCalleeSavedArea2Offset();
817  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
818    Offset -= AFI->getDPRCalleeSavedAreaOffset();
819  else if (needsStackRealignment(MF)) {
820    // When dynamically realigning the stack, use the frame pointer for
821    // parameters, and the stack pointer for locals.
822    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
823    if (isFixed) {
824      FrameReg = getFrameRegister(MF);
825      Offset -= AFI->getFramePtrSpillOffset();
826    }
827  } else if (hasFP(MF) && AFI->hasStackFrame()) {
828    if (isFixed || MFI->hasVarSizedObjects()) {
829      // Use frame pointer to reference fixed objects unless this is a
830      // frameless function.
831      FrameReg = getFrameRegister(MF);
832      Offset -= AFI->getFramePtrSpillOffset();
833    } else if (AFI->isThumb2Function()) {
834      // In Thumb2 mode, the negative offset is very limited.
835      int FPOffset = Offset - AFI->getFramePtrSpillOffset();
836      if (FPOffset >= -255 && FPOffset < 0) {
837        FrameReg = getFrameRegister(MF);
838        Offset = FPOffset;
839      }
840    }
841  }
842  return Offset;
843}
844
845
846int
847ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
848                                         int FI) const {
849  unsigned FrameReg;
850  return getFrameIndexReference(MF, FI, FrameReg);
851}
852
853unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
854  llvm_unreachable("What is the exception register");
855  return 0;
856}
857
858unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
859  llvm_unreachable("What is the exception handler register");
860  return 0;
861}
862
863int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
864  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
865}
866
867unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
868                                              const MachineFunction &MF) const {
869  switch (Reg) {
870  default: break;
871  // Return 0 if either register of the pair is a special register.
872  // So no R12, etc.
873  case ARM::R1:
874    return ARM::R0;
875  case ARM::R3:
876    return ARM::R2;
877  case ARM::R5:
878    return ARM::R4;
879  case ARM::R7:
880    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
881  case ARM::R9:
882    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
883  case ARM::R11:
884    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
885
886  case ARM::S1:
887    return ARM::S0;
888  case ARM::S3:
889    return ARM::S2;
890  case ARM::S5:
891    return ARM::S4;
892  case ARM::S7:
893    return ARM::S6;
894  case ARM::S9:
895    return ARM::S8;
896  case ARM::S11:
897    return ARM::S10;
898  case ARM::S13:
899    return ARM::S12;
900  case ARM::S15:
901    return ARM::S14;
902  case ARM::S17:
903    return ARM::S16;
904  case ARM::S19:
905    return ARM::S18;
906  case ARM::S21:
907    return ARM::S20;
908  case ARM::S23:
909    return ARM::S22;
910  case ARM::S25:
911    return ARM::S24;
912  case ARM::S27:
913    return ARM::S26;
914  case ARM::S29:
915    return ARM::S28;
916  case ARM::S31:
917    return ARM::S30;
918
919  case ARM::D1:
920    return ARM::D0;
921  case ARM::D3:
922    return ARM::D2;
923  case ARM::D5:
924    return ARM::D4;
925  case ARM::D7:
926    return ARM::D6;
927  case ARM::D9:
928    return ARM::D8;
929  case ARM::D11:
930    return ARM::D10;
931  case ARM::D13:
932    return ARM::D12;
933  case ARM::D15:
934    return ARM::D14;
935  case ARM::D17:
936    return ARM::D16;
937  case ARM::D19:
938    return ARM::D18;
939  case ARM::D21:
940    return ARM::D20;
941  case ARM::D23:
942    return ARM::D22;
943  case ARM::D25:
944    return ARM::D24;
945  case ARM::D27:
946    return ARM::D26;
947  case ARM::D29:
948    return ARM::D28;
949  case ARM::D31:
950    return ARM::D30;
951  }
952
953  return 0;
954}
955
956unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
957                                             const MachineFunction &MF) const {
958  switch (Reg) {
959  default: break;
960  // Return 0 if either register of the pair is a special register.
961  // So no R12, etc.
962  case ARM::R0:
963    return ARM::R1;
964  case ARM::R2:
965    return ARM::R3;
966  case ARM::R4:
967    return ARM::R5;
968  case ARM::R6:
969    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
970  case ARM::R8:
971    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
972  case ARM::R10:
973    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
974
975  case ARM::S0:
976    return ARM::S1;
977  case ARM::S2:
978    return ARM::S3;
979  case ARM::S4:
980    return ARM::S5;
981  case ARM::S6:
982    return ARM::S7;
983  case ARM::S8:
984    return ARM::S9;
985  case ARM::S10:
986    return ARM::S11;
987  case ARM::S12:
988    return ARM::S13;
989  case ARM::S14:
990    return ARM::S15;
991  case ARM::S16:
992    return ARM::S17;
993  case ARM::S18:
994    return ARM::S19;
995  case ARM::S20:
996    return ARM::S21;
997  case ARM::S22:
998    return ARM::S23;
999  case ARM::S24:
1000    return ARM::S25;
1001  case ARM::S26:
1002    return ARM::S27;
1003  case ARM::S28:
1004    return ARM::S29;
1005  case ARM::S30:
1006    return ARM::S31;
1007
1008  case ARM::D0:
1009    return ARM::D1;
1010  case ARM::D2:
1011    return ARM::D3;
1012  case ARM::D4:
1013    return ARM::D5;
1014  case ARM::D6:
1015    return ARM::D7;
1016  case ARM::D8:
1017    return ARM::D9;
1018  case ARM::D10:
1019    return ARM::D11;
1020  case ARM::D12:
1021    return ARM::D13;
1022  case ARM::D14:
1023    return ARM::D15;
1024  case ARM::D16:
1025    return ARM::D17;
1026  case ARM::D18:
1027    return ARM::D19;
1028  case ARM::D20:
1029    return ARM::D21;
1030  case ARM::D22:
1031    return ARM::D23;
1032  case ARM::D24:
1033    return ARM::D25;
1034  case ARM::D26:
1035    return ARM::D27;
1036  case ARM::D28:
1037    return ARM::D29;
1038  case ARM::D30:
1039    return ARM::D31;
1040  }
1041
1042  return 0;
1043}
1044
1045/// emitLoadConstPool - Emits a load from constpool to materialize the
1046/// specified immediate.
1047void ARMBaseRegisterInfo::
1048emitLoadConstPool(MachineBasicBlock &MBB,
1049                  MachineBasicBlock::iterator &MBBI,
1050                  DebugLoc dl,
1051                  unsigned DestReg, unsigned SubIdx, int Val,
1052                  ARMCC::CondCodes Pred,
1053                  unsigned PredReg) const {
1054  MachineFunction &MF = *MBB.getParent();
1055  MachineConstantPool *ConstantPool = MF.getConstantPool();
1056  const Constant *C =
1057        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1058  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1059
1060  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1061    .addReg(DestReg, getDefRegState(true), SubIdx)
1062    .addConstantPoolIndex(Idx)
1063    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1064}
1065
1066bool ARMBaseRegisterInfo::
1067requiresRegisterScavenging(const MachineFunction &MF) const {
1068  return true;
1069}
1070
1071bool ARMBaseRegisterInfo::
1072requiresFrameIndexScavenging(const MachineFunction &MF) const {
1073  return true;
1074}
1075
1076// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1077// not required, we reserve argument space for call sites in the function
1078// immediately on entry to the current function. This eliminates the need for
1079// add/sub sp brackets around call sites. Returns true if the call frame is
1080// included as part of the stack frame.
1081bool ARMBaseRegisterInfo::
1082hasReservedCallFrame(MachineFunction &MF) const {
1083  const MachineFrameInfo *FFI = MF.getFrameInfo();
1084  unsigned CFSize = FFI->getMaxCallFrameSize();
1085  // It's not always a good idea to include the call frame as part of the
1086  // stack frame. ARM (especially Thumb) has small immediate offset to
1087  // address the stack frame. So a large call frame can cause poor codegen
1088  // and may even makes it impossible to scavenge a register.
1089  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1090    return false;
1091
1092  return !MF.getFrameInfo()->hasVarSizedObjects();
1093}
1094
1095// canSimplifyCallFramePseudos - If there is a reserved call frame, the
1096// call frame pseudos can be simplified. Unlike most targets, having a FP
1097// is not sufficient here since we still may reference some objects via SP
1098// even when FP is available in Thumb2 mode.
1099bool ARMBaseRegisterInfo::
1100canSimplifyCallFramePseudos(MachineFunction &MF) const {
1101  return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1102}
1103
1104static void
1105emitSPUpdate(bool isARM,
1106             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1107             DebugLoc dl, const ARMBaseInstrInfo &TII,
1108             int NumBytes,
1109             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1110  if (isARM)
1111    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1112                            Pred, PredReg, TII);
1113  else
1114    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1115                           Pred, PredReg, TII);
1116}
1117
1118
1119void ARMBaseRegisterInfo::
1120eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1121                              MachineBasicBlock::iterator I) const {
1122  if (!hasReservedCallFrame(MF)) {
1123    // If we have alloca, convert as follows:
1124    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1125    // ADJCALLSTACKUP   -> add, sp, sp, amount
1126    MachineInstr *Old = I;
1127    DebugLoc dl = Old->getDebugLoc();
1128    unsigned Amount = Old->getOperand(0).getImm();
1129    if (Amount != 0) {
1130      // We need to keep the stack aligned properly.  To do this, we round the
1131      // amount of space needed for the outgoing arguments up to the next
1132      // alignment boundary.
1133      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1134      Amount = (Amount+Align-1)/Align*Align;
1135
1136      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1137      assert(!AFI->isThumb1OnlyFunction() &&
1138             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1139      bool isARM = !AFI->isThumbFunction();
1140
1141      // Replace the pseudo instruction with a new instruction...
1142      unsigned Opc = Old->getOpcode();
1143      int PIdx = Old->findFirstPredOperandIdx();
1144      ARMCC::CondCodes Pred = (PIdx == -1)
1145        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1146      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1147        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1148        unsigned PredReg = Old->getOperand(2).getReg();
1149        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1150      } else {
1151        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1152        unsigned PredReg = Old->getOperand(3).getReg();
1153        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1154        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1155      }
1156    }
1157  }
1158  MBB.erase(I);
1159}
1160
1161unsigned
1162ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1163                                         int SPAdj, FrameIndexValue *Value,
1164                                         RegScavenger *RS) const {
1165  unsigned i = 0;
1166  MachineInstr &MI = *II;
1167  MachineBasicBlock &MBB = *MI.getParent();
1168  MachineFunction &MF = *MBB.getParent();
1169  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1170  assert(!AFI->isThumb1OnlyFunction() &&
1171         "This eliminateFrameIndex does not support Thumb1!");
1172
1173  while (!MI.getOperand(i).isFI()) {
1174    ++i;
1175    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1176  }
1177
1178  int FrameIndex = MI.getOperand(i).getIndex();
1179  unsigned FrameReg;
1180
1181  int Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1182  if (FrameReg != ARM::SP)
1183    SPAdj = 0;
1184  Offset += SPAdj;
1185
1186  // Special handling of dbg_value instructions.
1187  if (MI.isDebugValue()) {
1188    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1189    MI.getOperand(i+1).ChangeToImmediate(Offset);
1190    return 0;
1191  }
1192
1193  // Modify MI as necessary to handle as much of 'Offset' as possible
1194  bool Done = false;
1195  if (!AFI->isThumbFunction())
1196    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1197  else {
1198    assert(AFI->isThumb2Function());
1199    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1200  }
1201  if (Done)
1202    return 0;
1203
1204  // If we get here, the immediate doesn't fit into the instruction.  We folded
1205  // as much as possible above, handle the rest, providing a register that is
1206  // SP+LargeImm.
1207  assert((Offset ||
1208          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1209          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1210         "This code isn't needed if offset already handled!");
1211
1212  unsigned ScratchReg = 0;
1213  int PIdx = MI.findFirstPredOperandIdx();
1214  ARMCC::CondCodes Pred = (PIdx == -1)
1215    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1216  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1217  if (Offset == 0)
1218    // Must be addrmode4/6.
1219    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1220  else {
1221    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1222    if (Value) {
1223      Value->first = FrameReg; // use the frame register as a kind indicator
1224      Value->second = Offset;
1225    }
1226    if (!AFI->isThumbFunction())
1227      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1228                              Offset, Pred, PredReg, TII);
1229    else {
1230      assert(AFI->isThumb2Function());
1231      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1232                             Offset, Pred, PredReg, TII);
1233    }
1234    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1235    if (!ReuseFrameIndexVals)
1236      ScratchReg = 0;
1237  }
1238  return ScratchReg;
1239}
1240
1241/// Move iterator past the next bunch of callee save load / store ops for
1242/// the particular spill area (1: integer area 1, 2: integer area 2,
1243/// 3: fp area, 0: don't care).
1244static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1245                                   MachineBasicBlock::iterator &MBBI,
1246                                   int Opc1, int Opc2, unsigned Area,
1247                                   const ARMSubtarget &STI) {
1248  while (MBBI != MBB.end() &&
1249         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1250         MBBI->getOperand(1).isFI()) {
1251    if (Area != 0) {
1252      bool Done = false;
1253      unsigned Category = 0;
1254      switch (MBBI->getOperand(0).getReg()) {
1255      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1256      case ARM::LR:
1257        Category = 1;
1258        break;
1259      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1260        Category = STI.isTargetDarwin() ? 2 : 1;
1261        break;
1262      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1263      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1264        Category = 3;
1265        break;
1266      default:
1267        Done = true;
1268        break;
1269      }
1270      if (Done || Category != Area)
1271        break;
1272    }
1273
1274    ++MBBI;
1275  }
1276}
1277
1278void ARMBaseRegisterInfo::
1279emitPrologue(MachineFunction &MF) const {
1280  MachineBasicBlock &MBB = MF.front();
1281  MachineBasicBlock::iterator MBBI = MBB.begin();
1282  MachineFrameInfo  *MFI = MF.getFrameInfo();
1283  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1284  assert(!AFI->isThumb1OnlyFunction() &&
1285         "This emitPrologue does not support Thumb1!");
1286  bool isARM = !AFI->isThumbFunction();
1287  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1288  unsigned NumBytes = MFI->getStackSize();
1289  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1290  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1291
1292  // Determine the sizes of each callee-save spill areas and record which frame
1293  // belongs to which callee-save spill areas.
1294  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1295  int FramePtrSpillFI = 0;
1296
1297  // Allocate the vararg register save area. This is not counted in NumBytes.
1298  if (VARegSaveSize)
1299    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1300
1301  if (!AFI->hasStackFrame()) {
1302    if (NumBytes != 0)
1303      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1304    return;
1305  }
1306
1307  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1308    unsigned Reg = CSI[i].getReg();
1309    int FI = CSI[i].getFrameIdx();
1310    switch (Reg) {
1311    case ARM::R4:
1312    case ARM::R5:
1313    case ARM::R6:
1314    case ARM::R7:
1315    case ARM::LR:
1316      if (Reg == FramePtr)
1317        FramePtrSpillFI = FI;
1318      AFI->addGPRCalleeSavedArea1Frame(FI);
1319      GPRCS1Size += 4;
1320      break;
1321    case ARM::R8:
1322    case ARM::R9:
1323    case ARM::R10:
1324    case ARM::R11:
1325      if (Reg == FramePtr)
1326        FramePtrSpillFI = FI;
1327      if (STI.isTargetDarwin()) {
1328        AFI->addGPRCalleeSavedArea2Frame(FI);
1329        GPRCS2Size += 4;
1330      } else {
1331        AFI->addGPRCalleeSavedArea1Frame(FI);
1332        GPRCS1Size += 4;
1333      }
1334      break;
1335    default:
1336      AFI->addDPRCalleeSavedAreaFrame(FI);
1337      DPRCSSize += 8;
1338    }
1339  }
1340
1341  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1342  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1343  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1344
1345  // Set FP to point to the stack slot that contains the previous FP.
1346  // For Darwin, FP is R7, which has now been stored in spill area 1.
1347  // Otherwise, if this is not Darwin, all the callee-saved registers go
1348  // into spill area 1, including the FP in R11.  In either case, it is
1349  // now safe to emit this assignment.
1350  if (STI.isTargetDarwin() || hasFP(MF)) {
1351    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1352    MachineInstrBuilder MIB =
1353      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1354      .addFrameIndex(FramePtrSpillFI).addImm(0);
1355    AddDefaultCC(AddDefaultPred(MIB));
1356  }
1357
1358  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1359  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1360
1361  // Build the new SUBri to adjust SP for FP callee-save spill area.
1362  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1363  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1364
1365  // Determine starting offsets of spill areas.
1366  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1367  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1368  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1369  if (STI.isTargetDarwin() || hasFP(MF))
1370    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1371                                NumBytes);
1372  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1373  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1374  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1375
1376  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1377  NumBytes = DPRCSOffset;
1378  if (NumBytes) {
1379    // Adjust SP after all the callee-save spills.
1380    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1381  }
1382
1383  if (STI.isTargetELF() && hasFP(MF)) {
1384    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1385                             AFI->getFramePtrSpillOffset());
1386  }
1387
1388  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1389  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1390  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1391
1392  // If we need dynamic stack realignment, do it here.
1393  if (needsStackRealignment(MF)) {
1394    unsigned MaxAlign = MFI->getMaxAlignment();
1395    assert (!AFI->isThumb1OnlyFunction());
1396    if (!AFI->isThumbFunction()) {
1397      // Emit bic sp, sp, MaxAlign
1398      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1399                                          TII.get(ARM::BICri), ARM::SP)
1400                                  .addReg(ARM::SP, RegState::Kill)
1401                                  .addImm(MaxAlign-1)));
1402    } else {
1403      // We cannot use sp as source/dest register here, thus we're emitting the
1404      // following sequence:
1405      // mov r4, sp
1406      // bic r4, r4, MaxAlign
1407      // mov sp, r4
1408      // FIXME: It will be better just to find spare register here.
1409      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1410        .addReg(ARM::SP, RegState::Kill);
1411      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1412                                          TII.get(ARM::t2BICri), ARM::R4)
1413                                  .addReg(ARM::R4, RegState::Kill)
1414                                  .addImm(MaxAlign-1)));
1415      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1416        .addReg(ARM::R4, RegState::Kill);
1417    }
1418  }
1419}
1420
1421static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1422  for (unsigned i = 0; CSRegs[i]; ++i)
1423    if (Reg == CSRegs[i])
1424      return true;
1425  return false;
1426}
1427
1428static bool isCSRestore(MachineInstr *MI,
1429                        const ARMBaseInstrInfo &TII,
1430                        const unsigned *CSRegs) {
1431  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1432           MI->getOpcode() == (int)ARM::LDR ||
1433           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1434          MI->getOperand(1).isFI() &&
1435          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1436}
1437
1438void ARMBaseRegisterInfo::
1439emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1440  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1441  assert(MBBI->getDesc().isReturn() &&
1442         "Can only insert epilog into returning blocks");
1443  DebugLoc dl = MBBI->getDebugLoc();
1444  MachineFrameInfo *MFI = MF.getFrameInfo();
1445  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1446  assert(!AFI->isThumb1OnlyFunction() &&
1447         "This emitEpilogue does not support Thumb1!");
1448  bool isARM = !AFI->isThumbFunction();
1449
1450  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1451  int NumBytes = (int)MFI->getStackSize();
1452
1453  if (!AFI->hasStackFrame()) {
1454    if (NumBytes != 0)
1455      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1456  } else {
1457    // Unwind MBBI to point to first LDR / VLDRD.
1458    const unsigned *CSRegs = getCalleeSavedRegs();
1459    if (MBBI != MBB.begin()) {
1460      do
1461        --MBBI;
1462      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1463      if (!isCSRestore(MBBI, TII, CSRegs))
1464        ++MBBI;
1465    }
1466
1467    // Move SP to start of FP callee save spill area.
1468    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1469                 AFI->getGPRCalleeSavedArea2Size() +
1470                 AFI->getDPRCalleeSavedAreaSize());
1471
1472    // Darwin ABI requires FP to point to the stack slot that contains the
1473    // previous FP.
1474    bool HasFP = hasFP(MF);
1475    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1476      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1477      // Reset SP based on frame pointer only if the stack frame extends beyond
1478      // frame pointer stack slot or target is ELF and the function has FP.
1479      if (HasFP ||
1480          AFI->getGPRCalleeSavedArea2Size() ||
1481          AFI->getDPRCalleeSavedAreaSize()  ||
1482          AFI->getDPRCalleeSavedAreaOffset()) {
1483        if (NumBytes) {
1484          if (isARM)
1485            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1486                                    ARMCC::AL, 0, TII);
1487          else
1488            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1489                                    ARMCC::AL, 0, TII);
1490        } else {
1491          // Thumb2 or ARM.
1492          if (isARM)
1493            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1494              .addReg(FramePtr)
1495              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1496          else
1497            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1498              .addReg(FramePtr);
1499        }
1500      }
1501    } else if (NumBytes)
1502      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1503
1504    // Move SP to start of integer callee save spill area 2.
1505    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1506    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1507
1508    // Move SP to start of integer callee save spill area 1.
1509    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1510    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1511
1512    // Move SP to SP upon entry to the function.
1513    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1514    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1515  }
1516
1517  if (VARegSaveSize)
1518    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1519}
1520
1521#include "ARMGenRegisterInfo.inc"
1522