ARMBaseRegisterInfo.cpp revision 202878 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41using namespace llvm;
42
43static cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46
47unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
48                                                   bool *isSPVFP) {
49  if (isSPVFP)
50    *isSPVFP = false;
51
52  using namespace ARM;
53  switch (RegEnum) {
54  default:
55    llvm_unreachable("Unknown ARM register!");
56  case R0:  case D0:  case Q0:  return 0;
57  case R1:  case D1:  case Q1:  return 1;
58  case R2:  case D2:  case Q2:  return 2;
59  case R3:  case D3:  case Q3:  return 3;
60  case R4:  case D4:  case Q4:  return 4;
61  case R5:  case D5:  case Q5:  return 5;
62  case R6:  case D6:  case Q6:  return 6;
63  case R7:  case D7:  case Q7:  return 7;
64  case R8:  case D8:  case Q8:  return 8;
65  case R9:  case D9:  case Q9:  return 9;
66  case R10: case D10: case Q10: return 10;
67  case R11: case D11: case Q11: return 11;
68  case R12: case D12: case Q12: return 12;
69  case SP:  case D13: case Q13: return 13;
70  case LR:  case D14: case Q14: return 14;
71  case PC:  case D15: case Q15: return 15;
72
73  case D16: return 16;
74  case D17: return 17;
75  case D18: return 18;
76  case D19: return 19;
77  case D20: return 20;
78  case D21: return 21;
79  case D22: return 22;
80  case D23: return 23;
81  case D24: return 24;
82  case D25: return 25;
83  case D26: return 27;
84  case D27: return 27;
85  case D28: return 28;
86  case D29: return 29;
87  case D30: return 30;
88  case D31: return 31;
89
90  case S0: case S1: case S2: case S3:
91  case S4: case S5: case S6: case S7:
92  case S8: case S9: case S10: case S11:
93  case S12: case S13: case S14: case S15:
94  case S16: case S17: case S18: case S19:
95  case S20: case S21: case S22: case S23:
96  case S24: case S25: case S26: case S27:
97  case S28: case S29: case S30: case S31: {
98    if (isSPVFP)
99      *isSPVFP = true;
100    switch (RegEnum) {
101    default: return 0; // Avoid compile time warning.
102    case S0: return 0;
103    case S1: return 1;
104    case S2: return 2;
105    case S3: return 3;
106    case S4: return 4;
107    case S5: return 5;
108    case S6: return 6;
109    case S7: return 7;
110    case S8: return 8;
111    case S9: return 9;
112    case S10: return 10;
113    case S11: return 11;
114    case S12: return 12;
115    case S13: return 13;
116    case S14: return 14;
117    case S15: return 15;
118    case S16: return 16;
119    case S17: return 17;
120    case S18: return 18;
121    case S19: return 19;
122    case S20: return 20;
123    case S21: return 21;
124    case S22: return 22;
125    case S23: return 23;
126    case S24: return 24;
127    case S25: return 25;
128    case S26: return 26;
129    case S27: return 27;
130    case S28: return 28;
131    case S29: return 29;
132    case S30: return 30;
133    case S31: return 31;
134    }
135  }
136  }
137}
138
139ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
140                                         const ARMSubtarget &sti)
141  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
142    TII(tii), STI(sti),
143    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
144}
145
146const unsigned*
147ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
148  static const unsigned CalleeSavedRegs[] = {
149    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
150    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
151
152    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
153    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
154    0
155  };
156
157  static const unsigned DarwinCalleeSavedRegs[] = {
158    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
159    // register.
160    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
161    ARM::R11, ARM::R10, ARM::R8,
162
163    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
164    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
165    0
166  };
167  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
168}
169
170const TargetRegisterClass* const *
171ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
172  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
173    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
174    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
175    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
176
177    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
178    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
179    0
180  };
181
182  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
183    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
184    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
185    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
186
187    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
188    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
189    0
190  };
191
192  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
193    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
194    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
195    &ARM::GPRRegClass, &ARM::GPRRegClass,
196
197    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
198    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
199    0
200  };
201
202  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
203    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
204    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
205    &ARM::GPRRegClass,  &ARM::GPRRegClass,
206
207    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
208    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
209    0
210  };
211
212  if (STI.isThumb1Only()) {
213    return STI.isTargetDarwin()
214      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
215  }
216  return STI.isTargetDarwin()
217    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
218}
219
220BitVector ARMBaseRegisterInfo::
221getReservedRegs(const MachineFunction &MF) const {
222  // FIXME: avoid re-calculating this everytime.
223  BitVector Reserved(getNumRegs());
224  Reserved.set(ARM::SP);
225  Reserved.set(ARM::PC);
226  if (STI.isTargetDarwin() || hasFP(MF))
227    Reserved.set(FramePtr);
228  // Some targets reserve R9.
229  if (STI.isR9Reserved())
230    Reserved.set(ARM::R9);
231  return Reserved;
232}
233
234bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
235                                        unsigned Reg) const {
236  switch (Reg) {
237  default: break;
238  case ARM::SP:
239  case ARM::PC:
240    return true;
241  case ARM::R7:
242  case ARM::R11:
243    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
244      return true;
245    break;
246  case ARM::R9:
247    return STI.isR9Reserved();
248  }
249
250  return false;
251}
252
253const TargetRegisterClass *
254ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
255                                              const TargetRegisterClass *B,
256                                              unsigned SubIdx) const {
257  switch (SubIdx) {
258  default: return 0;
259  case 1:
260  case 2:
261  case 3:
262  case 4:
263    // S sub-registers.
264    if (A->getSize() == 8) {
265      if (B == &ARM::SPR_8RegClass)
266        return &ARM::DPR_8RegClass;
267      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
268      if (A == &ARM::DPR_8RegClass)
269        return A;
270      return &ARM::DPR_VFP2RegClass;
271    }
272
273    assert(A->getSize() == 16 && "Expecting a Q register class!");
274    if (B == &ARM::SPR_8RegClass)
275      return &ARM::QPR_8RegClass;
276    return &ARM::QPR_VFP2RegClass;
277  case 5:
278  case 6:
279    // D sub-registers.
280    if (B == &ARM::DPR_VFP2RegClass)
281      return &ARM::QPR_VFP2RegClass;
282    if (B == &ARM::DPR_8RegClass)
283      return &ARM::QPR_8RegClass;
284    return A;
285  }
286  return 0;
287}
288
289const TargetRegisterClass *
290ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
291  return ARM::GPRRegisterClass;
292}
293
294/// getAllocationOrder - Returns the register allocation order for a specified
295/// register class in the form of a pair of TargetRegisterClass iterators.
296std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
297ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
298                                        unsigned HintType, unsigned HintReg,
299                                        const MachineFunction &MF) const {
300  // Alternative register allocation orders when favoring even / odd registers
301  // of register pairs.
302
303  // No FP, R9 is available.
304  static const unsigned GPREven1[] = {
305    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
306    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
307    ARM::R9, ARM::R11
308  };
309  static const unsigned GPROdd1[] = {
310    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
311    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
312    ARM::R8, ARM::R10
313  };
314
315  // FP is R7, R9 is available.
316  static const unsigned GPREven2[] = {
317    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
318    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
319    ARM::R9, ARM::R11
320  };
321  static const unsigned GPROdd2[] = {
322    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
323    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
324    ARM::R8, ARM::R10
325  };
326
327  // FP is R11, R9 is available.
328  static const unsigned GPREven3[] = {
329    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
330    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
331    ARM::R9
332  };
333  static const unsigned GPROdd3[] = {
334    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
335    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
336    ARM::R8
337  };
338
339  // No FP, R9 is not available.
340  static const unsigned GPREven4[] = {
341    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
342    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
343    ARM::R11
344  };
345  static const unsigned GPROdd4[] = {
346    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
347    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
348    ARM::R10
349  };
350
351  // FP is R7, R9 is not available.
352  static const unsigned GPREven5[] = {
353    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
354    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
355    ARM::R11
356  };
357  static const unsigned GPROdd5[] = {
358    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
359    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
360    ARM::R10
361  };
362
363  // FP is R11, R9 is not available.
364  static const unsigned GPREven6[] = {
365    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
366    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
367  };
368  static const unsigned GPROdd6[] = {
369    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
370    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
371  };
372
373
374  if (HintType == ARMRI::RegPairEven) {
375    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
376      // It's no longer possible to fulfill this hint. Return the default
377      // allocation order.
378      return std::make_pair(RC->allocation_order_begin(MF),
379                            RC->allocation_order_end(MF));
380
381    if (!STI.isTargetDarwin() && !hasFP(MF)) {
382      if (!STI.isR9Reserved())
383        return std::make_pair(GPREven1,
384                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
385      else
386        return std::make_pair(GPREven4,
387                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
388    } else if (FramePtr == ARM::R7) {
389      if (!STI.isR9Reserved())
390        return std::make_pair(GPREven2,
391                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
392      else
393        return std::make_pair(GPREven5,
394                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
395    } else { // FramePtr == ARM::R11
396      if (!STI.isR9Reserved())
397        return std::make_pair(GPREven3,
398                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
399      else
400        return std::make_pair(GPREven6,
401                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
402    }
403  } else if (HintType == ARMRI::RegPairOdd) {
404    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
405      // It's no longer possible to fulfill this hint. Return the default
406      // allocation order.
407      return std::make_pair(RC->allocation_order_begin(MF),
408                            RC->allocation_order_end(MF));
409
410    if (!STI.isTargetDarwin() && !hasFP(MF)) {
411      if (!STI.isR9Reserved())
412        return std::make_pair(GPROdd1,
413                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
414      else
415        return std::make_pair(GPROdd4,
416                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
417    } else if (FramePtr == ARM::R7) {
418      if (!STI.isR9Reserved())
419        return std::make_pair(GPROdd2,
420                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
421      else
422        return std::make_pair(GPROdd5,
423                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
424    } else { // FramePtr == ARM::R11
425      if (!STI.isR9Reserved())
426        return std::make_pair(GPROdd3,
427                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
428      else
429        return std::make_pair(GPROdd6,
430                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
431    }
432  }
433  return std::make_pair(RC->allocation_order_begin(MF),
434                        RC->allocation_order_end(MF));
435}
436
437/// ResolveRegAllocHint - Resolves the specified register allocation hint
438/// to a physical register. Returns the physical register if it is successful.
439unsigned
440ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
441                                         const MachineFunction &MF) const {
442  if (Reg == 0 || !isPhysicalRegister(Reg))
443    return 0;
444  if (Type == 0)
445    return Reg;
446  else if (Type == (unsigned)ARMRI::RegPairOdd)
447    // Odd register.
448    return getRegisterPairOdd(Reg, MF);
449  else if (Type == (unsigned)ARMRI::RegPairEven)
450    // Even register.
451    return getRegisterPairEven(Reg, MF);
452  return 0;
453}
454
455void
456ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
457                                        MachineFunction &MF) const {
458  MachineRegisterInfo *MRI = &MF.getRegInfo();
459  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
460  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
461       Hint.first == (unsigned)ARMRI::RegPairEven) &&
462      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
463    // If 'Reg' is one of the even / odd register pair and it's now changed
464    // (e.g. coalesced) into a different register. The other register of the
465    // pair allocation hint must be updated to reflect the relationship
466    // change.
467    unsigned OtherReg = Hint.second;
468    Hint = MRI->getRegAllocationHint(OtherReg);
469    if (Hint.second == Reg)
470      // Make sure the pair has not already divorced.
471      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
472  }
473}
474
475/// hasFP - Return true if the specified function should have a dedicated frame
476/// pointer register.  This is true if the function has variable sized allocas
477/// or if frame pointer elimination is disabled.
478///
479bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
480  const MachineFrameInfo *MFI = MF.getFrameInfo();
481  return (NoFramePointerElim ||
482          needsStackRealignment(MF) ||
483          MFI->hasVarSizedObjects() ||
484          MFI->isFrameAddressTaken());
485}
486
487bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
488  const MachineFrameInfo *MFI = MF.getFrameInfo();
489  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
490  return (RealignStack &&
491          !AFI->isThumb1OnlyFunction() &&
492          !MFI->hasVarSizedObjects());
493}
494
495bool ARMBaseRegisterInfo::
496needsStackRealignment(const MachineFunction &MF) const {
497  const MachineFrameInfo *MFI = MF.getFrameInfo();
498  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
499  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
500  return (RealignStack &&
501          !AFI->isThumb1OnlyFunction() &&
502          (MFI->getMaxAlignment() > StackAlign) &&
503          !MFI->hasVarSizedObjects());
504}
505
506bool ARMBaseRegisterInfo::
507cannotEliminateFrame(const MachineFunction &MF) const {
508  const MachineFrameInfo *MFI = MF.getFrameInfo();
509  if (NoFramePointerElim && MFI->hasCalls())
510    return true;
511  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
512    || needsStackRealignment(MF);
513}
514
515/// estimateStackSize - Estimate and return the size of the frame.
516static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
517  const MachineFrameInfo *FFI = MF.getFrameInfo();
518  int Offset = 0;
519  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
520    int FixedOff = -FFI->getObjectOffset(i);
521    if (FixedOff > Offset) Offset = FixedOff;
522  }
523  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
524    if (FFI->isDeadObjectIndex(i))
525      continue;
526    Offset += FFI->getObjectSize(i);
527    unsigned Align = FFI->getObjectAlignment(i);
528    // Adjust to alignment boundary
529    Offset = (Offset+Align-1)/Align*Align;
530  }
531  return (unsigned)Offset;
532}
533
534/// estimateRSStackSizeLimit - Look at each instruction that references stack
535/// frames and return the stack size limit beyond which some of these
536/// instructions will require a scratch register during their expansion later.
537unsigned
538ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
539  unsigned Limit = (1 << 12) - 1;
540  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
541    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
542         I != E; ++I) {
543      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
544        if (!I->getOperand(i).isFI()) continue;
545
546        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
547        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
548        if (AddrMode == ARMII::AddrMode3 ||
549            AddrMode == ARMII::AddrModeT2_i8)
550          return (1 << 8) - 1;
551
552        if (AddrMode == ARMII::AddrMode5 ||
553            AddrMode == ARMII::AddrModeT2_i8s4)
554          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
555
556        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
557          // When the stack offset is negative, we will end up using
558          // the i8 instructions instead.
559          return (1 << 8) - 1;
560
561        if (AddrMode == ARMII::AddrMode6)
562          return 0;
563        break; // At most one FI per instruction
564      }
565    }
566  }
567
568  return Limit;
569}
570
571void
572ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
573                                                       RegScavenger *RS) const {
574  // This tells PEI to spill the FP as if it is any other callee-save register
575  // to take advantage the eliminateFrameIndex machinery. This also ensures it
576  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
577  // to combine multiple loads / stores.
578  bool CanEliminateFrame = true;
579  bool CS1Spilled = false;
580  bool LRSpilled = false;
581  unsigned NumGPRSpills = 0;
582  SmallVector<unsigned, 4> UnspilledCS1GPRs;
583  SmallVector<unsigned, 4> UnspilledCS2GPRs;
584  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
585
586
587  // Calculate and set max stack object alignment early, so we can decide
588  // whether we will need stack realignment (and thus FP).
589  if (RealignStack) {
590    MachineFrameInfo *MFI = MF.getFrameInfo();
591    MFI->calculateMaxStackAlignment();
592  }
593
594  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
595  // scratch register.
596  // FIXME: It will be better just to find spare register here.
597  if (needsStackRealignment(MF) &&
598      AFI->isThumb2Function())
599    MF.getRegInfo().setPhysRegUsed(ARM::R4);
600
601  // Don't spill FP if the frame can be eliminated. This is determined
602  // by scanning the callee-save registers to see if any is used.
603  const unsigned *CSRegs = getCalleeSavedRegs();
604  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
605  for (unsigned i = 0; CSRegs[i]; ++i) {
606    unsigned Reg = CSRegs[i];
607    bool Spilled = false;
608    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
609      AFI->setCSRegisterIsSpilled(Reg);
610      Spilled = true;
611      CanEliminateFrame = false;
612    } else {
613      // Check alias registers too.
614      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
615        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
616          Spilled = true;
617          CanEliminateFrame = false;
618        }
619      }
620    }
621
622    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
623        CSRegClasses[i] == ARM::tGPRRegisterClass) {
624      if (Spilled) {
625        NumGPRSpills++;
626
627        if (!STI.isTargetDarwin()) {
628          if (Reg == ARM::LR)
629            LRSpilled = true;
630          CS1Spilled = true;
631          continue;
632        }
633
634        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
635        switch (Reg) {
636        case ARM::LR:
637          LRSpilled = true;
638          // Fallthrough
639        case ARM::R4:
640        case ARM::R5:
641        case ARM::R6:
642        case ARM::R7:
643          CS1Spilled = true;
644          break;
645        default:
646          break;
647        }
648      } else {
649        if (!STI.isTargetDarwin()) {
650          UnspilledCS1GPRs.push_back(Reg);
651          continue;
652        }
653
654        switch (Reg) {
655        case ARM::R4:
656        case ARM::R5:
657        case ARM::R6:
658        case ARM::R7:
659        case ARM::LR:
660          UnspilledCS1GPRs.push_back(Reg);
661          break;
662        default:
663          UnspilledCS2GPRs.push_back(Reg);
664          break;
665        }
666      }
667    }
668  }
669
670  bool ForceLRSpill = false;
671  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
672    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
673    // Force LR to be spilled if the Thumb function size is > 2048. This enables
674    // use of BL to implement far jump. If it turns out that it's not needed
675    // then the branch fix up path will undo it.
676    if (FnSize >= (1 << 11)) {
677      CanEliminateFrame = false;
678      ForceLRSpill = true;
679    }
680  }
681
682  bool ExtraCSSpill = false;
683  if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
684    AFI->setHasStackFrame(true);
685
686    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
687    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
688    if (!LRSpilled && CS1Spilled) {
689      MF.getRegInfo().setPhysRegUsed(ARM::LR);
690      AFI->setCSRegisterIsSpilled(ARM::LR);
691      NumGPRSpills++;
692      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
693                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
694      ForceLRSpill = false;
695      ExtraCSSpill = true;
696    }
697
698    // Darwin ABI requires FP to point to the stack slot that contains the
699    // previous FP.
700    if (STI.isTargetDarwin() || hasFP(MF)) {
701      MF.getRegInfo().setPhysRegUsed(FramePtr);
702      NumGPRSpills++;
703    }
704
705    // If stack and double are 8-byte aligned and we are spilling an odd number
706    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
707    // the integer and double callee save areas.
708    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
709    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
710      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
711        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
712          unsigned Reg = UnspilledCS1GPRs[i];
713          // Don't spill high register if the function is thumb1
714          if (!AFI->isThumb1OnlyFunction() ||
715              isARMLowRegister(Reg) || Reg == ARM::LR) {
716            MF.getRegInfo().setPhysRegUsed(Reg);
717            AFI->setCSRegisterIsSpilled(Reg);
718            if (!isReservedReg(MF, Reg))
719              ExtraCSSpill = true;
720            break;
721          }
722        }
723      } else if (!UnspilledCS2GPRs.empty() &&
724                 !AFI->isThumb1OnlyFunction()) {
725        unsigned Reg = UnspilledCS2GPRs.front();
726        MF.getRegInfo().setPhysRegUsed(Reg);
727        AFI->setCSRegisterIsSpilled(Reg);
728        if (!isReservedReg(MF, Reg))
729          ExtraCSSpill = true;
730      }
731    }
732
733    // Estimate if we might need to scavenge a register at some point in order
734    // to materialize a stack offset. If so, either spill one additional
735    // callee-saved register or reserve a special spill slot to facilitate
736    // register scavenging. Thumb1 needs a spill slot for stack pointer
737    // adjustments also, even when the frame itself is small.
738    if (RS && !ExtraCSSpill) {
739      MachineFrameInfo  *MFI = MF.getFrameInfo();
740      // If any of the stack slot references may be out of range of an
741      // immediate offset, make sure a register (or a spill slot) is
742      // available for the register scavenger. Note that if we're indexing
743      // off the frame pointer, the effective stack size is 4 bytes larger
744      // since the FP points to the stack slot of the previous FP.
745      if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
746          >= estimateRSStackSizeLimit(MF)) {
747        // If any non-reserved CS register isn't spilled, just spill one or two
748        // extra. That should take care of it!
749        unsigned NumExtras = TargetAlign / 4;
750        SmallVector<unsigned, 2> Extras;
751        while (NumExtras && !UnspilledCS1GPRs.empty()) {
752          unsigned Reg = UnspilledCS1GPRs.back();
753          UnspilledCS1GPRs.pop_back();
754          if (!isReservedReg(MF, Reg)) {
755            Extras.push_back(Reg);
756            NumExtras--;
757          }
758        }
759        // For non-Thumb1 functions, also check for hi-reg CS registers
760        if (!AFI->isThumb1OnlyFunction()) {
761          while (NumExtras && !UnspilledCS2GPRs.empty()) {
762            unsigned Reg = UnspilledCS2GPRs.back();
763            UnspilledCS2GPRs.pop_back();
764            if (!isReservedReg(MF, Reg)) {
765              Extras.push_back(Reg);
766              NumExtras--;
767            }
768          }
769        }
770        if (Extras.size() && NumExtras == 0) {
771          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
772            MF.getRegInfo().setPhysRegUsed(Extras[i]);
773            AFI->setCSRegisterIsSpilled(Extras[i]);
774          }
775        } else if (!AFI->isThumb1OnlyFunction()) {
776          // note: Thumb1 functions spill to R12, not the stack.
777          // Reserve a slot closest to SP or frame pointer.
778          const TargetRegisterClass *RC = ARM::GPRRegisterClass;
779          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
780                                                             RC->getAlignment(),
781                                                             false));
782        }
783      }
784    }
785  }
786
787  if (ForceLRSpill) {
788    MF.getRegInfo().setPhysRegUsed(ARM::LR);
789    AFI->setCSRegisterIsSpilled(ARM::LR);
790    AFI->setLRIsSpilledForFarJump(true);
791  }
792}
793
794unsigned ARMBaseRegisterInfo::getRARegister() const {
795  return ARM::LR;
796}
797
798unsigned
799ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
800  if (STI.isTargetDarwin() || hasFP(MF))
801    return FramePtr;
802  return ARM::SP;
803}
804
805int
806ARMBaseRegisterInfo::getFrameIndexReference(MachineFunction &MF, int FI,
807                                            unsigned &FrameReg) const {
808  const MachineFrameInfo *MFI = MF.getFrameInfo();
809  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
810  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
811  bool isFixed = MFI->isFixedObjectIndex(FI);
812
813  FrameReg = ARM::SP;
814  if (AFI->isGPRCalleeSavedArea1Frame(FI))
815    Offset -= AFI->getGPRCalleeSavedArea1Offset();
816  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
817    Offset -= AFI->getGPRCalleeSavedArea2Offset();
818  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
819    Offset -= AFI->getDPRCalleeSavedAreaOffset();
820  else if (needsStackRealignment(MF)) {
821    // When dynamically realigning the stack, use the frame pointer for
822    // parameters, and the stack pointer for locals.
823    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
824    if (isFixed) {
825      FrameReg = getFrameRegister(MF);
826      Offset -= AFI->getFramePtrSpillOffset();
827    }
828  } else if (hasFP(MF) && AFI->hasStackFrame()) {
829    if (isFixed || MFI->hasVarSizedObjects()) {
830      // Use frame pointer to reference fixed objects unless this is a
831      // frameless function.
832      FrameReg = getFrameRegister(MF);
833      Offset -= AFI->getFramePtrSpillOffset();
834    } else if (AFI->isThumb2Function()) {
835      // In Thumb2 mode, the negative offset is very limited.
836      int FPOffset = Offset - AFI->getFramePtrSpillOffset();
837      if (FPOffset >= -255 && FPOffset < 0) {
838        FrameReg = getFrameRegister(MF);
839        Offset = FPOffset;
840      }
841    }
842  }
843  return Offset;
844}
845
846
847int
848ARMBaseRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
849  unsigned FrameReg;
850  return getFrameIndexReference(MF, FI, FrameReg);
851}
852
853unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
854  llvm_unreachable("What is the exception register");
855  return 0;
856}
857
858unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
859  llvm_unreachable("What is the exception handler register");
860  return 0;
861}
862
863int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
864  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
865}
866
867unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
868                                              const MachineFunction &MF) const {
869  switch (Reg) {
870  default: break;
871  // Return 0 if either register of the pair is a special register.
872  // So no R12, etc.
873  case ARM::R1:
874    return ARM::R0;
875  case ARM::R3:
876    return ARM::R2;
877  case ARM::R5:
878    return ARM::R4;
879  case ARM::R7:
880    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
881  case ARM::R9:
882    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
883  case ARM::R11:
884    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
885
886  case ARM::S1:
887    return ARM::S0;
888  case ARM::S3:
889    return ARM::S2;
890  case ARM::S5:
891    return ARM::S4;
892  case ARM::S7:
893    return ARM::S6;
894  case ARM::S9:
895    return ARM::S8;
896  case ARM::S11:
897    return ARM::S10;
898  case ARM::S13:
899    return ARM::S12;
900  case ARM::S15:
901    return ARM::S14;
902  case ARM::S17:
903    return ARM::S16;
904  case ARM::S19:
905    return ARM::S18;
906  case ARM::S21:
907    return ARM::S20;
908  case ARM::S23:
909    return ARM::S22;
910  case ARM::S25:
911    return ARM::S24;
912  case ARM::S27:
913    return ARM::S26;
914  case ARM::S29:
915    return ARM::S28;
916  case ARM::S31:
917    return ARM::S30;
918
919  case ARM::D1:
920    return ARM::D0;
921  case ARM::D3:
922    return ARM::D2;
923  case ARM::D5:
924    return ARM::D4;
925  case ARM::D7:
926    return ARM::D6;
927  case ARM::D9:
928    return ARM::D8;
929  case ARM::D11:
930    return ARM::D10;
931  case ARM::D13:
932    return ARM::D12;
933  case ARM::D15:
934    return ARM::D14;
935  case ARM::D17:
936    return ARM::D16;
937  case ARM::D19:
938    return ARM::D18;
939  case ARM::D21:
940    return ARM::D20;
941  case ARM::D23:
942    return ARM::D22;
943  case ARM::D25:
944    return ARM::D24;
945  case ARM::D27:
946    return ARM::D26;
947  case ARM::D29:
948    return ARM::D28;
949  case ARM::D31:
950    return ARM::D30;
951  }
952
953  return 0;
954}
955
956unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
957                                             const MachineFunction &MF) const {
958  switch (Reg) {
959  default: break;
960  // Return 0 if either register of the pair is a special register.
961  // So no R12, etc.
962  case ARM::R0:
963    return ARM::R1;
964  case ARM::R2:
965    return ARM::R3;
966  case ARM::R4:
967    return ARM::R5;
968  case ARM::R6:
969    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
970  case ARM::R8:
971    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
972  case ARM::R10:
973    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
974
975  case ARM::S0:
976    return ARM::S1;
977  case ARM::S2:
978    return ARM::S3;
979  case ARM::S4:
980    return ARM::S5;
981  case ARM::S6:
982    return ARM::S7;
983  case ARM::S8:
984    return ARM::S9;
985  case ARM::S10:
986    return ARM::S11;
987  case ARM::S12:
988    return ARM::S13;
989  case ARM::S14:
990    return ARM::S15;
991  case ARM::S16:
992    return ARM::S17;
993  case ARM::S18:
994    return ARM::S19;
995  case ARM::S20:
996    return ARM::S21;
997  case ARM::S22:
998    return ARM::S23;
999  case ARM::S24:
1000    return ARM::S25;
1001  case ARM::S26:
1002    return ARM::S27;
1003  case ARM::S28:
1004    return ARM::S29;
1005  case ARM::S30:
1006    return ARM::S31;
1007
1008  case ARM::D0:
1009    return ARM::D1;
1010  case ARM::D2:
1011    return ARM::D3;
1012  case ARM::D4:
1013    return ARM::D5;
1014  case ARM::D6:
1015    return ARM::D7;
1016  case ARM::D8:
1017    return ARM::D9;
1018  case ARM::D10:
1019    return ARM::D11;
1020  case ARM::D12:
1021    return ARM::D13;
1022  case ARM::D14:
1023    return ARM::D15;
1024  case ARM::D16:
1025    return ARM::D17;
1026  case ARM::D18:
1027    return ARM::D19;
1028  case ARM::D20:
1029    return ARM::D21;
1030  case ARM::D22:
1031    return ARM::D23;
1032  case ARM::D24:
1033    return ARM::D25;
1034  case ARM::D26:
1035    return ARM::D27;
1036  case ARM::D28:
1037    return ARM::D29;
1038  case ARM::D30:
1039    return ARM::D31;
1040  }
1041
1042  return 0;
1043}
1044
1045/// emitLoadConstPool - Emits a load from constpool to materialize the
1046/// specified immediate.
1047void ARMBaseRegisterInfo::
1048emitLoadConstPool(MachineBasicBlock &MBB,
1049                  MachineBasicBlock::iterator &MBBI,
1050                  DebugLoc dl,
1051                  unsigned DestReg, unsigned SubIdx, int Val,
1052                  ARMCC::CondCodes Pred,
1053                  unsigned PredReg) const {
1054  MachineFunction &MF = *MBB.getParent();
1055  MachineConstantPool *ConstantPool = MF.getConstantPool();
1056  Constant *C =
1057        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1058  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1059
1060  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1061    .addReg(DestReg, getDefRegState(true), SubIdx)
1062    .addConstantPoolIndex(Idx)
1063    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1064}
1065
1066bool ARMBaseRegisterInfo::
1067requiresRegisterScavenging(const MachineFunction &MF) const {
1068  return true;
1069}
1070
1071bool ARMBaseRegisterInfo::
1072requiresFrameIndexScavenging(const MachineFunction &MF) const {
1073  return true;
1074}
1075
1076// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1077// not required, we reserve argument space for call sites in the function
1078// immediately on entry to the current function. This eliminates the need for
1079// add/sub sp brackets around call sites. Returns true if the call frame is
1080// included as part of the stack frame.
1081bool ARMBaseRegisterInfo::
1082hasReservedCallFrame(MachineFunction &MF) const {
1083  const MachineFrameInfo *FFI = MF.getFrameInfo();
1084  unsigned CFSize = FFI->getMaxCallFrameSize();
1085  // It's not always a good idea to include the call frame as part of the
1086  // stack frame. ARM (especially Thumb) has small immediate offset to
1087  // address the stack frame. So a large call frame can cause poor codegen
1088  // and may even makes it impossible to scavenge a register.
1089  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1090    return false;
1091
1092  return !MF.getFrameInfo()->hasVarSizedObjects();
1093}
1094
1095static void
1096emitSPUpdate(bool isARM,
1097             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1098             DebugLoc dl, const ARMBaseInstrInfo &TII,
1099             int NumBytes,
1100             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1101  if (isARM)
1102    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1103                            Pred, PredReg, TII);
1104  else
1105    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1106                           Pred, PredReg, TII);
1107}
1108
1109
1110void ARMBaseRegisterInfo::
1111eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1112                              MachineBasicBlock::iterator I) const {
1113  if (!hasReservedCallFrame(MF)) {
1114    // If we have alloca, convert as follows:
1115    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1116    // ADJCALLSTACKUP   -> add, sp, sp, amount
1117    MachineInstr *Old = I;
1118    DebugLoc dl = Old->getDebugLoc();
1119    unsigned Amount = Old->getOperand(0).getImm();
1120    if (Amount != 0) {
1121      // We need to keep the stack aligned properly.  To do this, we round the
1122      // amount of space needed for the outgoing arguments up to the next
1123      // alignment boundary.
1124      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1125      Amount = (Amount+Align-1)/Align*Align;
1126
1127      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1128      assert(!AFI->isThumb1OnlyFunction() &&
1129             "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1130      bool isARM = !AFI->isThumbFunction();
1131
1132      // Replace the pseudo instruction with a new instruction...
1133      unsigned Opc = Old->getOpcode();
1134      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1135      // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1136      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1137        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1138        unsigned PredReg = Old->getOperand(2).getReg();
1139        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1140      } else {
1141        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1142        unsigned PredReg = Old->getOperand(3).getReg();
1143        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1144        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1145      }
1146    }
1147  }
1148  MBB.erase(I);
1149}
1150
1151unsigned
1152ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1153                                         int SPAdj, int *Value,
1154                                         RegScavenger *RS) const {
1155  unsigned i = 0;
1156  MachineInstr &MI = *II;
1157  MachineBasicBlock &MBB = *MI.getParent();
1158  MachineFunction &MF = *MBB.getParent();
1159  const MachineFrameInfo *MFI = MF.getFrameInfo();
1160  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1161  assert(!AFI->isThumb1OnlyFunction() &&
1162         "This eliminateFrameIndex does not support Thumb1!");
1163
1164  while (!MI.getOperand(i).isFI()) {
1165    ++i;
1166    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1167  }
1168
1169  int FrameIndex = MI.getOperand(i).getIndex();
1170  int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1171  unsigned FrameReg;
1172
1173  Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1174  if (FrameReg != ARM::SP)
1175    SPAdj = 0;
1176
1177  // Modify MI as necessary to handle as much of 'Offset' as possible
1178  bool Done = false;
1179  if (!AFI->isThumbFunction())
1180    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1181  else {
1182    assert(AFI->isThumb2Function());
1183    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1184  }
1185  if (Done)
1186    return 0;
1187
1188  // If we get here, the immediate doesn't fit into the instruction.  We folded
1189  // as much as possible above, handle the rest, providing a register that is
1190  // SP+LargeImm.
1191  assert((Offset ||
1192          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1193          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1194         "This code isn't needed if offset already handled!");
1195
1196  unsigned ScratchReg = 0;
1197  int PIdx = MI.findFirstPredOperandIdx();
1198  ARMCC::CondCodes Pred = (PIdx == -1)
1199    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1200  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1201  if (Offset == 0)
1202    // Must be addrmode4/6.
1203    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1204  else {
1205    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1206    if (Value) *Value = Offset;
1207    if (!AFI->isThumbFunction())
1208      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1209                              Offset, Pred, PredReg, TII);
1210    else {
1211      assert(AFI->isThumb2Function());
1212      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1213                             Offset, Pred, PredReg, TII);
1214    }
1215    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1216    if (!ReuseFrameIndexVals)
1217      ScratchReg = 0;
1218  }
1219  return ScratchReg;
1220}
1221
1222/// Move iterator past the next bunch of callee save load / store ops for
1223/// the particular spill area (1: integer area 1, 2: integer area 2,
1224/// 3: fp area, 0: don't care).
1225static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1226                                   MachineBasicBlock::iterator &MBBI,
1227                                   int Opc1, int Opc2, unsigned Area,
1228                                   const ARMSubtarget &STI) {
1229  while (MBBI != MBB.end() &&
1230         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1231         MBBI->getOperand(1).isFI()) {
1232    if (Area != 0) {
1233      bool Done = false;
1234      unsigned Category = 0;
1235      switch (MBBI->getOperand(0).getReg()) {
1236      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1237      case ARM::LR:
1238        Category = 1;
1239        break;
1240      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1241        Category = STI.isTargetDarwin() ? 2 : 1;
1242        break;
1243      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1244      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1245        Category = 3;
1246        break;
1247      default:
1248        Done = true;
1249        break;
1250      }
1251      if (Done || Category != Area)
1252        break;
1253    }
1254
1255    ++MBBI;
1256  }
1257}
1258
1259void ARMBaseRegisterInfo::
1260emitPrologue(MachineFunction &MF) const {
1261  MachineBasicBlock &MBB = MF.front();
1262  MachineBasicBlock::iterator MBBI = MBB.begin();
1263  MachineFrameInfo  *MFI = MF.getFrameInfo();
1264  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1265  assert(!AFI->isThumb1OnlyFunction() &&
1266         "This emitPrologue does not suppor Thumb1!");
1267  bool isARM = !AFI->isThumbFunction();
1268  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1269  unsigned NumBytes = MFI->getStackSize();
1270  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1271  DebugLoc dl = (MBBI != MBB.end() ?
1272                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1273
1274  // Determine the sizes of each callee-save spill areas and record which frame
1275  // belongs to which callee-save spill areas.
1276  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1277  int FramePtrSpillFI = 0;
1278
1279  // Allocate the vararg register save area. This is not counted in NumBytes.
1280  if (VARegSaveSize)
1281    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1282
1283  if (!AFI->hasStackFrame()) {
1284    if (NumBytes != 0)
1285      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1286    return;
1287  }
1288
1289  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1290    unsigned Reg = CSI[i].getReg();
1291    int FI = CSI[i].getFrameIdx();
1292    switch (Reg) {
1293    case ARM::R4:
1294    case ARM::R5:
1295    case ARM::R6:
1296    case ARM::R7:
1297    case ARM::LR:
1298      if (Reg == FramePtr)
1299        FramePtrSpillFI = FI;
1300      AFI->addGPRCalleeSavedArea1Frame(FI);
1301      GPRCS1Size += 4;
1302      break;
1303    case ARM::R8:
1304    case ARM::R9:
1305    case ARM::R10:
1306    case ARM::R11:
1307      if (Reg == FramePtr)
1308        FramePtrSpillFI = FI;
1309      if (STI.isTargetDarwin()) {
1310        AFI->addGPRCalleeSavedArea2Frame(FI);
1311        GPRCS2Size += 4;
1312      } else {
1313        AFI->addGPRCalleeSavedArea1Frame(FI);
1314        GPRCS1Size += 4;
1315      }
1316      break;
1317    default:
1318      AFI->addDPRCalleeSavedAreaFrame(FI);
1319      DPRCSSize += 8;
1320    }
1321  }
1322
1323  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1324  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1325  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1326
1327  // Set FP to point to the stack slot that contains the previous FP.
1328  // For Darwin, FP is R7, which has now been stored in spill area 1.
1329  // Otherwise, if this is not Darwin, all the callee-saved registers go
1330  // into spill area 1, including the FP in R11.  In either case, it is
1331  // now safe to emit this assignment.
1332  if (STI.isTargetDarwin() || hasFP(MF)) {
1333    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1334    MachineInstrBuilder MIB =
1335      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1336      .addFrameIndex(FramePtrSpillFI).addImm(0);
1337    AddDefaultCC(AddDefaultPred(MIB));
1338  }
1339
1340  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1341  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1342
1343  // Build the new SUBri to adjust SP for FP callee-save spill area.
1344  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1345  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1346
1347  // Determine starting offsets of spill areas.
1348  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1349  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1350  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1351  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1352  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1353  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1354  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1355
1356  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1357  NumBytes = DPRCSOffset;
1358  if (NumBytes) {
1359    // Adjust SP after all the callee-save spills.
1360    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1361  }
1362
1363  if (STI.isTargetELF() && hasFP(MF)) {
1364    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1365                             AFI->getFramePtrSpillOffset());
1366  }
1367
1368  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1369  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1370  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1371
1372  // If we need dynamic stack realignment, do it here.
1373  if (needsStackRealignment(MF)) {
1374    unsigned MaxAlign = MFI->getMaxAlignment();
1375    assert (!AFI->isThumb1OnlyFunction());
1376    if (!AFI->isThumbFunction()) {
1377      // Emit bic sp, sp, MaxAlign
1378      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1379                                          TII.get(ARM::BICri), ARM::SP)
1380                                  .addReg(ARM::SP, RegState::Kill)
1381                                  .addImm(MaxAlign-1)));
1382    } else {
1383      // We cannot use sp as source/dest register here, thus we're emitting the
1384      // following sequence:
1385      // mov r4, sp
1386      // bic r4, r4, MaxAlign
1387      // mov sp, r4
1388      // FIXME: It will be better just to find spare register here.
1389      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1390        .addReg(ARM::SP, RegState::Kill);
1391      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1392                                          TII.get(ARM::t2BICri), ARM::R4)
1393                                  .addReg(ARM::R4, RegState::Kill)
1394                                  .addImm(MaxAlign-1)));
1395      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1396        .addReg(ARM::R4, RegState::Kill);
1397    }
1398  }
1399}
1400
1401static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1402  for (unsigned i = 0; CSRegs[i]; ++i)
1403    if (Reg == CSRegs[i])
1404      return true;
1405  return false;
1406}
1407
1408static bool isCSRestore(MachineInstr *MI,
1409                        const ARMBaseInstrInfo &TII,
1410                        const unsigned *CSRegs) {
1411  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1412           MI->getOpcode() == (int)ARM::LDR ||
1413           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1414          MI->getOperand(1).isFI() &&
1415          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1416}
1417
1418void ARMBaseRegisterInfo::
1419emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1420  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1421  assert(MBBI->getDesc().isReturn() &&
1422         "Can only insert epilog into returning blocks");
1423  DebugLoc dl = MBBI->getDebugLoc();
1424  MachineFrameInfo *MFI = MF.getFrameInfo();
1425  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1426  assert(!AFI->isThumb1OnlyFunction() &&
1427         "This emitEpilogue does not suppor Thumb1!");
1428  bool isARM = !AFI->isThumbFunction();
1429
1430  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1431  int NumBytes = (int)MFI->getStackSize();
1432
1433  if (!AFI->hasStackFrame()) {
1434    if (NumBytes != 0)
1435      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1436  } else {
1437    // Unwind MBBI to point to first LDR / VLDRD.
1438    const unsigned *CSRegs = getCalleeSavedRegs();
1439    if (MBBI != MBB.begin()) {
1440      do
1441        --MBBI;
1442      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1443      if (!isCSRestore(MBBI, TII, CSRegs))
1444        ++MBBI;
1445    }
1446
1447    // Move SP to start of FP callee save spill area.
1448    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1449                 AFI->getGPRCalleeSavedArea2Size() +
1450                 AFI->getDPRCalleeSavedAreaSize());
1451
1452    // Darwin ABI requires FP to point to the stack slot that contains the
1453    // previous FP.
1454    bool HasFP = hasFP(MF);
1455    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1456      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1457      // Reset SP based on frame pointer only if the stack frame extends beyond
1458      // frame pointer stack slot or target is ELF and the function has FP.
1459      if (HasFP ||
1460          AFI->getGPRCalleeSavedArea2Size() ||
1461          AFI->getDPRCalleeSavedAreaSize()  ||
1462          AFI->getDPRCalleeSavedAreaOffset()) {
1463        if (NumBytes) {
1464          if (isARM)
1465            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1466                                    ARMCC::AL, 0, TII);
1467          else
1468            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1469                                    ARMCC::AL, 0, TII);
1470        } else {
1471          // Thumb2 or ARM.
1472          if (isARM)
1473            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1474              .addReg(FramePtr)
1475              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1476          else
1477            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1478              .addReg(FramePtr);
1479        }
1480      }
1481    } else if (NumBytes)
1482      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1483
1484    // Move SP to start of integer callee save spill area 2.
1485    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1486    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1487
1488    // Move SP to start of integer callee save spill area 1.
1489    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1490    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1491
1492    // Move SP to SP upon entry to the function.
1493    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1494    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1495  }
1496
1497  if (VARegSaveSize)
1498    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1499}
1500
1501#include "ARMGenRegisterInfo.inc"
1502