ARMBaseRegisterInfo.cpp revision 201360 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41using namespace llvm;
42
43static cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46
47unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
48                                                   bool *isSPVFP) {
49  if (isSPVFP)
50    *isSPVFP = false;
51
52  using namespace ARM;
53  switch (RegEnum) {
54  default:
55    llvm_unreachable("Unknown ARM register!");
56  case R0:  case D0:  case Q0:  return 0;
57  case R1:  case D1:  case Q1:  return 1;
58  case R2:  case D2:  case Q2:  return 2;
59  case R3:  case D3:  case Q3:  return 3;
60  case R4:  case D4:  case Q4:  return 4;
61  case R5:  case D5:  case Q5:  return 5;
62  case R6:  case D6:  case Q6:  return 6;
63  case R7:  case D7:  case Q7:  return 7;
64  case R8:  case D8:  case Q8:  return 8;
65  case R9:  case D9:  case Q9:  return 9;
66  case R10: case D10: case Q10: return 10;
67  case R11: case D11: case Q11: return 11;
68  case R12: case D12: case Q12: return 12;
69  case SP:  case D13: case Q13: return 13;
70  case LR:  case D14: case Q14: return 14;
71  case PC:  case D15: case Q15: return 15;
72
73  case D16: return 16;
74  case D17: return 17;
75  case D18: return 18;
76  case D19: return 19;
77  case D20: return 20;
78  case D21: return 21;
79  case D22: return 22;
80  case D23: return 23;
81  case D24: return 24;
82  case D25: return 25;
83  case D26: return 27;
84  case D27: return 27;
85  case D28: return 28;
86  case D29: return 29;
87  case D30: return 30;
88  case D31: return 31;
89
90  case S0: case S1: case S2: case S3:
91  case S4: case S5: case S6: case S7:
92  case S8: case S9: case S10: case S11:
93  case S12: case S13: case S14: case S15:
94  case S16: case S17: case S18: case S19:
95  case S20: case S21: case S22: case S23:
96  case S24: case S25: case S26: case S27:
97  case S28: case S29: case S30: case S31: {
98    if (isSPVFP)
99      *isSPVFP = true;
100    switch (RegEnum) {
101    default: return 0; // Avoid compile time warning.
102    case S0: return 0;
103    case S1: return 1;
104    case S2: return 2;
105    case S3: return 3;
106    case S4: return 4;
107    case S5: return 5;
108    case S6: return 6;
109    case S7: return 7;
110    case S8: return 8;
111    case S9: return 9;
112    case S10: return 10;
113    case S11: return 11;
114    case S12: return 12;
115    case S13: return 13;
116    case S14: return 14;
117    case S15: return 15;
118    case S16: return 16;
119    case S17: return 17;
120    case S18: return 18;
121    case S19: return 19;
122    case S20: return 20;
123    case S21: return 21;
124    case S22: return 22;
125    case S23: return 23;
126    case S24: return 24;
127    case S25: return 25;
128    case S26: return 26;
129    case S27: return 27;
130    case S28: return 28;
131    case S29: return 29;
132    case S30: return 30;
133    case S31: return 31;
134    }
135  }
136  }
137}
138
139ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
140                                         const ARMSubtarget &sti)
141  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
142    TII(tii), STI(sti),
143    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
144}
145
146const unsigned*
147ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
148  static const unsigned CalleeSavedRegs[] = {
149    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
150    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
151
152    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
153    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
154    0
155  };
156
157  static const unsigned DarwinCalleeSavedRegs[] = {
158    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
159    // register.
160    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
161    ARM::R11, ARM::R10, ARM::R8,
162
163    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
164    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
165    0
166  };
167  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
168}
169
170const TargetRegisterClass* const *
171ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
172  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
173    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
174    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
175    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
176
177    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
178    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
179    0
180  };
181
182  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
183    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
184    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
185    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
186
187    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
188    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
189    0
190  };
191
192  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
193    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
194    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
195    &ARM::GPRRegClass, &ARM::GPRRegClass,
196
197    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
198    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
199    0
200  };
201
202  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
203    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
204    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
205    &ARM::GPRRegClass,  &ARM::GPRRegClass,
206
207    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
208    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
209    0
210  };
211
212  if (STI.isThumb1Only()) {
213    return STI.isTargetDarwin()
214      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
215  }
216  return STI.isTargetDarwin()
217    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
218}
219
220BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
221  // FIXME: avoid re-calculating this everytime.
222  BitVector Reserved(getNumRegs());
223  Reserved.set(ARM::SP);
224  Reserved.set(ARM::PC);
225  if (STI.isTargetDarwin() || hasFP(MF))
226    Reserved.set(FramePtr);
227  // Some targets reserve R9.
228  if (STI.isR9Reserved())
229    Reserved.set(ARM::R9);
230  return Reserved;
231}
232
233bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
234                                        unsigned Reg) const {
235  switch (Reg) {
236  default: break;
237  case ARM::SP:
238  case ARM::PC:
239    return true;
240  case ARM::R7:
241  case ARM::R11:
242    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
243      return true;
244    break;
245  case ARM::R9:
246    return STI.isR9Reserved();
247  }
248
249  return false;
250}
251
252const TargetRegisterClass *
253ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
254                                              const TargetRegisterClass *B,
255                                              unsigned SubIdx) const {
256  switch (SubIdx) {
257  default: return 0;
258  case 1:
259  case 2:
260  case 3:
261  case 4:
262    // S sub-registers.
263    if (A->getSize() == 8) {
264      if (B == &ARM::SPR_8RegClass)
265        return &ARM::DPR_8RegClass;
266      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
267      if (A == &ARM::DPR_8RegClass)
268        return A;
269      return &ARM::DPR_VFP2RegClass;
270    }
271
272    assert(A->getSize() == 16 && "Expecting a Q register class!");
273    if (B == &ARM::SPR_8RegClass)
274      return &ARM::QPR_8RegClass;
275    return &ARM::QPR_VFP2RegClass;
276  case 5:
277  case 6:
278    // D sub-registers.
279    if (B == &ARM::DPR_VFP2RegClass)
280      return &ARM::QPR_VFP2RegClass;
281    if (B == &ARM::DPR_8RegClass)
282      return &ARM::QPR_8RegClass;
283    return A;
284  }
285  return 0;
286}
287
288const TargetRegisterClass *
289ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
290  return ARM::GPRRegisterClass;
291}
292
293/// getAllocationOrder - Returns the register allocation order for a specified
294/// register class in the form of a pair of TargetRegisterClass iterators.
295std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
296ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
297                                        unsigned HintType, unsigned HintReg,
298                                        const MachineFunction &MF) const {
299  // Alternative register allocation orders when favoring even / odd registers
300  // of register pairs.
301
302  // No FP, R9 is available.
303  static const unsigned GPREven1[] = {
304    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
305    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
306    ARM::R9, ARM::R11
307  };
308  static const unsigned GPROdd1[] = {
309    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
310    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
311    ARM::R8, ARM::R10
312  };
313
314  // FP is R7, R9 is available.
315  static const unsigned GPREven2[] = {
316    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
317    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
318    ARM::R9, ARM::R11
319  };
320  static const unsigned GPROdd2[] = {
321    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
322    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
323    ARM::R8, ARM::R10
324  };
325
326  // FP is R11, R9 is available.
327  static const unsigned GPREven3[] = {
328    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
329    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
330    ARM::R9
331  };
332  static const unsigned GPROdd3[] = {
333    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
334    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
335    ARM::R8
336  };
337
338  // No FP, R9 is not available.
339  static const unsigned GPREven4[] = {
340    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
341    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
342    ARM::R11
343  };
344  static const unsigned GPROdd4[] = {
345    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
346    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
347    ARM::R10
348  };
349
350  // FP is R7, R9 is not available.
351  static const unsigned GPREven5[] = {
352    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
353    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
354    ARM::R11
355  };
356  static const unsigned GPROdd5[] = {
357    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
358    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
359    ARM::R10
360  };
361
362  // FP is R11, R9 is not available.
363  static const unsigned GPREven6[] = {
364    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
365    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
366  };
367  static const unsigned GPROdd6[] = {
368    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
369    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
370  };
371
372
373  if (HintType == ARMRI::RegPairEven) {
374    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
375      // It's no longer possible to fulfill this hint. Return the default
376      // allocation order.
377      return std::make_pair(RC->allocation_order_begin(MF),
378                            RC->allocation_order_end(MF));
379
380    if (!STI.isTargetDarwin() && !hasFP(MF)) {
381      if (!STI.isR9Reserved())
382        return std::make_pair(GPREven1,
383                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
384      else
385        return std::make_pair(GPREven4,
386                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
387    } else if (FramePtr == ARM::R7) {
388      if (!STI.isR9Reserved())
389        return std::make_pair(GPREven2,
390                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
391      else
392        return std::make_pair(GPREven5,
393                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
394    } else { // FramePtr == ARM::R11
395      if (!STI.isR9Reserved())
396        return std::make_pair(GPREven3,
397                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
398      else
399        return std::make_pair(GPREven6,
400                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
401    }
402  } else if (HintType == ARMRI::RegPairOdd) {
403    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
404      // It's no longer possible to fulfill this hint. Return the default
405      // allocation order.
406      return std::make_pair(RC->allocation_order_begin(MF),
407                            RC->allocation_order_end(MF));
408
409    if (!STI.isTargetDarwin() && !hasFP(MF)) {
410      if (!STI.isR9Reserved())
411        return std::make_pair(GPROdd1,
412                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
413      else
414        return std::make_pair(GPROdd4,
415                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
416    } else if (FramePtr == ARM::R7) {
417      if (!STI.isR9Reserved())
418        return std::make_pair(GPROdd2,
419                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
420      else
421        return std::make_pair(GPROdd5,
422                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
423    } else { // FramePtr == ARM::R11
424      if (!STI.isR9Reserved())
425        return std::make_pair(GPROdd3,
426                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
427      else
428        return std::make_pair(GPROdd6,
429                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
430    }
431  }
432  return std::make_pair(RC->allocation_order_begin(MF),
433                        RC->allocation_order_end(MF));
434}
435
436/// ResolveRegAllocHint - Resolves the specified register allocation hint
437/// to a physical register. Returns the physical register if it is successful.
438unsigned
439ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
440                                         const MachineFunction &MF) const {
441  if (Reg == 0 || !isPhysicalRegister(Reg))
442    return 0;
443  if (Type == 0)
444    return Reg;
445  else if (Type == (unsigned)ARMRI::RegPairOdd)
446    // Odd register.
447    return getRegisterPairOdd(Reg, MF);
448  else if (Type == (unsigned)ARMRI::RegPairEven)
449    // Even register.
450    return getRegisterPairEven(Reg, MF);
451  return 0;
452}
453
454void
455ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
456                                        MachineFunction &MF) const {
457  MachineRegisterInfo *MRI = &MF.getRegInfo();
458  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
459  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
460       Hint.first == (unsigned)ARMRI::RegPairEven) &&
461      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
462    // If 'Reg' is one of the even / odd register pair and it's now changed
463    // (e.g. coalesced) into a different register. The other register of the
464    // pair allocation hint must be updated to reflect the relationship
465    // change.
466    unsigned OtherReg = Hint.second;
467    Hint = MRI->getRegAllocationHint(OtherReg);
468    if (Hint.second == Reg)
469      // Make sure the pair has not already divorced.
470      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
471  }
472}
473
474/// hasFP - Return true if the specified function should have a dedicated frame
475/// pointer register.  This is true if the function has variable sized allocas
476/// or if frame pointer elimination is disabled.
477///
478bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
479  const MachineFrameInfo *MFI = MF.getFrameInfo();
480  return (NoFramePointerElim ||
481          needsStackRealignment(MF) ||
482          MFI->hasVarSizedObjects() ||
483          MFI->isFrameAddressTaken());
484}
485
486bool ARMBaseRegisterInfo::
487needsStackRealignment(const MachineFunction &MF) const {
488  const MachineFrameInfo *MFI = MF.getFrameInfo();
489  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
490  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
491  return (RealignStack &&
492          !AFI->isThumb1OnlyFunction() &&
493          (MFI->getMaxAlignment() > StackAlign) &&
494          !MFI->hasVarSizedObjects());
495}
496
497bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
498  const MachineFrameInfo *MFI = MF.getFrameInfo();
499  if (NoFramePointerElim && MFI->hasCalls())
500    return true;
501  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
502    || needsStackRealignment(MF);
503}
504
505/// estimateStackSize - Estimate and return the size of the frame.
506static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
507  const MachineFrameInfo *FFI = MF.getFrameInfo();
508  int Offset = 0;
509  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
510    int FixedOff = -FFI->getObjectOffset(i);
511    if (FixedOff > Offset) Offset = FixedOff;
512  }
513  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
514    if (FFI->isDeadObjectIndex(i))
515      continue;
516    Offset += FFI->getObjectSize(i);
517    unsigned Align = FFI->getObjectAlignment(i);
518    // Adjust to alignment boundary
519    Offset = (Offset+Align-1)/Align*Align;
520  }
521  return (unsigned)Offset;
522}
523
524/// estimateRSStackSizeLimit - Look at each instruction that references stack
525/// frames and return the stack size limit beyond which some of these
526/// instructions will require scratch register during their expansion later.
527unsigned
528ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
529  unsigned Limit = (1 << 12) - 1;
530  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
531    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
532         I != E; ++I) {
533      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
534        if (!I->getOperand(i).isFI()) continue;
535
536        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
537        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
538        if (AddrMode == ARMII::AddrMode3 ||
539            AddrMode == ARMII::AddrModeT2_i8)
540          return (1 << 8) - 1;
541
542        if (AddrMode == ARMII::AddrMode5 ||
543            AddrMode == ARMII::AddrModeT2_i8s4)
544          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
545
546        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
547          // When the stack offset is negative, we will end up using
548          // the i8 instructions instead.
549          return (1 << 8) - 1;
550        break; // At most one FI per instruction
551      }
552    }
553  }
554
555  return Limit;
556}
557
558void
559ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
560                                                          RegScavenger *RS) const {
561  // This tells PEI to spill the FP as if it is any other callee-save register
562  // to take advantage the eliminateFrameIndex machinery. This also ensures it
563  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
564  // to combine multiple loads / stores.
565  bool CanEliminateFrame = true;
566  bool CS1Spilled = false;
567  bool LRSpilled = false;
568  unsigned NumGPRSpills = 0;
569  SmallVector<unsigned, 4> UnspilledCS1GPRs;
570  SmallVector<unsigned, 4> UnspilledCS2GPRs;
571  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
572
573
574  // Calculate and set max stack object alignment early, so we can decide
575  // whether we will need stack realignment (and thus FP).
576  if (RealignStack) {
577    MachineFrameInfo *MFI = MF.getFrameInfo();
578    MFI->calculateMaxStackAlignment();
579  }
580
581  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
582  // scratch register.
583  // FIXME: It will be better just to find spare register here.
584  if (needsStackRealignment(MF) &&
585      AFI->isThumb2Function())
586    MF.getRegInfo().setPhysRegUsed(ARM::R4);
587
588  // Don't spill FP if the frame can be eliminated. This is determined
589  // by scanning the callee-save registers to see if any is used.
590  const unsigned *CSRegs = getCalleeSavedRegs();
591  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
592  for (unsigned i = 0; CSRegs[i]; ++i) {
593    unsigned Reg = CSRegs[i];
594    bool Spilled = false;
595    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
596      AFI->setCSRegisterIsSpilled(Reg);
597      Spilled = true;
598      CanEliminateFrame = false;
599    } else {
600      // Check alias registers too.
601      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
602        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
603          Spilled = true;
604          CanEliminateFrame = false;
605        }
606      }
607    }
608
609    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
610        CSRegClasses[i] == ARM::tGPRRegisterClass) {
611      if (Spilled) {
612        NumGPRSpills++;
613
614        if (!STI.isTargetDarwin()) {
615          if (Reg == ARM::LR)
616            LRSpilled = true;
617          CS1Spilled = true;
618          continue;
619        }
620
621        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
622        switch (Reg) {
623        case ARM::LR:
624          LRSpilled = true;
625          // Fallthrough
626        case ARM::R4:
627        case ARM::R5:
628        case ARM::R6:
629        case ARM::R7:
630          CS1Spilled = true;
631          break;
632        default:
633          break;
634        }
635      } else {
636        if (!STI.isTargetDarwin()) {
637          UnspilledCS1GPRs.push_back(Reg);
638          continue;
639        }
640
641        switch (Reg) {
642        case ARM::R4:
643        case ARM::R5:
644        case ARM::R6:
645        case ARM::R7:
646        case ARM::LR:
647          UnspilledCS1GPRs.push_back(Reg);
648          break;
649        default:
650          UnspilledCS2GPRs.push_back(Reg);
651          break;
652        }
653      }
654    }
655  }
656
657  bool ForceLRSpill = false;
658  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
659    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
660    // Force LR to be spilled if the Thumb function size is > 2048. This enables
661    // use of BL to implement far jump. If it turns out that it's not needed
662    // then the branch fix up path will undo it.
663    if (FnSize >= (1 << 11)) {
664      CanEliminateFrame = false;
665      ForceLRSpill = true;
666    }
667  }
668
669  bool ExtraCSSpill = false;
670  if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
671    AFI->setHasStackFrame(true);
672
673    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
674    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
675    if (!LRSpilled && CS1Spilled) {
676      MF.getRegInfo().setPhysRegUsed(ARM::LR);
677      AFI->setCSRegisterIsSpilled(ARM::LR);
678      NumGPRSpills++;
679      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
680                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
681      ForceLRSpill = false;
682      ExtraCSSpill = true;
683    }
684
685    // Darwin ABI requires FP to point to the stack slot that contains the
686    // previous FP.
687    if (STI.isTargetDarwin() || hasFP(MF)) {
688      MF.getRegInfo().setPhysRegUsed(FramePtr);
689      NumGPRSpills++;
690    }
691
692    // If stack and double are 8-byte aligned and we are spilling an odd number
693    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
694    // the integer and double callee save areas.
695    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
696    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
697      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
698        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
699          unsigned Reg = UnspilledCS1GPRs[i];
700          // Don't spill high register if the function is thumb1
701          if (!AFI->isThumb1OnlyFunction() ||
702              isARMLowRegister(Reg) || Reg == ARM::LR) {
703            MF.getRegInfo().setPhysRegUsed(Reg);
704            AFI->setCSRegisterIsSpilled(Reg);
705            if (!isReservedReg(MF, Reg))
706              ExtraCSSpill = true;
707            break;
708          }
709        }
710      } else if (!UnspilledCS2GPRs.empty() &&
711                 !AFI->isThumb1OnlyFunction()) {
712        unsigned Reg = UnspilledCS2GPRs.front();
713        MF.getRegInfo().setPhysRegUsed(Reg);
714        AFI->setCSRegisterIsSpilled(Reg);
715        if (!isReservedReg(MF, Reg))
716          ExtraCSSpill = true;
717      }
718    }
719
720    // Estimate if we might need to scavenge a register at some point in order
721    // to materialize a stack offset. If so, either spill one additional
722    // callee-saved register or reserve a special spill slot to facilitate
723    // register scavenging. Thumb1 needs a spill slot for stack pointer
724    // adjustments also, even when the frame itself is small.
725    if (RS && !ExtraCSSpill) {
726      MachineFrameInfo  *MFI = MF.getFrameInfo();
727      // If any of the stack slot references may be out of range of an
728      // immediate offset, make sure a register (or a spill slot) is
729      // available for the register scavenger. Note that if we're indexing
730      // off the frame pointer, the effective stack size is 4 bytes larger
731      // since the FP points to the stack slot of the previous FP.
732      if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
733          >= estimateRSStackSizeLimit(MF)) {
734        // If any non-reserved CS register isn't spilled, just spill one or two
735        // extra. That should take care of it!
736        unsigned NumExtras = TargetAlign / 4;
737        SmallVector<unsigned, 2> Extras;
738        while (NumExtras && !UnspilledCS1GPRs.empty()) {
739          unsigned Reg = UnspilledCS1GPRs.back();
740          UnspilledCS1GPRs.pop_back();
741          if (!isReservedReg(MF, Reg)) {
742            Extras.push_back(Reg);
743            NumExtras--;
744          }
745        }
746        // For non-Thumb1 functions, also check for hi-reg CS registers
747        if (!AFI->isThumb1OnlyFunction()) {
748          while (NumExtras && !UnspilledCS2GPRs.empty()) {
749            unsigned Reg = UnspilledCS2GPRs.back();
750            UnspilledCS2GPRs.pop_back();
751            if (!isReservedReg(MF, Reg)) {
752              Extras.push_back(Reg);
753              NumExtras--;
754            }
755          }
756        }
757        if (Extras.size() && NumExtras == 0) {
758          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
759            MF.getRegInfo().setPhysRegUsed(Extras[i]);
760            AFI->setCSRegisterIsSpilled(Extras[i]);
761          }
762        } else if (!AFI->isThumb1OnlyFunction()) {
763          // note: Thumb1 functions spill to R12, not the stack.
764          // Reserve a slot closest to SP or frame pointer.
765          const TargetRegisterClass *RC = ARM::GPRRegisterClass;
766          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
767                                                             RC->getAlignment(),
768                                                             false));
769        }
770      }
771    }
772  }
773
774  if (ForceLRSpill) {
775    MF.getRegInfo().setPhysRegUsed(ARM::LR);
776    AFI->setCSRegisterIsSpilled(ARM::LR);
777    AFI->setLRIsSpilledForFarJump(true);
778  }
779}
780
781unsigned ARMBaseRegisterInfo::getRARegister() const {
782  return ARM::LR;
783}
784
785unsigned
786ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
787  if (STI.isTargetDarwin() || hasFP(MF))
788    return FramePtr;
789  return ARM::SP;
790}
791
792int
793ARMBaseRegisterInfo::getFrameIndexReference(MachineFunction &MF, int FI,
794                                            unsigned &FrameReg) const {
795  const MachineFrameInfo *MFI = MF.getFrameInfo();
796  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
797  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
798  bool isFixed = MFI->isFixedObjectIndex(FI);
799
800  FrameReg = ARM::SP;
801  if (AFI->isGPRCalleeSavedArea1Frame(FI))
802    Offset -= AFI->getGPRCalleeSavedArea1Offset();
803  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
804    Offset -= AFI->getGPRCalleeSavedArea2Offset();
805  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
806    Offset -= AFI->getDPRCalleeSavedAreaOffset();
807  else if (needsStackRealignment(MF)) {
808    // When dynamically realigning the stack, use the frame pointer for
809    // parameters, and the stack pointer for locals.
810    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
811    if (isFixed) {
812      FrameReg = getFrameRegister(MF);
813      Offset -= AFI->getFramePtrSpillOffset();
814    }
815  } else if (hasFP(MF) && AFI->hasStackFrame()) {
816    if (isFixed || MFI->hasVarSizedObjects()) {
817      // Use frame pointer to reference fixed objects unless this is a
818      // frameless function.
819      FrameReg = getFrameRegister(MF);
820      Offset -= AFI->getFramePtrSpillOffset();
821    } else if (AFI->isThumb2Function()) {
822      // In Thumb2 mode, the negative offset is very limited.
823      int FPOffset = Offset - AFI->getFramePtrSpillOffset();
824      if (FPOffset >= -255 && FPOffset < 0) {
825        FrameReg = getFrameRegister(MF);
826        Offset = FPOffset;
827      }
828    }
829  }
830  return Offset;
831}
832
833
834int
835ARMBaseRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
836  unsigned FrameReg;
837  return getFrameIndexReference(MF, FI, FrameReg);
838}
839
840unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
841  llvm_unreachable("What is the exception register");
842  return 0;
843}
844
845unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
846  llvm_unreachable("What is the exception handler register");
847  return 0;
848}
849
850int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
851  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
852}
853
854unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
855                                               const MachineFunction &MF) const {
856  switch (Reg) {
857  default: break;
858  // Return 0 if either register of the pair is a special register.
859  // So no R12, etc.
860  case ARM::R1:
861    return ARM::R0;
862  case ARM::R3:
863    return ARM::R2;
864  case ARM::R5:
865    return ARM::R4;
866  case ARM::R7:
867    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
868  case ARM::R9:
869    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
870  case ARM::R11:
871    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
872
873  case ARM::S1:
874    return ARM::S0;
875  case ARM::S3:
876    return ARM::S2;
877  case ARM::S5:
878    return ARM::S4;
879  case ARM::S7:
880    return ARM::S6;
881  case ARM::S9:
882    return ARM::S8;
883  case ARM::S11:
884    return ARM::S10;
885  case ARM::S13:
886    return ARM::S12;
887  case ARM::S15:
888    return ARM::S14;
889  case ARM::S17:
890    return ARM::S16;
891  case ARM::S19:
892    return ARM::S18;
893  case ARM::S21:
894    return ARM::S20;
895  case ARM::S23:
896    return ARM::S22;
897  case ARM::S25:
898    return ARM::S24;
899  case ARM::S27:
900    return ARM::S26;
901  case ARM::S29:
902    return ARM::S28;
903  case ARM::S31:
904    return ARM::S30;
905
906  case ARM::D1:
907    return ARM::D0;
908  case ARM::D3:
909    return ARM::D2;
910  case ARM::D5:
911    return ARM::D4;
912  case ARM::D7:
913    return ARM::D6;
914  case ARM::D9:
915    return ARM::D8;
916  case ARM::D11:
917    return ARM::D10;
918  case ARM::D13:
919    return ARM::D12;
920  case ARM::D15:
921    return ARM::D14;
922  case ARM::D17:
923    return ARM::D16;
924  case ARM::D19:
925    return ARM::D18;
926  case ARM::D21:
927    return ARM::D20;
928  case ARM::D23:
929    return ARM::D22;
930  case ARM::D25:
931    return ARM::D24;
932  case ARM::D27:
933    return ARM::D26;
934  case ARM::D29:
935    return ARM::D28;
936  case ARM::D31:
937    return ARM::D30;
938  }
939
940  return 0;
941}
942
943unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
944                                             const MachineFunction &MF) const {
945  switch (Reg) {
946  default: break;
947  // Return 0 if either register of the pair is a special register.
948  // So no R12, etc.
949  case ARM::R0:
950    return ARM::R1;
951  case ARM::R2:
952    return ARM::R3;
953  case ARM::R4:
954    return ARM::R5;
955  case ARM::R6:
956    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
957  case ARM::R8:
958    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
959  case ARM::R10:
960    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
961
962  case ARM::S0:
963    return ARM::S1;
964  case ARM::S2:
965    return ARM::S3;
966  case ARM::S4:
967    return ARM::S5;
968  case ARM::S6:
969    return ARM::S7;
970  case ARM::S8:
971    return ARM::S9;
972  case ARM::S10:
973    return ARM::S11;
974  case ARM::S12:
975    return ARM::S13;
976  case ARM::S14:
977    return ARM::S15;
978  case ARM::S16:
979    return ARM::S17;
980  case ARM::S18:
981    return ARM::S19;
982  case ARM::S20:
983    return ARM::S21;
984  case ARM::S22:
985    return ARM::S23;
986  case ARM::S24:
987    return ARM::S25;
988  case ARM::S26:
989    return ARM::S27;
990  case ARM::S28:
991    return ARM::S29;
992  case ARM::S30:
993    return ARM::S31;
994
995  case ARM::D0:
996    return ARM::D1;
997  case ARM::D2:
998    return ARM::D3;
999  case ARM::D4:
1000    return ARM::D5;
1001  case ARM::D6:
1002    return ARM::D7;
1003  case ARM::D8:
1004    return ARM::D9;
1005  case ARM::D10:
1006    return ARM::D11;
1007  case ARM::D12:
1008    return ARM::D13;
1009  case ARM::D14:
1010    return ARM::D15;
1011  case ARM::D16:
1012    return ARM::D17;
1013  case ARM::D18:
1014    return ARM::D19;
1015  case ARM::D20:
1016    return ARM::D21;
1017  case ARM::D22:
1018    return ARM::D23;
1019  case ARM::D24:
1020    return ARM::D25;
1021  case ARM::D26:
1022    return ARM::D27;
1023  case ARM::D28:
1024    return ARM::D29;
1025  case ARM::D30:
1026    return ARM::D31;
1027  }
1028
1029  return 0;
1030}
1031
1032/// emitLoadConstPool - Emits a load from constpool to materialize the
1033/// specified immediate.
1034void ARMBaseRegisterInfo::
1035emitLoadConstPool(MachineBasicBlock &MBB,
1036                  MachineBasicBlock::iterator &MBBI,
1037                  DebugLoc dl,
1038                  unsigned DestReg, unsigned SubIdx, int Val,
1039                  ARMCC::CondCodes Pred,
1040                  unsigned PredReg) const {
1041  MachineFunction &MF = *MBB.getParent();
1042  MachineConstantPool *ConstantPool = MF.getConstantPool();
1043  Constant *C =
1044        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1045  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1046
1047  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1048    .addReg(DestReg, getDefRegState(true), SubIdx)
1049    .addConstantPoolIndex(Idx)
1050    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1051}
1052
1053bool ARMBaseRegisterInfo::
1054requiresRegisterScavenging(const MachineFunction &MF) const {
1055  return true;
1056}
1057
1058bool ARMBaseRegisterInfo::
1059requiresFrameIndexScavenging(const MachineFunction &MF) const {
1060  return true;
1061}
1062
1063// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1064// not required, we reserve argument space for call sites in the function
1065// immediately on entry to the current function. This eliminates the need for
1066// add/sub sp brackets around call sites. Returns true if the call frame is
1067// included as part of the stack frame.
1068bool ARMBaseRegisterInfo::
1069hasReservedCallFrame(MachineFunction &MF) const {
1070  const MachineFrameInfo *FFI = MF.getFrameInfo();
1071  unsigned CFSize = FFI->getMaxCallFrameSize();
1072  // It's not always a good idea to include the call frame as part of the
1073  // stack frame. ARM (especially Thumb) has small immediate offset to
1074  // address the stack frame. So a large call frame can cause poor codegen
1075  // and may even makes it impossible to scavenge a register.
1076  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1077    return false;
1078
1079  return !MF.getFrameInfo()->hasVarSizedObjects();
1080}
1081
1082static void
1083emitSPUpdate(bool isARM,
1084             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1085             DebugLoc dl, const ARMBaseInstrInfo &TII,
1086             int NumBytes,
1087             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1088  if (isARM)
1089    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1090                            Pred, PredReg, TII);
1091  else
1092    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1093                           Pred, PredReg, TII);
1094}
1095
1096
1097void ARMBaseRegisterInfo::
1098eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1099                              MachineBasicBlock::iterator I) const {
1100  if (!hasReservedCallFrame(MF)) {
1101    // If we have alloca, convert as follows:
1102    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1103    // ADJCALLSTACKUP   -> add, sp, sp, amount
1104    MachineInstr *Old = I;
1105    DebugLoc dl = Old->getDebugLoc();
1106    unsigned Amount = Old->getOperand(0).getImm();
1107    if (Amount != 0) {
1108      // We need to keep the stack aligned properly.  To do this, we round the
1109      // amount of space needed for the outgoing arguments up to the next
1110      // alignment boundary.
1111      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1112      Amount = (Amount+Align-1)/Align*Align;
1113
1114      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1115      assert(!AFI->isThumb1OnlyFunction() &&
1116             "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1117      bool isARM = !AFI->isThumbFunction();
1118
1119      // Replace the pseudo instruction with a new instruction...
1120      unsigned Opc = Old->getOpcode();
1121      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1122      // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1123      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1124        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1125        unsigned PredReg = Old->getOperand(2).getReg();
1126        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1127      } else {
1128        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1129        unsigned PredReg = Old->getOperand(3).getReg();
1130        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1131        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1132      }
1133    }
1134  }
1135  MBB.erase(I);
1136}
1137
1138unsigned
1139ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1140                                         int SPAdj, int *Value,
1141                                         RegScavenger *RS) const {
1142  unsigned i = 0;
1143  MachineInstr &MI = *II;
1144  MachineBasicBlock &MBB = *MI.getParent();
1145  MachineFunction &MF = *MBB.getParent();
1146  const MachineFrameInfo *MFI = MF.getFrameInfo();
1147  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1148  assert(!AFI->isThumb1OnlyFunction() &&
1149         "This eliminateFrameIndex does not support Thumb1!");
1150
1151  while (!MI.getOperand(i).isFI()) {
1152    ++i;
1153    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1154  }
1155
1156  int FrameIndex = MI.getOperand(i).getIndex();
1157  int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1158  unsigned FrameReg;
1159
1160  Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1161  if (FrameReg != ARM::SP)
1162    SPAdj = 0;
1163
1164  // Modify MI as necessary to handle as much of 'Offset' as possible
1165  bool Done = false;
1166  if (!AFI->isThumbFunction())
1167    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1168  else {
1169    assert(AFI->isThumb2Function());
1170    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1171  }
1172  if (Done)
1173    return 0;
1174
1175  // If we get here, the immediate doesn't fit into the instruction.  We folded
1176  // as much as possible above, handle the rest, providing a register that is
1177  // SP+LargeImm.
1178  assert((Offset ||
1179          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1180          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1181         "This code isn't needed if offset already handled!");
1182
1183  unsigned ScratchReg = 0;
1184  int PIdx = MI.findFirstPredOperandIdx();
1185  ARMCC::CondCodes Pred = (PIdx == -1)
1186    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1187  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1188  if (Offset == 0)
1189    // Must be addrmode4/6.
1190    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1191  else {
1192    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1193    if (Value) *Value = Offset;
1194    if (!AFI->isThumbFunction())
1195      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1196                              Offset, Pred, PredReg, TII);
1197    else {
1198      assert(AFI->isThumb2Function());
1199      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1200                             Offset, Pred, PredReg, TII);
1201    }
1202    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1203    if (!ReuseFrameIndexVals)
1204      ScratchReg = 0;
1205  }
1206  return ScratchReg;
1207}
1208
1209/// Move iterator past the next bunch of callee save load / store ops for
1210/// the particular spill area (1: integer area 1, 2: integer area 2,
1211/// 3: fp area, 0: don't care).
1212static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1213                                   MachineBasicBlock::iterator &MBBI,
1214                                   int Opc1, int Opc2, unsigned Area,
1215                                   const ARMSubtarget &STI) {
1216  while (MBBI != MBB.end() &&
1217         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1218         MBBI->getOperand(1).isFI()) {
1219    if (Area != 0) {
1220      bool Done = false;
1221      unsigned Category = 0;
1222      switch (MBBI->getOperand(0).getReg()) {
1223      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1224      case ARM::LR:
1225        Category = 1;
1226        break;
1227      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1228        Category = STI.isTargetDarwin() ? 2 : 1;
1229        break;
1230      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1231      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1232        Category = 3;
1233        break;
1234      default:
1235        Done = true;
1236        break;
1237      }
1238      if (Done || Category != Area)
1239        break;
1240    }
1241
1242    ++MBBI;
1243  }
1244}
1245
1246void ARMBaseRegisterInfo::
1247emitPrologue(MachineFunction &MF) const {
1248  MachineBasicBlock &MBB = MF.front();
1249  MachineBasicBlock::iterator MBBI = MBB.begin();
1250  MachineFrameInfo  *MFI = MF.getFrameInfo();
1251  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1252  assert(!AFI->isThumb1OnlyFunction() &&
1253         "This emitPrologue does not suppor Thumb1!");
1254  bool isARM = !AFI->isThumbFunction();
1255  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1256  unsigned NumBytes = MFI->getStackSize();
1257  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1258  DebugLoc dl = (MBBI != MBB.end() ?
1259                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1260
1261  // Determine the sizes of each callee-save spill areas and record which frame
1262  // belongs to which callee-save spill areas.
1263  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1264  int FramePtrSpillFI = 0;
1265
1266  // Allocate the vararg register save area. This is not counted in NumBytes.
1267  if (VARegSaveSize)
1268    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1269
1270  if (!AFI->hasStackFrame()) {
1271    if (NumBytes != 0)
1272      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1273    return;
1274  }
1275
1276  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1277    unsigned Reg = CSI[i].getReg();
1278    int FI = CSI[i].getFrameIdx();
1279    switch (Reg) {
1280    case ARM::R4:
1281    case ARM::R5:
1282    case ARM::R6:
1283    case ARM::R7:
1284    case ARM::LR:
1285      if (Reg == FramePtr)
1286        FramePtrSpillFI = FI;
1287      AFI->addGPRCalleeSavedArea1Frame(FI);
1288      GPRCS1Size += 4;
1289      break;
1290    case ARM::R8:
1291    case ARM::R9:
1292    case ARM::R10:
1293    case ARM::R11:
1294      if (Reg == FramePtr)
1295        FramePtrSpillFI = FI;
1296      if (STI.isTargetDarwin()) {
1297        AFI->addGPRCalleeSavedArea2Frame(FI);
1298        GPRCS2Size += 4;
1299      } else {
1300        AFI->addGPRCalleeSavedArea1Frame(FI);
1301        GPRCS1Size += 4;
1302      }
1303      break;
1304    default:
1305      AFI->addDPRCalleeSavedAreaFrame(FI);
1306      DPRCSSize += 8;
1307    }
1308  }
1309
1310  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1311  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1312  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1313
1314  // Set FP to point to the stack slot that contains the previous FP.
1315  // For Darwin, FP is R7, which has now been stored in spill area 1.
1316  // Otherwise, if this is not Darwin, all the callee-saved registers go
1317  // into spill area 1, including the FP in R11.  In either case, it is
1318  // now safe to emit this assignment.
1319  if (STI.isTargetDarwin() || hasFP(MF)) {
1320    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1321    MachineInstrBuilder MIB =
1322      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1323      .addFrameIndex(FramePtrSpillFI).addImm(0);
1324    AddDefaultCC(AddDefaultPred(MIB));
1325  }
1326
1327  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1328  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1329
1330  // Build the new SUBri to adjust SP for FP callee-save spill area.
1331  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1332  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1333
1334  // Determine starting offsets of spill areas.
1335  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1336  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1337  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1338  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1339  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1340  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1341  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1342
1343  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1344  NumBytes = DPRCSOffset;
1345  if (NumBytes) {
1346    // Adjust SP after all the callee-save spills.
1347    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1348  }
1349
1350  if (STI.isTargetELF() && hasFP(MF)) {
1351    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1352                             AFI->getFramePtrSpillOffset());
1353  }
1354
1355  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1356  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1357  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1358
1359  // If we need dynamic stack realignment, do it here.
1360  if (needsStackRealignment(MF)) {
1361    unsigned MaxAlign = MFI->getMaxAlignment();
1362    assert (!AFI->isThumb1OnlyFunction());
1363    if (!AFI->isThumbFunction()) {
1364      // Emit bic sp, sp, MaxAlign
1365      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1366                                          TII.get(ARM::BICri), ARM::SP)
1367                                  .addReg(ARM::SP, RegState::Kill)
1368                                  .addImm(MaxAlign-1)));
1369    } else {
1370      // We cannot use sp as source/dest register here, thus we're emitting the
1371      // following sequence:
1372      // mov r4, sp
1373      // bic r4, r4, MaxAlign
1374      // mov sp, r4
1375      // FIXME: It will be better just to find spare register here.
1376      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1377        .addReg(ARM::SP, RegState::Kill);
1378      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1379                                          TII.get(ARM::t2BICri), ARM::R4)
1380                                  .addReg(ARM::R4, RegState::Kill)
1381                                  .addImm(MaxAlign-1)));
1382      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1383        .addReg(ARM::R4, RegState::Kill);
1384    }
1385  }
1386}
1387
1388static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1389  for (unsigned i = 0; CSRegs[i]; ++i)
1390    if (Reg == CSRegs[i])
1391      return true;
1392  return false;
1393}
1394
1395static bool isCSRestore(MachineInstr *MI,
1396                        const ARMBaseInstrInfo &TII,
1397                        const unsigned *CSRegs) {
1398  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1399           MI->getOpcode() == (int)ARM::LDR ||
1400           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1401          MI->getOperand(1).isFI() &&
1402          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1403}
1404
1405void ARMBaseRegisterInfo::
1406emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1407  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1408  assert(MBBI->getDesc().isReturn() &&
1409         "Can only insert epilog into returning blocks");
1410  DebugLoc dl = MBBI->getDebugLoc();
1411  MachineFrameInfo *MFI = MF.getFrameInfo();
1412  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1413  assert(!AFI->isThumb1OnlyFunction() &&
1414         "This emitEpilogue does not suppor Thumb1!");
1415  bool isARM = !AFI->isThumbFunction();
1416
1417  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1418  int NumBytes = (int)MFI->getStackSize();
1419
1420  if (!AFI->hasStackFrame()) {
1421    if (NumBytes != 0)
1422      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1423  } else {
1424    // Unwind MBBI to point to first LDR / VLDRD.
1425    const unsigned *CSRegs = getCalleeSavedRegs();
1426    if (MBBI != MBB.begin()) {
1427      do
1428        --MBBI;
1429      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1430      if (!isCSRestore(MBBI, TII, CSRegs))
1431        ++MBBI;
1432    }
1433
1434    // Move SP to start of FP callee save spill area.
1435    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1436                 AFI->getGPRCalleeSavedArea2Size() +
1437                 AFI->getDPRCalleeSavedAreaSize());
1438
1439    // Darwin ABI requires FP to point to the stack slot that contains the
1440    // previous FP.
1441    bool HasFP = hasFP(MF);
1442    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1443      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1444      // Reset SP based on frame pointer only if the stack frame extends beyond
1445      // frame pointer stack slot or target is ELF and the function has FP.
1446      if (HasFP ||
1447          AFI->getGPRCalleeSavedArea2Size() ||
1448          AFI->getDPRCalleeSavedAreaSize()  ||
1449          AFI->getDPRCalleeSavedAreaOffset()) {
1450        if (NumBytes) {
1451          if (isARM)
1452            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1453                                    ARMCC::AL, 0, TII);
1454          else
1455            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1456                                    ARMCC::AL, 0, TII);
1457        } else {
1458          // Thumb2 or ARM.
1459          if (isARM)
1460            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1461              .addReg(FramePtr)
1462              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1463          else
1464            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1465              .addReg(FramePtr);
1466        }
1467      }
1468    } else if (NumBytes)
1469      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1470
1471    // Move SP to start of integer callee save spill area 2.
1472    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1473    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1474
1475    // Move SP to start of integer callee save spill area 1.
1476    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1477    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1478
1479    // Move SP to SP upon entry to the function.
1480    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1481    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1482  }
1483
1484  if (VARegSaveSize)
1485    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1486}
1487
1488#include "ARMGenRegisterInfo.inc"
1489