1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/GCStrategy.h" 15#include "ScheduleDAGSDNodes.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/PostOrderIterator.h" 18#include "llvm/ADT/Statistic.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/BranchProbabilityInfo.h" 21#include "llvm/Analysis/CFG.h" 22#include "llvm/Analysis/EHPersonalities.h" 23#include "llvm/Analysis/TargetLibraryInfo.h" 24#include "llvm/CodeGen/Analysis.h" 25#include "llvm/CodeGen/FastISel.h" 26#include "llvm/CodeGen/FunctionLoweringInfo.h" 27#include "llvm/CodeGen/GCMetadata.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/SelectionDAGISel.h" 37#include "llvm/CodeGen/WinEHFuncInfo.h" 38#include "llvm/IR/Constants.h" 39#include "llvm/IR/DebugInfo.h" 40#include "llvm/IR/Function.h" 41#include "llvm/IR/InlineAsm.h" 42#include "llvm/IR/Instructions.h" 43#include "llvm/IR/IntrinsicInst.h" 44#include "llvm/IR/Intrinsics.h" 45#include "llvm/IR/LLVMContext.h" 46#include "llvm/IR/Module.h" 47#include "llvm/MC/MCAsmInfo.h" 48#include "llvm/Support/Compiler.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/Timer.h" 52#include "llvm/Support/raw_ostream.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetIntrinsicInfo.h" 55#include "llvm/Target/TargetLowering.h" 56#include "llvm/Target/TargetMachine.h" 57#include "llvm/Target/TargetOptions.h" 58#include "llvm/Target/TargetRegisterInfo.h" 59#include "llvm/Target/TargetSubtargetInfo.h" 60#include "llvm/Transforms/Utils/BasicBlockUtils.h" 61#include <algorithm> 62using namespace llvm; 63 64#define DEBUG_TYPE "isel" 65 66STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 67STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 68STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 69STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 70STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 71STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 72STATISTIC(NumFastIselFailLowerArguments, 73 "Number of entry blocks where fast isel failed to lower arguments"); 74 75#ifndef NDEBUG 76static cl::opt<bool> 77EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 78 cl::desc("Enable extra verbose messages in the \"fast\" " 79 "instruction selector")); 80 81 // Terminators 82STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 83STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 84STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 85STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 86STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 87STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 88STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 89 90 // Standard binary operators... 91STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 92STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 93STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 94STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 95STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 96STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 97STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 98STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 99STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 100STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 101STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 102STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 103 104 // Logical operators... 105STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 106STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 107STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 108 109 // Memory instructions... 110STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 111STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 112STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 113STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 114STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 115STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 116STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 117 118 // Convert instructions... 119STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 120STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 121STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 122STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 123STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 124STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 125STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 126STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 127STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 128STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 129STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 130STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 131 132 // Other instructions... 133STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 134STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 135STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 136STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 137STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 138STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 139STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 140STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 141STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 142STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 143STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 144STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 145STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 146STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 147STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 148 149// Intrinsic instructions... 150STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call"); 151STATISTIC(NumFastIselFailSAddWithOverflow, 152 "Fast isel fails on sadd.with.overflow"); 153STATISTIC(NumFastIselFailUAddWithOverflow, 154 "Fast isel fails on uadd.with.overflow"); 155STATISTIC(NumFastIselFailSSubWithOverflow, 156 "Fast isel fails on ssub.with.overflow"); 157STATISTIC(NumFastIselFailUSubWithOverflow, 158 "Fast isel fails on usub.with.overflow"); 159STATISTIC(NumFastIselFailSMulWithOverflow, 160 "Fast isel fails on smul.with.overflow"); 161STATISTIC(NumFastIselFailUMulWithOverflow, 162 "Fast isel fails on umul.with.overflow"); 163STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress"); 164STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call"); 165STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call"); 166STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call"); 167#endif 168 169static cl::opt<bool> 170EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 171 cl::desc("Enable verbose messages in the \"fast\" " 172 "instruction selector")); 173static cl::opt<int> EnableFastISelAbort( 174 "fast-isel-abort", cl::Hidden, 175 cl::desc("Enable abort calls when \"fast\" instruction selection " 176 "fails to lower an instruction: 0 disable the abort, 1 will " 177 "abort but for args, calls and terminators, 2 will also " 178 "abort for argument lowering, and 3 will never fallback " 179 "to SelectionDAG.")); 180 181static cl::opt<bool> 182UseMBPI("use-mbpi", 183 cl::desc("use Machine Branch Probability Info"), 184 cl::init(true), cl::Hidden); 185 186#ifndef NDEBUG 187static cl::opt<std::string> 188FilterDAGBasicBlockName("filter-view-dags", cl::Hidden, 189 cl::desc("Only display the basic block whose name " 190 "matches this for all view-*-dags options")); 191static cl::opt<bool> 192ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 193 cl::desc("Pop up a window to show dags before the first " 194 "dag combine pass")); 195static cl::opt<bool> 196ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 197 cl::desc("Pop up a window to show dags before legalize types")); 198static cl::opt<bool> 199ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 200 cl::desc("Pop up a window to show dags before legalize")); 201static cl::opt<bool> 202ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 203 cl::desc("Pop up a window to show dags before the second " 204 "dag combine pass")); 205static cl::opt<bool> 206ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 207 cl::desc("Pop up a window to show dags before the post legalize types" 208 " dag combine pass")); 209static cl::opt<bool> 210ViewISelDAGs("view-isel-dags", cl::Hidden, 211 cl::desc("Pop up a window to show isel dags as they are selected")); 212static cl::opt<bool> 213ViewSchedDAGs("view-sched-dags", cl::Hidden, 214 cl::desc("Pop up a window to show sched dags as they are processed")); 215static cl::opt<bool> 216ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 217 cl::desc("Pop up a window to show SUnit dags after they are processed")); 218#else 219static const bool ViewDAGCombine1 = false, 220 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 221 ViewDAGCombine2 = false, 222 ViewDAGCombineLT = false, 223 ViewISelDAGs = false, ViewSchedDAGs = false, 224 ViewSUnitDAGs = false; 225#endif 226 227//===---------------------------------------------------------------------===// 228/// 229/// RegisterScheduler class - Track the registration of instruction schedulers. 230/// 231//===---------------------------------------------------------------------===// 232MachinePassRegistry RegisterScheduler::Registry; 233 234//===---------------------------------------------------------------------===// 235/// 236/// ISHeuristic command line option for instruction schedulers. 237/// 238//===---------------------------------------------------------------------===// 239static cl::opt<RegisterScheduler::FunctionPassCtor, false, 240 RegisterPassParser<RegisterScheduler> > 241ISHeuristic("pre-RA-sched", 242 cl::init(&createDefaultScheduler), cl::Hidden, 243 cl::desc("Instruction schedulers available (before register" 244 " allocation):")); 245 246static RegisterScheduler 247defaultListDAGScheduler("default", "Best scheduler for the target", 248 createDefaultScheduler); 249 250namespace llvm { 251 //===--------------------------------------------------------------------===// 252 /// \brief This class is used by SelectionDAGISel to temporarily override 253 /// the optimization level on a per-function basis. 254 class OptLevelChanger { 255 SelectionDAGISel &IS; 256 CodeGenOpt::Level SavedOptLevel; 257 bool SavedFastISel; 258 259 public: 260 OptLevelChanger(SelectionDAGISel &ISel, 261 CodeGenOpt::Level NewOptLevel) : IS(ISel) { 262 SavedOptLevel = IS.OptLevel; 263 if (NewOptLevel == SavedOptLevel) 264 return; 265 IS.OptLevel = NewOptLevel; 266 IS.TM.setOptLevel(NewOptLevel); 267 DEBUG(dbgs() << "\nChanging optimization level for Function " 268 << IS.MF->getFunction()->getName() << "\n"); 269 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel 270 << " ; After: -O" << NewOptLevel << "\n"); 271 SavedFastISel = IS.TM.Options.EnableFastISel; 272 if (NewOptLevel == CodeGenOpt::None) { 273 IS.TM.setFastISel(IS.TM.getO0WantsFastISel()); 274 DEBUG(dbgs() << "\tFastISel is " 275 << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled") 276 << "\n"); 277 } 278 } 279 280 ~OptLevelChanger() { 281 if (IS.OptLevel == SavedOptLevel) 282 return; 283 DEBUG(dbgs() << "\nRestoring optimization level for Function " 284 << IS.MF->getFunction()->getName() << "\n"); 285 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel 286 << " ; After: -O" << SavedOptLevel << "\n"); 287 IS.OptLevel = SavedOptLevel; 288 IS.TM.setOptLevel(SavedOptLevel); 289 IS.TM.setFastISel(SavedFastISel); 290 } 291 }; 292 293 //===--------------------------------------------------------------------===// 294 /// createDefaultScheduler - This creates an instruction scheduler appropriate 295 /// for the target. 296 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 297 CodeGenOpt::Level OptLevel) { 298 const TargetLowering *TLI = IS->TLI; 299 const TargetSubtargetInfo &ST = IS->MF->getSubtarget(); 300 301 // Try first to see if the Target has its own way of selecting a scheduler 302 if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) { 303 return SchedulerCtor(IS, OptLevel); 304 } 305 306 if (OptLevel == CodeGenOpt::None || 307 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) || 308 TLI->getSchedulingPreference() == Sched::Source) 309 return createSourceListDAGScheduler(IS, OptLevel); 310 if (TLI->getSchedulingPreference() == Sched::RegPressure) 311 return createBURRListDAGScheduler(IS, OptLevel); 312 if (TLI->getSchedulingPreference() == Sched::Hybrid) 313 return createHybridListDAGScheduler(IS, OptLevel); 314 if (TLI->getSchedulingPreference() == Sched::VLIW) 315 return createVLIWDAGScheduler(IS, OptLevel); 316 assert(TLI->getSchedulingPreference() == Sched::ILP && 317 "Unknown sched type!"); 318 return createILPListDAGScheduler(IS, OptLevel); 319 } 320} 321 322// EmitInstrWithCustomInserter - This method should be implemented by targets 323// that mark instructions with the 'usesCustomInserter' flag. These 324// instructions are special in various ways, which require special support to 325// insert. The specified MachineInstr is created but not inserted into any 326// basic blocks, and this method is called to expand it into a sequence of 327// instructions, potentially also creating new basic blocks and control flow. 328// When new basic blocks are inserted and the edges from MBB to its successors 329// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 330// DenseMap. 331MachineBasicBlock * 332TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 333 MachineBasicBlock *MBB) const { 334#ifndef NDEBUG 335 dbgs() << "If a target marks an instruction with " 336 "'usesCustomInserter', it must implement " 337 "TargetLowering::EmitInstrWithCustomInserter!"; 338#endif 339 llvm_unreachable(nullptr); 340} 341 342void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 343 SDNode *Node) const { 344 assert(!MI->hasPostISelHook() && 345 "If a target marks an instruction with 'hasPostISelHook', " 346 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 347} 348 349//===----------------------------------------------------------------------===// 350// SelectionDAGISel code 351//===----------------------------------------------------------------------===// 352 353SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 354 CodeGenOpt::Level OL) : 355 MachineFunctionPass(ID), TM(tm), 356 FuncInfo(new FunctionLoweringInfo()), 357 CurDAG(new SelectionDAG(tm, OL)), 358 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 359 GFI(), 360 OptLevel(OL), 361 DAGSize(0) { 362 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 363 initializeBranchProbabilityInfoWrapperPassPass( 364 *PassRegistry::getPassRegistry()); 365 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry()); 366 initializeTargetLibraryInfoWrapperPassPass( 367 *PassRegistry::getPassRegistry()); 368 } 369 370SelectionDAGISel::~SelectionDAGISel() { 371 delete SDB; 372 delete CurDAG; 373 delete FuncInfo; 374} 375 376void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 377 AU.addRequired<AAResultsWrapperPass>(); 378 AU.addRequired<GCModuleInfo>(); 379 AU.addPreserved<GCModuleInfo>(); 380 AU.addRequired<TargetLibraryInfoWrapperPass>(); 381 if (UseMBPI && OptLevel != CodeGenOpt::None) 382 AU.addRequired<BranchProbabilityInfoWrapperPass>(); 383 MachineFunctionPass::getAnalysisUsage(AU); 384} 385 386/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 387/// may trap on it. In this case we have to split the edge so that the path 388/// through the predecessor block that doesn't go to the phi block doesn't 389/// execute the possibly trapping instruction. 390/// 391/// This is required for correctness, so it must be done at -O0. 392/// 393static void SplitCriticalSideEffectEdges(Function &Fn) { 394 // Loop for blocks with phi nodes. 395 for (BasicBlock &BB : Fn) { 396 PHINode *PN = dyn_cast<PHINode>(BB.begin()); 397 if (!PN) continue; 398 399 ReprocessBlock: 400 // For each block with a PHI node, check to see if any of the input values 401 // are potentially trapping constant expressions. Constant expressions are 402 // the only potentially trapping value that can occur as the argument to a 403 // PHI. 404 for (BasicBlock::iterator I = BB.begin(); (PN = dyn_cast<PHINode>(I)); ++I) 405 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 406 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 407 if (!CE || !CE->canTrap()) continue; 408 409 // The only case we have to worry about is when the edge is critical. 410 // Since this block has a PHI Node, we assume it has multiple input 411 // edges: check to see if the pred has multiple successors. 412 BasicBlock *Pred = PN->getIncomingBlock(i); 413 if (Pred->getTerminator()->getNumSuccessors() == 1) 414 continue; 415 416 // Okay, we have to split this edge. 417 SplitCriticalEdge( 418 Pred->getTerminator(), GetSuccessorNumber(Pred, &BB), 419 CriticalEdgeSplittingOptions().setMergeIdenticalEdges()); 420 goto ReprocessBlock; 421 } 422 } 423} 424 425bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 426 // Do some sanity-checking on the command-line options. 427 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 428 "-fast-isel-verbose requires -fast-isel"); 429 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 430 "-fast-isel-abort > 0 requires -fast-isel"); 431 432 const Function &Fn = *mf.getFunction(); 433 MF = &mf; 434 435 // Reset the target options before resetting the optimization 436 // level below. 437 // FIXME: This is a horrible hack and should be processed via 438 // codegen looking at the optimization level explicitly when 439 // it wants to look at it. 440 TM.resetTargetOptions(Fn); 441 // Reset OptLevel to None for optnone functions. 442 CodeGenOpt::Level NewOptLevel = OptLevel; 443 if (Fn.hasFnAttribute(Attribute::OptimizeNone)) 444 NewOptLevel = CodeGenOpt::None; 445 OptLevelChanger OLC(*this, NewOptLevel); 446 447 TII = MF->getSubtarget().getInstrInfo(); 448 TLI = MF->getSubtarget().getTargetLowering(); 449 RegInfo = &MF->getRegInfo(); 450 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); 451 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(); 452 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr; 453 454 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 455 456 SplitCriticalSideEffectEdges(const_cast<Function &>(Fn)); 457 458 CurDAG->init(*MF); 459 FuncInfo->set(Fn, *MF, CurDAG); 460 461 if (UseMBPI && OptLevel != CodeGenOpt::None) 462 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI(); 463 else 464 FuncInfo->BPI = nullptr; 465 466 SDB->init(GFI, *AA, LibInfo); 467 468 MF->setHasInlineAsm(false); 469 470 FuncInfo->SplitCSR = false; 471 SmallVector<MachineBasicBlock*, 4> Returns; 472 473 // We split CSR if the target supports it for the given function 474 // and the function has only return exits. 475 if (TLI->supportSplitCSR(MF)) { 476 FuncInfo->SplitCSR = true; 477 478 // Collect all the return blocks. 479 for (const BasicBlock &BB : Fn) { 480 if (!succ_empty(&BB)) 481 continue; 482 483 const TerminatorInst *Term = BB.getTerminator(); 484 if (isa<UnreachableInst>(Term)) 485 continue; 486 if (isa<ReturnInst>(Term)) { 487 Returns.push_back(FuncInfo->MBBMap[&BB]); 488 continue; 489 } 490 491 // Bail out if the exit block is not Return nor Unreachable. 492 FuncInfo->SplitCSR = false; 493 break; 494 } 495 } 496 497 MachineBasicBlock *EntryMBB = &MF->front(); 498 if (FuncInfo->SplitCSR) 499 // This performs initialization so lowering for SplitCSR will be correct. 500 TLI->initializeSplitCSR(EntryMBB); 501 502 SelectAllBasicBlocks(Fn); 503 504 // If the first basic block in the function has live ins that need to be 505 // copied into vregs, emit the copies into the top of the block before 506 // emitting the code for the block. 507 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo(); 508 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII); 509 510 // Insert copies in the entry block and the return blocks. 511 if (FuncInfo->SplitCSR) 512 TLI->insertCopiesSplitCSR(EntryMBB, Returns); 513 514 DenseMap<unsigned, unsigned> LiveInMap; 515 if (!FuncInfo->ArgDbgValues.empty()) 516 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 517 E = RegInfo->livein_end(); LI != E; ++LI) 518 if (LI->second) 519 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 520 521 // Insert DBG_VALUE instructions for function arguments to the entry block. 522 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 523 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 524 bool hasFI = MI->getOperand(0).isFI(); 525 unsigned Reg = 526 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 527 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 528 EntryMBB->insert(EntryMBB->begin(), MI); 529 else { 530 MachineInstr *Def = RegInfo->getVRegDef(Reg); 531 if (Def) { 532 MachineBasicBlock::iterator InsertPos = Def; 533 // FIXME: VR def may not be in entry block. 534 Def->getParent()->insert(std::next(InsertPos), MI); 535 } else 536 DEBUG(dbgs() << "Dropping debug info for dead vreg" 537 << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); 538 } 539 540 // If Reg is live-in then update debug info to track its copy in a vreg. 541 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 542 if (LDI != LiveInMap.end()) { 543 assert(!hasFI && "There's no handling of frame pointer updating here yet " 544 "- add if needed"); 545 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 546 MachineBasicBlock::iterator InsertPos = Def; 547 const MDNode *Variable = MI->getDebugVariable(); 548 const MDNode *Expr = MI->getDebugExpression(); 549 DebugLoc DL = MI->getDebugLoc(); 550 bool IsIndirect = MI->isIndirectDebugValue(); 551 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 552 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && 553 "Expected inlined-at fields to agree"); 554 // Def is never a terminator here, so it is ok to increment InsertPos. 555 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE), 556 IsIndirect, LDI->second, Offset, Variable, Expr); 557 558 // If this vreg is directly copied into an exported register then 559 // that COPY instructions also need DBG_VALUE, if it is the only 560 // user of LDI->second. 561 MachineInstr *CopyUseMI = nullptr; 562 for (MachineRegisterInfo::use_instr_iterator 563 UI = RegInfo->use_instr_begin(LDI->second), 564 E = RegInfo->use_instr_end(); UI != E; ) { 565 MachineInstr *UseMI = &*(UI++); 566 if (UseMI->isDebugValue()) continue; 567 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 568 CopyUseMI = UseMI; continue; 569 } 570 // Otherwise this is another use or second copy use. 571 CopyUseMI = nullptr; break; 572 } 573 if (CopyUseMI) { 574 // Use MI's debug location, which describes where Variable was 575 // declared, rather than whatever is attached to CopyUseMI. 576 MachineInstr *NewMI = 577 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect, 578 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr); 579 MachineBasicBlock::iterator Pos = CopyUseMI; 580 EntryMBB->insertAfter(Pos, NewMI); 581 } 582 } 583 } 584 585 // Determine if there are any calls in this machine function. 586 MachineFrameInfo *MFI = MF->getFrameInfo(); 587 for (const auto &MBB : *MF) { 588 if (MFI->hasCalls() && MF->hasInlineAsm()) 589 break; 590 591 for (const auto &MI : MBB) { 592 const MCInstrDesc &MCID = TII->get(MI.getOpcode()); 593 if ((MCID.isCall() && !MCID.isReturn()) || 594 MI.isStackAligningInlineAsm()) { 595 MFI->setHasCalls(true); 596 } 597 if (MI.isInlineAsm()) { 598 MF->setHasInlineAsm(true); 599 } 600 } 601 } 602 603 // Determine if there is a call to setjmp in the machine function. 604 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 605 606 // Replace forward-declared registers with the registers containing 607 // the desired value. 608 MachineRegisterInfo &MRI = MF->getRegInfo(); 609 for (DenseMap<unsigned, unsigned>::iterator 610 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 611 I != E; ++I) { 612 unsigned From = I->first; 613 unsigned To = I->second; 614 // If To is also scheduled to be replaced, find what its ultimate 615 // replacement is. 616 for (;;) { 617 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 618 if (J == E) break; 619 To = J->second; 620 } 621 // Make sure the new register has a sufficiently constrained register class. 622 if (TargetRegisterInfo::isVirtualRegister(From) && 623 TargetRegisterInfo::isVirtualRegister(To)) 624 MRI.constrainRegClass(To, MRI.getRegClass(From)); 625 // Replace it. 626 627 628 // Replacing one register with another won't touch the kill flags. 629 // We need to conservatively clear the kill flags as a kill on the old 630 // register might dominate existing uses of the new register. 631 if (!MRI.use_empty(To)) 632 MRI.clearKillFlags(From); 633 MRI.replaceRegWith(From, To); 634 } 635 636 if (TLI->hasCopyImplyingStackAdjustment(MF)) 637 MFI->setHasCopyImplyingStackAdjustment(true); 638 639 // Freeze the set of reserved registers now that MachineFrameInfo has been 640 // set up. All the information required by getReservedRegs() should be 641 // available now. 642 MRI.freezeReservedRegs(*MF); 643 644 // Release function-specific state. SDB and CurDAG are already cleared 645 // at this point. 646 FuncInfo->clear(); 647 648 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n"); 649 DEBUG(MF->print(dbgs())); 650 651 return true; 652} 653 654void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 655 BasicBlock::const_iterator End, 656 bool &HadTailCall) { 657 // Lower the instructions. If a call is emitted as a tail call, cease emitting 658 // nodes for this block. 659 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 660 SDB->visit(*I); 661 662 // Make sure the root of the DAG is up-to-date. 663 CurDAG->setRoot(SDB->getControlRoot()); 664 HadTailCall = SDB->HasTailCall; 665 SDB->clear(); 666 667 // Final step, emit the lowered DAG as machine code. 668 CodeGenAndEmitDAG(); 669} 670 671void SelectionDAGISel::ComputeLiveOutVRegInfo() { 672 SmallPtrSet<SDNode*, 128> VisitedNodes; 673 SmallVector<SDNode*, 128> Worklist; 674 675 Worklist.push_back(CurDAG->getRoot().getNode()); 676 677 APInt KnownZero; 678 APInt KnownOne; 679 680 do { 681 SDNode *N = Worklist.pop_back_val(); 682 683 // If we've already seen this node, ignore it. 684 if (!VisitedNodes.insert(N).second) 685 continue; 686 687 // Otherwise, add all chain operands to the worklist. 688 for (const SDValue &Op : N->op_values()) 689 if (Op.getValueType() == MVT::Other) 690 Worklist.push_back(Op.getNode()); 691 692 // If this is a CopyToReg with a vreg dest, process it. 693 if (N->getOpcode() != ISD::CopyToReg) 694 continue; 695 696 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 697 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 698 continue; 699 700 // Ignore non-scalar or non-integer values. 701 SDValue Src = N->getOperand(2); 702 EVT SrcVT = Src.getValueType(); 703 if (!SrcVT.isInteger() || SrcVT.isVector()) 704 continue; 705 706 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 707 CurDAG->computeKnownBits(Src, KnownZero, KnownOne); 708 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 709 } while (!Worklist.empty()); 710} 711 712void SelectionDAGISel::CodeGenAndEmitDAG() { 713 std::string GroupName; 714 if (TimePassesIsEnabled) 715 GroupName = "Instruction Selection and Scheduling"; 716 std::string BlockName; 717 int BlockNumber = -1; 718 (void)BlockNumber; 719 bool MatchFilterBB = false; (void)MatchFilterBB; 720#ifndef NDEBUG 721 MatchFilterBB = (FilterDAGBasicBlockName.empty() || 722 FilterDAGBasicBlockName == 723 FuncInfo->MBB->getBasicBlock()->getName().str()); 724#endif 725#ifdef NDEBUG 726 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 727 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 728 ViewSUnitDAGs) 729#endif 730 { 731 BlockNumber = FuncInfo->MBB->getNumber(); 732 BlockName = 733 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str(); 734 } 735 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 736 << " '" << BlockName << "'\n"; CurDAG->dump()); 737 738 if (ViewDAGCombine1 && MatchFilterBB) 739 CurDAG->viewGraph("dag-combine1 input for " + BlockName); 740 741 // Run the DAG combiner in pre-legalize mode. 742 { 743 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 744 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 745 } 746 747 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 748 << " '" << BlockName << "'\n"; CurDAG->dump()); 749 750 // Second step, hack on the DAG until it only uses operations and types that 751 // the target supports. 752 if (ViewLegalizeTypesDAGs && MatchFilterBB) 753 CurDAG->viewGraph("legalize-types input for " + BlockName); 754 755 bool Changed; 756 { 757 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 758 Changed = CurDAG->LegalizeTypes(); 759 } 760 761 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 762 << " '" << BlockName << "'\n"; CurDAG->dump()); 763 764 CurDAG->NewNodesMustHaveLegalTypes = true; 765 766 if (Changed) { 767 if (ViewDAGCombineLT && MatchFilterBB) 768 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 769 770 // Run the DAG combiner in post-type-legalize mode. 771 { 772 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 773 TimePassesIsEnabled); 774 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 775 } 776 777 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 778 << " '" << BlockName << "'\n"; CurDAG->dump()); 779 780 } 781 782 { 783 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 784 Changed = CurDAG->LegalizeVectors(); 785 } 786 787 if (Changed) { 788 { 789 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 790 CurDAG->LegalizeTypes(); 791 } 792 793 if (ViewDAGCombineLT && MatchFilterBB) 794 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 795 796 // Run the DAG combiner in post-type-legalize mode. 797 { 798 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 799 TimePassesIsEnabled); 800 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 801 } 802 803 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 804 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 805 } 806 807 if (ViewLegalizeDAGs && MatchFilterBB) 808 CurDAG->viewGraph("legalize input for " + BlockName); 809 810 { 811 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 812 CurDAG->Legalize(); 813 } 814 815 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 816 << " '" << BlockName << "'\n"; CurDAG->dump()); 817 818 if (ViewDAGCombine2 && MatchFilterBB) 819 CurDAG->viewGraph("dag-combine2 input for " + BlockName); 820 821 // Run the DAG combiner in post-legalize mode. 822 { 823 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 824 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 825 } 826 827 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 828 << " '" << BlockName << "'\n"; CurDAG->dump()); 829 830 if (OptLevel != CodeGenOpt::None) 831 ComputeLiveOutVRegInfo(); 832 833 if (ViewISelDAGs && MatchFilterBB) 834 CurDAG->viewGraph("isel input for " + BlockName); 835 836 // Third, instruction select all of the operations to machine code, adding the 837 // code to the MachineBasicBlock. 838 { 839 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 840 DoInstructionSelection(); 841 } 842 843 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 844 << " '" << BlockName << "'\n"; CurDAG->dump()); 845 846 if (ViewSchedDAGs && MatchFilterBB) 847 CurDAG->viewGraph("scheduler input for " + BlockName); 848 849 // Schedule machine code. 850 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 851 { 852 NamedRegionTimer T("Instruction Scheduling", GroupName, 853 TimePassesIsEnabled); 854 Scheduler->Run(CurDAG, FuncInfo->MBB); 855 } 856 857 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph(); 858 859 // Emit machine code to BB. This can change 'BB' to the last block being 860 // inserted into. 861 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 862 { 863 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 864 865 // FuncInfo->InsertPt is passed by reference and set to the end of the 866 // scheduled instructions. 867 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 868 } 869 870 // If the block was split, make sure we update any references that are used to 871 // update PHI nodes later on. 872 if (FirstMBB != LastMBB) 873 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 874 875 // Free the scheduler state. 876 { 877 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 878 TimePassesIsEnabled); 879 delete Scheduler; 880 } 881 882 // Free the SelectionDAG state, now that we're finished with it. 883 CurDAG->clear(); 884} 885 886namespace { 887/// ISelUpdater - helper class to handle updates of the instruction selection 888/// graph. 889class ISelUpdater : public SelectionDAG::DAGUpdateListener { 890 SelectionDAG::allnodes_iterator &ISelPosition; 891public: 892 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 893 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 894 895 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 896 /// deleted is the current ISelPosition node, update ISelPosition. 897 /// 898 void NodeDeleted(SDNode *N, SDNode *E) override { 899 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 900 ++ISelPosition; 901 } 902}; 903} // end anonymous namespace 904 905void SelectionDAGISel::DoInstructionSelection() { 906 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 907 << FuncInfo->MBB->getNumber() 908 << " '" << FuncInfo->MBB->getName() << "'\n"); 909 910 PreprocessISelDAG(); 911 912 // Select target instructions for the DAG. 913 { 914 // Number all nodes with a topological order and set DAGSize. 915 DAGSize = CurDAG->AssignTopologicalOrder(); 916 917 // Create a dummy node (which is not added to allnodes), that adds 918 // a reference to the root node, preventing it from being deleted, 919 // and tracking any changes of the root. 920 HandleSDNode Dummy(CurDAG->getRoot()); 921 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 922 ++ISelPosition; 923 924 // Make sure that ISelPosition gets properly updated when nodes are deleted 925 // in calls made from this function. 926 ISelUpdater ISU(*CurDAG, ISelPosition); 927 928 // The AllNodes list is now topological-sorted. Visit the 929 // nodes by starting at the end of the list (the root of the 930 // graph) and preceding back toward the beginning (the entry 931 // node). 932 while (ISelPosition != CurDAG->allnodes_begin()) { 933 SDNode *Node = &*--ISelPosition; 934 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 935 // but there are currently some corner cases that it misses. Also, this 936 // makes it theoretically possible to disable the DAGCombiner. 937 if (Node->use_empty()) 938 continue; 939 940 SDNode *ResNode = Select(Node); 941 942 // FIXME: This is pretty gross. 'Select' should be changed to not return 943 // anything at all and this code should be nuked with a tactical strike. 944 945 // If node should not be replaced, continue with the next one. 946 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 947 continue; 948 // Replace node. 949 if (ResNode) { 950 ReplaceUses(Node, ResNode); 951 } 952 953 // If after the replacement this node is not used any more, 954 // remove this dead node. 955 if (Node->use_empty()) // Don't delete EntryToken, etc. 956 CurDAG->RemoveDeadNode(Node); 957 } 958 959 CurDAG->setRoot(Dummy.getValue()); 960 } 961 962 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 963 964 PostprocessISelDAG(); 965} 966 967static bool hasExceptionPointerOrCodeUser(const CatchPadInst *CPI) { 968 for (const User *U : CPI->users()) { 969 if (const IntrinsicInst *EHPtrCall = dyn_cast<IntrinsicInst>(U)) { 970 Intrinsic::ID IID = EHPtrCall->getIntrinsicID(); 971 if (IID == Intrinsic::eh_exceptionpointer || 972 IID == Intrinsic::eh_exceptioncode) 973 return true; 974 } 975 } 976 return false; 977} 978 979/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 980/// do other setup for EH landing-pad blocks. 981bool SelectionDAGISel::PrepareEHLandingPad() { 982 MachineBasicBlock *MBB = FuncInfo->MBB; 983 const Constant *PersonalityFn = FuncInfo->Fn->getPersonalityFn(); 984 const BasicBlock *LLVMBB = MBB->getBasicBlock(); 985 const TargetRegisterClass *PtrRC = 986 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout())); 987 988 // Catchpads have one live-in register, which typically holds the exception 989 // pointer or code. 990 if (const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->getFirstNonPHI())) { 991 if (hasExceptionPointerOrCodeUser(CPI)) { 992 // Get or create the virtual register to hold the pointer or code. Mark 993 // the live in physreg and copy into the vreg. 994 MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister(PersonalityFn); 995 assert(EHPhysReg && "target lacks exception pointer register"); 996 MBB->addLiveIn(EHPhysReg); 997 unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC); 998 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), 999 TII->get(TargetOpcode::COPY), VReg) 1000 .addReg(EHPhysReg, RegState::Kill); 1001 } 1002 return true; 1003 } 1004 1005 if (!LLVMBB->isLandingPad()) 1006 return true; 1007 1008 // Add a label to mark the beginning of the landing pad. Deletion of the 1009 // landing pad can thus be detected via the MachineModuleInfo. 1010 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 1011 1012 // Assign the call site to the landing pad's begin label. 1013 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 1014 1015 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL); 1016 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 1017 .addSym(Label); 1018 1019 // Mark exception register as live in. 1020 if (unsigned Reg = TLI->getExceptionPointerRegister(PersonalityFn)) 1021 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 1022 1023 // Mark exception selector register as live in. 1024 if (unsigned Reg = TLI->getExceptionSelectorRegister(PersonalityFn)) 1025 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 1026 1027 return true; 1028} 1029 1030/// isFoldedOrDeadInstruction - Return true if the specified instruction is 1031/// side-effect free and is either dead or folded into a generated instruction. 1032/// Return false if it needs to be emitted. 1033static bool isFoldedOrDeadInstruction(const Instruction *I, 1034 FunctionLoweringInfo *FuncInfo) { 1035 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 1036 !isa<TerminatorInst>(I) && // Terminators aren't folded. 1037 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 1038 !I->isEHPad() && // EH pad instructions aren't folded. 1039 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 1040} 1041 1042#ifndef NDEBUG 1043// Collect per Instruction statistics for fast-isel misses. Only those 1044// instructions that cause the bail are accounted for. It does not account for 1045// instructions higher in the block. Thus, summing the per instructions stats 1046// will not add up to what is reported by NumFastIselFailures. 1047static void collectFailStats(const Instruction *I) { 1048 switch (I->getOpcode()) { 1049 default: assert (0 && "<Invalid operator> "); 1050 1051 // Terminators 1052 case Instruction::Ret: NumFastIselFailRet++; return; 1053 case Instruction::Br: NumFastIselFailBr++; return; 1054 case Instruction::Switch: NumFastIselFailSwitch++; return; 1055 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 1056 case Instruction::Invoke: NumFastIselFailInvoke++; return; 1057 case Instruction::Resume: NumFastIselFailResume++; return; 1058 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 1059 1060 // Standard binary operators... 1061 case Instruction::Add: NumFastIselFailAdd++; return; 1062 case Instruction::FAdd: NumFastIselFailFAdd++; return; 1063 case Instruction::Sub: NumFastIselFailSub++; return; 1064 case Instruction::FSub: NumFastIselFailFSub++; return; 1065 case Instruction::Mul: NumFastIselFailMul++; return; 1066 case Instruction::FMul: NumFastIselFailFMul++; return; 1067 case Instruction::UDiv: NumFastIselFailUDiv++; return; 1068 case Instruction::SDiv: NumFastIselFailSDiv++; return; 1069 case Instruction::FDiv: NumFastIselFailFDiv++; return; 1070 case Instruction::URem: NumFastIselFailURem++; return; 1071 case Instruction::SRem: NumFastIselFailSRem++; return; 1072 case Instruction::FRem: NumFastIselFailFRem++; return; 1073 1074 // Logical operators... 1075 case Instruction::And: NumFastIselFailAnd++; return; 1076 case Instruction::Or: NumFastIselFailOr++; return; 1077 case Instruction::Xor: NumFastIselFailXor++; return; 1078 1079 // Memory instructions... 1080 case Instruction::Alloca: NumFastIselFailAlloca++; return; 1081 case Instruction::Load: NumFastIselFailLoad++; return; 1082 case Instruction::Store: NumFastIselFailStore++; return; 1083 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 1084 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 1085 case Instruction::Fence: NumFastIselFailFence++; return; 1086 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 1087 1088 // Convert instructions... 1089 case Instruction::Trunc: NumFastIselFailTrunc++; return; 1090 case Instruction::ZExt: NumFastIselFailZExt++; return; 1091 case Instruction::SExt: NumFastIselFailSExt++; return; 1092 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 1093 case Instruction::FPExt: NumFastIselFailFPExt++; return; 1094 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 1095 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 1096 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 1097 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 1098 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 1099 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 1100 case Instruction::BitCast: NumFastIselFailBitCast++; return; 1101 1102 // Other instructions... 1103 case Instruction::ICmp: NumFastIselFailICmp++; return; 1104 case Instruction::FCmp: NumFastIselFailFCmp++; return; 1105 case Instruction::PHI: NumFastIselFailPHI++; return; 1106 case Instruction::Select: NumFastIselFailSelect++; return; 1107 case Instruction::Call: { 1108 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) { 1109 switch (Intrinsic->getIntrinsicID()) { 1110 default: 1111 NumFastIselFailIntrinsicCall++; return; 1112 case Intrinsic::sadd_with_overflow: 1113 NumFastIselFailSAddWithOverflow++; return; 1114 case Intrinsic::uadd_with_overflow: 1115 NumFastIselFailUAddWithOverflow++; return; 1116 case Intrinsic::ssub_with_overflow: 1117 NumFastIselFailSSubWithOverflow++; return; 1118 case Intrinsic::usub_with_overflow: 1119 NumFastIselFailUSubWithOverflow++; return; 1120 case Intrinsic::smul_with_overflow: 1121 NumFastIselFailSMulWithOverflow++; return; 1122 case Intrinsic::umul_with_overflow: 1123 NumFastIselFailUMulWithOverflow++; return; 1124 case Intrinsic::frameaddress: 1125 NumFastIselFailFrameaddress++; return; 1126 case Intrinsic::sqrt: 1127 NumFastIselFailSqrt++; return; 1128 case Intrinsic::experimental_stackmap: 1129 NumFastIselFailStackMap++; return; 1130 case Intrinsic::experimental_patchpoint_void: // fall-through 1131 case Intrinsic::experimental_patchpoint_i64: 1132 NumFastIselFailPatchPoint++; return; 1133 } 1134 } 1135 NumFastIselFailCall++; 1136 return; 1137 } 1138 case Instruction::Shl: NumFastIselFailShl++; return; 1139 case Instruction::LShr: NumFastIselFailLShr++; return; 1140 case Instruction::AShr: NumFastIselFailAShr++; return; 1141 case Instruction::VAArg: NumFastIselFailVAArg++; return; 1142 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 1143 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 1144 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 1145 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 1146 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 1147 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 1148 } 1149} 1150#endif 1151 1152void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 1153 // Initialize the Fast-ISel state, if needed. 1154 FastISel *FastIS = nullptr; 1155 if (TM.Options.EnableFastISel) 1156 FastIS = TLI->createFastISel(*FuncInfo, LibInfo); 1157 1158 // Iterate over all basic blocks in the function. 1159 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 1160 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 1161 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 1162 const BasicBlock *LLVMBB = *I; 1163 1164 if (OptLevel != CodeGenOpt::None) { 1165 bool AllPredsVisited = true; 1166 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 1167 PI != PE; ++PI) { 1168 if (!FuncInfo->VisitedBBs.count(*PI)) { 1169 AllPredsVisited = false; 1170 break; 1171 } 1172 } 1173 1174 if (AllPredsVisited) { 1175 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1176 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1177 FuncInfo->ComputePHILiveOutRegInfo(PN); 1178 } else { 1179 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1180 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1181 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 1182 } 1183 1184 FuncInfo->VisitedBBs.insert(LLVMBB); 1185 } 1186 1187 BasicBlock::const_iterator const Begin = 1188 LLVMBB->getFirstNonPHI()->getIterator(); 1189 BasicBlock::const_iterator const End = LLVMBB->end(); 1190 BasicBlock::const_iterator BI = End; 1191 1192 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1193 if (!FuncInfo->MBB) 1194 continue; // Some blocks like catchpads have no code or MBB. 1195 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1196 1197 // Setup an EH landing-pad block. 1198 FuncInfo->ExceptionPointerVirtReg = 0; 1199 FuncInfo->ExceptionSelectorVirtReg = 0; 1200 if (LLVMBB->isEHPad()) 1201 if (!PrepareEHLandingPad()) 1202 continue; 1203 1204 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1205 if (FastIS) { 1206 FastIS->startNewBlock(); 1207 1208 // Emit code for any incoming arguments. This must happen before 1209 // beginning FastISel on the entry block. 1210 if (LLVMBB == &Fn.getEntryBlock()) { 1211 ++NumEntryBlocks; 1212 1213 // Lower any arguments needed in this block if this is the entry block. 1214 if (!FastIS->lowerArguments()) { 1215 // Fast isel failed to lower these arguments 1216 ++NumFastIselFailLowerArguments; 1217 if (EnableFastISelAbort > 1) 1218 report_fatal_error("FastISel didn't lower all arguments"); 1219 1220 // Use SelectionDAG argument lowering 1221 LowerArguments(Fn); 1222 CurDAG->setRoot(SDB->getControlRoot()); 1223 SDB->clear(); 1224 CodeGenAndEmitDAG(); 1225 } 1226 1227 // If we inserted any instructions at the beginning, make a note of 1228 // where they are, so we can be sure to emit subsequent instructions 1229 // after them. 1230 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1231 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt)); 1232 else 1233 FastIS->setLastLocalValue(nullptr); 1234 } 1235 1236 unsigned NumFastIselRemaining = std::distance(Begin, End); 1237 // Do FastISel on as many instructions as possible. 1238 for (; BI != Begin; --BI) { 1239 const Instruction *Inst = &*std::prev(BI); 1240 1241 // If we no longer require this instruction, skip it. 1242 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1243 --NumFastIselRemaining; 1244 continue; 1245 } 1246 1247 // Bottom-up: reset the insert pos at the top, after any local-value 1248 // instructions. 1249 FastIS->recomputeInsertPt(); 1250 1251 // Try to select the instruction with FastISel. 1252 if (FastIS->selectInstruction(Inst)) { 1253 --NumFastIselRemaining; 1254 ++NumFastIselSuccess; 1255 // If fast isel succeeded, skip over all the folded instructions, and 1256 // then see if there is a load right before the selected instructions. 1257 // Try to fold the load if so. 1258 const Instruction *BeforeInst = Inst; 1259 while (BeforeInst != &*Begin) { 1260 BeforeInst = &*std::prev(BasicBlock::const_iterator(BeforeInst)); 1261 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1262 break; 1263 } 1264 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1265 BeforeInst->hasOneUse() && 1266 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1267 // If we succeeded, don't re-select the load. 1268 BI = std::next(BasicBlock::const_iterator(BeforeInst)); 1269 --NumFastIselRemaining; 1270 ++NumFastIselSuccess; 1271 } 1272 continue; 1273 } 1274 1275#ifndef NDEBUG 1276 if (EnableFastISelVerbose2) 1277 collectFailStats(Inst); 1278#endif 1279 1280 // Then handle certain instructions as single-LLVM-Instruction blocks. 1281 if (isa<CallInst>(Inst)) { 1282 1283 if (EnableFastISelVerbose || EnableFastISelAbort) { 1284 dbgs() << "FastISel missed call: "; 1285 Inst->dump(); 1286 } 1287 if (EnableFastISelAbort > 2) 1288 // FastISel selector couldn't handle something and bailed. 1289 // For the purpose of debugging, just abort. 1290 report_fatal_error("FastISel didn't select the entire block"); 1291 1292 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() && 1293 !Inst->use_empty()) { 1294 unsigned &R = FuncInfo->ValueMap[Inst]; 1295 if (!R) 1296 R = FuncInfo->CreateRegs(Inst->getType()); 1297 } 1298 1299 bool HadTailCall = false; 1300 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1301 SelectBasicBlock(Inst->getIterator(), BI, HadTailCall); 1302 1303 // If the call was emitted as a tail call, we're done with the block. 1304 // We also need to delete any previously emitted instructions. 1305 if (HadTailCall) { 1306 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1307 --BI; 1308 break; 1309 } 1310 1311 // Recompute NumFastIselRemaining as Selection DAG instruction 1312 // selection may have handled the call, input args, etc. 1313 unsigned RemainingNow = std::distance(Begin, BI); 1314 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1315 NumFastIselRemaining = RemainingNow; 1316 continue; 1317 } 1318 1319 bool ShouldAbort = EnableFastISelAbort; 1320 if (EnableFastISelVerbose || EnableFastISelAbort) { 1321 if (isa<TerminatorInst>(Inst)) { 1322 // Use a different message for terminator misses. 1323 dbgs() << "FastISel missed terminator: "; 1324 // Don't abort unless for terminator unless the level is really high 1325 ShouldAbort = (EnableFastISelAbort > 2); 1326 } else { 1327 dbgs() << "FastISel miss: "; 1328 } 1329 Inst->dump(); 1330 } 1331 if (ShouldAbort) 1332 // FastISel selector couldn't handle something and bailed. 1333 // For the purpose of debugging, just abort. 1334 report_fatal_error("FastISel didn't select the entire block"); 1335 1336 NumFastIselFailures += NumFastIselRemaining; 1337 break; 1338 } 1339 1340 FastIS->recomputeInsertPt(); 1341 } else { 1342 // Lower any arguments needed in this block if this is the entry block. 1343 if (LLVMBB == &Fn.getEntryBlock()) { 1344 ++NumEntryBlocks; 1345 LowerArguments(Fn); 1346 } 1347 } 1348 1349 if (Begin != BI) 1350 ++NumDAGBlocks; 1351 else 1352 ++NumFastIselBlocks; 1353 1354 if (Begin != BI) { 1355 // Run SelectionDAG instruction selection on the remainder of the block 1356 // not handled by FastISel. If FastISel is not run, this is the entire 1357 // block. 1358 bool HadTailCall; 1359 SelectBasicBlock(Begin, BI, HadTailCall); 1360 } 1361 1362 FinishBasicBlock(); 1363 FuncInfo->PHINodesToUpdate.clear(); 1364 } 1365 1366 delete FastIS; 1367 SDB->clearDanglingDebugInfo(); 1368 SDB->SPDescriptor.resetPerFunctionState(); 1369} 1370 1371/// Given that the input MI is before a partial terminator sequence TSeq, return 1372/// true if M + TSeq also a partial terminator sequence. 1373/// 1374/// A Terminator sequence is a sequence of MachineInstrs which at this point in 1375/// lowering copy vregs into physical registers, which are then passed into 1376/// terminator instructors so we can satisfy ABI constraints. A partial 1377/// terminator sequence is an improper subset of a terminator sequence (i.e. it 1378/// may be the whole terminator sequence). 1379static bool MIIsInTerminatorSequence(const MachineInstr *MI) { 1380 // If we do not have a copy or an implicit def, we return true if and only if 1381 // MI is a debug value. 1382 if (!MI->isCopy() && !MI->isImplicitDef()) 1383 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the 1384 // physical registers if there is debug info associated with the terminator 1385 // of our mbb. We want to include said debug info in our terminator 1386 // sequence, so we return true in that case. 1387 return MI->isDebugValue(); 1388 1389 // We have left the terminator sequence if we are not doing one of the 1390 // following: 1391 // 1392 // 1. Copying a vreg into a physical register. 1393 // 2. Copying a vreg into a vreg. 1394 // 3. Defining a register via an implicit def. 1395 1396 // OPI should always be a register definition... 1397 MachineInstr::const_mop_iterator OPI = MI->operands_begin(); 1398 if (!OPI->isReg() || !OPI->isDef()) 1399 return false; 1400 1401 // Defining any register via an implicit def is always ok. 1402 if (MI->isImplicitDef()) 1403 return true; 1404 1405 // Grab the copy source... 1406 MachineInstr::const_mop_iterator OPI2 = OPI; 1407 ++OPI2; 1408 assert(OPI2 != MI->operands_end() 1409 && "Should have a copy implying we should have 2 arguments."); 1410 1411 // Make sure that the copy dest is not a vreg when the copy source is a 1412 // physical register. 1413 if (!OPI2->isReg() || 1414 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) && 1415 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg()))) 1416 return false; 1417 1418 return true; 1419} 1420 1421/// Find the split point at which to splice the end of BB into its success stack 1422/// protector check machine basic block. 1423/// 1424/// On many platforms, due to ABI constraints, terminators, even before register 1425/// allocation, use physical registers. This creates an issue for us since 1426/// physical registers at this point can not travel across basic 1427/// blocks. Luckily, selectiondag always moves physical registers into vregs 1428/// when they enter functions and moves them through a sequence of copies back 1429/// into the physical registers right before the terminator creating a 1430/// ``Terminator Sequence''. This function is searching for the beginning of the 1431/// terminator sequence so that we can ensure that we splice off not just the 1432/// terminator, but additionally the copies that move the vregs into the 1433/// physical registers. 1434static MachineBasicBlock::iterator 1435FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) { 1436 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator(); 1437 // 1438 if (SplitPoint == BB->begin()) 1439 return SplitPoint; 1440 1441 MachineBasicBlock::iterator Start = BB->begin(); 1442 MachineBasicBlock::iterator Previous = SplitPoint; 1443 --Previous; 1444 1445 while (MIIsInTerminatorSequence(Previous)) { 1446 SplitPoint = Previous; 1447 if (Previous == Start) 1448 break; 1449 --Previous; 1450 } 1451 1452 return SplitPoint; 1453} 1454 1455void 1456SelectionDAGISel::FinishBasicBlock() { 1457 1458 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1459 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1460 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1461 dbgs() << "Node " << i << " : (" 1462 << FuncInfo->PHINodesToUpdate[i].first 1463 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1464 1465 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1466 // PHI nodes in successors. 1467 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1468 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1469 assert(PHI->isPHI() && 1470 "This is not a machine PHI node that we are updating!"); 1471 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1472 continue; 1473 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1474 } 1475 1476 // Handle stack protector. 1477 if (SDB->SPDescriptor.shouldEmitStackProtector()) { 1478 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB(); 1479 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB(); 1480 1481 // Find the split point to split the parent mbb. At the same time copy all 1482 // physical registers used in the tail of parent mbb into virtual registers 1483 // before the split point and back into physical registers after the split 1484 // point. This prevents us needing to deal with Live-ins and many other 1485 // register allocation issues caused by us splitting the parent mbb. The 1486 // register allocator will clean up said virtual copies later on. 1487 MachineBasicBlock::iterator SplitPoint = 1488 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc()); 1489 1490 // Splice the terminator of ParentMBB into SuccessMBB. 1491 SuccessMBB->splice(SuccessMBB->end(), ParentMBB, 1492 SplitPoint, 1493 ParentMBB->end()); 1494 1495 // Add compare/jump on neq/jump to the parent BB. 1496 FuncInfo->MBB = ParentMBB; 1497 FuncInfo->InsertPt = ParentMBB->end(); 1498 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB); 1499 CurDAG->setRoot(SDB->getRoot()); 1500 SDB->clear(); 1501 CodeGenAndEmitDAG(); 1502 1503 // CodeGen Failure MBB if we have not codegened it yet. 1504 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB(); 1505 if (!FailureMBB->size()) { 1506 FuncInfo->MBB = FailureMBB; 1507 FuncInfo->InsertPt = FailureMBB->end(); 1508 SDB->visitSPDescriptorFailure(SDB->SPDescriptor); 1509 CurDAG->setRoot(SDB->getRoot()); 1510 SDB->clear(); 1511 CodeGenAndEmitDAG(); 1512 } 1513 1514 // Clear the Per-BB State. 1515 SDB->SPDescriptor.resetPerBBState(); 1516 } 1517 1518 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1519 // Lower header first, if it wasn't already lowered 1520 if (!SDB->BitTestCases[i].Emitted) { 1521 // Set the current basic block to the mbb we wish to insert the code into 1522 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1523 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1524 // Emit the code 1525 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1526 CurDAG->setRoot(SDB->getRoot()); 1527 SDB->clear(); 1528 CodeGenAndEmitDAG(); 1529 } 1530 1531 BranchProbability UnhandledProb = SDB->BitTestCases[i].Prob; 1532 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1533 UnhandledProb -= SDB->BitTestCases[i].Cases[j].ExtraProb; 1534 // Set the current basic block to the mbb we wish to insert the code into 1535 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1536 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1537 // Emit the code 1538 1539 // If all cases cover a contiguous range, it is not necessary to jump to 1540 // the default block after the last bit test fails. This is because the 1541 // range check during bit test header creation has guaranteed that every 1542 // case here doesn't go outside the range. 1543 MachineBasicBlock *NextMBB; 1544 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej) 1545 NextMBB = SDB->BitTestCases[i].Cases[j + 1].TargetBB; 1546 else if (j + 1 != ej) 1547 NextMBB = SDB->BitTestCases[i].Cases[j + 1].ThisBB; 1548 else 1549 NextMBB = SDB->BitTestCases[i].Default; 1550 1551 SDB->visitBitTestCase(SDB->BitTestCases[i], 1552 NextMBB, 1553 UnhandledProb, 1554 SDB->BitTestCases[i].Reg, 1555 SDB->BitTestCases[i].Cases[j], 1556 FuncInfo->MBB); 1557 1558 CurDAG->setRoot(SDB->getRoot()); 1559 SDB->clear(); 1560 CodeGenAndEmitDAG(); 1561 1562 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej) 1563 break; 1564 } 1565 1566 // Update PHI Nodes 1567 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1568 pi != pe; ++pi) { 1569 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1570 MachineBasicBlock *PHIBB = PHI->getParent(); 1571 assert(PHI->isPHI() && 1572 "This is not a machine PHI node that we are updating!"); 1573 // This is "default" BB. We have two jumps to it. From "header" BB and 1574 // from last "case" BB. 1575 if (PHIBB == SDB->BitTestCases[i].Default) 1576 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1577 .addMBB(SDB->BitTestCases[i].Parent) 1578 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1579 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1580 // One of "cases" BB. 1581 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1582 j != ej; ++j) { 1583 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1584 if (cBB->isSuccessor(PHIBB)) 1585 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1586 } 1587 } 1588 } 1589 SDB->BitTestCases.clear(); 1590 1591 // If the JumpTable record is filled in, then we need to emit a jump table. 1592 // Updating the PHI nodes is tricky in this case, since we need to determine 1593 // whether the PHI is a successor of the range check MBB or the jump table MBB 1594 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1595 // Lower header first, if it wasn't already lowered 1596 if (!SDB->JTCases[i].first.Emitted) { 1597 // Set the current basic block to the mbb we wish to insert the code into 1598 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1599 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1600 // Emit the code 1601 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1602 FuncInfo->MBB); 1603 CurDAG->setRoot(SDB->getRoot()); 1604 SDB->clear(); 1605 CodeGenAndEmitDAG(); 1606 } 1607 1608 // Set the current basic block to the mbb we wish to insert the code into 1609 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1610 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1611 // Emit the code 1612 SDB->visitJumpTable(SDB->JTCases[i].second); 1613 CurDAG->setRoot(SDB->getRoot()); 1614 SDB->clear(); 1615 CodeGenAndEmitDAG(); 1616 1617 // Update PHI Nodes 1618 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1619 pi != pe; ++pi) { 1620 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1621 MachineBasicBlock *PHIBB = PHI->getParent(); 1622 assert(PHI->isPHI() && 1623 "This is not a machine PHI node that we are updating!"); 1624 // "default" BB. We can go there only from header BB. 1625 if (PHIBB == SDB->JTCases[i].second.Default) 1626 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1627 .addMBB(SDB->JTCases[i].first.HeaderBB); 1628 // JT BB. Just iterate over successors here 1629 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1630 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1631 } 1632 } 1633 SDB->JTCases.clear(); 1634 1635 // If we generated any switch lowering information, build and codegen any 1636 // additional DAGs necessary. 1637 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1638 // Set the current basic block to the mbb we wish to insert the code into 1639 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1640 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1641 1642 // Determine the unique successors. 1643 SmallVector<MachineBasicBlock *, 2> Succs; 1644 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1645 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1646 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1647 1648 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1649 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1650 CurDAG->setRoot(SDB->getRoot()); 1651 SDB->clear(); 1652 CodeGenAndEmitDAG(); 1653 1654 // Remember the last block, now that any splitting is done, for use in 1655 // populating PHI nodes in successors. 1656 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1657 1658 // Handle any PHI nodes in successors of this chunk, as if we were coming 1659 // from the original BB before switch expansion. Note that PHI nodes can 1660 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1661 // handle them the right number of times. 1662 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1663 FuncInfo->MBB = Succs[i]; 1664 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1665 // FuncInfo->MBB may have been removed from the CFG if a branch was 1666 // constant folded. 1667 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1668 for (MachineBasicBlock::iterator 1669 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1670 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1671 MachineInstrBuilder PHI(*MF, MBBI); 1672 // This value for this PHI node is recorded in PHINodesToUpdate. 1673 for (unsigned pn = 0; ; ++pn) { 1674 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1675 "Didn't find PHI entry!"); 1676 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1677 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1678 break; 1679 } 1680 } 1681 } 1682 } 1683 } 1684 } 1685 SDB->SwitchCases.clear(); 1686} 1687 1688 1689/// Create the scheduler. If a specific scheduler was specified 1690/// via the SchedulerRegistry, use it, otherwise select the 1691/// one preferred by the target. 1692/// 1693ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1694 return ISHeuristic(this, OptLevel); 1695} 1696 1697//===----------------------------------------------------------------------===// 1698// Helper functions used by the generated instruction selector. 1699//===----------------------------------------------------------------------===// 1700// Calls to these methods are generated by tblgen. 1701 1702/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1703/// the dag combiner simplified the 255, we still want to match. RHS is the 1704/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1705/// specified in the .td file (e.g. 255). 1706bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1707 int64_t DesiredMaskS) const { 1708 const APInt &ActualMask = RHS->getAPIntValue(); 1709 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1710 1711 // If the actual mask exactly matches, success! 1712 if (ActualMask == DesiredMask) 1713 return true; 1714 1715 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1716 if (ActualMask.intersects(~DesiredMask)) 1717 return false; 1718 1719 // Otherwise, the DAG Combiner may have proven that the value coming in is 1720 // either already zero or is not demanded. Check for known zero input bits. 1721 APInt NeededMask = DesiredMask & ~ActualMask; 1722 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1723 return true; 1724 1725 // TODO: check to see if missing bits are just not demanded. 1726 1727 // Otherwise, this pattern doesn't match. 1728 return false; 1729} 1730 1731/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1732/// the dag combiner simplified the 255, we still want to match. RHS is the 1733/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1734/// specified in the .td file (e.g. 255). 1735bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1736 int64_t DesiredMaskS) const { 1737 const APInt &ActualMask = RHS->getAPIntValue(); 1738 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1739 1740 // If the actual mask exactly matches, success! 1741 if (ActualMask == DesiredMask) 1742 return true; 1743 1744 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1745 if (ActualMask.intersects(~DesiredMask)) 1746 return false; 1747 1748 // Otherwise, the DAG Combiner may have proven that the value coming in is 1749 // either already zero or is not demanded. Check for known zero input bits. 1750 APInt NeededMask = DesiredMask & ~ActualMask; 1751 1752 APInt KnownZero, KnownOne; 1753 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne); 1754 1755 // If all the missing bits in the or are already known to be set, match! 1756 if ((NeededMask & KnownOne) == NeededMask) 1757 return true; 1758 1759 // TODO: check to see if missing bits are just not demanded. 1760 1761 // Otherwise, this pattern doesn't match. 1762 return false; 1763} 1764 1765/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1766/// by tblgen. Others should not call it. 1767void SelectionDAGISel:: 1768SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) { 1769 std::vector<SDValue> InOps; 1770 std::swap(InOps, Ops); 1771 1772 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1773 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1774 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1775 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1776 1777 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1778 if (InOps[e-1].getValueType() == MVT::Glue) 1779 --e; // Don't process a glue operand if it is here. 1780 1781 while (i != e) { 1782 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1783 if (!InlineAsm::isMemKind(Flags)) { 1784 // Just skip over this operand, copying the operands verbatim. 1785 Ops.insert(Ops.end(), InOps.begin()+i, 1786 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1787 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1788 } else { 1789 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1790 "Memory operand with multiple values?"); 1791 1792 unsigned TiedToOperand; 1793 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) { 1794 // We need the constraint ID from the operand this is tied to. 1795 unsigned CurOp = InlineAsm::Op_FirstOperand; 1796 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue(); 1797 for (; TiedToOperand; --TiedToOperand) { 1798 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1; 1799 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue(); 1800 } 1801 } 1802 1803 // Otherwise, this is a memory operand. Ask the target to select it. 1804 std::vector<SDValue> SelOps; 1805 if (SelectInlineAsmMemoryOperand(InOps[i+1], 1806 InlineAsm::getMemoryConstraintID(Flags), 1807 SelOps)) 1808 report_fatal_error("Could not match memory address. Inline asm" 1809 " failure!"); 1810 1811 // Add this to the output node. 1812 unsigned NewFlags = 1813 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1814 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32)); 1815 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1816 i += 2; 1817 } 1818 } 1819 1820 // Add the glue input back if present. 1821 if (e != InOps.size()) 1822 Ops.push_back(InOps.back()); 1823} 1824 1825/// findGlueUse - Return use of MVT::Glue value produced by the specified 1826/// SDNode. 1827/// 1828static SDNode *findGlueUse(SDNode *N) { 1829 unsigned FlagResNo = N->getNumValues()-1; 1830 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1831 SDUse &Use = I.getUse(); 1832 if (Use.getResNo() == FlagResNo) 1833 return Use.getUser(); 1834 } 1835 return nullptr; 1836} 1837 1838/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1839/// This function recursively traverses up the operand chain, ignoring 1840/// certain nodes. 1841static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1842 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited, 1843 bool IgnoreChains) { 1844 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1845 // greater than all of its (recursive) operands. If we scan to a point where 1846 // 'use' is smaller than the node we're scanning for, then we know we will 1847 // never find it. 1848 // 1849 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1850 // happen because we scan down to newly selected nodes in the case of glue 1851 // uses. 1852 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1853 return false; 1854 1855 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1856 // won't fail if we scan it again. 1857 if (!Visited.insert(Use).second) 1858 return false; 1859 1860 for (const SDValue &Op : Use->op_values()) { 1861 // Ignore chain uses, they are validated by HandleMergeInputChains. 1862 if (Op.getValueType() == MVT::Other && IgnoreChains) 1863 continue; 1864 1865 SDNode *N = Op.getNode(); 1866 if (N == Def) { 1867 if (Use == ImmedUse || Use == Root) 1868 continue; // We are not looking for immediate use. 1869 assert(N != Root); 1870 return true; 1871 } 1872 1873 // Traverse up the operand chain. 1874 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1875 return true; 1876 } 1877 return false; 1878} 1879 1880/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1881/// operand node N of U during instruction selection that starts at Root. 1882bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1883 SDNode *Root) const { 1884 if (OptLevel == CodeGenOpt::None) return false; 1885 return N.hasOneUse(); 1886} 1887 1888/// IsLegalToFold - Returns true if the specific operand node N of 1889/// U can be folded during instruction selection that starts at Root. 1890bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1891 CodeGenOpt::Level OptLevel, 1892 bool IgnoreChains) { 1893 if (OptLevel == CodeGenOpt::None) return false; 1894 1895 // If Root use can somehow reach N through a path that that doesn't contain 1896 // U then folding N would create a cycle. e.g. In the following 1897 // diagram, Root can reach N through X. If N is folded into into Root, then 1898 // X is both a predecessor and a successor of U. 1899 // 1900 // [N*] // 1901 // ^ ^ // 1902 // / \ // 1903 // [U*] [X]? // 1904 // ^ ^ // 1905 // \ / // 1906 // \ / // 1907 // [Root*] // 1908 // 1909 // * indicates nodes to be folded together. 1910 // 1911 // If Root produces glue, then it gets (even more) interesting. Since it 1912 // will be "glued" together with its glue use in the scheduler, we need to 1913 // check if it might reach N. 1914 // 1915 // [N*] // 1916 // ^ ^ // 1917 // / \ // 1918 // [U*] [X]? // 1919 // ^ ^ // 1920 // \ \ // 1921 // \ | // 1922 // [Root*] | // 1923 // ^ | // 1924 // f | // 1925 // | / // 1926 // [Y] / // 1927 // ^ / // 1928 // f / // 1929 // | / // 1930 // [GU] // 1931 // 1932 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1933 // (call it Fold), then X is a predecessor of GU and a successor of 1934 // Fold. But since Fold and GU are glued together, this will create 1935 // a cycle in the scheduling graph. 1936 1937 // If the node has glue, walk down the graph to the "lowest" node in the 1938 // glueged set. 1939 EVT VT = Root->getValueType(Root->getNumValues()-1); 1940 while (VT == MVT::Glue) { 1941 SDNode *GU = findGlueUse(Root); 1942 if (!GU) 1943 break; 1944 Root = GU; 1945 VT = Root->getValueType(Root->getNumValues()-1); 1946 1947 // If our query node has a glue result with a use, we've walked up it. If 1948 // the user (which has already been selected) has a chain or indirectly uses 1949 // the chain, our WalkChainUsers predicate will not consider it. Because of 1950 // this, we cannot ignore chains in this predicate. 1951 IgnoreChains = false; 1952 } 1953 1954 1955 SmallPtrSet<SDNode*, 16> Visited; 1956 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1957} 1958 1959SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1960 SDLoc DL(N); 1961 1962 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1963 SelectInlineAsmMemoryOperands(Ops, DL); 1964 1965 const EVT VTs[] = {MVT::Other, MVT::Glue}; 1966 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops); 1967 New->setNodeId(-1); 1968 return New.getNode(); 1969} 1970 1971SDNode 1972*SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) { 1973 SDLoc dl(Op); 1974 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1)); 1975 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); 1976 unsigned Reg = 1977 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0), 1978 *CurDAG); 1979 SDValue New = CurDAG->getCopyFromReg( 1980 Op->getOperand(0), dl, Reg, Op->getValueType(0)); 1981 New->setNodeId(-1); 1982 return New.getNode(); 1983} 1984 1985SDNode 1986*SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) { 1987 SDLoc dl(Op); 1988 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1)); 1989 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); 1990 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(), 1991 Op->getOperand(2).getValueType(), 1992 *CurDAG); 1993 SDValue New = CurDAG->getCopyToReg( 1994 Op->getOperand(0), dl, Reg, Op->getOperand(2)); 1995 New->setNodeId(-1); 1996 return New.getNode(); 1997} 1998 1999 2000 2001SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 2002 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 2003} 2004 2005/// GetVBR - decode a vbr encoding whose top bit is set. 2006LLVM_ATTRIBUTE_ALWAYS_INLINE static inline uint64_t 2007GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 2008 assert(Val >= 128 && "Not a VBR"); 2009 Val &= 127; // Remove first vbr bit. 2010 2011 unsigned Shift = 7; 2012 uint64_t NextBits; 2013 do { 2014 NextBits = MatcherTable[Idx++]; 2015 Val |= (NextBits&127) << Shift; 2016 Shift += 7; 2017 } while (NextBits & 128); 2018 2019 return Val; 2020} 2021 2022 2023/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 2024/// interior glue and chain results to use the new glue and chain results. 2025void SelectionDAGISel:: 2026UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 2027 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 2028 SDValue InputGlue, 2029 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 2030 bool isMorphNodeTo) { 2031 SmallVector<SDNode*, 4> NowDeadNodes; 2032 2033 // Now that all the normal results are replaced, we replace the chain and 2034 // glue results if present. 2035 if (!ChainNodesMatched.empty()) { 2036 assert(InputChain.getNode() && 2037 "Matched input chains but didn't produce a chain"); 2038 // Loop over all of the nodes we matched that produced a chain result. 2039 // Replace all the chain results with the final chain we ended up with. 2040 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2041 SDNode *ChainNode = ChainNodesMatched[i]; 2042 2043 // If this node was already deleted, don't look at it. 2044 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 2045 continue; 2046 2047 // Don't replace the results of the root node if we're doing a 2048 // MorphNodeTo. 2049 if (ChainNode == NodeToMatch && isMorphNodeTo) 2050 continue; 2051 2052 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 2053 if (ChainVal.getValueType() == MVT::Glue) 2054 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 2055 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 2056 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 2057 2058 // If the node became dead and we haven't already seen it, delete it. 2059 if (ChainNode->use_empty() && 2060 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 2061 NowDeadNodes.push_back(ChainNode); 2062 } 2063 } 2064 2065 // If the result produces glue, update any glue results in the matched 2066 // pattern with the glue result. 2067 if (InputGlue.getNode()) { 2068 // Handle any interior nodes explicitly marked. 2069 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 2070 SDNode *FRN = GlueResultNodesMatched[i]; 2071 2072 // If this node was already deleted, don't look at it. 2073 if (FRN->getOpcode() == ISD::DELETED_NODE) 2074 continue; 2075 2076 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 2077 "Doesn't have a glue result"); 2078 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 2079 InputGlue); 2080 2081 // If the node became dead and we haven't already seen it, delete it. 2082 if (FRN->use_empty() && 2083 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 2084 NowDeadNodes.push_back(FRN); 2085 } 2086 } 2087 2088 if (!NowDeadNodes.empty()) 2089 CurDAG->RemoveDeadNodes(NowDeadNodes); 2090 2091 DEBUG(dbgs() << "ISEL: Match complete!\n"); 2092} 2093 2094enum ChainResult { 2095 CR_Simple, 2096 CR_InducesCycle, 2097 CR_LeadsToInteriorNode 2098}; 2099 2100/// WalkChainUsers - Walk down the users of the specified chained node that is 2101/// part of the pattern we're matching, looking at all of the users we find. 2102/// This determines whether something is an interior node, whether we have a 2103/// non-pattern node in between two pattern nodes (which prevent folding because 2104/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 2105/// between pattern nodes (in which case the TF becomes part of the pattern). 2106/// 2107/// The walk we do here is guaranteed to be small because we quickly get down to 2108/// already selected nodes "below" us. 2109static ChainResult 2110WalkChainUsers(const SDNode *ChainedNode, 2111 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 2112 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 2113 ChainResult Result = CR_Simple; 2114 2115 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 2116 E = ChainedNode->use_end(); UI != E; ++UI) { 2117 // Make sure the use is of the chain, not some other value we produce. 2118 if (UI.getUse().getValueType() != MVT::Other) continue; 2119 2120 SDNode *User = *UI; 2121 2122 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 2123 continue; 2124 2125 // If we see an already-selected machine node, then we've gone beyond the 2126 // pattern that we're selecting down into the already selected chunk of the 2127 // DAG. 2128 unsigned UserOpcode = User->getOpcode(); 2129 if (User->isMachineOpcode() || 2130 UserOpcode == ISD::CopyToReg || 2131 UserOpcode == ISD::CopyFromReg || 2132 UserOpcode == ISD::INLINEASM || 2133 UserOpcode == ISD::EH_LABEL || 2134 UserOpcode == ISD::LIFETIME_START || 2135 UserOpcode == ISD::LIFETIME_END) { 2136 // If their node ID got reset to -1 then they've already been selected. 2137 // Treat them like a MachineOpcode. 2138 if (User->getNodeId() == -1) 2139 continue; 2140 } 2141 2142 // If we have a TokenFactor, we handle it specially. 2143 if (User->getOpcode() != ISD::TokenFactor) { 2144 // If the node isn't a token factor and isn't part of our pattern, then it 2145 // must be a random chained node in between two nodes we're selecting. 2146 // This happens when we have something like: 2147 // x = load ptr 2148 // call 2149 // y = x+4 2150 // store y -> ptr 2151 // Because we structurally match the load/store as a read/modify/write, 2152 // but the call is chained between them. We cannot fold in this case 2153 // because it would induce a cycle in the graph. 2154 if (!std::count(ChainedNodesInPattern.begin(), 2155 ChainedNodesInPattern.end(), User)) 2156 return CR_InducesCycle; 2157 2158 // Otherwise we found a node that is part of our pattern. For example in: 2159 // x = load ptr 2160 // y = x+4 2161 // store y -> ptr 2162 // This would happen when we're scanning down from the load and see the 2163 // store as a user. Record that there is a use of ChainedNode that is 2164 // part of the pattern and keep scanning uses. 2165 Result = CR_LeadsToInteriorNode; 2166 InteriorChainedNodes.push_back(User); 2167 continue; 2168 } 2169 2170 // If we found a TokenFactor, there are two cases to consider: first if the 2171 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 2172 // uses of the TF are in our pattern) we just want to ignore it. Second, 2173 // the TokenFactor can be sandwiched in between two chained nodes, like so: 2174 // [Load chain] 2175 // ^ 2176 // | 2177 // [Load] 2178 // ^ ^ 2179 // | \ DAG's like cheese 2180 // / \ do you? 2181 // / | 2182 // [TokenFactor] [Op] 2183 // ^ ^ 2184 // | | 2185 // \ / 2186 // \ / 2187 // [Store] 2188 // 2189 // In this case, the TokenFactor becomes part of our match and we rewrite it 2190 // as a new TokenFactor. 2191 // 2192 // To distinguish these two cases, do a recursive walk down the uses. 2193 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 2194 case CR_Simple: 2195 // If the uses of the TokenFactor are just already-selected nodes, ignore 2196 // it, it is "below" our pattern. 2197 continue; 2198 case CR_InducesCycle: 2199 // If the uses of the TokenFactor lead to nodes that are not part of our 2200 // pattern that are not selected, folding would turn this into a cycle, 2201 // bail out now. 2202 return CR_InducesCycle; 2203 case CR_LeadsToInteriorNode: 2204 break; // Otherwise, keep processing. 2205 } 2206 2207 // Okay, we know we're in the interesting interior case. The TokenFactor 2208 // is now going to be considered part of the pattern so that we rewrite its 2209 // uses (it may have uses that are not part of the pattern) with the 2210 // ultimate chain result of the generated code. We will also add its chain 2211 // inputs as inputs to the ultimate TokenFactor we create. 2212 Result = CR_LeadsToInteriorNode; 2213 ChainedNodesInPattern.push_back(User); 2214 InteriorChainedNodes.push_back(User); 2215 continue; 2216 } 2217 2218 return Result; 2219} 2220 2221/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 2222/// operation for when the pattern matched at least one node with a chains. The 2223/// input vector contains a list of all of the chained nodes that we match. We 2224/// must determine if this is a valid thing to cover (i.e. matching it won't 2225/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 2226/// be used as the input node chain for the generated nodes. 2227static SDValue 2228HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 2229 SelectionDAG *CurDAG) { 2230 // Walk all of the chained nodes we've matched, recursively scanning down the 2231 // users of the chain result. This adds any TokenFactor nodes that are caught 2232 // in between chained nodes to the chained and interior nodes list. 2233 SmallVector<SDNode*, 3> InteriorChainedNodes; 2234 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2235 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 2236 InteriorChainedNodes) == CR_InducesCycle) 2237 return SDValue(); // Would induce a cycle. 2238 } 2239 2240 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 2241 // that we are interested in. Form our input TokenFactor node. 2242 SmallVector<SDValue, 3> InputChains; 2243 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2244 // Add the input chain of this node to the InputChains list (which will be 2245 // the operands of the generated TokenFactor) if it's not an interior node. 2246 SDNode *N = ChainNodesMatched[i]; 2247 if (N->getOpcode() != ISD::TokenFactor) { 2248 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 2249 continue; 2250 2251 // Otherwise, add the input chain. 2252 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 2253 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 2254 InputChains.push_back(InChain); 2255 continue; 2256 } 2257 2258 // If we have a token factor, we want to add all inputs of the token factor 2259 // that are not part of the pattern we're matching. 2260 for (const SDValue &Op : N->op_values()) { 2261 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 2262 Op.getNode())) 2263 InputChains.push_back(Op); 2264 } 2265 } 2266 2267 if (InputChains.size() == 1) 2268 return InputChains[0]; 2269 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 2270 MVT::Other, InputChains); 2271} 2272 2273/// MorphNode - Handle morphing a node in place for the selector. 2274SDNode *SelectionDAGISel:: 2275MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 2276 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) { 2277 // It is possible we're using MorphNodeTo to replace a node with no 2278 // normal results with one that has a normal result (or we could be 2279 // adding a chain) and the input could have glue and chains as well. 2280 // In this case we need to shift the operands down. 2281 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2282 // than the old isel though. 2283 int OldGlueResultNo = -1, OldChainResultNo = -1; 2284 2285 unsigned NTMNumResults = Node->getNumValues(); 2286 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 2287 OldGlueResultNo = NTMNumResults-1; 2288 if (NTMNumResults != 1 && 2289 Node->getValueType(NTMNumResults-2) == MVT::Other) 2290 OldChainResultNo = NTMNumResults-2; 2291 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 2292 OldChainResultNo = NTMNumResults-1; 2293 2294 // Call the underlying SelectionDAG routine to do the transmogrification. Note 2295 // that this deletes operands of the old node that become dead. 2296 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops); 2297 2298 // MorphNodeTo can operate in two ways: if an existing node with the 2299 // specified operands exists, it can just return it. Otherwise, it 2300 // updates the node in place to have the requested operands. 2301 if (Res == Node) { 2302 // If we updated the node in place, reset the node ID. To the isel, 2303 // this should be just like a newly allocated machine node. 2304 Res->setNodeId(-1); 2305 } 2306 2307 unsigned ResNumResults = Res->getNumValues(); 2308 // Move the glue if needed. 2309 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 2310 (unsigned)OldGlueResultNo != ResNumResults-1) 2311 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2312 SDValue(Res, ResNumResults-1)); 2313 2314 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2315 --ResNumResults; 2316 2317 // Move the chain reference if needed. 2318 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2319 (unsigned)OldChainResultNo != ResNumResults-1) 2320 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2321 SDValue(Res, ResNumResults-1)); 2322 2323 // Otherwise, no replacement happened because the node already exists. Replace 2324 // Uses of the old node with the new one. 2325 if (Res != Node) 2326 CurDAG->ReplaceAllUsesWith(Node, Res); 2327 2328 return Res; 2329} 2330 2331/// CheckSame - Implements OP_CheckSame. 2332LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2333CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2334 SDValue N, 2335 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2336 // Accept if it is exactly the same as a previously recorded node. 2337 unsigned RecNo = MatcherTable[MatcherIndex++]; 2338 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2339 return N == RecordedNodes[RecNo].first; 2340} 2341 2342/// CheckChildSame - Implements OP_CheckChildXSame. 2343LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2344CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2345 SDValue N, 2346 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes, 2347 unsigned ChildNo) { 2348 if (ChildNo >= N.getNumOperands()) 2349 return false; // Match fails if out of range child #. 2350 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo), 2351 RecordedNodes); 2352} 2353 2354/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2355LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2356CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2357 const SelectionDAGISel &SDISel) { 2358 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2359} 2360 2361/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2362LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2363CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2364 const SelectionDAGISel &SDISel, SDNode *N) { 2365 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2366} 2367 2368LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2369CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2370 SDNode *N) { 2371 uint16_t Opc = MatcherTable[MatcherIndex++]; 2372 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2373 return N->getOpcode() == Opc; 2374} 2375 2376LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2377CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, 2378 const TargetLowering *TLI, const DataLayout &DL) { 2379 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2380 if (N.getValueType() == VT) return true; 2381 2382 // Handle the case when VT is iPTR. 2383 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL); 2384} 2385 2386LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2387CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2388 SDValue N, const TargetLowering *TLI, const DataLayout &DL, 2389 unsigned ChildNo) { 2390 if (ChildNo >= N.getNumOperands()) 2391 return false; // Match fails if out of range child #. 2392 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI, 2393 DL); 2394} 2395 2396LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2397CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2398 SDValue N) { 2399 return cast<CondCodeSDNode>(N)->get() == 2400 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2401} 2402 2403LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2404CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2405 SDValue N, const TargetLowering *TLI, const DataLayout &DL) { 2406 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2407 if (cast<VTSDNode>(N)->getVT() == VT) 2408 return true; 2409 2410 // Handle the case when VT is iPTR. 2411 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL); 2412} 2413 2414LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2415CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2416 SDValue N) { 2417 int64_t Val = MatcherTable[MatcherIndex++]; 2418 if (Val & 128) 2419 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2420 2421 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2422 return C && C->getSExtValue() == Val; 2423} 2424 2425LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2426CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2427 SDValue N, unsigned ChildNo) { 2428 if (ChildNo >= N.getNumOperands()) 2429 return false; // Match fails if out of range child #. 2430 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo)); 2431} 2432 2433LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2434CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2435 SDValue N, const SelectionDAGISel &SDISel) { 2436 int64_t Val = MatcherTable[MatcherIndex++]; 2437 if (Val & 128) 2438 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2439 2440 if (N->getOpcode() != ISD::AND) return false; 2441 2442 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2443 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2444} 2445 2446LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool 2447CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2448 SDValue N, const SelectionDAGISel &SDISel) { 2449 int64_t Val = MatcherTable[MatcherIndex++]; 2450 if (Val & 128) 2451 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2452 2453 if (N->getOpcode() != ISD::OR) return false; 2454 2455 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2456 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2457} 2458 2459/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2460/// scope, evaluate the current node. If the current predicate is known to 2461/// fail, set Result=true and return anything. If the current predicate is 2462/// known to pass, set Result=false and return the MatcherIndex to continue 2463/// with. If the current predicate is unknown, set Result=false and return the 2464/// MatcherIndex to continue with. 2465static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2466 unsigned Index, SDValue N, 2467 bool &Result, 2468 const SelectionDAGISel &SDISel, 2469 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2470 switch (Table[Index++]) { 2471 default: 2472 Result = false; 2473 return Index-1; // Could not evaluate this predicate. 2474 case SelectionDAGISel::OPC_CheckSame: 2475 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2476 return Index; 2477 case SelectionDAGISel::OPC_CheckChild0Same: 2478 case SelectionDAGISel::OPC_CheckChild1Same: 2479 case SelectionDAGISel::OPC_CheckChild2Same: 2480 case SelectionDAGISel::OPC_CheckChild3Same: 2481 Result = !::CheckChildSame(Table, Index, N, RecordedNodes, 2482 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same); 2483 return Index; 2484 case SelectionDAGISel::OPC_CheckPatternPredicate: 2485 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2486 return Index; 2487 case SelectionDAGISel::OPC_CheckPredicate: 2488 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2489 return Index; 2490 case SelectionDAGISel::OPC_CheckOpcode: 2491 Result = !::CheckOpcode(Table, Index, N.getNode()); 2492 return Index; 2493 case SelectionDAGISel::OPC_CheckType: 2494 Result = !::CheckType(Table, Index, N, SDISel.TLI, 2495 SDISel.CurDAG->getDataLayout()); 2496 return Index; 2497 case SelectionDAGISel::OPC_CheckChild0Type: 2498 case SelectionDAGISel::OPC_CheckChild1Type: 2499 case SelectionDAGISel::OPC_CheckChild2Type: 2500 case SelectionDAGISel::OPC_CheckChild3Type: 2501 case SelectionDAGISel::OPC_CheckChild4Type: 2502 case SelectionDAGISel::OPC_CheckChild5Type: 2503 case SelectionDAGISel::OPC_CheckChild6Type: 2504 case SelectionDAGISel::OPC_CheckChild7Type: 2505 Result = !::CheckChildType( 2506 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(), 2507 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type); 2508 return Index; 2509 case SelectionDAGISel::OPC_CheckCondCode: 2510 Result = !::CheckCondCode(Table, Index, N); 2511 return Index; 2512 case SelectionDAGISel::OPC_CheckValueType: 2513 Result = !::CheckValueType(Table, Index, N, SDISel.TLI, 2514 SDISel.CurDAG->getDataLayout()); 2515 return Index; 2516 case SelectionDAGISel::OPC_CheckInteger: 2517 Result = !::CheckInteger(Table, Index, N); 2518 return Index; 2519 case SelectionDAGISel::OPC_CheckChild0Integer: 2520 case SelectionDAGISel::OPC_CheckChild1Integer: 2521 case SelectionDAGISel::OPC_CheckChild2Integer: 2522 case SelectionDAGISel::OPC_CheckChild3Integer: 2523 case SelectionDAGISel::OPC_CheckChild4Integer: 2524 Result = !::CheckChildInteger(Table, Index, N, 2525 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer); 2526 return Index; 2527 case SelectionDAGISel::OPC_CheckAndImm: 2528 Result = !::CheckAndImm(Table, Index, N, SDISel); 2529 return Index; 2530 case SelectionDAGISel::OPC_CheckOrImm: 2531 Result = !::CheckOrImm(Table, Index, N, SDISel); 2532 return Index; 2533 } 2534} 2535 2536namespace { 2537 2538struct MatchScope { 2539 /// FailIndex - If this match fails, this is the index to continue with. 2540 unsigned FailIndex; 2541 2542 /// NodeStack - The node stack when the scope was formed. 2543 SmallVector<SDValue, 4> NodeStack; 2544 2545 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2546 unsigned NumRecordedNodes; 2547 2548 /// NumMatchedMemRefs - The number of matched memref entries. 2549 unsigned NumMatchedMemRefs; 2550 2551 /// InputChain/InputGlue - The current chain/glue 2552 SDValue InputChain, InputGlue; 2553 2554 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2555 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2556}; 2557 2558/// \\brief A DAG update listener to keep the matching state 2559/// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to 2560/// change the DAG while matching. X86 addressing mode matcher is an example 2561/// for this. 2562class MatchStateUpdater : public SelectionDAG::DAGUpdateListener 2563{ 2564 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes; 2565 SmallVectorImpl<MatchScope> &MatchScopes; 2566public: 2567 MatchStateUpdater(SelectionDAG &DAG, 2568 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN, 2569 SmallVectorImpl<MatchScope> &MS) : 2570 SelectionDAG::DAGUpdateListener(DAG), 2571 RecordedNodes(RN), MatchScopes(MS) { } 2572 2573 void NodeDeleted(SDNode *N, SDNode *E) override { 2574 // Some early-returns here to avoid the search if we deleted the node or 2575 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we 2576 // do, so it's unnecessary to update matching state at that point). 2577 // Neither of these can occur currently because we only install this 2578 // update listener during matching a complex patterns. 2579 if (!E || E->isMachineOpcode()) 2580 return; 2581 // Performing linear search here does not matter because we almost never 2582 // run this code. You'd have to have a CSE during complex pattern 2583 // matching. 2584 for (auto &I : RecordedNodes) 2585 if (I.first.getNode() == N) 2586 I.first.setNode(E); 2587 2588 for (auto &I : MatchScopes) 2589 for (auto &J : I.NodeStack) 2590 if (J.getNode() == N) 2591 J.setNode(E); 2592 } 2593}; 2594} 2595 2596SDNode *SelectionDAGISel:: 2597SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2598 unsigned TableSize) { 2599 // FIXME: Should these even be selected? Handle these cases in the caller? 2600 switch (NodeToMatch->getOpcode()) { 2601 default: 2602 break; 2603 case ISD::EntryToken: // These nodes remain the same. 2604 case ISD::BasicBlock: 2605 case ISD::Register: 2606 case ISD::RegisterMask: 2607 case ISD::HANDLENODE: 2608 case ISD::MDNODE_SDNODE: 2609 case ISD::TargetConstant: 2610 case ISD::TargetConstantFP: 2611 case ISD::TargetConstantPool: 2612 case ISD::TargetFrameIndex: 2613 case ISD::TargetExternalSymbol: 2614 case ISD::MCSymbol: 2615 case ISD::TargetBlockAddress: 2616 case ISD::TargetJumpTable: 2617 case ISD::TargetGlobalTLSAddress: 2618 case ISD::TargetGlobalAddress: 2619 case ISD::TokenFactor: 2620 case ISD::CopyFromReg: 2621 case ISD::CopyToReg: 2622 case ISD::EH_LABEL: 2623 case ISD::LIFETIME_START: 2624 case ISD::LIFETIME_END: 2625 NodeToMatch->setNodeId(-1); // Mark selected. 2626 return nullptr; 2627 case ISD::AssertSext: 2628 case ISD::AssertZext: 2629 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2630 NodeToMatch->getOperand(0)); 2631 return nullptr; 2632 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2633 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch); 2634 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch); 2635 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2636 } 2637 2638 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2639 2640 // Set up the node stack with NodeToMatch as the only node on the stack. 2641 SmallVector<SDValue, 8> NodeStack; 2642 SDValue N = SDValue(NodeToMatch, 0); 2643 NodeStack.push_back(N); 2644 2645 // MatchScopes - Scopes used when matching, if a match failure happens, this 2646 // indicates where to continue checking. 2647 SmallVector<MatchScope, 8> MatchScopes; 2648 2649 // RecordedNodes - This is the set of nodes that have been recorded by the 2650 // state machine. The second value is the parent of the node, or null if the 2651 // root is recorded. 2652 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2653 2654 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2655 // pattern. 2656 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2657 2658 // These are the current input chain and glue for use when generating nodes. 2659 // Various Emit operations change these. For example, emitting a copytoreg 2660 // uses and updates these. 2661 SDValue InputChain, InputGlue; 2662 2663 // ChainNodesMatched - If a pattern matches nodes that have input/output 2664 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2665 // which ones they are. The result is captured into this list so that we can 2666 // update the chain results when the pattern is complete. 2667 SmallVector<SDNode*, 3> ChainNodesMatched; 2668 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2669 2670 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2671 NodeToMatch->dump(CurDAG); 2672 dbgs() << '\n'); 2673 2674 // Determine where to start the interpreter. Normally we start at opcode #0, 2675 // but if the state machine starts with an OPC_SwitchOpcode, then we 2676 // accelerate the first lookup (which is guaranteed to be hot) with the 2677 // OpcodeOffset table. 2678 unsigned MatcherIndex = 0; 2679 2680 if (!OpcodeOffset.empty()) { 2681 // Already computed the OpcodeOffset table, just index into it. 2682 if (N.getOpcode() < OpcodeOffset.size()) 2683 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2684 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2685 2686 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2687 // Otherwise, the table isn't computed, but the state machine does start 2688 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2689 // is the first time we're selecting an instruction. 2690 unsigned Idx = 1; 2691 while (1) { 2692 // Get the size of this case. 2693 unsigned CaseSize = MatcherTable[Idx++]; 2694 if (CaseSize & 128) 2695 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2696 if (CaseSize == 0) break; 2697 2698 // Get the opcode, add the index to the table. 2699 uint16_t Opc = MatcherTable[Idx++]; 2700 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2701 if (Opc >= OpcodeOffset.size()) 2702 OpcodeOffset.resize((Opc+1)*2); 2703 OpcodeOffset[Opc] = Idx; 2704 Idx += CaseSize; 2705 } 2706 2707 // Okay, do the lookup for the first opcode. 2708 if (N.getOpcode() < OpcodeOffset.size()) 2709 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2710 } 2711 2712 while (1) { 2713 assert(MatcherIndex < TableSize && "Invalid index"); 2714#ifndef NDEBUG 2715 unsigned CurrentOpcodeIndex = MatcherIndex; 2716#endif 2717 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2718 switch (Opcode) { 2719 case OPC_Scope: { 2720 // Okay, the semantics of this operation are that we should push a scope 2721 // then evaluate the first child. However, pushing a scope only to have 2722 // the first check fail (which then pops it) is inefficient. If we can 2723 // determine immediately that the first check (or first several) will 2724 // immediately fail, don't even bother pushing a scope for them. 2725 unsigned FailIndex; 2726 2727 while (1) { 2728 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2729 if (NumToSkip & 128) 2730 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2731 // Found the end of the scope with no match. 2732 if (NumToSkip == 0) { 2733 FailIndex = 0; 2734 break; 2735 } 2736 2737 FailIndex = MatcherIndex+NumToSkip; 2738 2739 unsigned MatcherIndexOfPredicate = MatcherIndex; 2740 (void)MatcherIndexOfPredicate; // silence warning. 2741 2742 // If we can't evaluate this predicate without pushing a scope (e.g. if 2743 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2744 // push the scope and evaluate the full predicate chain. 2745 bool Result; 2746 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2747 Result, *this, RecordedNodes); 2748 if (!Result) 2749 break; 2750 2751 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2752 << "index " << MatcherIndexOfPredicate 2753 << ", continuing at " << FailIndex << "\n"); 2754 ++NumDAGIselRetries; 2755 2756 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2757 // move to the next case. 2758 MatcherIndex = FailIndex; 2759 } 2760 2761 // If the whole scope failed to match, bail. 2762 if (FailIndex == 0) break; 2763 2764 // Push a MatchScope which indicates where to go if the first child fails 2765 // to match. 2766 MatchScope NewEntry; 2767 NewEntry.FailIndex = FailIndex; 2768 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2769 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2770 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2771 NewEntry.InputChain = InputChain; 2772 NewEntry.InputGlue = InputGlue; 2773 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2774 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2775 MatchScopes.push_back(NewEntry); 2776 continue; 2777 } 2778 case OPC_RecordNode: { 2779 // Remember this node, it may end up being an operand in the pattern. 2780 SDNode *Parent = nullptr; 2781 if (NodeStack.size() > 1) 2782 Parent = NodeStack[NodeStack.size()-2].getNode(); 2783 RecordedNodes.push_back(std::make_pair(N, Parent)); 2784 continue; 2785 } 2786 2787 case OPC_RecordChild0: case OPC_RecordChild1: 2788 case OPC_RecordChild2: case OPC_RecordChild3: 2789 case OPC_RecordChild4: case OPC_RecordChild5: 2790 case OPC_RecordChild6: case OPC_RecordChild7: { 2791 unsigned ChildNo = Opcode-OPC_RecordChild0; 2792 if (ChildNo >= N.getNumOperands()) 2793 break; // Match fails if out of range child #. 2794 2795 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2796 N.getNode())); 2797 continue; 2798 } 2799 case OPC_RecordMemRef: 2800 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2801 continue; 2802 2803 case OPC_CaptureGlueInput: 2804 // If the current node has an input glue, capture it in InputGlue. 2805 if (N->getNumOperands() != 0 && 2806 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2807 InputGlue = N->getOperand(N->getNumOperands()-1); 2808 continue; 2809 2810 case OPC_MoveChild: { 2811 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2812 if (ChildNo >= N.getNumOperands()) 2813 break; // Match fails if out of range child #. 2814 N = N.getOperand(ChildNo); 2815 NodeStack.push_back(N); 2816 continue; 2817 } 2818 2819 case OPC_MoveParent: 2820 // Pop the current node off the NodeStack. 2821 NodeStack.pop_back(); 2822 assert(!NodeStack.empty() && "Node stack imbalance!"); 2823 N = NodeStack.back(); 2824 continue; 2825 2826 case OPC_CheckSame: 2827 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2828 continue; 2829 2830 case OPC_CheckChild0Same: case OPC_CheckChild1Same: 2831 case OPC_CheckChild2Same: case OPC_CheckChild3Same: 2832 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes, 2833 Opcode-OPC_CheckChild0Same)) 2834 break; 2835 continue; 2836 2837 case OPC_CheckPatternPredicate: 2838 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2839 continue; 2840 case OPC_CheckPredicate: 2841 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2842 N.getNode())) 2843 break; 2844 continue; 2845 case OPC_CheckComplexPat: { 2846 unsigned CPNum = MatcherTable[MatcherIndex++]; 2847 unsigned RecNo = MatcherTable[MatcherIndex++]; 2848 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2849 2850 // If target can modify DAG during matching, keep the matching state 2851 // consistent. 2852 std::unique_ptr<MatchStateUpdater> MSU; 2853 if (ComplexPatternFuncMutatesDAG()) 2854 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes, 2855 MatchScopes)); 2856 2857 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2858 RecordedNodes[RecNo].first, CPNum, 2859 RecordedNodes)) 2860 break; 2861 continue; 2862 } 2863 case OPC_CheckOpcode: 2864 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2865 continue; 2866 2867 case OPC_CheckType: 2868 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI, 2869 CurDAG->getDataLayout())) 2870 break; 2871 continue; 2872 2873 case OPC_SwitchOpcode: { 2874 unsigned CurNodeOpcode = N.getOpcode(); 2875 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2876 unsigned CaseSize; 2877 while (1) { 2878 // Get the size of this case. 2879 CaseSize = MatcherTable[MatcherIndex++]; 2880 if (CaseSize & 128) 2881 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2882 if (CaseSize == 0) break; 2883 2884 uint16_t Opc = MatcherTable[MatcherIndex++]; 2885 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2886 2887 // If the opcode matches, then we will execute this case. 2888 if (CurNodeOpcode == Opc) 2889 break; 2890 2891 // Otherwise, skip over this case. 2892 MatcherIndex += CaseSize; 2893 } 2894 2895 // If no cases matched, bail out. 2896 if (CaseSize == 0) break; 2897 2898 // Otherwise, execute the case we found. 2899 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2900 << " to " << MatcherIndex << "\n"); 2901 continue; 2902 } 2903 2904 case OPC_SwitchType: { 2905 MVT CurNodeVT = N.getSimpleValueType(); 2906 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2907 unsigned CaseSize; 2908 while (1) { 2909 // Get the size of this case. 2910 CaseSize = MatcherTable[MatcherIndex++]; 2911 if (CaseSize & 128) 2912 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2913 if (CaseSize == 0) break; 2914 2915 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2916 if (CaseVT == MVT::iPTR) 2917 CaseVT = TLI->getPointerTy(CurDAG->getDataLayout()); 2918 2919 // If the VT matches, then we will execute this case. 2920 if (CurNodeVT == CaseVT) 2921 break; 2922 2923 // Otherwise, skip over this case. 2924 MatcherIndex += CaseSize; 2925 } 2926 2927 // If no cases matched, bail out. 2928 if (CaseSize == 0) break; 2929 2930 // Otherwise, execute the case we found. 2931 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2932 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2933 continue; 2934 } 2935 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2936 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2937 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2938 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2939 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2940 CurDAG->getDataLayout(), 2941 Opcode - OPC_CheckChild0Type)) 2942 break; 2943 continue; 2944 case OPC_CheckCondCode: 2945 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2946 continue; 2947 case OPC_CheckValueType: 2948 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI, 2949 CurDAG->getDataLayout())) 2950 break; 2951 continue; 2952 case OPC_CheckInteger: 2953 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2954 continue; 2955 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer: 2956 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer: 2957 case OPC_CheckChild4Integer: 2958 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N, 2959 Opcode-OPC_CheckChild0Integer)) break; 2960 continue; 2961 case OPC_CheckAndImm: 2962 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2963 continue; 2964 case OPC_CheckOrImm: 2965 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2966 continue; 2967 2968 case OPC_CheckFoldableChainNode: { 2969 assert(NodeStack.size() != 1 && "No parent node"); 2970 // Verify that all intermediate nodes between the root and this one have 2971 // a single use. 2972 bool HasMultipleUses = false; 2973 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2974 if (!NodeStack[i].hasOneUse()) { 2975 HasMultipleUses = true; 2976 break; 2977 } 2978 if (HasMultipleUses) break; 2979 2980 // Check to see that the target thinks this is profitable to fold and that 2981 // we can fold it without inducing cycles in the graph. 2982 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2983 NodeToMatch) || 2984 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2985 NodeToMatch, OptLevel, 2986 true/*We validate our own chains*/)) 2987 break; 2988 2989 continue; 2990 } 2991 case OPC_EmitInteger: { 2992 MVT::SimpleValueType VT = 2993 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2994 int64_t Val = MatcherTable[MatcherIndex++]; 2995 if (Val & 128) 2996 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2997 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2998 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch), 2999 VT), nullptr)); 3000 continue; 3001 } 3002 case OPC_EmitRegister: { 3003 MVT::SimpleValueType VT = 3004 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 3005 unsigned RegNo = MatcherTable[MatcherIndex++]; 3006 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 3007 CurDAG->getRegister(RegNo, VT), nullptr)); 3008 continue; 3009 } 3010 case OPC_EmitRegister2: { 3011 // For targets w/ more than 256 register names, the register enum 3012 // values are stored in two bytes in the matcher table (just like 3013 // opcodes). 3014 MVT::SimpleValueType VT = 3015 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 3016 unsigned RegNo = MatcherTable[MatcherIndex++]; 3017 RegNo |= MatcherTable[MatcherIndex++] << 8; 3018 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 3019 CurDAG->getRegister(RegNo, VT), nullptr)); 3020 continue; 3021 } 3022 3023 case OPC_EmitConvertToTarget: { 3024 // Convert from IMM/FPIMM to target version. 3025 unsigned RecNo = MatcherTable[MatcherIndex++]; 3026 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget"); 3027 SDValue Imm = RecordedNodes[RecNo].first; 3028 3029 if (Imm->getOpcode() == ISD::Constant) { 3030 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 3031 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(), 3032 true); 3033 } else if (Imm->getOpcode() == ISD::ConstantFP) { 3034 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 3035 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch), 3036 Imm.getValueType(), true); 3037 } 3038 3039 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 3040 continue; 3041 } 3042 3043 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 3044 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 3045 // These are space-optimized forms of OPC_EmitMergeInputChains. 3046 assert(!InputChain.getNode() && 3047 "EmitMergeInputChains should be the first chain producing node"); 3048 assert(ChainNodesMatched.empty() && 3049 "Should only have one EmitMergeInputChains per match"); 3050 3051 // Read all of the chained nodes. 3052 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 3053 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 3054 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3055 3056 // FIXME: What if other value results of the node have uses not matched 3057 // by this pattern? 3058 if (ChainNodesMatched.back() != NodeToMatch && 3059 !RecordedNodes[RecNo].first.hasOneUse()) { 3060 ChainNodesMatched.clear(); 3061 break; 3062 } 3063 3064 // Merge the input chains if they are not intra-pattern references. 3065 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 3066 3067 if (!InputChain.getNode()) 3068 break; // Failed to merge. 3069 continue; 3070 } 3071 3072 case OPC_EmitMergeInputChains: { 3073 assert(!InputChain.getNode() && 3074 "EmitMergeInputChains should be the first chain producing node"); 3075 // This node gets a list of nodes we matched in the input that have 3076 // chains. We want to token factor all of the input chains to these nodes 3077 // together. However, if any of the input chains is actually one of the 3078 // nodes matched in this pattern, then we have an intra-match reference. 3079 // Ignore these because the newly token factored chain should not refer to 3080 // the old nodes. 3081 unsigned NumChains = MatcherTable[MatcherIndex++]; 3082 assert(NumChains != 0 && "Can't TF zero chains"); 3083 3084 assert(ChainNodesMatched.empty() && 3085 "Should only have one EmitMergeInputChains per match"); 3086 3087 // Read all of the chained nodes. 3088 for (unsigned i = 0; i != NumChains; ++i) { 3089 unsigned RecNo = MatcherTable[MatcherIndex++]; 3090 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 3091 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3092 3093 // FIXME: What if other value results of the node have uses not matched 3094 // by this pattern? 3095 if (ChainNodesMatched.back() != NodeToMatch && 3096 !RecordedNodes[RecNo].first.hasOneUse()) { 3097 ChainNodesMatched.clear(); 3098 break; 3099 } 3100 } 3101 3102 // If the inner loop broke out, the match fails. 3103 if (ChainNodesMatched.empty()) 3104 break; 3105 3106 // Merge the input chains if they are not intra-pattern references. 3107 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 3108 3109 if (!InputChain.getNode()) 3110 break; // Failed to merge. 3111 3112 continue; 3113 } 3114 3115 case OPC_EmitCopyToReg: { 3116 unsigned RecNo = MatcherTable[MatcherIndex++]; 3117 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg"); 3118 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 3119 3120 if (!InputChain.getNode()) 3121 InputChain = CurDAG->getEntryNode(); 3122 3123 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 3124 DestPhysReg, RecordedNodes[RecNo].first, 3125 InputGlue); 3126 3127 InputGlue = InputChain.getValue(1); 3128 continue; 3129 } 3130 3131 case OPC_EmitNodeXForm: { 3132 unsigned XFormNo = MatcherTable[MatcherIndex++]; 3133 unsigned RecNo = MatcherTable[MatcherIndex++]; 3134 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm"); 3135 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 3136 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr)); 3137 continue; 3138 } 3139 3140 case OPC_EmitNode: 3141 case OPC_MorphNodeTo: { 3142 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 3143 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 3144 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 3145 // Get the result VT list. 3146 unsigned NumVTs = MatcherTable[MatcherIndex++]; 3147 SmallVector<EVT, 4> VTs; 3148 for (unsigned i = 0; i != NumVTs; ++i) { 3149 MVT::SimpleValueType VT = 3150 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 3151 if (VT == MVT::iPTR) 3152 VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy; 3153 VTs.push_back(VT); 3154 } 3155 3156 if (EmitNodeInfo & OPFL_Chain) 3157 VTs.push_back(MVT::Other); 3158 if (EmitNodeInfo & OPFL_GlueOutput) 3159 VTs.push_back(MVT::Glue); 3160 3161 // This is hot code, so optimize the two most common cases of 1 and 2 3162 // results. 3163 SDVTList VTList; 3164 if (VTs.size() == 1) 3165 VTList = CurDAG->getVTList(VTs[0]); 3166 else if (VTs.size() == 2) 3167 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 3168 else 3169 VTList = CurDAG->getVTList(VTs); 3170 3171 // Get the operand list. 3172 unsigned NumOps = MatcherTable[MatcherIndex++]; 3173 SmallVector<SDValue, 8> Ops; 3174 for (unsigned i = 0; i != NumOps; ++i) { 3175 unsigned RecNo = MatcherTable[MatcherIndex++]; 3176 if (RecNo & 128) 3177 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 3178 3179 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 3180 Ops.push_back(RecordedNodes[RecNo].first); 3181 } 3182 3183 // If there are variadic operands to add, handle them now. 3184 if (EmitNodeInfo & OPFL_VariadicInfo) { 3185 // Determine the start index to copy from. 3186 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 3187 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 3188 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 3189 "Invalid variadic node"); 3190 // Copy all of the variadic operands, not including a potential glue 3191 // input. 3192 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 3193 i != e; ++i) { 3194 SDValue V = NodeToMatch->getOperand(i); 3195 if (V.getValueType() == MVT::Glue) break; 3196 Ops.push_back(V); 3197 } 3198 } 3199 3200 // If this has chain/glue inputs, add them. 3201 if (EmitNodeInfo & OPFL_Chain) 3202 Ops.push_back(InputChain); 3203 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr) 3204 Ops.push_back(InputGlue); 3205 3206 // Create the node. 3207 SDNode *Res = nullptr; 3208 if (Opcode != OPC_MorphNodeTo) { 3209 // If this is a normal EmitNode command, just create the new node and 3210 // add the results to the RecordedNodes list. 3211 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 3212 VTList, Ops); 3213 3214 // Add all the non-glue/non-chain results to the RecordedNodes list. 3215 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 3216 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 3217 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 3218 nullptr)); 3219 } 3220 3221 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 3222 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo); 3223 } else { 3224 // NodeToMatch was eliminated by CSE when the target changed the DAG. 3225 // We will visit the equivalent node later. 3226 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 3227 return nullptr; 3228 } 3229 3230 // If the node had chain/glue results, update our notion of the current 3231 // chain and glue. 3232 if (EmitNodeInfo & OPFL_GlueOutput) { 3233 InputGlue = SDValue(Res, VTs.size()-1); 3234 if (EmitNodeInfo & OPFL_Chain) 3235 InputChain = SDValue(Res, VTs.size()-2); 3236 } else if (EmitNodeInfo & OPFL_Chain) 3237 InputChain = SDValue(Res, VTs.size()-1); 3238 3239 // If the OPFL_MemRefs glue is set on this node, slap all of the 3240 // accumulated memrefs onto it. 3241 // 3242 // FIXME: This is vastly incorrect for patterns with multiple outputs 3243 // instructions that access memory and for ComplexPatterns that match 3244 // loads. 3245 if (EmitNodeInfo & OPFL_MemRefs) { 3246 // Only attach load or store memory operands if the generated 3247 // instruction may load or store. 3248 const MCInstrDesc &MCID = TII->get(TargetOpc); 3249 bool mayLoad = MCID.mayLoad(); 3250 bool mayStore = MCID.mayStore(); 3251 3252 unsigned NumMemRefs = 0; 3253 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 3254 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 3255 if ((*I)->isLoad()) { 3256 if (mayLoad) 3257 ++NumMemRefs; 3258 } else if ((*I)->isStore()) { 3259 if (mayStore) 3260 ++NumMemRefs; 3261 } else { 3262 ++NumMemRefs; 3263 } 3264 } 3265 3266 MachineSDNode::mmo_iterator MemRefs = 3267 MF->allocateMemRefsArray(NumMemRefs); 3268 3269 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 3270 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 3271 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 3272 if ((*I)->isLoad()) { 3273 if (mayLoad) 3274 *MemRefsPos++ = *I; 3275 } else if ((*I)->isStore()) { 3276 if (mayStore) 3277 *MemRefsPos++ = *I; 3278 } else { 3279 *MemRefsPos++ = *I; 3280 } 3281 } 3282 3283 cast<MachineSDNode>(Res) 3284 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 3285 } 3286 3287 DEBUG(dbgs() << " " 3288 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 3289 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 3290 3291 // If this was a MorphNodeTo then we're completely done! 3292 if (Opcode == OPC_MorphNodeTo) { 3293 // Update chain and glue uses. 3294 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3295 InputGlue, GlueResultNodesMatched, true); 3296 return Res; 3297 } 3298 3299 continue; 3300 } 3301 3302 case OPC_MarkGlueResults: { 3303 unsigned NumNodes = MatcherTable[MatcherIndex++]; 3304 3305 // Read and remember all the glue-result nodes. 3306 for (unsigned i = 0; i != NumNodes; ++i) { 3307 unsigned RecNo = MatcherTable[MatcherIndex++]; 3308 if (RecNo & 128) 3309 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 3310 3311 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults"); 3312 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3313 } 3314 continue; 3315 } 3316 3317 case OPC_CompleteMatch: { 3318 // The match has been completed, and any new nodes (if any) have been 3319 // created. Patch up references to the matched dag to use the newly 3320 // created nodes. 3321 unsigned NumResults = MatcherTable[MatcherIndex++]; 3322 3323 for (unsigned i = 0; i != NumResults; ++i) { 3324 unsigned ResSlot = MatcherTable[MatcherIndex++]; 3325 if (ResSlot & 128) 3326 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 3327 3328 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch"); 3329 SDValue Res = RecordedNodes[ResSlot].first; 3330 3331 assert(i < NodeToMatch->getNumValues() && 3332 NodeToMatch->getValueType(i) != MVT::Other && 3333 NodeToMatch->getValueType(i) != MVT::Glue && 3334 "Invalid number of results to complete!"); 3335 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 3336 NodeToMatch->getValueType(i) == MVT::iPTR || 3337 Res.getValueType() == MVT::iPTR || 3338 NodeToMatch->getValueType(i).getSizeInBits() == 3339 Res.getValueType().getSizeInBits()) && 3340 "invalid replacement"); 3341 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 3342 } 3343 3344 // If the root node defines glue, add it to the glue nodes to update list. 3345 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 3346 GlueResultNodesMatched.push_back(NodeToMatch); 3347 3348 // Update chain and glue uses. 3349 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3350 InputGlue, GlueResultNodesMatched, false); 3351 3352 assert(NodeToMatch->use_empty() && 3353 "Didn't replace all uses of the node?"); 3354 3355 // FIXME: We just return here, which interacts correctly with SelectRoot 3356 // above. We should fix this to not return an SDNode* anymore. 3357 return nullptr; 3358 } 3359 } 3360 3361 // If the code reached this point, then the match failed. See if there is 3362 // another child to try in the current 'Scope', otherwise pop it until we 3363 // find a case to check. 3364 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 3365 ++NumDAGIselRetries; 3366 while (1) { 3367 if (MatchScopes.empty()) { 3368 CannotYetSelect(NodeToMatch); 3369 return nullptr; 3370 } 3371 3372 // Restore the interpreter state back to the point where the scope was 3373 // formed. 3374 MatchScope &LastScope = MatchScopes.back(); 3375 RecordedNodes.resize(LastScope.NumRecordedNodes); 3376 NodeStack.clear(); 3377 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 3378 N = NodeStack.back(); 3379 3380 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 3381 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 3382 MatcherIndex = LastScope.FailIndex; 3383 3384 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 3385 3386 InputChain = LastScope.InputChain; 3387 InputGlue = LastScope.InputGlue; 3388 if (!LastScope.HasChainNodesMatched) 3389 ChainNodesMatched.clear(); 3390 if (!LastScope.HasGlueResultNodesMatched) 3391 GlueResultNodesMatched.clear(); 3392 3393 // Check to see what the offset is at the new MatcherIndex. If it is zero 3394 // we have reached the end of this scope, otherwise we have another child 3395 // in the current scope to try. 3396 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 3397 if (NumToSkip & 128) 3398 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 3399 3400 // If we have another child in this scope to match, update FailIndex and 3401 // try it. 3402 if (NumToSkip != 0) { 3403 LastScope.FailIndex = MatcherIndex+NumToSkip; 3404 break; 3405 } 3406 3407 // End of this scope, pop it and try the next child in the containing 3408 // scope. 3409 MatchScopes.pop_back(); 3410 } 3411 } 3412} 3413 3414 3415 3416void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3417 std::string msg; 3418 raw_string_ostream Msg(msg); 3419 Msg << "Cannot select: "; 3420 3421 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3422 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3423 N->getOpcode() != ISD::INTRINSIC_VOID) { 3424 N->printrFull(Msg, CurDAG); 3425 Msg << "\nIn function: " << MF->getName(); 3426 } else { 3427 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3428 unsigned iid = 3429 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3430 if (iid < Intrinsic::num_intrinsics) 3431 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3432 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3433 Msg << "target intrinsic %" << TII->getName(iid); 3434 else 3435 Msg << "unknown intrinsic #" << iid; 3436 } 3437 report_fatal_error(Msg.str()); 3438} 3439 3440char SelectionDAGISel::ID = 0; 3441