1169695Skan/* Xtensa configuration settings. 2169695Skan Copyright (C) 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 3169695Skan Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. 4169695Skan 5169695Skan This program is free software; you can redistribute it and/or modify 6169695Skan it under the terms of the GNU General Public License as published by 7169695Skan the Free Software Foundation; either version 2, or (at your option) 8169695Skan any later version. 9169695Skan 10169695Skan This program is distributed in the hope that it will be useful, but 11169695Skan WITHOUT ANY WARRANTY; without even the implied warranty of 12169695Skan MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13169695Skan General Public License for more details. 14169695Skan 15169695Skan You should have received a copy of the GNU General Public License 16169695Skan along with this program; if not, write to the Free Software 17169695Skan Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 18169695Skan 19169695Skan#ifndef XTENSA_CONFIG_H 20169695Skan#define XTENSA_CONFIG_H 21169695Skan 22169695Skan/* The macros defined here match those with the same names in the Xtensa 23169695Skan compile-time HAL (Hardware Abstraction Layer). Please refer to the 24169695Skan Xtensa System Software Reference Manual for documentation of these 25169695Skan macros. */ 26169695Skan 27169695Skan#undef XCHAL_HAVE_BE 28169695Skan#define XCHAL_HAVE_BE 1 29169695Skan 30169695Skan#undef XCHAL_HAVE_DENSITY 31169695Skan#define XCHAL_HAVE_DENSITY 1 32169695Skan 33169695Skan#undef XCHAL_HAVE_CONST16 34169695Skan#define XCHAL_HAVE_CONST16 0 35169695Skan 36169695Skan#undef XCHAL_HAVE_ABS 37169695Skan#define XCHAL_HAVE_ABS 1 38169695Skan 39169695Skan#undef XCHAL_HAVE_ADDX 40169695Skan#define XCHAL_HAVE_ADDX 1 41169695Skan 42169695Skan#undef XCHAL_HAVE_L32R 43169695Skan#define XCHAL_HAVE_L32R 1 44169695Skan 45169695Skan#undef XSHAL_USE_ABSOLUTE_LITERALS 46169695Skan#define XSHAL_USE_ABSOLUTE_LITERALS 0 47169695Skan 48169695Skan#undef XCHAL_HAVE_MAC16 49169695Skan#define XCHAL_HAVE_MAC16 0 50169695Skan 51169695Skan#undef XCHAL_HAVE_MUL16 52169695Skan#define XCHAL_HAVE_MUL16 0 53169695Skan 54169695Skan#undef XCHAL_HAVE_MUL32 55169695Skan#define XCHAL_HAVE_MUL32 0 56169695Skan 57169695Skan#undef XCHAL_HAVE_MUL32_HIGH 58169695Skan#define XCHAL_HAVE_MUL32_HIGH 0 59169695Skan 60169695Skan#undef XCHAL_HAVE_DIV32 61169695Skan#define XCHAL_HAVE_DIV32 0 62169695Skan 63169695Skan#undef XCHAL_HAVE_NSA 64169695Skan#define XCHAL_HAVE_NSA 1 65169695Skan 66169695Skan#undef XCHAL_HAVE_MINMAX 67169695Skan#define XCHAL_HAVE_MINMAX 0 68169695Skan 69169695Skan#undef XCHAL_HAVE_SEXT 70169695Skan#define XCHAL_HAVE_SEXT 0 71169695Skan 72169695Skan#undef XCHAL_HAVE_LOOPS 73169695Skan#define XCHAL_HAVE_LOOPS 1 74169695Skan 75169695Skan#undef XCHAL_HAVE_BOOLEANS 76169695Skan#define XCHAL_HAVE_BOOLEANS 0 77169695Skan 78169695Skan#undef XCHAL_HAVE_FP 79169695Skan#define XCHAL_HAVE_FP 0 80169695Skan 81169695Skan#undef XCHAL_HAVE_FP_DIV 82169695Skan#define XCHAL_HAVE_FP_DIV 0 83169695Skan 84169695Skan#undef XCHAL_HAVE_FP_RECIP 85169695Skan#define XCHAL_HAVE_FP_RECIP 0 86169695Skan 87169695Skan#undef XCHAL_HAVE_FP_SQRT 88169695Skan#define XCHAL_HAVE_FP_SQRT 0 89169695Skan 90169695Skan#undef XCHAL_HAVE_FP_RSQRT 91169695Skan#define XCHAL_HAVE_FP_RSQRT 0 92169695Skan 93169695Skan#undef XCHAL_HAVE_WINDOWED 94169695Skan#define XCHAL_HAVE_WINDOWED 1 95169695Skan 96169695Skan#undef XCHAL_HAVE_WIDE_BRANCHES 97169695Skan#define XCHAL_HAVE_WIDE_BRANCHES 0 98169695Skan 99169695Skan#undef XCHAL_HAVE_PREDICTED_BRANCHES 100169695Skan#define XCHAL_HAVE_PREDICTED_BRANCHES 0 101169695Skan 102169695Skan 103169695Skan#undef XCHAL_ICACHE_SIZE 104169695Skan#define XCHAL_ICACHE_SIZE 8192 105169695Skan 106169695Skan#undef XCHAL_DCACHE_SIZE 107169695Skan#define XCHAL_DCACHE_SIZE 8192 108169695Skan 109169695Skan#undef XCHAL_ICACHE_LINESIZE 110169695Skan#define XCHAL_ICACHE_LINESIZE 16 111169695Skan 112169695Skan#undef XCHAL_DCACHE_LINESIZE 113169695Skan#define XCHAL_DCACHE_LINESIZE 16 114169695Skan 115169695Skan#undef XCHAL_ICACHE_LINEWIDTH 116169695Skan#define XCHAL_ICACHE_LINEWIDTH 4 117169695Skan 118169695Skan#undef XCHAL_DCACHE_LINEWIDTH 119169695Skan#define XCHAL_DCACHE_LINEWIDTH 4 120169695Skan 121169695Skan#undef XCHAL_DCACHE_IS_WRITEBACK 122169695Skan#define XCHAL_DCACHE_IS_WRITEBACK 0 123169695Skan 124169695Skan 125169695Skan#undef XCHAL_HAVE_MMU 126169695Skan#define XCHAL_HAVE_MMU 1 127169695Skan 128169695Skan#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE 129169695Skan#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 130169695Skan 131169695Skan 132169695Skan#undef XCHAL_HAVE_DEBUG 133169695Skan#define XCHAL_HAVE_DEBUG 1 134169695Skan 135169695Skan#undef XCHAL_NUM_IBREAK 136169695Skan#define XCHAL_NUM_IBREAK 2 137169695Skan 138169695Skan#undef XCHAL_NUM_DBREAK 139169695Skan#define XCHAL_NUM_DBREAK 2 140169695Skan 141169695Skan#undef XCHAL_DEBUGLEVEL 142169695Skan#define XCHAL_DEBUGLEVEL 4 143169695Skan 144169695Skan 145169695Skan#undef XCHAL_INST_FETCH_WIDTH 146169695Skan#define XCHAL_INST_FETCH_WIDTH 4 147169695Skan 148169695Skan#endif /* !XTENSA_CONFIG_H */ 149