1;; Itanium1 (original Itanium) DFA descriptions for insn scheduling 2;; and bundling. 3;; Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc. 4;; Contributed by Vladimir Makarov <vmakarov@redhat.com>. 5;; 6;; This file is part of GCC. 7;; 8;; GCC is free software; you can redistribute it and/or modify 9;; it under the terms of the GNU General Public License as published by 10;; the Free Software Foundation; either version 2, or (at your option) 11;; any later version. 12;; 13;; GCC is distributed in the hope that it will be useful, 14;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16;; GNU General Public License for more details. 17;; 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING. If not, write to 20;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 21;; Boston, MA 02110-1301, USA. */ 22;; 23 24 25/* This is description of pipeline hazards based on DFA. The 26 following constructions can be used for this: 27 28 o define_cpu_unit string [string]) describes a cpu functional unit 29 (separated by comma). 30 31 1st operand: Names of cpu function units. 32 2nd operand: Name of automaton (see comments for 33 DEFINE_AUTOMATON). 34 35 All define_reservations and define_cpu_units should have unique 36 names which cannot be "nothing". 37 38 o (exclusion_set string string) means that each CPU function unit 39 in the first string cannot be reserved simultaneously with each 40 unit whose name is in the second string and vise versa. CPU 41 units in the string are separated by commas. For example, it is 42 useful for description CPU with fully pipelined floating point 43 functional unit which can execute simultaneously only single 44 floating point insns or only double floating point insns. 45 46 o (presence_set string string) means that each CPU function unit in 47 the first string cannot be reserved unless at least one of 48 pattern of units whose names are in the second string is 49 reserved. This is an asymmetric relation. CPU units or unit 50 patterns in the strings are separated by commas. Pattern is one 51 unit name or unit names separated by white-spaces. 52 53 For example, it is useful for description that slot1 is reserved 54 after slot0 reservation for a VLIW processor. We could describe 55 it by the following construction 56 57 (presence_set "slot1" "slot0") 58 59 Or slot1 is reserved only after slot0 and unit b0 reservation. 60 In this case we could write 61 62 (presence_set "slot1" "slot0 b0") 63 64 All CPU functional units in a set should belong to the same 65 automaton. 66 67 o (final_presence_set string string) is analogous to 68 `presence_set'. The difference between them is when checking is 69 done. When an instruction is issued in given automaton state 70 reflecting all current and planned unit reservations, the 71 automaton state is changed. The first state is a source state, 72 the second one is a result state. Checking for `presence_set' is 73 done on the source state reservation, checking for 74 `final_presence_set' is done on the result reservation. This 75 construction is useful to describe a reservation which is 76 actually two subsequent reservations. For example, if we use 77 78 (presence_set "slot1" "slot0") 79 80 the following insn will be never issued (because slot1 requires 81 slot0 which is absent in the source state). 82 83 (define_reservation "insn_and_nop" "slot0 + slot1") 84 85 but it can be issued if we use analogous `final_presence_set'. 86 87 o (absence_set string string) means that each CPU function unit in 88 the first string can be reserved only if each pattern of units 89 whose names are in the second string is not reserved. This is an 90 asymmetric relation (actually exclusion set is analogous to this 91 one but it is symmetric). CPU units or unit patterns in the 92 string are separated by commas. Pattern is one unit name or unit 93 names separated by white-spaces. 94 95 For example, it is useful for description that slot0 cannot be 96 reserved after slot1 or slot2 reservation for a VLIW processor. 97 We could describe it by the following construction 98 99 (absence_set "slot2" "slot0, slot1") 100 101 Or slot2 cannot be reserved if slot0 and unit b0 are reserved or 102 slot1 and unit b1 are reserved . In this case we could write 103 104 (absence_set "slot2" "slot0 b0, slot1 b1") 105 106 All CPU functional units in a set should to belong the same 107 automaton. 108 109 o (final_absence_set string string) is analogous to `absence_set' but 110 checking is done on the result (state) reservation. See comments 111 for final_presence_set. 112 113 o (define_bypass number out_insn_names in_insn_names) names bypass with 114 given latency (the first number) from insns given by the first 115 string (see define_insn_reservation) into insns given by the 116 second string. Insn names in the strings are separated by 117 commas. 118 119 o (define_automaton string) describes names of an automaton 120 generated and used for pipeline hazards recognition. The names 121 are separated by comma. Actually it is possibly to generate the 122 single automaton but unfortunately it can be very large. If we 123 use more one automata, the summary size of the automata usually 124 is less than the single one. The automaton name is used in 125 define_cpu_unit. All automata should have unique names. 126 127 o (automata_option string) describes option for generation of 128 automata. Currently there are the following options: 129 130 o "no-minimization" which makes no minimization of automata. 131 This is only worth to do when we are debugging the description 132 and need to look more accurately at reservations of states. 133 134 o "ndfa" which makes automata with nondetermenistic reservation 135 by insns. 136 137 o (define_reservation string string) names reservation (the first 138 string) of cpu functional units (the 2nd string). Sometimes unit 139 reservations for different insns contain common parts. In such 140 case, you describe common part and use one its name (the 1st 141 parameter) in regular expression in define_insn_reservation. All 142 define_reservations, define results and define_cpu_units should 143 have unique names which cannot be "nothing". 144 145 o (define_insn_reservation name default_latency condition regexpr) 146 describes reservation of cpu functional units (the 3nd operand) 147 for instruction which is selected by the condition (the 2nd 148 parameter). The first parameter is used for output of debugging 149 information. The reservations are described by a regular 150 expression according the following syntax: 151 152 regexp = regexp "," oneof 153 | oneof 154 155 oneof = oneof "|" allof 156 | allof 157 158 allof = allof "+" repeat 159 | repeat 160 161 repeat = element "*" number 162 | element 163 164 element = cpu_function_name 165 | reservation_name 166 | result_name 167 | "nothing" 168 | "(" regexp ")" 169 170 1. "," is used for describing start of the next cycle in 171 reservation. 172 173 2. "|" is used for describing the reservation described by the 174 first regular expression *or* the reservation described by 175 the second regular expression *or* etc. 176 177 3. "+" is used for describing the reservation described by the 178 first regular expression *and* the reservation described by 179 the second regular expression *and* etc. 180 181 4. "*" is used for convenience and simply means sequence in 182 which the regular expression are repeated NUMBER times with 183 cycle advancing (see ","). 184 185 5. cpu function unit name which means reservation. 186 187 6. reservation name -- see define_reservation. 188 189 7. string "nothing" means no units reservation. 190 191*/ 192 193(define_automaton "one") 194 195;; All possible combinations of bundles/syllables 196(define_cpu_unit "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 197 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx" "one") 198(define_cpu_unit "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b,\ 199 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx." "one") 200(define_cpu_unit "1_0mii., 1_0mmi., 1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb.,\ 201 1_0mib., 1_0mmb., 1_0mfb." "one") 202 203(define_cpu_unit "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb,\ 204 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx" "one") 205(define_cpu_unit "1_1mi.i, 1_1mm.i, 1_1mf.i, 1_1bb.b, 1_1mb.b,\ 206 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx." "one") 207(define_cpu_unit "1_1mii., 1_1mmi., 1_1mfi., 1_1bbb., 1_1mbb.,\ 208 1_1mib., 1_1mmb., 1_1mfb." "one") 209 210;; Slot 1 211(exclusion_set "1_0m.ii" 212 "1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb,\ 213 1_0m.lx") 214(exclusion_set "1_0m.mi" 215 "1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 216(exclusion_set "1_0m.fi" 217 "1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 218(exclusion_set "1_0m.mf" 219 "1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 220(exclusion_set "1_0b.bb" "1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 221(exclusion_set "1_0m.bb" "1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 222(exclusion_set "1_0m.ib" "1_0m.mb, 1_0m.fb, 1_0m.lx") 223(exclusion_set "1_0m.mb" "1_0m.fb, 1_0m.lx") 224(exclusion_set "1_0m.fb" "1_0m.lx") 225 226;; Slot 2 227(exclusion_set "1_0mi.i" 228 "1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b,\ 229 1_0mlx.") 230(exclusion_set "1_0mm.i" 231 "1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 232(exclusion_set "1_0mf.i" 233 "1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 234(exclusion_set "1_0mm.f" 235 "1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 236(exclusion_set "1_0bb.b" "1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 237(exclusion_set "1_0mb.b" "1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 238(exclusion_set "1_0mi.b" "1_0mm.b, 1_0mf.b, 1_0mlx.") 239(exclusion_set "1_0mm.b" "1_0mf.b, 1_0mlx.") 240(exclusion_set "1_0mf.b" "1_0mlx.") 241 242;; Slot 3 243(exclusion_set "1_0mii." 244 "1_0mmi., 1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb.,\ 245 1_0mlx.") 246(exclusion_set "1_0mmi." 247 "1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 248(exclusion_set "1_0mfi." 249 "1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 250(exclusion_set "1_0mmf." 251 "1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 252(exclusion_set "1_0bbb." "1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 253(exclusion_set "1_0mbb." "1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 254(exclusion_set "1_0mib." "1_0mmb., 1_0mfb., 1_0mlx.") 255(exclusion_set "1_0mmb." "1_0mfb., 1_0mlx.") 256(exclusion_set "1_0mfb." "1_0mlx.") 257 258;; Slot 4 259(exclusion_set "1_1m.ii" 260 "1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 261(exclusion_set "1_1m.mi" 262 "1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 263(exclusion_set "1_1m.fi" 264 "1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 265(exclusion_set "1_1b.bb" "1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 266(exclusion_set "1_1m.bb" "1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 267(exclusion_set "1_1m.ib" "1_1m.mb, 1_1m.fb, 1_1m.lx") 268(exclusion_set "1_1m.mb" "1_1m.fb, 1_1m.lx") 269(exclusion_set "1_1m.fb" "1_1m.lx") 270 271;; Slot 5 272(exclusion_set "1_1mi.i" 273 "1_1mm.i, 1_1mf.i, 1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 274(exclusion_set "1_1mm.i" 275 "1_1mf.i, 1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 276(exclusion_set "1_1mf.i" 277 "1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 278(exclusion_set "1_1bb.b" "1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 279(exclusion_set "1_1mb.b" "1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 280(exclusion_set "1_1mi.b" "1_1mm.b, 1_1mf.b, 1_1mlx.") 281(exclusion_set "1_1mm.b" "1_1mf.b, 1_1mlx.") 282(exclusion_set "1_1mf.b" "1_1mlx.") 283 284;; Slot 6 285(exclusion_set "1_1mii." 286 "1_1mmi., 1_1mfi., 1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 287(exclusion_set "1_1mmi." 288 "1_1mfi., 1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 289(exclusion_set "1_1mfi." 290 "1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 291(exclusion_set "1_1bbb." "1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 292(exclusion_set "1_1mbb." "1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 293(exclusion_set "1_1mib." "1_1mmb., 1_1mfb., 1_1mlx.") 294(exclusion_set "1_1mmb." "1_1mfb., 1_1mlx.") 295(exclusion_set "1_1mfb." "1_1mlx.") 296 297(final_presence_set "1_0mi.i" "1_0m.ii") 298(final_presence_set "1_0mii." "1_0mi.i") 299(final_presence_set "1_1mi.i" "1_1m.ii") 300(final_presence_set "1_1mii." "1_1mi.i") 301 302(final_presence_set "1_0mm.i" "1_0m.mi") 303(final_presence_set "1_0mmi." "1_0mm.i") 304(final_presence_set "1_1mm.i" "1_1m.mi") 305(final_presence_set "1_1mmi." "1_1mm.i") 306 307(final_presence_set "1_0mf.i" "1_0m.fi") 308(final_presence_set "1_0mfi." "1_0mf.i") 309(final_presence_set "1_1mf.i" "1_1m.fi") 310(final_presence_set "1_1mfi." "1_1mf.i") 311 312(final_presence_set "1_0mm.f" "1_0m.mf") 313(final_presence_set "1_0mmf." "1_0mm.f") 314 315(final_presence_set "1_0bb.b" "1_0b.bb") 316(final_presence_set "1_0bbb." "1_0bb.b") 317(final_presence_set "1_1bb.b" "1_1b.bb") 318(final_presence_set "1_1bbb." "1_1bb.b") 319 320(final_presence_set "1_0mb.b" "1_0m.bb") 321(final_presence_set "1_0mbb." "1_0mb.b") 322(final_presence_set "1_1mb.b" "1_1m.bb") 323(final_presence_set "1_1mbb." "1_1mb.b") 324 325(final_presence_set "1_0mi.b" "1_0m.ib") 326(final_presence_set "1_0mib." "1_0mi.b") 327(final_presence_set "1_1mi.b" "1_1m.ib") 328(final_presence_set "1_1mib." "1_1mi.b") 329 330(final_presence_set "1_0mm.b" "1_0m.mb") 331(final_presence_set "1_0mmb." "1_0mm.b") 332(final_presence_set "1_1mm.b" "1_1m.mb") 333(final_presence_set "1_1mmb." "1_1mm.b") 334 335(final_presence_set "1_0mf.b" "1_0m.fb") 336(final_presence_set "1_0mfb." "1_0mf.b") 337(final_presence_set "1_1mf.b" "1_1m.fb") 338(final_presence_set "1_1mfb." "1_1mf.b") 339 340(final_presence_set "1_0mlx." "1_0m.lx") 341(final_presence_set "1_1mlx." "1_1m.lx") 342 343(final_presence_set 344 "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx" 345 "1_0mii.,1_0mmi.,1_0mfi.,1_0mmf.,1_0bbb.,1_0mbb.,1_0mib.,1_0mmb.,1_0mfb.,\ 346 1_0mlx.") 347 348;; Microarchitecture units: 349(define_cpu_unit 350 "1_um0, 1_um1, 1_ui0, 1_ui1, 1_uf0, 1_uf1, 1_ub0, 1_ub1, 1_ub2,\ 351 1_unb0, 1_unb1, 1_unb2" "one") 352 353(exclusion_set "1_ub0" "1_unb0") 354(exclusion_set "1_ub1" "1_unb1") 355(exclusion_set "1_ub2" "1_unb2") 356 357;; The following rules are used to decrease number of alternatives. 358;; They are consequences of Itanium microarchitecture. They also 359;; describe the following rules mentioned in Itanium 360;; microarchitecture: rules mentioned in Itanium microarchitecture: 361;; o "MMF: Always splits issue before the first M and after F regardless 362;; of surrounding bundles and stops". 363;; o "BBB/MBB: Always splits issue after either of these bundles". 364;; o "MIB BBB: Split issue after the first bundle in this pair". 365 366(exclusion_set "1_0m.mf,1_0mm.f,1_0mmf." 367 "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx") 368(exclusion_set "1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb." 369 "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx") 370(exclusion_set "1_0m.ib,1_0mi.b,1_0mib." "1_1b.bb") 371 372;; For exceptions of M, I, B, F insns: 373(define_cpu_unit "1_not_um1, 1_not_ui1, 1_not_uf1" "one") 374 375(final_absence_set "1_not_um1" "1_um1") 376(final_absence_set "1_not_ui1" "1_ui1") 377(final_absence_set "1_not_uf1" "1_uf1") 378 379;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 380;;; B-slot contains a nop.b or a brp instruction". 381;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 382;;; nop.b, otherwise it disperses to B2". 383(final_absence_set 384 "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb,\ 385 1_1m.lx" 386 "1_0mib. 1_ub2, 1_0mfb. 1_ub2, 1_0mmb. 1_ub2") 387 388;; This is necessary to start new processor cycle when we meet stop bit. 389(define_cpu_unit "1_stop" "one") 390(final_absence_set 391 "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\ 392 1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\ 393 1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\ 394 1_0m.lx,1_0mlx., \ 395 1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\ 396 1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,1_1m.ib,1_1mi.b,1_1mib.,\ 397 1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,1_1m.lx,1_1mlx." 398 "1_stop") 399 400;; M and I instruction is dispersed to the lowest numbered M or I unit 401;; not already in use. An I slot in the 3rd position of 2nd bundle is 402;; always dispersed to I1 403(final_presence_set "1_um1" "1_um0") 404(final_presence_set "1_ui1" "1_ui0, 1_1mii., 1_1mmi., 1_1mfi.") 405 406;; Insns 407 408;; M and I instruction is dispersed to the lowest numbered M or I unit 409;; not already in use. An I slot in the 3rd position of 2nd bundle is 410;; always dispersed to I1 411(define_reservation "1_M0" 412 "1_0m.ii+1_um0|1_0m.mi+1_um0|1_0mm.i+(1_um0|1_um1)\ 413 |1_0m.fi+1_um0|1_0m.mf+1_um0|1_0mm.f+1_um1\ 414 |1_0m.bb+1_um0|1_0m.ib+1_um0|1_0m.mb+1_um0\ 415 |1_0mm.b+1_um1|1_0m.fb+1_um0|1_0m.lx+1_um0\ 416 |1_1mm.i+1_um1|1_1mm.b+1_um1\ 417 |(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\ 418 +(1_um0|1_um1)") 419 420(define_reservation "1_M1" 421 "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 422 |1_0mib.+1_unb0|1_0mfb.+1_unb0|1_0mmb.+1_unb0)\ 423 +(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\ 424 +(1_um0|1_um1)") 425 426(define_reservation "1_M" "1_M0|1_M1") 427 428;; Exceptions for dispersal rules. 429;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1". 430(define_reservation "1_I0" 431 "1_0mi.i+1_ui0|1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 432 |1_0mi.b+1_ui0|(1_1mi.i|1_1mi.b)+(1_ui0|1_ui1)\ 433 |1_1mii.+1_ui1|1_1mmi.+1_ui1|1_1mfi.+1_ui1") 434 435(define_reservation "1_I1" 436 "1_0m.ii+1_um0+1_0mi.i+1_ui0|1_0mm.i+(1_um0|1_um1)+1_0mmi.+1_ui0\ 437 |1_0mf.i+1_uf0+1_0mfi.+1_ui0|1_0m.ib+1_um0+1_0mi.b+1_ui0\ 438 |(1_1m.ii+(1_um0|1_um1)+1_1mi.i\ 439 |1_1m.ib+(1_um0|1_um1)+1_1mi.b)+(1_ui0|1_ui1)\ 440 |1_1mm.i+1_um1+1_1mmi.+1_ui1|1_1mf.i+1_uf1+1_1mfi.+1_ui1") 441 442(define_reservation "1_I" "1_I0|1_I1") 443 444;; "An F slot in the 1st bundle disperses to F0". 445;; "An F slot in the 2st bundle disperses to F1". 446(define_reservation "1_F0" 447 "1_0mf.i+1_uf0|1_0mmf.+1_uf0|1_0mf.b+1_uf0|1_1mf.i+1_uf1|1_1mf.b+1_uf1") 448 449(define_reservation "1_F1" 450 "1_0m.fi+1_um0+1_0mf.i+1_uf0|1_0mm.f+(1_um0|1_um1)+1_0mmf.+1_uf0\ 451 |1_0m.fb+1_um0+1_0mf.b+1_uf0|1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\ 452 |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1") 453 454(define_reservation "1_F2" 455 "1_0m.mf+1_um0+1_0mm.f+1_um1+1_0mmf.+1_uf0\ 456 |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 457 |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0)\ 458 +(1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\ 459 |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1)") 460 461(define_reservation "1_F" "1_F0|1_F1|1_F2") 462 463;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 464;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 465;;; 2nd position it is dispersed to B2". 466(define_reservation "1_NB" 467 "1_0b.bb+1_unb0|1_0bb.b+1_unb1|1_0bbb.+1_unb2\ 468 |1_0mb.b+1_unb1|1_0mbb.+1_unb2\ 469 |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0\ 470 |1_1b.bb+1_unb0|1_1bb.b+1_unb1\ 471 |1_1bbb.+1_unb2|1_1mb.b+1_unb1|1_1mbb.+1_unb2|1_1mib.+1_unb0\ 472 |1_1mmb.+1_unb0|1_1mfb.+1_unb0") 473 474(define_reservation "1_B0" 475 "1_0b.bb+1_ub0|1_0bb.b+1_ub1|1_0bbb.+1_ub2\ 476 |1_0mb.b+1_ub1|1_0mbb.+1_ub2|1_0mib.+1_ub2\ 477 |1_0mfb.+1_ub2|1_1b.bb+1_ub0|1_1bb.b+1_ub1\ 478 |1_1bbb.+1_ub2|1_1mb.b+1_ub1\ 479 |1_1mib.+1_ub2|1_1mmb.+1_ub2|1_1mfb.+1_ub2") 480 481(define_reservation "1_B1" 482 "1_0m.bb+1_um0+1_0mb.b+1_ub1|1_0mi.b+1_ui0+1_0mib.+1_ub2\ 483 |1_0mf.b+1_uf0+1_0mfb.+1_ub2\ 484 |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0)+1_1b.bb+1_ub0\ 485 |1_1m.bb+(1_um0|1_um1)+1_1mb.b+1_ub1\ 486 |1_1mi.b+(1_ui0|1_ui1)+1_1mib.+1_ub2\ 487 |1_1mm.b+1_um1+1_1mmb.+1_ub2\ 488 |1_1mf.b+1_uf1+1_1mfb.+1_ub2") 489 490(define_reservation "1_B" "1_B0|1_B1") 491 492;; MLX bunlde uses ports equivalent to MFI bundles. 493(define_reservation "1_L0" "1_0mlx.+1_ui0+1_uf0|1_1mlx.+(1_ui0|1_ui1)+1_uf1") 494(define_reservation "1_L1" 495 "1_0m.lx+1_um0+1_0mlx.+1_ui0+1_uf0\ 496 |1_1m.lx+(1_um0|1_um1)+1_1mlx.+(1_ui0|1_ui1)+1_uf1") 497(define_reservation "1_L2" 498 "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 499 |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0) 500 +1_1m.lx+(1_um0|1_um1)+1_1mlx.+1_ui1+1_uf1") 501(define_reservation "1_L" "1_L0|1_L1|1_L2") 502 503(define_reservation "1_A" "1_M|1_I") 504 505(define_insn_reservation "1_stop_bit" 0 506 (and (and (eq_attr "cpu" "itanium") 507 (eq_attr "itanium_class" "stop_bit")) 508 (eq (symbol_ref "bundling_p") (const_int 0))) 509 "1_stop|1_m0_stop|1_m1_stop|1_mi0_stop|1_mi1_stop") 510 511(define_insn_reservation "1_br" 0 512 (and (and (eq_attr "cpu" "itanium") 513 (eq_attr "itanium_class" "br")) 514 (eq (symbol_ref "bundling_p") (const_int 0))) "1_B") 515(define_insn_reservation "1_scall" 0 516 (and (and (eq_attr "cpu" "itanium") 517 (eq_attr "itanium_class" "scall")) 518 (eq (symbol_ref "bundling_p") (const_int 0))) "1_B") 519(define_insn_reservation "1_fcmp" 2 520 (and (and (eq_attr "cpu" "itanium") 521 (eq_attr "itanium_class" "fcmp")) 522 (eq (symbol_ref "bundling_p") (const_int 0))) 523 "1_F+1_not_uf1") 524(define_insn_reservation "1_fcvtfx" 7 525 (and (and (eq_attr "cpu" "itanium") 526 (eq_attr "itanium_class" "fcvtfx")) 527 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F") 528 529(define_insn_reservation "1_fld" 9 530 (and (and (and (eq_attr "cpu" "itanium") 531 (eq_attr "itanium_class" "fld")) 532 (eq_attr "check_load" "no")) 533 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 534(define_insn_reservation "1_fldc" 0 535 (and (and (and (eq_attr "cpu" "itanium") 536 (eq_attr "itanium_class" "fld")) 537 (eq_attr "check_load" "yes")) 538 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 539 540(define_insn_reservation "1_fldp" 9 541 (and (and (and (eq_attr "cpu" "itanium") 542 (eq_attr "itanium_class" "fldp")) 543 (eq_attr "check_load" "no")) 544 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 545(define_insn_reservation "1_fldpc" 0 546 (and (and (and (eq_attr "cpu" "itanium") 547 (eq_attr "itanium_class" "fldp")) 548 (eq_attr "check_load" "yes")) 549 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 550 551(define_insn_reservation "1_fmac" 5 552 (and (and (eq_attr "cpu" "itanium") 553 (eq_attr "itanium_class" "fmac")) 554 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F") 555(define_insn_reservation "1_fmisc" 5 556 (and (and (eq_attr "cpu" "itanium") 557 (eq_attr "itanium_class" "fmisc")) 558 (eq (symbol_ref "bundling_p") (const_int 0))) 559 "1_F+1_not_uf1") 560 561;; There is only one insn `mov = ar.bsp' for frar_i: 562(define_insn_reservation "1_frar_i" 13 563 (and (and (eq_attr "cpu" "itanium") 564 (eq_attr "itanium_class" "frar_i")) 565 (eq (symbol_ref "bundling_p") (const_int 0))) 566 "1_I+1_not_ui1") 567;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m: 568(define_insn_reservation "1_frar_m" 6 569 (and (and (eq_attr "cpu" "itanium") 570 (eq_attr "itanium_class" "frar_m")) 571 (eq (symbol_ref "bundling_p") (const_int 0))) 572 "1_M+1_not_um1") 573(define_insn_reservation "1_frbr" 2 574 (and (and (eq_attr "cpu" "itanium") 575 (eq_attr "itanium_class" "frbr")) 576 (eq (symbol_ref "bundling_p") (const_int 0))) 577 "1_I+1_not_ui1") 578(define_insn_reservation "1_frfr" 2 579 (and (and (eq_attr "cpu" "itanium") 580 (eq_attr "itanium_class" "frfr")) 581 (eq (symbol_ref "bundling_p") (const_int 0))) 582 "1_M+1_not_um1") 583(define_insn_reservation "1_frpr" 2 584 (and (and (eq_attr "cpu" "itanium") 585 (eq_attr "itanium_class" "frpr")) 586 (eq (symbol_ref "bundling_p") (const_int 0))) 587 "1_I+1_not_ui1") 588 589(define_insn_reservation "1_ialu" 1 590 (and (and (eq_attr "cpu" "itanium") 591 (eq_attr "itanium_class" "ialu")) 592 (eq (symbol_ref 593 "bundling_p || ia64_produce_address_p (insn)") 594 (const_int 0))) 595 "1_A") 596(define_insn_reservation "1_ialu_addr" 1 597 (and (and (eq_attr "cpu" "itanium") 598 (eq_attr "itanium_class" "ialu")) 599 (eq (symbol_ref 600 "!bundling_p && ia64_produce_address_p (insn)") 601 (const_int 1))) 602 "1_M") 603(define_insn_reservation "1_icmp" 1 604 (and (and (eq_attr "cpu" "itanium") 605 (eq_attr "itanium_class" "icmp")) 606 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A") 607(define_insn_reservation "1_ilog" 1 608 (and (and (eq_attr "cpu" "itanium") 609 (eq_attr "itanium_class" "ilog")) 610 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A") 611(define_insn_reservation "1_mmalua" 2 612 (and (and (eq_attr "cpu" "itanium") 613 (eq_attr "itanium_class" "mmalua")) 614 (eq (symbol_ref "bundling_p") (const_int 0))) 615 "1_A") 616(define_insn_reservation "1_ishf" 1 617 (and (and (eq_attr "cpu" "itanium") 618 (eq_attr "itanium_class" "ishf")) 619 (eq (symbol_ref "bundling_p") (const_int 0))) 620 "1_I+1_not_ui1") 621(define_insn_reservation "1_ld" 2 622 (and (and (and (eq_attr "cpu" "itanium") 623 (eq_attr "itanium_class" "ld")) 624 (eq_attr "check_load" "no")) 625 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 626(define_insn_reservation "1_ldc" 0 627 (and (and (and (eq_attr "cpu" "itanium") 628 (eq_attr "itanium_class" "ld")) 629 (eq_attr "check_load" "yes")) 630 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 631(define_insn_reservation "1_long_i" 1 632 (and (and (eq_attr "cpu" "itanium") 633 (eq_attr "itanium_class" "long_i")) 634 (eq (symbol_ref "bundling_p") (const_int 0))) "1_L") 635(define_insn_reservation "1_mmmul" 2 636 (and (and (eq_attr "cpu" "itanium") 637 (eq_attr "itanium_class" "mmmul")) 638 (eq (symbol_ref "bundling_p") (const_int 0))) 639 "1_I+1_not_ui1") 640(define_insn_reservation "1_mmshf" 2 641 (and (and (eq_attr "cpu" "itanium") 642 (eq_attr "itanium_class" "mmshf")) 643 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I") 644(define_insn_reservation "1_mmshfi" 1 645 (and (and (eq_attr "cpu" "itanium") 646 (eq_attr "itanium_class" "mmshfi")) 647 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I") 648 649;; Now we have only one insn (flushrs) of such class. We assume that flushrs 650;; is the 1st syllable of the bundle after stop bit. 651(define_insn_reservation "1_rse_m" 0 652 (and (and (eq_attr "cpu" "itanium") 653 (eq_attr "itanium_class" "rse_m")) 654 (eq (symbol_ref "bundling_p") (const_int 0))) 655 "(1_0m.ii|1_0m.mi|1_0m.fi|1_0m.mf|1_0b.bb|1_0m.bb\ 656 |1_0m.ib|1_0m.mb|1_0m.fb|1_0m.lx)+1_um0") 657(define_insn_reservation "1_sem" 0 658 (and (and (eq_attr "cpu" "itanium") 659 (eq_attr "itanium_class" "sem")) 660 (eq (symbol_ref "bundling_p") (const_int 0))) 661 "1_M+1_not_um1") 662(define_insn_reservation "1_stf" 1 663 (and (and (eq_attr "cpu" "itanium") 664 (eq_attr "itanium_class" "stf")) 665 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 666(define_insn_reservation "1_st" 1 667 (and (and (eq_attr "cpu" "itanium") 668 (eq_attr "itanium_class" "st")) 669 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 670(define_insn_reservation "1_syst_m0" 0 671 (and (and (eq_attr "cpu" "itanium") 672 (eq_attr "itanium_class" "syst_m0")) 673 (eq (symbol_ref "bundling_p") (const_int 0))) 674 "1_M+1_not_um1") 675(define_insn_reservation "1_syst_m" 0 676 (and (and (eq_attr "cpu" "itanium") 677 (eq_attr "itanium_class" "syst_m")) 678 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 679(define_insn_reservation "1_tbit" 1 680 (and (and (eq_attr "cpu" "itanium") 681 (eq_attr "itanium_class" "tbit")) 682 (eq (symbol_ref "bundling_p") (const_int 0))) 683 "1_I+1_not_ui1") 684 685;; There is only ony insn `mov ar.pfs =' for toar_i: 686(define_insn_reservation "1_toar_i" 0 687 (and (and (eq_attr "cpu" "itanium") 688 (eq_attr "itanium_class" "toar_i")) 689 (eq (symbol_ref "bundling_p") (const_int 0))) 690 "1_I+1_not_ui1") 691;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: 692(define_insn_reservation "1_toar_m" 5 693 (and (and (eq_attr "cpu" "itanium") 694 (eq_attr "itanium_class" "toar_m")) 695 (eq (symbol_ref "bundling_p") (const_int 0))) 696 "1_M+1_not_um1") 697(define_insn_reservation "1_tobr" 1 698 (and (and (eq_attr "cpu" "itanium") 699 (eq_attr "itanium_class" "tobr")) 700 (eq (symbol_ref "bundling_p") (const_int 0))) 701 "1_I+1_not_ui1") 702(define_insn_reservation "1_tofr" 9 703 (and (and (eq_attr "cpu" "itanium") 704 (eq_attr "itanium_class" "tofr")) 705 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 706(define_insn_reservation "1_topr" 1 707 (and (and (eq_attr "cpu" "itanium") 708 (eq_attr "itanium_class" "topr")) 709 (eq (symbol_ref "bundling_p") (const_int 0))) 710 "1_I+1_not_ui1") 711(define_insn_reservation "1_xmpy" 7 712 (and (and (eq_attr "cpu" "itanium") 713 (eq_attr "itanium_class" "xmpy")) 714 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F") 715(define_insn_reservation "1_xtd" 1 716 (and (and (eq_attr "cpu" "itanium") 717 (eq_attr "itanium_class" "xtd")) 718 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I") 719 720(define_insn_reservation "1_chk_s_i" 0 721 (and (and (eq_attr "cpu" "itanium") 722 (eq_attr "itanium_class" "chk_s_i")) 723 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A") 724(define_insn_reservation "1_chk_s_f" 0 725 (and (and (eq_attr "cpu" "itanium") 726 (eq_attr "itanium_class" "chk_s_f")) 727 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 728(define_insn_reservation "1_chk_a" 0 729 (and (and (eq_attr "cpu" "itanium") 730 (eq_attr "itanium_class" "chk_a")) 731 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 732 733(define_insn_reservation "1_lfetch" 0 734 (and (and (eq_attr "cpu" "itanium") 735 (eq_attr "itanium_class" "lfetch")) 736 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 737 738(define_insn_reservation "1_nop_m" 0 739 (and (and (eq_attr "cpu" "itanium") 740 (eq_attr "itanium_class" "nop_m")) 741 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M0") 742(define_insn_reservation "1_nop_b" 0 743 (and (and (eq_attr "cpu" "itanium") 744 (eq_attr "itanium_class" "nop_b")) 745 (eq (symbol_ref "bundling_p") (const_int 0))) "1_NB") 746(define_insn_reservation "1_nop_i" 0 747 (and (and (eq_attr "cpu" "itanium") 748 (eq_attr "itanium_class" "nop_i")) 749 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I0") 750(define_insn_reservation "1_nop_f" 0 751 (and (and (eq_attr "cpu" "itanium") 752 (eq_attr "itanium_class" "nop_f")) 753 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F0") 754(define_insn_reservation "1_nop_x" 0 755 (and (and (eq_attr "cpu" "itanium") 756 (eq_attr "itanium_class" "nop_x")) 757 (eq (symbol_ref "bundling_p") (const_int 0))) "1_L0") 758 759;; We assume that there is no insn issued on the same cycle as unknown insn. 760(define_cpu_unit "1_empty" "one") 761(exclusion_set "1_empty" 762 "1_0m.ii,1_0m.mi,1_0m.fi,1_0m.mf,1_0b.bb,1_0m.bb,1_0m.ib,1_0m.mb,1_0m.fb,\ 763 1_0m.lx") 764 765(define_insn_reservation "1_unknown" 1 766 (and (and (eq_attr "cpu" "itanium") 767 (eq_attr "itanium_class" "unknown")) 768 (eq (symbol_ref "bundling_p") (const_int 0))) "1_empty") 769 770(define_insn_reservation "1_nop" 1 771 (and (and (eq_attr "cpu" "itanium") 772 (eq_attr "itanium_class" "nop")) 773 (eq (symbol_ref "bundling_p") (const_int 0))) 774 "1_M0|1_NB|1_I0|1_F0") 775 776(define_insn_reservation "1_ignore" 0 777 (and (and (eq_attr "cpu" "itanium") 778 (eq_attr "itanium_class" "ignore")) 779 (eq (symbol_ref "bundling_p") (const_int 0))) "nothing") 780 781 782(define_cpu_unit 783 "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs" 784 "one") 785(define_cpu_unit 786 "1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs" 787 "one") 788 789(define_cpu_unit "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont, 1_mb_cont,\ 790 1_b_cont, 1_bb_cont" "one") 791 792;; For stop in the middle of the bundles. 793(define_cpu_unit "1_m_stop, 1_m0_stop, 1_m1_stop, 1_0mmi_cont" "one") 794(define_cpu_unit "1_mi_stop, 1_mi0_stop, 1_mi1_stop, 1_0mii_cont" "one") 795 796(final_presence_set "1_0m_bs" 797 "1_0m.ii, 1_0m.mi, 1_0m.mf, 1_0m.fi, 1_0m.bb,\ 798 1_0m.ib, 1_0m.fb, 1_0m.mb, 1_0m.lx") 799(final_presence_set "1_1m_bs" 800 "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1m.bb, 1_1m.ib, 1_1m.fb, 1_1m.mb,\ 801 1_1m.lx") 802(final_presence_set "1_0mi_bs" "1_0mi.i, 1_0mi.i") 803(final_presence_set "1_1mi_bs" "1_1mi.i, 1_1mi.i") 804(final_presence_set "1_0mm_bs" "1_0mm.i, 1_0mm.f, 1_0mm.b") 805(final_presence_set "1_1mm_bs" "1_1mm.i, 1_1mm.b") 806(final_presence_set "1_0mf_bs" "1_0mf.i, 1_0mf.b") 807(final_presence_set "1_1mf_bs" "1_1mf.i, 1_1mf.b") 808(final_presence_set "1_0b_bs" "1_0b.bb") 809(final_presence_set "1_1b_bs" "1_1b.bb") 810(final_presence_set "1_0bb_bs" "1_0bb.b") 811(final_presence_set "1_1bb_bs" "1_1bb.b") 812(final_presence_set "1_0mb_bs" "1_0mb.b") 813(final_presence_set "1_1mb_bs" "1_1mb.b") 814 815(exclusion_set "1_0m_bs" 816 "1_0mi.i, 1_0mm.i, 1_0mm.f, 1_0mf.i, 1_0mb.b,\ 817 1_0mi.b, 1_0mf.b, 1_0mm.b, 1_0mlx., 1_m0_stop") 818(exclusion_set "1_1m_bs" 819 "1_1mi.i, 1_1mm.i, 1_1mf.i, 1_1mb.b, 1_1mi.b, 1_1mf.b, 1_1mm.b,\ 820 1_1mlx., 1_m1_stop") 821(exclusion_set "1_0mi_bs" "1_0mii., 1_0mib., 1_mi0_stop") 822(exclusion_set "1_1mi_bs" "1_1mii., 1_1mib., 1_mi1_stop") 823(exclusion_set "1_0mm_bs" "1_0mmi., 1_0mmf., 1_0mmb.") 824(exclusion_set "1_1mm_bs" "1_1mmi., 1_1mmb.") 825(exclusion_set "1_0mf_bs" "1_0mfi., 1_0mfb.") 826(exclusion_set "1_1mf_bs" "1_1mfi., 1_1mfb.") 827(exclusion_set "1_0b_bs" "1_0bb.b") 828(exclusion_set "1_1b_bs" "1_1bb.b") 829(exclusion_set "1_0bb_bs" "1_0bbb.") 830(exclusion_set "1_1bb_bs" "1_1bbb.") 831(exclusion_set "1_0mb_bs" "1_0mbb.") 832(exclusion_set "1_1mb_bs" "1_1mbb.") 833 834(exclusion_set 835 "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs, 836 1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs" 837 "1_stop") 838 839(final_presence_set 840 "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\ 841 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx." 842 "1_m_cont") 843(final_presence_set "1_0mii., 1_0mib." "1_mi_cont") 844(final_presence_set "1_0mmi., 1_0mmf., 1_0mmb." "1_mm_cont") 845(final_presence_set "1_0mfi., 1_0mfb." "1_mf_cont") 846(final_presence_set "1_0bb.b" "1_b_cont") 847(final_presence_set "1_0bbb." "1_bb_cont") 848(final_presence_set "1_0mbb." "1_mb_cont") 849 850(exclusion_set 851 "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 852 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx" 853 "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont,\ 854 1_mb_cont, 1_b_cont, 1_bb_cont") 855 856(exclusion_set "1_empty" 857 "1_m_cont,1_mi_cont,1_mm_cont,1_mf_cont,\ 858 1_mb_cont,1_b_cont,1_bb_cont") 859 860;; For m;mi bundle 861(final_presence_set "1_m0_stop" "1_0m.mi") 862(final_presence_set "1_0mm.i" "1_0mmi_cont") 863(exclusion_set "1_0mmi_cont" 864 "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 865 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 866(exclusion_set "1_m0_stop" "1_0mm.i") 867(final_presence_set "1_m1_stop" "1_1m.mi") 868(exclusion_set "1_m1_stop" "1_1mm.i") 869(final_presence_set "1_m_stop" "1_m0_stop, 1_m1_stop") 870 871;; For mi;i bundle 872(final_presence_set "1_mi0_stop" "1_0mi.i") 873(final_presence_set "1_0mii." "1_0mii_cont") 874(exclusion_set "1_0mii_cont" 875 "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 876 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 877(exclusion_set "1_mi0_stop" "1_0mii.") 878(final_presence_set "1_mi1_stop" "1_1mi.i") 879(exclusion_set "1_mi1_stop" "1_1mii.") 880(final_presence_set "1_mi_stop" "1_mi0_stop, 1_mi1_stop") 881 882(final_absence_set 883 "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\ 884 1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\ 885 1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\ 886 1_0m.lx,1_0mlx., \ 887 1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\ 888 1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,\ 889 1_1m.ib,1_1mi.b,1_1mib.,1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,\ 890 1_1m.lx,1_1mlx." 891 "1_m0_stop,1_m1_stop,1_mi0_stop,1_mi1_stop") 892 893(define_cpu_unit "1_m_cont_only, 1_b_cont_only" "one") 894(define_cpu_unit "1_mi_cont_only, 1_mm_cont_only, 1_mf_cont_only" "one") 895(define_cpu_unit "1_mb_cont_only, 1_bb_cont_only" "one") 896 897(final_presence_set "1_m_cont_only" "1_m_cont") 898(exclusion_set "1_m_cont_only" 899 "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\ 900 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 901 902(final_presence_set "1_b_cont_only" "1_b_cont") 903(exclusion_set "1_b_cont_only" "1_0bb.b") 904 905(final_presence_set "1_mi_cont_only" "1_mi_cont") 906(exclusion_set "1_mi_cont_only" "1_0mii., 1_0mib.") 907 908(final_presence_set "1_mm_cont_only" "1_mm_cont") 909(exclusion_set "1_mm_cont_only" "1_0mmi., 1_0mmf., 1_0mmb.") 910 911(final_presence_set "1_mf_cont_only" "1_mf_cont") 912(exclusion_set "1_mf_cont_only" "1_0mfi., 1_0mfb.") 913 914(final_presence_set "1_mb_cont_only" "1_mb_cont") 915(exclusion_set "1_mb_cont_only" "1_0mbb.") 916 917(final_presence_set "1_bb_cont_only" "1_bb_cont") 918(exclusion_set "1_bb_cont_only" "1_0bbb.") 919 920(define_insn_reservation "1_pre_cycle" 0 921 (and (and (eq_attr "cpu" "itanium") 922 (eq_attr "itanium_class" "pre_cycle")) 923 (eq (symbol_ref "bundling_p") (const_int 0))) 924 "(1_0m_bs, 1_m_cont) \ 925 | (1_0mi_bs, (1_mi_cont|nothing)) \ 926 | (1_0mm_bs, 1_mm_cont) \ 927 | (1_0mf_bs, (1_mf_cont|nothing)) \ 928 | (1_0b_bs, (1_b_cont|nothing)) \ 929 | (1_0bb_bs, (1_bb_cont|nothing)) \ 930 | (1_0mb_bs, (1_mb_cont|nothing)) \ 931 | (1_1m_bs, 1_m_cont) \ 932 | (1_1mi_bs, (1_mi_cont|nothing)) \ 933 | (1_1mm_bs, 1_mm_cont) \ 934 | (1_1mf_bs, (1_mf_cont|nothing)) \ 935 | (1_1b_bs, (1_b_cont|nothing)) \ 936 | (1_1bb_bs, (1_bb_cont|nothing)) \ 937 | (1_1mb_bs, (1_mb_cont|nothing)) \ 938 | (1_m_cont_only, (1_m_cont|nothing)) \ 939 | (1_b_cont_only, (1_b_cont|nothing)) \ 940 | (1_mi_cont_only, (1_mi_cont|nothing)) \ 941 | (1_mm_cont_only, (1_mm_cont|nothing)) \ 942 | (1_mf_cont_only, (1_mf_cont|nothing)) \ 943 | (1_mb_cont_only, (1_mb_cont|nothing)) \ 944 | (1_bb_cont_only, (1_bb_cont|nothing)) \ 945 | (1_m_stop, (1_0mmi_cont|nothing)) \ 946 | (1_mi_stop, (1_0mii_cont|nothing))") 947 948;; Bypasses: 949(define_bypass 1 "1_fcmp" "1_br,1_scall") 950;; ??? I found 7 cycle delay for 1_fmac -> 1_fcmp for Itanium1 951(define_bypass 7 "1_fmac" "1_fmisc,1_fcvtfx,1_xmpy,1_fcmp") 952 953;; ??? 954(define_bypass 3 "1_frbr" "1_mmmul,1_mmshf") 955(define_bypass 14 "1_frar_i" "1_mmmul,1_mmshf") 956(define_bypass 7 "1_frar_m" "1_mmmul,1_mmshf") 957 958;; ???? 959;; There is only one insn `mov ar.pfs =' for toar_i. 960(define_bypass 0 "1_tobr,1_topr,1_toar_i" "1_br,1_scall") 961 962(define_bypass 3 "1_ialu,1_ialu_addr" "1_mmmul,1_mmshf,1_mmalua") 963;; ??? howto describe ialu for I slot only. We use ialu_addr for that 964;;(define_bypass 2 "1_ialu" "1_ld" "ia64_ld_address_bypass_p") 965;; ??? howto describe ialu st/address for I slot only. We use ialu_addr 966;; for that. 967;;(define_bypass 2 "1_ialu" "1_st" "ia64_st_address_bypass_p") 968 969(define_bypass 0 "1_icmp" "1_br,1_scall") 970 971(define_bypass 3 "1_ilog" "1_mmmul,1_mmshf") 972 973(define_bypass 2 "1_ilog,1_xtd" "1_ld" "ia64_ld_address_bypass_p") 974(define_bypass 2 "1_ilog,1_xtd" "1_st" "ia64_st_address_bypass_p") 975 976(define_bypass 3 "1_ld,1_ldc" "1_mmmul,1_mmshf") 977(define_bypass 3 "1_ld" "1_ld" "ia64_ld_address_bypass_p") 978(define_bypass 3 "1_ld" "1_st" "ia64_st_address_bypass_p") 979 980;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4, 981;; but HP engineers say any non-MM operation. 982(define_bypass 4 "1_mmmul,1_mmshf,1_mmalua" 983 "1_br,1_fcmp,1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\ 984 1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,1_chk_s_i,1_chk_s_f,1_chk_a,\ 985 1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\ 986 1_tbit,1_toar_i,1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd") 987 988;; ??? how to describe that if scheduled < 4 cycle then latency is 10 cycles. 989;; (define_bypass 10 "1_mmmul,1_mmshf" "1_ialu,1_ilog,1_ishf,1_st,1_ld") 990 991(define_bypass 0 "1_tbit" "1_br,1_scall") 992 993(define_bypass 8 "1_tofr" "1_frfr,1_stf") 994(define_bypass 7 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_frfr") 995(define_bypass 8 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_stf") 996 997;; We don't use here fcmp because scall may be predicated. 998(define_bypass 0 "1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\ 999 1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\ 1000 1_ld,1_ldc,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,\ 1001 1_toar_m,1_tofr,1_xmpy,1_xtd" "1_scall") 1002 1003(define_bypass 0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\ 1004 1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\ 1005 1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,\ 1006 1_chk_s_i,1_chk_s_f,1_chk_a,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_nop,\ 1007 1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\ 1008 1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\ 1009 1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch" 1010 "1_ignore") 1011 1012 1013;; Bundling 1014 1015(define_automaton "oneb") 1016 1017;; Pseudo units for quicker searching for position in two packet window. */ 1018(define_query_cpu_unit "1_1,1_2,1_3,1_4,1_5,1_6" "oneb") 1019 1020;; All possible combinations of bundles/syllables 1021(define_cpu_unit 1022 "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1023 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx" "oneb") 1024(define_cpu_unit 1025 "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\ 1026 1b_0mi.b, 1b_0mm.b, 1b_0mf.b" "oneb") 1027(define_query_cpu_unit 1028 "1b_0mii., 1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\ 1029 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx." "oneb") 1030 1031(define_cpu_unit "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\ 1032 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx" "oneb") 1033(define_cpu_unit "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\ 1034 1b_1mi.b, 1b_1mm.b, 1b_1mf.b" "oneb") 1035(define_query_cpu_unit "1b_1mii., 1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\ 1036 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx." "oneb") 1037 1038;; Slot 1 1039(exclusion_set "1b_0m.ii" 1040 "1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1041 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1042(exclusion_set "1b_0m.mi" 1043 "1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib,\ 1044 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1045(exclusion_set "1b_0m.fi" 1046 "1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1047(exclusion_set "1b_0m.mf" 1048 "1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1049(exclusion_set "1b_0b.bb" "1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1050(exclusion_set "1b_0m.bb" "1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1051(exclusion_set "1b_0m.ib" "1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1052(exclusion_set "1b_0m.mb" "1b_0m.fb, 1b_0m.lx") 1053(exclusion_set "1b_0m.fb" "1b_0m.lx") 1054 1055;; Slot 2 1056(exclusion_set "1b_0mi.i" 1057 "1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\ 1058 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1059(exclusion_set "1b_0mm.i" 1060 "1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\ 1061 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1062(exclusion_set "1b_0mf.i" 1063 "1b_0mm.f, 1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1064(exclusion_set "1b_0mm.f" 1065 "1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1066(exclusion_set "1b_0bb.b" "1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1067(exclusion_set "1b_0mb.b" "1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1068(exclusion_set "1b_0mi.b" "1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1069(exclusion_set "1b_0mm.b" "1b_0mf.b, 1b_0mlx.") 1070(exclusion_set "1b_0mf.b" "1b_0mlx.") 1071 1072;; Slot 3 1073(exclusion_set "1b_0mii." 1074 "1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\ 1075 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1076(exclusion_set "1b_0mmi." 1077 "1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\ 1078 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1079(exclusion_set "1b_0mfi." 1080 "1b_0mmf., 1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1081(exclusion_set "1b_0mmf." 1082 "1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1083(exclusion_set "1b_0bbb." "1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1084(exclusion_set "1b_0mbb." "1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1085(exclusion_set "1b_0mib." "1b_0mmb., 1b_0mfb., 1b_0mlx.") 1086(exclusion_set "1b_0mmb." "1b_0mfb., 1b_0mlx.") 1087(exclusion_set "1b_0mfb." "1b_0mlx.") 1088 1089;; Slot 4 1090(exclusion_set "1b_1m.ii" 1091 "1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\ 1092 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1093(exclusion_set "1b_1m.mi" 1094 "1b_1m.fi, 1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1095(exclusion_set "1b_1m.fi" 1096 "1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1097(exclusion_set "1b_1b.bb" "1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1098(exclusion_set "1b_1m.bb" "1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1099(exclusion_set "1b_1m.ib" "1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1100(exclusion_set "1b_1m.mb" "1b_1m.fb, 1b_1m.lx") 1101(exclusion_set "1b_1m.fb" "1b_1m.lx") 1102 1103;; Slot 5 1104(exclusion_set "1b_1mi.i" 1105 "1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\ 1106 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1107(exclusion_set "1b_1mm.i" 1108 "1b_1mf.i, 1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1109(exclusion_set "1b_1mf.i" 1110 "1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1111(exclusion_set "1b_1bb.b" "1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1112(exclusion_set "1b_1mb.b" "1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1113(exclusion_set "1b_1mi.b" "1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1114(exclusion_set "1b_1mm.b" "1b_1mf.b, 1b_1mlx.") 1115(exclusion_set "1b_1mf.b" "1b_1mlx.") 1116 1117;; Slot 6 1118(exclusion_set "1b_1mii." 1119 "1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\ 1120 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1121(exclusion_set "1b_1mmi." 1122 "1b_1mfi., 1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1123(exclusion_set "1b_1mfi." 1124 "1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1125(exclusion_set "1b_1bbb." "1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1126(exclusion_set "1b_1mbb." "1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1127(exclusion_set "1b_1mib." "1b_1mmb., 1b_1mfb., 1b_1mlx.") 1128(exclusion_set "1b_1mmb." "1b_1mfb., 1b_1mlx.") 1129(exclusion_set "1b_1mfb." "1b_1mlx.") 1130 1131(final_presence_set "1b_0mi.i" "1b_0m.ii") 1132(final_presence_set "1b_0mii." "1b_0mi.i") 1133(final_presence_set "1b_1mi.i" "1b_1m.ii") 1134(final_presence_set "1b_1mii." "1b_1mi.i") 1135 1136(final_presence_set "1b_0mm.i" "1b_0m.mi") 1137(final_presence_set "1b_0mmi." "1b_0mm.i") 1138(final_presence_set "1b_1mm.i" "1b_1m.mi") 1139(final_presence_set "1b_1mmi." "1b_1mm.i") 1140 1141(final_presence_set "1b_0mf.i" "1b_0m.fi") 1142(final_presence_set "1b_0mfi." "1b_0mf.i") 1143(final_presence_set "1b_1mf.i" "1b_1m.fi") 1144(final_presence_set "1b_1mfi." "1b_1mf.i") 1145 1146(final_presence_set "1b_0mm.f" "1b_0m.mf") 1147(final_presence_set "1b_0mmf." "1b_0mm.f") 1148 1149(final_presence_set "1b_0bb.b" "1b_0b.bb") 1150(final_presence_set "1b_0bbb." "1b_0bb.b") 1151(final_presence_set "1b_1bb.b" "1b_1b.bb") 1152(final_presence_set "1b_1bbb." "1b_1bb.b") 1153 1154(final_presence_set "1b_0mb.b" "1b_0m.bb") 1155(final_presence_set "1b_0mbb." "1b_0mb.b") 1156(final_presence_set "1b_1mb.b" "1b_1m.bb") 1157(final_presence_set "1b_1mbb." "1b_1mb.b") 1158 1159(final_presence_set "1b_0mi.b" "1b_0m.ib") 1160(final_presence_set "1b_0mib." "1b_0mi.b") 1161(final_presence_set "1b_1mi.b" "1b_1m.ib") 1162(final_presence_set "1b_1mib." "1b_1mi.b") 1163 1164(final_presence_set "1b_0mm.b" "1b_0m.mb") 1165(final_presence_set "1b_0mmb." "1b_0mm.b") 1166(final_presence_set "1b_1mm.b" "1b_1m.mb") 1167(final_presence_set "1b_1mmb." "1b_1mm.b") 1168 1169(final_presence_set "1b_0mf.b" "1b_0m.fb") 1170(final_presence_set "1b_0mfb." "1b_0mf.b") 1171(final_presence_set "1b_1mf.b" "1b_1m.fb") 1172(final_presence_set "1b_1mfb." "1b_1mf.b") 1173 1174(final_presence_set "1b_0mlx." "1b_0m.lx") 1175(final_presence_set "1b_1mlx." "1b_1m.lx") 1176 1177(final_presence_set 1178 "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\ 1179 1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx" 1180 "1b_0mii.,1b_0mmi.,1b_0mfi.,1b_0mmf.,1b_0bbb.,1b_0mbb.,\ 1181 1b_0mib.,1b_0mmb.,1b_0mfb.,1b_0mlx.") 1182 1183;; Microarchitecture units: 1184(define_cpu_unit 1185 "1b_um0, 1b_um1, 1b_ui0, 1b_ui1, 1b_uf0, 1b_uf1, 1b_ub0, 1b_ub1, 1b_ub2,\ 1186 1b_unb0, 1b_unb1, 1b_unb2" "oneb") 1187 1188(exclusion_set "1b_ub0" "1b_unb0") 1189(exclusion_set "1b_ub1" "1b_unb1") 1190(exclusion_set "1b_ub2" "1b_unb2") 1191 1192;; The following rules are used to decrease number of alternatives. 1193;; They are consequences of Itanium microarchitecture. They also 1194;; describe the following rules mentioned in Itanium 1195;; microarchitecture: rules mentioned in Itanium microarchitecture: 1196;; o "MMF: Always splits issue before the first M and after F regardless 1197;; of surrounding bundles and stops". 1198;; o "BBB/MBB: Always splits issue after either of these bundles". 1199;; o "MIB BBB: Split issue after the first bundle in this pair". 1200 1201(exclusion_set "1b_0m.mf,1b_0mm.f,1b_0mmf." 1202 "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\ 1203 1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx") 1204(exclusion_set "1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb." 1205 "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\ 1206 1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx") 1207(exclusion_set "1b_0m.ib,1b_0mi.b,1b_0mib." "1b_1b.bb") 1208 1209;; For exceptions of M, I, B, F insns: 1210(define_cpu_unit "1b_not_um1, 1b_not_ui1, 1b_not_uf1" "oneb") 1211 1212(final_absence_set "1b_not_um1" "1b_um1") 1213(final_absence_set "1b_not_ui1" "1b_ui1") 1214(final_absence_set "1b_not_uf1" "1b_uf1") 1215 1216;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 1217;;; B-slot contains a nop.b or a brp instruction". 1218;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 1219;;; nop.b, otherwise it disperses to B2". 1220(final_absence_set 1221 "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\ 1222 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx" 1223 "1b_0mib. 1b_ub2, 1b_0mfb. 1b_ub2, 1b_0mmb. 1b_ub2") 1224 1225;; This is necessary to start new processor cycle when we meet stop bit. 1226(define_cpu_unit "1b_stop" "oneb") 1227(final_absence_set 1228 "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\ 1229 1b_0m.fi,1b_0mf.i,1b_0mfi.,\ 1230 1b_0m.mf,1b_0mm.f,1b_0mmf.,1b_0b.bb,1b_0bb.b,1b_0bbb.,\ 1231 1b_0m.bb,1b_0mb.b,1b_0mbb.,\ 1232 1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\ 1233 1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \ 1234 1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\ 1235 1b_1m.fi,1b_1mf.i,1b_1mfi.,\ 1236 1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\ 1237 1b_1m.ib,1b_1mi.b,1b_1mib.,\ 1238 1b_1m.mb,1b_1mm.b,1b_1mmb.,1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx." 1239 "1b_stop") 1240 1241;; M and I instruction is dispersed to the lowest numbered M or I unit 1242;; not already in use. An I slot in the 3rd position of 2nd bundle is 1243;; always dispersed to I1 1244(final_presence_set "1b_um1" "1b_um0") 1245(final_presence_set "1b_ui1" "1b_ui0, 1b_1mii., 1b_1mmi., 1b_1mfi.") 1246 1247;; Insns 1248 1249;; M and I instruction is dispersed to the lowest numbered M or I unit 1250;; not already in use. An I slot in the 3rd position of 2nd bundle is 1251;; always dispersed to I1 1252(define_reservation "1b_M" 1253 "1b_0m.ii+1_1+1b_um0|1b_0m.mi+1_1+1b_um0|1b_0mm.i+1_2+(1b_um0|1b_um1)\ 1254 |1b_0m.fi+1_1+1b_um0|1b_0m.mf+1_1+1b_um0|1b_0mm.f+1_2+1b_um1\ 1255 |1b_0m.bb+1_1+1b_um0|1b_0m.ib+1_1+1b_um0|1b_0m.mb+1_1+1b_um0\ 1256 |1b_0mm.b+1_2+1b_um1|1b_0m.fb+1_1+1b_um0|1b_0m.lx+1_1+1b_um0\ 1257 |1b_1mm.i+1_5+1b_um1|1b_1mm.b+1_5+1b_um1\ 1258 |(1b_1m.ii+1_4|1b_1m.mi+1_4|1b_1m.fi+1_4|1b_1m.bb+1_4|1b_1m.ib+1_4\ 1259 |1b_1m.mb+1_4|1b_1m.fb+1_4|1b_1m.lx+1_4)\ 1260 +(1b_um0|1b_um1)") 1261 1262;; Exceptions for dispersal rules. 1263;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1". 1264(define_reservation "1b_I" 1265 "1b_0mi.i+1_2+1b_ui0|1b_0mii.+1_3+(1b_ui0|1b_ui1)|1b_0mmi.+1_3+1b_ui0\ 1266 |1b_0mfi.+1_3+1b_ui0|1b_0mi.b+1_2+1b_ui0\ 1267 |(1b_1mi.i+1_5|1b_1mi.b+1_5)+(1b_ui0|1b_ui1)\ 1268 |1b_1mii.+1_6+1b_ui1|1b_1mmi.+1_6+1b_ui1|1b_1mfi.+1_6+1b_ui1") 1269 1270;; "An F slot in the 1st bundle disperses to F0". 1271;; "An F slot in the 2st bundle disperses to F1". 1272(define_reservation "1b_F" 1273 "1b_0mf.i+1_2+1b_uf0|1b_0mmf.+1_3+1b_uf0|1b_0mf.b+1_2+1b_uf0\ 1274 |1b_1mf.i+1_5+1b_uf1|1b_1mf.b+1_5+1b_uf1") 1275 1276;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 1277;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 1278;;; 2nd position it is dispersed to B2". 1279(define_reservation "1b_NB" 1280 "1b_0b.bb+1_1+1b_unb0|1b_0bb.b+1_2+1b_unb1|1b_0bbb.+1_3+1b_unb2\ 1281 |1b_0mb.b+1_2+1b_unb1|1b_0mbb.+1_3+1b_unb2\ 1282 |1b_0mib.+1_3+1b_unb0|1b_0mmb.+1_3+1b_unb0|1b_0mfb.+1_3+1b_unb0\ 1283 |1b_1b.bb+1_4+1b_unb0|1b_1bb.b+1_5+1b_unb1\ 1284 |1b_1bbb.+1_6+1b_unb2|1b_1mb.b+1_5+1b_unb1|1b_1mbb.+1_6+1b_unb2\ 1285 |1b_1mib.+1_6+1b_unb0|1b_1mmb.+1_6+1b_unb0|1b_1mfb.+1_6+1b_unb0") 1286 1287(define_reservation "1b_B" 1288 "1b_0b.bb+1_1+1b_ub0|1b_0bb.b+1_2+1b_ub1|1b_0bbb.+1_3+1b_ub2\ 1289 |1b_0mb.b+1_2+1b_ub1|1b_0mbb.+1_3+1b_ub2|1b_0mib.+1_3+1b_ub2\ 1290 |1b_0mfb.+1_3+1b_ub2|1b_1b.bb+1_4+1b_ub0|1b_1bb.b+1_5+1b_ub1\ 1291 |1b_1bbb.+1_6+1b_ub2|1b_1mb.b+1_5+1b_ub1\ 1292 |1b_1mib.+1_6+1b_ub2|1b_1mmb.+1_6+1b_ub2|1b_1mfb.+1_6+1b_ub2") 1293 1294(define_reservation "1b_L" "1b_0mlx.+1_3+1b_ui0+1b_uf0\ 1295 |1b_1mlx.+1_6+(1b_ui0|1b_ui1)+1b_uf1") 1296 1297;; We assume that there is no insn issued on the same cycle as unknown insn. 1298(define_cpu_unit "1b_empty" "oneb") 1299(exclusion_set "1b_empty" 1300 "1b_0m.ii,1b_0m.mi,1b_0m.fi,1b_0m.mf,1b_0b.bb,1b_0m.bb,\ 1301 1b_0m.ib,1b_0m.mb,1b_0m.fb,1b_0m.lx") 1302 1303(define_cpu_unit 1304 "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs" 1305 "oneb") 1306(define_cpu_unit 1307 "1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs" 1308 "oneb") 1309 1310(define_cpu_unit "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont, 1b_mb_cont,\ 1311 1b_b_cont, 1b_bb_cont" "oneb") 1312 1313;; For stop in the middle of the bundles. 1314(define_cpu_unit "1b_m_stop, 1b_m0_stop, 1b_m1_stop, 1b_0mmi_cont" "oneb") 1315(define_cpu_unit "1b_mi_stop, 1b_mi0_stop, 1b_mi1_stop, 1b_0mii_cont" "oneb") 1316 1317(final_presence_set "1b_0m_bs" 1318 "1b_0m.ii, 1b_0m.mi, 1b_0m.mf, 1b_0m.fi, 1b_0m.bb,\ 1319 1b_0m.ib, 1b_0m.fb, 1b_0m.mb, 1b_0m.lx") 1320(final_presence_set "1b_1m_bs" 1321 "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1m.bb, 1b_1m.ib, 1b_1m.fb, 1b_1m.mb,\ 1322 1b_1m.lx") 1323(final_presence_set "1b_0mi_bs" "1b_0mi.i, 1b_0mi.i") 1324(final_presence_set "1b_1mi_bs" "1b_1mi.i, 1b_1mi.i") 1325(final_presence_set "1b_0mm_bs" "1b_0mm.i, 1b_0mm.f, 1b_0mm.b") 1326(final_presence_set "1b_1mm_bs" "1b_1mm.i, 1b_1mm.b") 1327(final_presence_set "1b_0mf_bs" "1b_0mf.i, 1b_0mf.b") 1328(final_presence_set "1b_1mf_bs" "1b_1mf.i, 1b_1mf.b") 1329(final_presence_set "1b_0b_bs" "1b_0b.bb") 1330(final_presence_set "1b_1b_bs" "1b_1b.bb") 1331(final_presence_set "1b_0bb_bs" "1b_0bb.b") 1332(final_presence_set "1b_1bb_bs" "1b_1bb.b") 1333(final_presence_set "1b_0mb_bs" "1b_0mb.b") 1334(final_presence_set "1b_1mb_bs" "1b_1mb.b") 1335 1336(exclusion_set "1b_0m_bs" 1337 "1b_0mi.i, 1b_0mm.i, 1b_0mm.f, 1b_0mf.i, 1b_0mb.b,\ 1338 1b_0mi.b, 1b_0mf.b, 1b_0mm.b, 1b_0mlx., 1b_m0_stop") 1339(exclusion_set "1b_1m_bs" 1340 "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1mb.b, 1b_1mi.b, 1b_1mf.b, 1b_1mm.b,\ 1341 1b_1mlx., 1b_m1_stop") 1342(exclusion_set "1b_0mi_bs" "1b_0mii., 1b_0mib., 1b_mi0_stop") 1343(exclusion_set "1b_1mi_bs" "1b_1mii., 1b_1mib., 1b_mi1_stop") 1344(exclusion_set "1b_0mm_bs" "1b_0mmi., 1b_0mmf., 1b_0mmb.") 1345(exclusion_set "1b_1mm_bs" "1b_1mmi., 1b_1mmb.") 1346(exclusion_set "1b_0mf_bs" "1b_0mfi., 1b_0mfb.") 1347(exclusion_set "1b_1mf_bs" "1b_1mfi., 1b_1mfb.") 1348(exclusion_set "1b_0b_bs" "1b_0bb.b") 1349(exclusion_set "1b_1b_bs" "1b_1bb.b") 1350(exclusion_set "1b_0bb_bs" "1b_0bbb.") 1351(exclusion_set "1b_1bb_bs" "1b_1bbb.") 1352(exclusion_set "1b_0mb_bs" "1b_0mbb.") 1353(exclusion_set "1b_1mb_bs" "1b_1mbb.") 1354 1355(exclusion_set 1356 "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs, 1357 1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs" 1358 "1b_stop") 1359 1360(final_presence_set 1361 "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0mb.b,\ 1362 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx." 1363 "1b_m_cont") 1364(final_presence_set "1b_0mii., 1b_0mib." "1b_mi_cont") 1365(final_presence_set "1b_0mmi., 1b_0mmf., 1b_0mmb." "1b_mm_cont") 1366(final_presence_set "1b_0mfi., 1b_0mfb." "1b_mf_cont") 1367(final_presence_set "1b_0bb.b" "1b_b_cont") 1368(final_presence_set "1b_0bbb." "1b_bb_cont") 1369(final_presence_set "1b_0mbb." "1b_mb_cont") 1370 1371(exclusion_set 1372 "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1373 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx" 1374 "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont,\ 1375 1b_mb_cont, 1b_b_cont, 1b_bb_cont") 1376 1377(exclusion_set "1b_empty" 1378 "1b_m_cont,1b_mi_cont,1b_mm_cont,1b_mf_cont,\ 1379 1b_mb_cont,1b_b_cont,1b_bb_cont") 1380 1381;; For m;mi bundle 1382(final_presence_set "1b_m0_stop" "1b_0m.mi") 1383(final_presence_set "1b_0mm.i" "1b_0mmi_cont") 1384(exclusion_set "1b_0mmi_cont" 1385 "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1386 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1387(exclusion_set "1b_m0_stop" "1b_0mm.i") 1388(final_presence_set "1b_m1_stop" "1b_1m.mi") 1389(exclusion_set "1b_m1_stop" "1b_1mm.i") 1390(final_presence_set "1b_m_stop" "1b_m0_stop, 1b_m1_stop") 1391 1392;; For mi;i bundle 1393(final_presence_set "1b_mi0_stop" "1b_0mi.i") 1394(final_presence_set "1b_0mii." "1b_0mii_cont") 1395(exclusion_set "1b_0mii_cont" 1396 "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1397 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1398(exclusion_set "1b_mi0_stop" "1b_0mii.") 1399(final_presence_set "1b_mi1_stop" "1b_1mi.i") 1400(exclusion_set "1b_mi1_stop" "1b_1mii.") 1401(final_presence_set "1b_mi_stop" "1b_mi0_stop, 1b_mi1_stop") 1402 1403(final_absence_set 1404 "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\ 1405 1b_0m.fi,1b_0mf.i,1b_0mfi.,1b_0m.mf,1b_0mm.f,1b_0mmf.,\ 1406 1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb.,\ 1407 1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\ 1408 1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \ 1409 1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\ 1410 1b_1m.fi,1b_1mf.i,1b_1mfi.,\ 1411 1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\ 1412 1b_1m.ib,1b_1mi.b,1b_1mib.,1b_1m.mb,1b_1mm.b,1b_1mmb.,\ 1413 1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx." 1414 "1b_m0_stop,1b_m1_stop,1b_mi0_stop,1b_mi1_stop") 1415 1416(define_reservation "1b_A" "1b_M|1b_I") 1417 1418(define_insn_reservation "1b_stop_bit" 0 1419 (and (and (eq_attr "cpu" "itanium") 1420 (eq_attr "itanium_class" "stop_bit")) 1421 (ne (symbol_ref "bundling_p") (const_int 0))) 1422 "1b_stop|1b_m0_stop|1b_m1_stop|1b_mi0_stop|1b_mi1_stop") 1423(define_insn_reservation "1b_br" 0 1424 (and (and (eq_attr "cpu" "itanium") 1425 (eq_attr "itanium_class" "br")) 1426 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B") 1427(define_insn_reservation "1b_scall" 0 1428 (and (and (eq_attr "cpu" "itanium") 1429 (eq_attr "itanium_class" "scall")) 1430 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B") 1431(define_insn_reservation "1b_fcmp" 2 1432 (and (and (eq_attr "cpu" "itanium") 1433 (eq_attr "itanium_class" "fcmp")) 1434 (ne (symbol_ref "bundling_p") (const_int 0))) 1435 "1b_F+1b_not_uf1") 1436(define_insn_reservation "1b_fcvtfx" 7 1437 (and (and (eq_attr "cpu" "itanium") 1438 (eq_attr "itanium_class" "fcvtfx")) 1439 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1440 1441(define_insn_reservation "1b_fld" 9 1442 (and (and (and (eq_attr "cpu" "itanium") 1443 (eq_attr "itanium_class" "fld")) 1444 (eq_attr "check_load" "no")) 1445 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1446(define_insn_reservation "1b_fldc" 0 1447 (and (and (and (eq_attr "cpu" "itanium") 1448 (eq_attr "itanium_class" "fld")) 1449 (eq_attr "check_load" "yes")) 1450 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1451 1452(define_insn_reservation "1b_fldp" 9 1453 (and (and (and (eq_attr "cpu" "itanium") 1454 (eq_attr "itanium_class" "fldp")) 1455 (eq_attr "check_load" "no")) 1456 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1457(define_insn_reservation "1b_fldpc" 0 1458 (and (and (and (eq_attr "cpu" "itanium") 1459 (eq_attr "itanium_class" "fldp")) 1460 (eq_attr "check_load" "yes")) 1461 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1462 1463(define_insn_reservation "1b_fmac" 5 1464 (and (and (eq_attr "cpu" "itanium") 1465 (eq_attr "itanium_class" "fmac")) 1466 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1467(define_insn_reservation "1b_fmisc" 5 1468 (and (and (eq_attr "cpu" "itanium") 1469 (eq_attr "itanium_class" "fmisc")) 1470 (ne (symbol_ref "bundling_p") (const_int 0))) 1471 "1b_F+1b_not_uf1") 1472(define_insn_reservation "1b_frar_i" 13 1473 (and (and (eq_attr "cpu" "itanium") 1474 (eq_attr "itanium_class" "frar_i")) 1475 (ne (symbol_ref "bundling_p") (const_int 0))) 1476 "1b_I+1b_not_ui1") 1477(define_insn_reservation "1b_frar_m" 6 1478 (and (and (eq_attr "cpu" "itanium") 1479 (eq_attr "itanium_class" "frar_m")) 1480 (ne (symbol_ref "bundling_p") (const_int 0))) 1481 "1b_M+1b_not_um1") 1482(define_insn_reservation "1b_frbr" 2 1483 (and (and (eq_attr "cpu" "itanium") 1484 (eq_attr "itanium_class" "frbr")) 1485 (ne (symbol_ref "bundling_p") (const_int 0))) 1486 "1b_I+1b_not_ui1") 1487(define_insn_reservation "1b_frfr" 2 1488 (and (and (eq_attr "cpu" "itanium") 1489 (eq_attr "itanium_class" "frfr")) 1490 (ne (symbol_ref "bundling_p") (const_int 0))) 1491 "1b_M+1b_not_um1") 1492(define_insn_reservation "1b_frpr" 2 1493 (and (and (eq_attr "cpu" "itanium") 1494 (eq_attr "itanium_class" "frpr")) 1495 (ne (symbol_ref "bundling_p") (const_int 0))) 1496 "1b_I+1b_not_ui1") 1497(define_insn_reservation "1b_ialu" 1 1498 (and (and (eq_attr "cpu" "itanium") 1499 (eq_attr "itanium_class" "ialu")) 1500 (ne (symbol_ref 1501 "bundling_p && !ia64_produce_address_p (insn)") 1502 (const_int 0))) 1503 "1b_A") 1504(define_insn_reservation "1b_ialu_addr" 1 1505 (and (and (eq_attr "cpu" "itanium") 1506 (eq_attr "itanium_class" "ialu")) 1507 (eq (symbol_ref 1508 "bundling_p && ia64_produce_address_p (insn)") 1509 (const_int 1))) 1510 "1b_M") 1511(define_insn_reservation "1b_icmp" 1 1512 (and (and (eq_attr "cpu" "itanium") 1513 (eq_attr "itanium_class" "icmp")) 1514 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1515(define_insn_reservation "1b_ilog" 1 1516 (and (and (eq_attr "cpu" "itanium") 1517 (eq_attr "itanium_class" "ilog")) 1518 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1519(define_insn_reservation "1b_mmalua" 2 1520 (and (and (eq_attr "cpu" "itanium") 1521 (eq_attr "itanium_class" "mmalua")) 1522 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1523(define_insn_reservation "1b_ishf" 1 1524 (and (and (eq_attr "cpu" "itanium") 1525 (eq_attr "itanium_class" "ishf")) 1526 (ne (symbol_ref "bundling_p") (const_int 0))) 1527 "1b_I+1b_not_ui1") 1528 1529(define_insn_reservation "1b_ld" 2 1530 (and (and (and (eq_attr "cpu" "itanium") 1531 (eq_attr "itanium_class" "ld")) 1532 (eq_attr "check_load" "no")) 1533 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1534(define_insn_reservation "1b_ldc" 0 1535 (and (and (and (eq_attr "cpu" "itanium") 1536 (eq_attr "itanium_class" "ld")) 1537 (eq_attr "check_load" "yes")) 1538 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1539 1540(define_insn_reservation "1b_long_i" 1 1541 (and (and (eq_attr "cpu" "itanium") 1542 (eq_attr "itanium_class" "long_i")) 1543 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L") 1544(define_insn_reservation "1b_mmmul" 2 1545 (and (and (eq_attr "cpu" "itanium") 1546 (eq_attr "itanium_class" "mmmul")) 1547 (ne (symbol_ref "bundling_p") (const_int 0))) 1548 "1b_I+1b_not_ui1") 1549(define_insn_reservation "1b_mmshf" 2 1550 (and (and (eq_attr "cpu" "itanium") 1551 (eq_attr "itanium_class" "mmshf")) 1552 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1553(define_insn_reservation "1b_mmshfi" 2 1554 (and (and (eq_attr "cpu" "itanium") 1555 (eq_attr "itanium_class" "mmshfi")) 1556 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1557(define_insn_reservation "1b_rse_m" 0 1558 (and (and (eq_attr "cpu" "itanium") 1559 (eq_attr "itanium_class" "rse_m")) 1560 (ne (symbol_ref "bundling_p") (const_int 0))) 1561 "(1b_0m.ii|1b_0m.mi|1b_0m.fi|1b_0m.mf|1b_0b.bb|1b_0m.bb\ 1562 |1b_0m.ib|1b_0m.mb|1b_0m.fb|1b_0m.lx)+1_1+1b_um0") 1563(define_insn_reservation "1b_sem" 0 1564 (and (and (eq_attr "cpu" "itanium") 1565 (eq_attr "itanium_class" "sem")) 1566 (ne (symbol_ref "bundling_p") (const_int 0))) 1567 "1b_M+1b_not_um1") 1568(define_insn_reservation "1b_stf" 1 1569 (and (and (eq_attr "cpu" "itanium") 1570 (eq_attr "itanium_class" "stf")) 1571 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1572(define_insn_reservation "1b_st" 1 1573 (and (and (eq_attr "cpu" "itanium") 1574 (eq_attr "itanium_class" "st")) 1575 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1576(define_insn_reservation "1b_syst_m0" 0 1577 (and (and (eq_attr "cpu" "itanium") 1578 (eq_attr "itanium_class" "syst_m0")) 1579 (ne (symbol_ref "bundling_p") (const_int 0))) 1580 "1b_M+1b_not_um1") 1581(define_insn_reservation "1b_syst_m" 0 1582 (and (and (eq_attr "cpu" "itanium") 1583 (eq_attr "itanium_class" "syst_m")) 1584 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1585(define_insn_reservation "1b_tbit" 1 1586 (and (and (eq_attr "cpu" "itanium") 1587 (eq_attr "itanium_class" "tbit")) 1588 (ne (symbol_ref "bundling_p") (const_int 0))) 1589 "1b_I+1b_not_ui1") 1590(define_insn_reservation "1b_toar_i" 0 1591 (and (and (eq_attr "cpu" "itanium") 1592 (eq_attr "itanium_class" "toar_i")) 1593 (ne (symbol_ref "bundling_p") (const_int 0))) 1594 "1b_I+1b_not_ui1") 1595(define_insn_reservation "1b_toar_m" 5 1596 (and (and (eq_attr "cpu" "itanium") 1597 (eq_attr "itanium_class" "toar_m")) 1598 (ne (symbol_ref "bundling_p") (const_int 0))) 1599 "1b_M+1b_not_um1") 1600(define_insn_reservation "1b_tobr" 1 1601 (and (and (eq_attr "cpu" "itanium") 1602 (eq_attr "itanium_class" "tobr")) 1603 (ne (symbol_ref "bundling_p") (const_int 0))) 1604 "1b_I+1b_not_ui1") 1605(define_insn_reservation "1b_tofr" 9 1606 (and (and (eq_attr "cpu" "itanium") 1607 (eq_attr "itanium_class" "tofr")) 1608 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1609(define_insn_reservation "1b_topr" 1 1610 (and (and (eq_attr "cpu" "itanium") 1611 (eq_attr "itanium_class" "topr")) 1612 (ne (symbol_ref "bundling_p") (const_int 0))) 1613 "1b_I+1b_not_ui1") 1614(define_insn_reservation "1b_xmpy" 7 1615 (and (and (eq_attr "cpu" "itanium") 1616 (eq_attr "itanium_class" "xmpy")) 1617 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1618(define_insn_reservation "1b_xtd" 1 1619 (and (and (eq_attr "cpu" "itanium") 1620 (eq_attr "itanium_class" "xtd")) 1621 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1622 1623(define_insn_reservation "1b_chk_s_i" 0 1624 (and (and (eq_attr "cpu" "itanium") 1625 (eq_attr "itanium_class" "chk_s_i")) 1626 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1627(define_insn_reservation "1b_chk_s_f" 0 1628 (and (and (eq_attr "cpu" "itanium") 1629 (eq_attr "itanium_class" "chk_s_f")) 1630 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1631(define_insn_reservation "1b_chk_a" 0 1632 (and (and (eq_attr "cpu" "itanium") 1633 (eq_attr "itanium_class" "chk_a")) 1634 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1635 1636(define_insn_reservation "1b_lfetch" 0 1637 (and (and (eq_attr "cpu" "itanium") 1638 (eq_attr "itanium_class" "lfetch")) 1639 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1640(define_insn_reservation "1b_nop_m" 0 1641 (and (and (eq_attr "cpu" "itanium") 1642 (eq_attr "itanium_class" "nop_m")) 1643 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1644(define_insn_reservation "1b_nop_b" 0 1645 (and (and (eq_attr "cpu" "itanium") 1646 (eq_attr "itanium_class" "nop_b")) 1647 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_NB") 1648(define_insn_reservation "1b_nop_i" 0 1649 (and (and (eq_attr "cpu" "itanium") 1650 (eq_attr "itanium_class" "nop_i")) 1651 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1652(define_insn_reservation "1b_nop_f" 0 1653 (and (and (eq_attr "cpu" "itanium") 1654 (eq_attr "itanium_class" "nop_f")) 1655 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1656(define_insn_reservation "1b_nop_x" 0 1657 (and (and (eq_attr "cpu" "itanium") 1658 (eq_attr "itanium_class" "nop_x")) 1659 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L") 1660(define_insn_reservation "1b_unknown" 1 1661 (and (and (eq_attr "cpu" "itanium") 1662 (eq_attr "itanium_class" "unknown")) 1663 (ne (symbol_ref "bundling_p") (const_int 0))) 1664 "1b_empty") 1665(define_insn_reservation "1b_nop" 1 1666 (and (and (eq_attr "cpu" "itanium") 1667 (eq_attr "itanium_class" "nop")) 1668 (ne (symbol_ref "bundling_p") (const_int 0))) 1669 "1b_M|1b_NB|1b_I|1b_F") 1670(define_insn_reservation "1b_ignore" 0 1671 (and (and (eq_attr "cpu" "itanium") 1672 (eq_attr "itanium_class" "ignore")) 1673 (ne (symbol_ref "bundling_p") (const_int 0))) 1674 "nothing") 1675 1676(define_insn_reservation "1b_pre_cycle" 0 1677 (and (and (eq_attr "cpu" "itanium") 1678 (eq_attr "itanium_class" "pre_cycle")) 1679 (ne (symbol_ref "bundling_p") (const_int 0))) 1680 "(1b_0m_bs, 1b_m_cont) \ 1681 | (1b_0mi_bs, 1b_mi_cont) \ 1682 | (1b_0mm_bs, 1b_mm_cont) \ 1683 | (1b_0mf_bs, 1b_mf_cont) \ 1684 | (1b_0b_bs, 1b_b_cont) \ 1685 | (1b_0bb_bs, 1b_bb_cont) \ 1686 | (1b_0mb_bs, 1b_mb_cont) \ 1687 | (1b_1m_bs, 1b_m_cont) \ 1688 | (1b_1mi_bs, 1b_mi_cont) \ 1689 | (1b_1mm_bs, 1b_mm_cont) \ 1690 | (1b_1mf_bs, 1b_mf_cont) \ 1691 | (1b_1b_bs, 1b_b_cont) \ 1692 | (1b_1bb_bs, 1b_bb_cont) \ 1693 | (1b_1mb_bs, 1b_mb_cont) \ 1694 | (1b_m_stop, 1b_0mmi_cont) \ 1695 | (1b_mi_stop, 1b_0mii_cont)") 1696 1697