i386.h revision 97912
1/* Definitions of target machine for GNU compiler for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002 Free Software Foundation, Inc. 4 5This file is part of GNU CC. 6 7GNU CC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GNU CC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GNU CC; see the file COPYING. If not, write to 19the Free Software Foundation, 59 Temple Place - Suite 330, 20Boston, MA 02111-1307, USA. */ 21 22/* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37 38/* $FreeBSD: head/contrib/gcc/config/i386/i386.h 97912 2002-06-06 03:39:03Z obrien $ */ 39 40 41/* Stubs for half-pic support if not OSF/1 reference platform. */ 42 43#ifndef HALF_PIC_P 44#define HALF_PIC_P() 0 45#define HALF_PIC_NUMBER_PTRS 0 46#define HALF_PIC_NUMBER_REFS 0 47#define HALF_PIC_ENCODE(DECL) 48#define HALF_PIC_DECLARE(NAME) 49#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it") 50#define HALF_PIC_ADDRESS_P(X) 0 51#define HALF_PIC_PTR(X) (X) 52#define HALF_PIC_FINISH(STREAM) 53#endif 54 55/* Define the specific costs for a given cpu */ 56 57struct processor_costs { 58 const int add; /* cost of an add instruction */ 59 const int lea; /* cost of a lea instruction */ 60 const int shift_var; /* variable shift costs */ 61 const int shift_const; /* constant shift costs */ 62 const int mult_init; /* cost of starting a multiply */ 63 const int mult_bit; /* cost of multiply per each bit set */ 64 const int divide; /* cost of a divide/mod */ 65 int movsx; /* The cost of movsx operation. */ 66 int movzx; /* The cost of movzx operation. */ 67 const int large_insn; /* insns larger than this cost more */ 68 const int move_ratio; /* The threshold of number of scalar 69 memory-to-memory move insns. */ 70 const int movzbl_load; /* cost of loading using movzbl */ 71 const int int_load[3]; /* cost of loading integer registers 72 in QImode, HImode and SImode relative 73 to reg-reg move (2). */ 74 const int int_store[3]; /* cost of storing integer register 75 in QImode, HImode and SImode */ 76 const int fp_move; /* cost of reg,reg fld/fst */ 77 const int fp_load[3]; /* cost of loading FP register 78 in SFmode, DFmode and XFmode */ 79 const int fp_store[3]; /* cost of storing FP register 80 in SFmode, DFmode and XFmode */ 81 const int mmx_move; /* cost of moving MMX register. */ 82 const int mmx_load[2]; /* cost of loading MMX register 83 in SImode and DImode */ 84 const int mmx_store[2]; /* cost of storing MMX register 85 in SImode and DImode */ 86 const int sse_move; /* cost of moving SSE register. */ 87 const int sse_load[3]; /* cost of loading SSE register 88 in SImode, DImode and TImode*/ 89 const int sse_store[3]; /* cost of storing SSE register 90 in SImode, DImode and TImode*/ 91 const int mmxsse_to_integer; /* cost of moving mmxsse register to 92 integer and vice versa. */ 93 const int prefetch_block; /* bytes moved to cache for prefetch. */ 94 const int simultaneous_prefetches; /* number of parallel prefetch 95 operations. */ 96}; 97 98extern const struct processor_costs *ix86_cost; 99 100/* Run-time compilation parameters selecting different hardware subsets. */ 101 102extern int target_flags; 103 104/* Macros used in the machine description to test the flags. */ 105 106/* configure can arrange to make this 2, to force a 486. */ 107 108#ifndef TARGET_CPU_DEFAULT 109#define TARGET_CPU_DEFAULT 0 110#endif 111 112/* Masks for the -m switches */ 113#define MASK_80387 0x00000001 /* Hardware floating point */ 114#define MASK_RTD 0x00000002 /* Use ret that pops args */ 115#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ 116#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ 117#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ 118#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ 119#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ 120#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ 121#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ 122#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ 123#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ 124#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ 125#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ 126#define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000 127#define MASK_MMX 0x00004000 /* Support MMX regs/builtins */ 128#define MASK_MMX_SET 0x00008000 129#define MASK_SSE 0x00010000 /* Support SSE regs/builtins */ 130#define MASK_SSE_SET 0x00020000 131#define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */ 132#define MASK_SSE2_SET 0x00080000 133#define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */ 134#define MASK_3DNOW_SET 0x00200000 135#define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */ 136#define MASK_3DNOW_A_SET 0x00800000 137#define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */ 138#define MASK_64BIT 0x02000000 /* Produce 64bit code */ 139/* ... overlap with subtarget options starts by 0x04000000. */ 140#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ 141#define MASK_NO_ALIGN_LONG_STRINGS 0x08000000 /* Do not align long strings specially */ 142 143/* Use the floating point instructions */ 144#define TARGET_80387 (target_flags & MASK_80387) 145 146/* Compile using ret insn that pops args. 147 This will not work unless you use prototypes at least 148 for all functions that can take varying numbers of args. */ 149#define TARGET_RTD (target_flags & MASK_RTD) 150 151/* Align doubles to a two word boundary. This breaks compatibility with 152 the published ABI's for structures containing doubles, but produces 153 faster code on the pentium. */ 154#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) 155 156/* Use push instructions to save outgoing args. */ 157#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) 158 159/* Accumulate stack adjustments to prologue/epilogue. */ 160#define TARGET_ACCUMULATE_OUTGOING_ARGS \ 161 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) 162 163/* Put uninitialized locals into bss, not data. 164 Meaningful only on svr3. */ 165#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) 166 167/* Use IEEE floating point comparisons. These handle correctly the cases 168 where the result of a comparison is unordered. Normally SIGFPE is 169 generated in such cases, in which case this isn't needed. */ 170#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) 171 172/* Functions that return a floating point value may return that value 173 in the 387 FPU or in 386 integer registers. If set, this flag causes 174 the 387 to be used, which is compatible with most calling conventions. */ 175#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) 176 177/* Long double is 128bit instead of 96bit, even when only 80bits are used. 178 This mode wastes cache, but avoid misaligned data accesses and simplifies 179 address calculations. */ 180#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) 181 182/* Disable generation of FP sin, cos and sqrt operations for 387. 183 This is because FreeBSD lacks these in the math-emulator-code */ 184#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) 185 186/* Don't create frame pointers for leaf functions */ 187#define TARGET_OMIT_LEAF_FRAME_POINTER \ 188 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) 189 190/* Debug GO_IF_LEGITIMATE_ADDRESS */ 191#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) 192 193/* Debug FUNCTION_ARG macros */ 194#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) 195 196/* 64bit Sledgehammer mode */ 197#ifdef TARGET_BI_ARCH 198#define TARGET_64BIT (target_flags & MASK_64BIT) 199#else 200#ifdef TARGET_64BIT_DEFAULT 201#define TARGET_64BIT 1 202#else 203#define TARGET_64BIT 0 204#endif 205#endif 206 207#define TARGET_386 (ix86_cpu == PROCESSOR_I386) 208#define TARGET_486 (ix86_cpu == PROCESSOR_I486) 209#define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) 210#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) 211#define TARGET_K6 (ix86_cpu == PROCESSOR_K6) 212#define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) 213#define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4) 214 215#define CPUMASK (1 << ix86_cpu) 216extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 217extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 218extern const int x86_branch_hints, x86_unroll_strlen; 219extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 220extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; 221extern const int x86_use_cltd, x86_read_modify_write; 222extern const int x86_read_modify, x86_split_long_moves; 223extern const int x86_promote_QImode, x86_single_stringop; 224extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 225extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 226extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 227extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 228extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 229extern const int x86_epilogue_using_move, x86_decompose_lea; 230extern const int x86_arch_always_fancy_math_387; 231extern int x86_prefetch_sse; 232 233#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) 234#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) 235#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) 236#define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) 237#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) 238/* For sane SSE instruction set generation we need fcomi instruction. It is 239 safe to enable all CMOVE instructions. */ 240#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 241#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) 242#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK) 243#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) 244#define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT) 245#define TARGET_MOVX (x86_movx & CPUMASK) 246#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) 247#define TARGET_USE_LOOP (x86_use_loop & CPUMASK) 248#define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) 249#define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) 250#define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) 251#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) 252#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) 253#define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) 254#define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) 255#define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) 256#define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) 257#define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) 258#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) 259#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) 260#define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK) 261#define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK) 262#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK) 263#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK) 264#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK) 265#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK) 266#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK) 267#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK) 268#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK) 269#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK) 270#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 271 272#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) 273 274#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) 275#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) 276 277#define ASSEMBLER_DIALECT (ix86_asm_dialect) 278 279#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0) 280#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) 281#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 282#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 283 && (ix86_fpmath & FPMATH_387)) 284#define TARGET_MMX ((target_flags & MASK_MMX) != 0) 285#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) 286#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) 287 288#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) 289 290#define TARGET_NO_ALIGN_LONG_STRINGS (target_flags & MASK_NO_ALIGN_LONG_STRINGS) 291 292/* WARNING: Do not mark empty strings for translation, as calling 293 gettext on an empty string does NOT return an empty 294 string. */ 295 296 297#define TARGET_SWITCHES \ 298{ { "80387", MASK_80387, N_("Use hardware fp") }, \ 299 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ 300 { "hard-float", MASK_80387, N_("Use hardware fp") }, \ 301 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ 302 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ 303 { "386", 0, "" /*Deprecated.*/}, \ 304 { "486", 0, "" /*Deprecated.*/}, \ 305 { "pentium", 0, "" /*Deprecated.*/}, \ 306 { "pentiumpro", 0, "" /*Deprecated.*/}, \ 307 { "intel-syntax", 0, "" /*Deprecated.*/}, \ 308 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ 309 { "rtd", MASK_RTD, \ 310 N_("Alternate calling convention") }, \ 311 { "no-rtd", -MASK_RTD, \ 312 N_("Use normal calling convention") }, \ 313 { "align-double", MASK_ALIGN_DOUBLE, \ 314 N_("Align some doubles on dword boundary") }, \ 315 { "no-align-double", -MASK_ALIGN_DOUBLE, \ 316 N_("Align doubles on word boundary") }, \ 317 { "svr3-shlib", MASK_SVR3_SHLIB, \ 318 N_("Uninitialized locals in .bss") }, \ 319 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ 320 N_("Uninitialized locals in .data") }, \ 321 { "ieee-fp", MASK_IEEE_FP, \ 322 N_("Use IEEE math for fp comparisons") }, \ 323 { "no-ieee-fp", -MASK_IEEE_FP, \ 324 N_("Do not use IEEE math for fp comparisons") }, \ 325 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ 326 N_("Return values of functions in FPU registers") }, \ 327 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ 328 N_("Do not return values of functions in FPU registers")}, \ 329 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ 330 N_("Do not generate sin, cos, sqrt for FPU") }, \ 331 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ 332 N_("Generate sin, cos, sqrt for FPU")}, \ 333 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ 334 N_("Omit the frame pointer in leaf functions") }, \ 335 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ 336 { "stack-arg-probe", MASK_STACK_PROBE, \ 337 N_("Enable stack probing") }, \ 338 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ 339 { "windows", 0, 0 /* undocumented */ }, \ 340 { "dll", 0, 0 /* undocumented */ }, \ 341 { "align-stringops", -MASK_NO_ALIGN_STROPS, \ 342 N_("Align destination of the string operations") }, \ 343 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ 344 N_("Do not align destination of the string operations") }, \ 345 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ 346 N_("Inline all known string operations") }, \ 347 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ 348 N_("Do not inline all known string operations") }, \ 349 { "push-args", -MASK_NO_PUSH_ARGS, \ 350 N_("Use push instructions to save outgoing arguments") }, \ 351 { "no-push-args", MASK_NO_PUSH_ARGS, \ 352 N_("Do not use push instructions to save outgoing arguments") }, \ 353 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \ 354 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \ 355 N_("Use push instructions to save outgoing arguments") }, \ 356 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \ 357 N_("Do not use push instructions to save outgoing arguments") }, \ 358 { "mmx", MASK_MMX | MASK_MMX_SET, \ 359 N_("Support MMX built-in functions") }, \ 360 { "no-mmx", -MASK_MMX, \ 361 N_("Do not support MMX built-in functions") }, \ 362 { "no-mmx", MASK_MMX_SET, "" }, \ 363 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \ 364 N_("Support 3DNow! built-in functions") }, \ 365 { "no-3dnow", -MASK_3DNOW, "" }, \ 366 { "no-3dnow", MASK_3DNOW_SET, \ 367 N_("Do not support 3DNow! built-in functions") }, \ 368 { "sse", MASK_SSE | MASK_SSE_SET, \ 369 N_("Support MMX and SSE built-in functions and code generation") }, \ 370 { "no-sse", -MASK_SSE, "" }, \ 371 { "no-sse", MASK_SSE_SET, \ 372 N_("Do not support MMX and SSE built-in functions and code generation") },\ 373 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \ 374 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ 375 { "no-sse2", -MASK_SSE2, "" }, \ 376 { "no-sse2", MASK_SSE2_SET, \ 377 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ 378 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ 379 N_("sizeof(long double) is 16") }, \ 380 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ 381 N_("sizeof(long double) is 12") }, \ 382 { "64", MASK_64BIT, \ 383 N_("Generate 64bit x86-64 code") }, \ 384 { "32", -MASK_64BIT, \ 385 N_("Generate 32bit i386 code") }, \ 386 { "red-zone", -MASK_NO_RED_ZONE, \ 387 N_("Use red-zone in the x86-64 code") }, \ 388 { "no-red-zone", MASK_NO_RED_ZONE, \ 389 N_("Do not use red-zone in the x86-64 code") }, \ 390 { "no-align-long-strings", MASK_NO_ALIGN_LONG_STRINGS, \ 391 N_("Do not align long strings specially") }, \ 392 { "align-long-strings", -MASK_NO_ALIGN_LONG_STRINGS, \ 393 N_("Align strings longer than 30 on a 32-byte boundary") }, \ 394 SUBTARGET_SWITCHES \ 395 { "", TARGET_DEFAULT, 0 }} 396 397#ifdef TARGET_64BIT_DEFAULT 398#define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT) 399#else 400#define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT 401#endif 402 403/* Which processor to schedule for. The cpu attribute defines a list that 404 mirrors this list, so changes to i386.md must be made at the same time. */ 405 406enum processor_type 407{ 408 PROCESSOR_I386, /* 80386 */ 409 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 410 PROCESSOR_PENTIUM, 411 PROCESSOR_PENTIUMPRO, 412 PROCESSOR_K6, 413 PROCESSOR_ATHLON, 414 PROCESSOR_PENTIUM4, 415 PROCESSOR_max 416}; 417enum fpmath_unit 418{ 419 FPMATH_387 = 1, 420 FPMATH_SSE = 2 421}; 422 423extern enum processor_type ix86_cpu; 424extern enum fpmath_unit ix86_fpmath; 425 426extern int ix86_arch; 427 428/* This macro is similar to `TARGET_SWITCHES' but defines names of 429 command options that have values. Its definition is an 430 initializer with a subgrouping for each command option. 431 432 Each subgrouping contains a string constant, that defines the 433 fixed part of the option name, and the address of a variable. The 434 variable, type `char *', is set to the variable part of the given 435 option if the fixed part matches. The actual option name is made 436 by appending `-m' to the specified name. */ 437#define TARGET_OPTIONS \ 438{ { "cpu=", &ix86_cpu_string, \ 439 N_("Schedule code for given CPU")}, \ 440 { "fpmath=", &ix86_fpmath_string, \ 441 N_("Generate floating point mathematics using given instruction set")},\ 442 { "arch=", &ix86_arch_string, \ 443 N_("Generate code for given CPU")}, \ 444 { "regparm=", &ix86_regparm_string, \ 445 N_("Number of registers used to pass integer arguments") }, \ 446 { "align-loops=", &ix86_align_loops_string, \ 447 N_("Loop code aligned to this power of 2") }, \ 448 { "align-jumps=", &ix86_align_jumps_string, \ 449 N_("Jump targets are aligned to this power of 2") }, \ 450 { "align-functions=", &ix86_align_funcs_string, \ 451 N_("Function starts are aligned to this power of 2") }, \ 452 { "preferred-stack-boundary=", \ 453 &ix86_preferred_stack_boundary_string, \ 454 N_("Attempt to keep stack aligned to this power of 2") }, \ 455 { "branch-cost=", &ix86_branch_cost_string, \ 456 N_("Branches are this expensive (1-5, arbitrary units)") }, \ 457 { "cmodel=", &ix86_cmodel_string, \ 458 N_("Use given x86-64 code model") }, \ 459 { "debug-arg", &ix86_debug_arg_string, \ 460 "" /* Undocumented. */ }, \ 461 { "debug-addr", &ix86_debug_addr_string, \ 462 "" /* Undocumented. */ }, \ 463 { "asm=", &ix86_asm_string, \ 464 N_("Use given assembler dialect") }, \ 465 SUBTARGET_OPTIONS \ 466} 467 468/* Sometimes certain combinations of command options do not make 469 sense on a particular target machine. You can define a macro 470 `OVERRIDE_OPTIONS' to take account of this. This macro, if 471 defined, is executed once just after all the command options have 472 been parsed. 473 474 Don't use this macro to turn on various extra optimizations for 475 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 476 477#define OVERRIDE_OPTIONS override_options () 478 479/* These are meant to be redefined in the host dependent files */ 480#define SUBTARGET_SWITCHES 481#define SUBTARGET_OPTIONS 482 483/* Define this to change the optimizations performed by default. */ 484#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 485 optimization_options ((LEVEL), (SIZE)) 486 487/* Specs for the compiler proper */ 488 489#ifndef CC1_CPU_SPEC 490#define CC1_CPU_SPEC "\ 491%{!mcpu*: \ 492%{m386:-mcpu=i386 \ 493%n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \ 494%{m486:-mcpu=i486 \ 495%n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \ 496%{mpentium:-mcpu=pentium \ 497%n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \ 498%{mpentiumpro:-mcpu=pentiumpro \ 499%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \ 500%{mintel-syntax:-masm=intel \ 501%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 502%{mno-intel-syntax:-masm=att \ 503%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 504#endif 505 506#define TARGET_CPU_DEFAULT_i386 0 507#define TARGET_CPU_DEFAULT_i486 1 508#define TARGET_CPU_DEFAULT_pentium 2 509#define TARGET_CPU_DEFAULT_pentium_mmx 3 510#define TARGET_CPU_DEFAULT_pentiumpro 4 511#define TARGET_CPU_DEFAULT_pentium2 5 512#define TARGET_CPU_DEFAULT_pentium3 6 513#define TARGET_CPU_DEFAULT_pentium4 7 514#define TARGET_CPU_DEFAULT_k6 8 515#define TARGET_CPU_DEFAULT_k6_2 9 516#define TARGET_CPU_DEFAULT_k6_3 10 517#define TARGET_CPU_DEFAULT_athlon 11 518#define TARGET_CPU_DEFAULT_athlon_sse 12 519 520#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 521 "pentiumpro", "pentium2", "pentium3", \ 522 "pentium4", "k6", "k6-2", "k6-3",\ 523 "athlon", "athlon-4"} 524#ifndef CPP_CPU_DEFAULT_SPEC 525#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486 526#define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__" 527#endif 528#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium 529#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__" 530#endif 531#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx 532#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__" 533#endif 534#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro 535#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__" 536#endif 537#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2 538#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 539-D__tune_pentium2__" 540#endif 541#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3 542#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 543-D__tune_pentium2__ -D__tune_pentium3__" 544#endif 545#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4 546#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__" 547#endif 548#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6 549#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__" 550#endif 551#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2 552#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__" 553#endif 554#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3 555#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__" 556#endif 557#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon 558#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__" 559#endif 560#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse 561#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__" 562#endif 563#ifndef CPP_CPU_DEFAULT_SPEC 564#define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__" 565#endif 566#endif /* CPP_CPU_DEFAULT_SPEC */ 567 568#ifdef TARGET_BI_ARCH 569#define NO_BUILTIN_SIZE_TYPE 570#define NO_BUILTIN_PTRDIFF_TYPE 571#endif 572 573#ifdef NO_BUILTIN_SIZE_TYPE 574#define CPP_CPU32_SIZE_TYPE_SPEC \ 575 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int" 576#define CPP_CPU64_SIZE_TYPE_SPEC \ 577 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int" 578#else 579#define CPP_CPU32_SIZE_TYPE_SPEC "" 580#define CPP_CPU64_SIZE_TYPE_SPEC "" 581#endif 582 583#define CPP_CPU32_SPEC \ 584 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \ 585-D__i386__ %(cpp_cpu32sizet)" 586 587#define CPP_CPU64_SPEC \ 588 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)" 589 590#define CPP_CPUCOMMON_SPEC "\ 591%{march=i386:%{!mcpu*:-D__tune_i386__ }}\ 592%{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\ 593%{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 594 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\ 595%{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 596 -D__pentium__mmx__ \ 597 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\ 598%{march=pentiumpro|march=i686:-D__i686 -D__i686__ \ 599 -D__pentiumpro -D__pentiumpro__ \ 600 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\ 601%{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\ 602%{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \ 603 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\ 604%{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \ 605 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\ 606%{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \ 607 %{!mcpu*:-D__tune_athlon__ }}\ 608%{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \ 609 -D__athlon_sse__ \ 610 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\ 611%{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\ 612%{m386|mcpu=i386:-D__tune_i386__ }\ 613%{m486|mcpu=i486:-D__tune_i486__ }\ 614%{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\ 615%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \ 616-D__tune_pentiumpro__ }\ 617%{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\ 618%{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 619-D__tune_athlon__ }\ 620%{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 621-D__tune_athlon_sse__ }\ 622%{mcpu=pentium4:-D__tune_pentium4__ }\ 623%{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\ 624-D__SSE__ }\ 625%{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\ 626|march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 627|march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\ 628%{march=k6-2|march=k6-3\ 629|march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 630|march=athlon-mp: -D__3dNOW__ }\ 631%{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 632|march=athlon-mp: -D__3dNOW_A__ }\ 633%{march=pentium4: -D__SSE2__ }\ 634%{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}" 635 636#ifndef CPP_CPU_SPEC 637#ifdef TARGET_BI_ARCH 638#ifdef TARGET_64BIT_DEFAULT 639#define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)" 640#else 641#define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)" 642#endif 643#else 644#ifdef TARGET_64BIT_DEFAULT 645#define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)" 646#else 647#define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)" 648#endif 649#endif 650#endif 651 652#ifndef CC1_SPEC 653#define CC1_SPEC "%(cc1_cpu) " 654#endif 655 656/* This macro defines names of additional specifications to put in the 657 specs that can be used in various specifications like CC1_SPEC. Its 658 definition is an initializer with a subgrouping for each command option. 659 660 Each subgrouping contains a string constant, that defines the 661 specification name, and a string constant that used by the GNU CC driver 662 program. 663 664 Do not define this macro if it does not need to do anything. */ 665 666#ifndef SUBTARGET_EXTRA_SPECS 667#define SUBTARGET_EXTRA_SPECS 668#endif 669 670#define EXTRA_SPECS \ 671 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 672 { "cpp_cpu", CPP_CPU_SPEC }, \ 673 { "cpp_cpu32", CPP_CPU32_SPEC }, \ 674 { "cpp_cpu64", CPP_CPU64_SPEC }, \ 675 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \ 676 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \ 677 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \ 678 { "cc1_cpu", CC1_CPU_SPEC }, \ 679 SUBTARGET_EXTRA_SPECS 680 681/* target machine storage layout */ 682 683/* Define for XFmode or TFmode extended real floating point support. 684 This will automatically cause REAL_ARITHMETIC to be defined. 685 686 The XFmode is specified by i386 ABI, while TFmode may be faster 687 due to alignment and simplifications in the address calculations. 688 */ 689#define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96) 690#define MAX_LONG_DOUBLE_TYPE_SIZE 128 691#ifdef __x86_64__ 692#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 693#else 694#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 695#endif 696/* Tell real.c that this is the 80-bit Intel extended float format 697 packaged in a 128-bit or 96bit entity. */ 698#define INTEL_EXTENDED_IEEE_FORMAT 1 699 700 701#define SHORT_TYPE_SIZE 16 702#define INT_TYPE_SIZE 32 703#define FLOAT_TYPE_SIZE 32 704#ifndef LONG_TYPE_SIZE 705#define LONG_TYPE_SIZE BITS_PER_WORD 706#endif 707#define MAX_WCHAR_TYPE_SIZE 32 708#define DOUBLE_TYPE_SIZE 64 709#define LONG_LONG_TYPE_SIZE 64 710 711#if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT) 712#define MAX_BITS_PER_WORD 64 713#define MAX_LONG_TYPE_SIZE 64 714#else 715#define MAX_BITS_PER_WORD 32 716#define MAX_LONG_TYPE_SIZE 32 717#endif 718 719/* Define if you don't want extended real, but do want to use the 720 software floating point emulator for REAL_ARITHMETIC and 721 decimal <-> binary conversion. */ 722/* #define REAL_ARITHMETIC */ 723 724/* Define this if most significant byte of a word is the lowest numbered. */ 725/* That is true on the 80386. */ 726 727#define BITS_BIG_ENDIAN 0 728 729/* Define this if most significant byte of a word is the lowest numbered. */ 730/* That is not true on the 80386. */ 731#define BYTES_BIG_ENDIAN 0 732 733/* Define this if most significant word of a multiword number is the lowest 734 numbered. */ 735/* Not true for 80386 */ 736#define WORDS_BIG_ENDIAN 0 737 738/* number of bits in an addressable storage unit */ 739#define BITS_PER_UNIT 8 740 741/* Width in bits of a "word", which is the contents of a machine register. 742 Note that this is not necessarily the width of data type `int'; 743 if using 16-bit ints on a 80386, this would still be 32. 744 But on a machine with 16-bit registers, this would be 16. */ 745#define BITS_PER_WORD (TARGET_64BIT ? 64 : 32) 746 747/* Width of a word, in units (bytes). */ 748#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 749#define MIN_UNITS_PER_WORD 4 750 751/* Width in bits of a pointer. 752 See also the macro `Pmode' defined below. */ 753#define POINTER_SIZE BITS_PER_WORD 754 755/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 756#define PARM_BOUNDARY BITS_PER_WORD 757 758/* Boundary (in *bits*) on which stack pointer should be aligned. */ 759#define STACK_BOUNDARY BITS_PER_WORD 760 761/* Boundary (in *bits*) on which the stack pointer preferrs to be 762 aligned; the compiler cannot rely on having this alignment. */ 763#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 764 765/* As of July 2001, many runtimes to not align the stack properly when 766 entering main. This causes expand_main_function to forcably align 767 the stack, which results in aligned frames for functions called from 768 main, though it does nothing for the alignment of main itself. */ 769#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 770 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 771 772/* Allocation boundary for the code of a function. */ 773#define FUNCTION_BOUNDARY 16 774 775/* Alignment of field after `int : 0' in a structure. */ 776 777#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 778 779/* Minimum size in bits of the largest boundary to which any 780 and all fundamental data types supported by the hardware 781 might need to be aligned. No data type wants to be aligned 782 rounder than this. 783 784 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary 785 and Pentium Pro XFmode values at 128 bit boundaries. */ 786 787#define BIGGEST_ALIGNMENT 128 788 789/* Decide whether a variable of mode MODE must be 128 bit aligned. */ 790#define ALIGN_MODE_128(MODE) \ 791 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \ 792 || (MODE) == V4SFmode || (MODE) == V4SImode) 793 794/* The published ABIs say that doubles should be aligned on word 795 boundaries, so lower the aligment for structure fields unless 796 -malign-double is set. */ 797/* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be 798 constant. Use the smaller value in that context. */ 799#ifndef IN_TARGET_LIBS 800#define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32)) 801#else 802#define BIGGEST_FIELD_ALIGNMENT 32 803#endif 804 805/* If defined, a C expression to compute the alignment given to a 806 constant that is being placed in memory. EXP is the constant 807 and ALIGN is the alignment that the object would ordinarily have. 808 The value of this macro is used instead of that alignment to align 809 the object. 810 811 If this macro is not defined, then ALIGN is used. 812 813 The typical use of this macro is to increase alignment for string 814 constants to be word aligned so that `strcpy' calls that copy 815 constants can be done inline. */ 816 817#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 818 819/* If defined, a C expression to compute the alignment for a static 820 variable. TYPE is the data type, and ALIGN is the alignment that 821 the object would ordinarily have. The value of this macro is used 822 instead of that alignment to align the object. 823 824 If this macro is not defined, then ALIGN is used. 825 826 One use of this macro is to increase alignment of medium-size 827 data to make it all fit in fewer cache lines. Another is to 828 cause character arrays to be word-aligned so that `strcpy' calls 829 that copy constants to character arrays can be done inline. */ 830 831#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 832 833/* If defined, a C expression to compute the alignment for a local 834 variable. TYPE is the data type, and ALIGN is the alignment that 835 the object would ordinarily have. The value of this macro is used 836 instead of that alignment to align the object. 837 838 If this macro is not defined, then ALIGN is used. 839 840 One use of this macro is to increase alignment of medium-size 841 data to make it all fit in fewer cache lines. */ 842 843#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 844 845/* If defined, a C expression that gives the alignment boundary, in 846 bits, of an argument with the specified mode and type. If it is 847 not defined, `PARM_BOUNDARY' is used for all arguments. */ 848 849#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 850 ix86_function_arg_boundary ((MODE), (TYPE)) 851 852/* Set this non-zero if move instructions will actually fail to work 853 when given unaligned data. */ 854#define STRICT_ALIGNMENT 0 855 856/* If bit field type is int, don't let it cross an int, 857 and give entire struct the alignment of an int. */ 858/* Required on the 386 since it doesn't have bitfield insns. */ 859#define PCC_BITFIELD_TYPE_MATTERS 1 860 861/* Standard register usage. */ 862 863/* This processor has special stack-like registers. See reg-stack.c 864 for details. */ 865 866#define STACK_REGS 867#define IS_STACK_MODE(MODE) \ 868 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ 869 || (MODE) == TFmode) 870 871/* Number of actual hardware registers. 872 The hardware registers are assigned numbers for the compiler 873 from 0 to just below FIRST_PSEUDO_REGISTER. 874 All registers that the compiler knows about must be given numbers, 875 even those that are not normally considered general registers. 876 877 In the 80386 we give the 8 general purpose registers the numbers 0-7. 878 We number the floating point registers 8-15. 879 Note that registers 0-7 can be accessed as a short or int, 880 while only 0-3 may be used with byte `mov' instructions. 881 882 Reg 16 does not correspond to any hardware register, but instead 883 appears in the RTL as an argument pointer prior to reload, and is 884 eliminated during reloading in favor of either the stack or frame 885 pointer. */ 886 887#define FIRST_PSEUDO_REGISTER 53 888 889/* Number of hardware registers that go into the DWARF-2 unwind info. 890 If not defined, equals FIRST_PSEUDO_REGISTER. */ 891 892#define DWARF_FRAME_REGISTERS 17 893 894/* 1 for registers that have pervasive standard uses 895 and are not available for the register allocator. 896 On the 80386, the stack pointer is such, as is the arg pointer. 897 898 The value is an mask - bit 1 is set for fixed registers 899 for 32bit target, while 2 is set for fixed registers for 64bit. 900 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 901 */ 902#define FIXED_REGISTERS \ 903/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 904{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ 905/*arg,flags,fpsr,dir,frame*/ \ 906 3, 3, 3, 3, 3, \ 907/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 908 0, 0, 0, 0, 0, 0, 0, 0, \ 909/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 910 0, 0, 0, 0, 0, 0, 0, 0, \ 911/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 912 1, 1, 1, 1, 1, 1, 1, 1, \ 913/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 914 1, 1, 1, 1, 1, 1, 1, 1} 915 916 917/* 1 for registers not available across function calls. 918 These must include the FIXED_REGISTERS and also any 919 registers that can be used without being saved. 920 The latter must include the registers where values are returned 921 and the register where structure-value addresses are passed. 922 Aside from that, you can include as many other registers as you like. 923 924 The value is an mask - bit 1 is set for call used 925 for 32bit target, while 2 is set for call used for 64bit. 926 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 927*/ 928#define CALL_USED_REGISTERS \ 929/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 930{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 931/*arg,flags,fpsr,dir,frame*/ \ 932 3, 3, 3, 3, 3, \ 933/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 934 3, 3, 3, 3, 3, 3, 3, 3, \ 935/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 936 3, 3, 3, 3, 3, 3, 3, 3, \ 937/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 938 3, 3, 3, 3, 1, 1, 1, 1, \ 939/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 940 3, 3, 3, 3, 3, 3, 3, 3} \ 941 942/* Order in which to allocate registers. Each register must be 943 listed once, even those in FIXED_REGISTERS. List frame pointer 944 late and fixed registers last. Note that, in general, we prefer 945 registers listed in CALL_USED_REGISTERS, keeping the others 946 available for storage of persistent values. 947 948 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 949 so this is just empty initializer for array. */ 950 951#define REG_ALLOC_ORDER \ 952{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 953 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 954 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 955 48, 49, 50, 51, 52 } 956 957/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 958 to be rearranged based on a particular function. When using sse math, 959 we want to allocase SSE before x87 registers and vice vera. */ 960 961#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 962 963 964/* Macro to conditionally modify fixed_regs/call_used_regs. */ 965#define CONDITIONAL_REGISTER_USAGE \ 966do { \ 967 int i; \ 968 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 969 { \ 970 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ 971 call_used_regs[i] = (call_used_regs[i] \ 972 & (TARGET_64BIT ? 2 : 1)) != 0; \ 973 } \ 974 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 975 { \ 976 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 977 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 978 } \ 979 if (! TARGET_MMX) \ 980 { \ 981 int i; \ 982 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 983 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 984 fixed_regs[i] = call_used_regs[i] = 1; \ 985 } \ 986 if (! TARGET_SSE) \ 987 { \ 988 int i; \ 989 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 990 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 991 fixed_regs[i] = call_used_regs[i] = 1; \ 992 } \ 993 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 994 { \ 995 int i; \ 996 HARD_REG_SET x; \ 997 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 998 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 999 if (TEST_HARD_REG_BIT (x, i)) \ 1000 fixed_regs[i] = call_used_regs[i] = 1; \ 1001 } \ 1002 } while (0) 1003 1004/* Return number of consecutive hard regs needed starting at reg REGNO 1005 to hold something of mode MODE. 1006 This is ordinarily the length in words of a value of mode MODE 1007 but can be less for certain modes in special long registers. 1008 1009 Actually there are no two word move instructions for consecutive 1010 registers. And only registers 0-3 may have mov byte instructions 1011 applied to them. 1012 */ 1013 1014#define HARD_REGNO_NREGS(REGNO, MODE) \ 1015 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1016 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1017 : ((MODE) == TFmode \ 1018 ? (TARGET_64BIT ? 2 : 3) \ 1019 : (MODE) == TCmode \ 1020 ? (TARGET_64BIT ? 4 : 6) \ 1021 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1022 1023#define VALID_SSE_REG_MODE(MODE) \ 1024 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1025 || (MODE) == SFmode \ 1026 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) 1027 1028#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1029 ((MODE) == V2SFmode || (MODE) == SFmode) 1030 1031#define VALID_MMX_REG_MODE(MODE) \ 1032 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 1033 || (MODE) == V2SImode || (MODE) == SImode) 1034 1035#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1036 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ 1037 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ 1038 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) 1039 1040#define VALID_FP_MODE_P(MODE) \ 1041 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 1042 || (!TARGET_64BIT && (MODE) == XFmode) \ 1043 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \ 1044 || (!TARGET_64BIT && (MODE) == XCmode)) 1045 1046#define VALID_INT_MODE_P(MODE) \ 1047 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1048 || (MODE) == DImode \ 1049 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1050 || (MODE) == CDImode \ 1051 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) 1052 1053/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1054 1055#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1056 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1057 1058/* Value is 1 if it is a good idea to tie two pseudo registers 1059 when one has mode MODE1 and one has mode MODE2. 1060 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1061 for any hard reg, then this must be 0 for correct output. */ 1062 1063#define MODES_TIEABLE_P(MODE1, MODE2) \ 1064 ((MODE1) == (MODE2) \ 1065 || (((MODE1) == HImode || (MODE1) == SImode \ 1066 || ((MODE1) == QImode \ 1067 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1068 || ((MODE1) == DImode && TARGET_64BIT)) \ 1069 && ((MODE2) == HImode || (MODE2) == SImode \ 1070 || ((MODE1) == QImode \ 1071 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1072 || ((MODE2) == DImode && TARGET_64BIT)))) 1073 1074 1075/* Specify the modes required to caller save a given hard regno. 1076 We do this on i386 to prevent flags from being saved at all. 1077 1078 Kill any attempts to combine saving of modes. */ 1079 1080#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1081 (CC_REGNO_P (REGNO) ? VOIDmode \ 1082 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1083 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \ 1084 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1085 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 1086 : (MODE)) 1087/* Specify the registers used for certain standard purposes. 1088 The values of these macros are register numbers. */ 1089 1090/* on the 386 the pc register is %eip, and is not usable as a general 1091 register. The ordinary mov instructions won't work */ 1092/* #define PC_REGNUM */ 1093 1094/* Register to use for pushing function arguments. */ 1095#define STACK_POINTER_REGNUM 7 1096 1097/* Base register for access to local variables of the function. */ 1098#define HARD_FRAME_POINTER_REGNUM 6 1099 1100/* Base register for access to local variables of the function. */ 1101#define FRAME_POINTER_REGNUM 20 1102 1103/* First floating point reg */ 1104#define FIRST_FLOAT_REG 8 1105 1106/* First & last stack-like regs */ 1107#define FIRST_STACK_REG FIRST_FLOAT_REG 1108#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1109 1110#define FLAGS_REG 17 1111#define FPSR_REG 18 1112#define DIRFLAG_REG 19 1113 1114#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1115#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1116 1117#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1118#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1119 1120#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1121#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1122 1123#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1124#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1125 1126/* Value should be nonzero if functions must have frame pointers. 1127 Zero means the frame pointer need not be set up (and parms 1128 may be accessed via the stack pointer) in functions that seem suitable. 1129 This is computed in `reload', in reload1.c. */ 1130#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1131 1132/* Override this in other tm.h files to cope with various OS losage 1133 requiring a frame pointer. */ 1134#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1135#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1136#endif 1137 1138/* Make sure we can access arbitrary call frames. */ 1139#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1140 1141/* Base register for access to arguments of the function. */ 1142#define ARG_POINTER_REGNUM 16 1143 1144/* Register in which static-chain is passed to a function. 1145 We do use ECX as static chain register for 32 bit ABI. On the 1146 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1147#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1148 1149/* Register to hold the addressing base for position independent 1150 code access to data items. We don't use PIC pointer for 64bit 1151 mode. Define the regnum to dummy value to prevent gcc from 1152 pessimizing code dealing with EBX. */ 1153#define PIC_OFFSET_TABLE_REGNUM \ 1154 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM : 3) 1155 1156/* Register in which address to store a structure value 1157 arrives in the function. On the 386, the prologue 1158 copies this from the stack to register %eax. */ 1159#define STRUCT_VALUE_INCOMING 0 1160 1161/* Place in which caller passes the structure value address. 1162 0 means push the value on the stack like an argument. */ 1163#define STRUCT_VALUE 0 1164 1165/* A C expression which can inhibit the returning of certain function 1166 values in registers, based on the type of value. A nonzero value 1167 says to return the function value in memory, just as large 1168 structures are always returned. Here TYPE will be a C expression 1169 of type `tree', representing the data type of the value. 1170 1171 Note that values of mode `BLKmode' must be explicitly handled by 1172 this macro. Also, the option `-fpcc-struct-return' takes effect 1173 regardless of this macro. On most systems, it is possible to 1174 leave the macro undefined; this causes a default definition to be 1175 used, whose value is the constant 1 for `BLKmode' values, and 0 1176 otherwise. 1177 1178 Do not use this macro to indicate that structures and unions 1179 should always be returned in memory. You should instead use 1180 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1181 1182#define RETURN_IN_MEMORY(TYPE) \ 1183 ix86_return_in_memory (TYPE) 1184 1185 1186/* Define the classes of registers for register constraints in the 1187 machine description. Also define ranges of constants. 1188 1189 One of the classes must always be named ALL_REGS and include all hard regs. 1190 If there is more than one class, another class must be named NO_REGS 1191 and contain no registers. 1192 1193 The name GENERAL_REGS must be the name of a class (or an alias for 1194 another name such as ALL_REGS). This is the class of registers 1195 that is allowed by "g" or "r" in a register constraint. 1196 Also, registers outside this class are allocated only when 1197 instructions express preferences for them. 1198 1199 The classes must be numbered in nondecreasing order; that is, 1200 a larger-numbered class must never be contained completely 1201 in a smaller-numbered class. 1202 1203 For any two classes, it is very desirable that there be another 1204 class that represents their union. 1205 1206 It might seem that class BREG is unnecessary, since no useful 386 1207 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1208 and the "b" register constraint is useful in asms for syscalls. 1209 1210 The flags and fpsr registers are in no class. */ 1211 1212enum reg_class 1213{ 1214 NO_REGS, 1215 AREG, DREG, CREG, BREG, SIREG, DIREG, 1216 AD_REGS, /* %eax/%edx for DImode */ 1217 Q_REGS, /* %eax %ebx %ecx %edx */ 1218 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1219 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1220 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1221 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1222 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1223 FLOAT_REGS, 1224 SSE_REGS, 1225 MMX_REGS, 1226 FP_TOP_SSE_REGS, 1227 FP_SECOND_SSE_REGS, 1228 FLOAT_SSE_REGS, 1229 FLOAT_INT_REGS, 1230 INT_SSE_REGS, 1231 FLOAT_INT_SSE_REGS, 1232 ALL_REGS, LIM_REG_CLASSES 1233}; 1234 1235#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1236 1237#define INTEGER_CLASS_P(CLASS) \ 1238 reg_class_subset_p ((CLASS), GENERAL_REGS) 1239#define FLOAT_CLASS_P(CLASS) \ 1240 reg_class_subset_p ((CLASS), FLOAT_REGS) 1241#define SSE_CLASS_P(CLASS) \ 1242 reg_class_subset_p ((CLASS), SSE_REGS) 1243#define MMX_CLASS_P(CLASS) \ 1244 reg_class_subset_p ((CLASS), MMX_REGS) 1245#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1246 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1247#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1248 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1249#define MAYBE_SSE_CLASS_P(CLASS) \ 1250 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1251#define MAYBE_MMX_CLASS_P(CLASS) \ 1252 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1253 1254#define Q_CLASS_P(CLASS) \ 1255 reg_class_subset_p ((CLASS), Q_REGS) 1256 1257/* Give names of register classes as strings for dump file. */ 1258 1259#define REG_CLASS_NAMES \ 1260{ "NO_REGS", \ 1261 "AREG", "DREG", "CREG", "BREG", \ 1262 "SIREG", "DIREG", \ 1263 "AD_REGS", \ 1264 "Q_REGS", "NON_Q_REGS", \ 1265 "INDEX_REGS", \ 1266 "LEGACY_REGS", \ 1267 "GENERAL_REGS", \ 1268 "FP_TOP_REG", "FP_SECOND_REG", \ 1269 "FLOAT_REGS", \ 1270 "SSE_REGS", \ 1271 "MMX_REGS", \ 1272 "FP_TOP_SSE_REGS", \ 1273 "FP_SECOND_SSE_REGS", \ 1274 "FLOAT_SSE_REGS", \ 1275 "FLOAT_INT_REGS", \ 1276 "INT_SSE_REGS", \ 1277 "FLOAT_INT_SSE_REGS", \ 1278 "ALL_REGS" } 1279 1280/* Define which registers fit in which classes. 1281 This is an initializer for a vector of HARD_REG_SET 1282 of length N_REG_CLASSES. */ 1283 1284#define REG_CLASS_CONTENTS \ 1285{ { 0x00, 0x0 }, \ 1286 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1287 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1288 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1289 { 0x03, 0x0 }, /* AD_REGS */ \ 1290 { 0x0f, 0x0 }, /* Q_REGS */ \ 1291 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1292 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1293 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1294 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1295 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1296 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1297{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1298{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1299{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1300{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1301{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1302 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1303{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1304{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1305{ 0xffffffff,0x1fffff } \ 1306} 1307 1308/* The same information, inverted: 1309 Return the class number of the smallest class containing 1310 reg number REGNO. This could be a conditional expression 1311 or could index an array. */ 1312 1313#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1314 1315/* When defined, the compiler allows registers explicitly used in the 1316 rtl to be used as spill registers but prevents the compiler from 1317 extending the lifetime of these registers. */ 1318 1319#define SMALL_REGISTER_CLASSES 1 1320 1321#define QI_REG_P(X) \ 1322 (REG_P (X) && REGNO (X) < 4) 1323 1324#define GENERAL_REGNO_P(N) \ 1325 ((N) < 8 || REX_INT_REGNO_P (N)) 1326 1327#define GENERAL_REG_P(X) \ 1328 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1329 1330#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1331 1332#define NON_QI_REG_P(X) \ 1333 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1334 1335#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1336#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1337 1338#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1339#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1340#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1341#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1342 1343#define SSE_REGNO_P(N) \ 1344 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1345 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1346 1347#define SSE_REGNO(N) \ 1348 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1349#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1350 1351#define SSE_FLOAT_MODE_P(MODE) \ 1352 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1353 1354#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1355#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1356 1357#define STACK_REG_P(XOP) \ 1358 (REG_P (XOP) && \ 1359 REGNO (XOP) >= FIRST_STACK_REG && \ 1360 REGNO (XOP) <= LAST_STACK_REG) 1361 1362#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1363 1364#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1365 1366#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1367#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1368 1369/* Indicate whether hard register numbered REG_NO should be converted 1370 to SSA form. */ 1371#define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \ 1372 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM) 1373 1374/* The class value for index registers, and the one for base regs. */ 1375 1376#define INDEX_REG_CLASS INDEX_REGS 1377#define BASE_REG_CLASS GENERAL_REGS 1378 1379/* Get reg_class from a letter such as appears in the machine description. */ 1380 1381#define REG_CLASS_FROM_LETTER(C) \ 1382 ((C) == 'r' ? GENERAL_REGS : \ 1383 (C) == 'R' ? LEGACY_REGS : \ 1384 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1385 (C) == 'Q' ? Q_REGS : \ 1386 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1387 ? FLOAT_REGS \ 1388 : NO_REGS) : \ 1389 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1390 ? FP_TOP_REG \ 1391 : NO_REGS) : \ 1392 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1393 ? FP_SECOND_REG \ 1394 : NO_REGS) : \ 1395 (C) == 'a' ? AREG : \ 1396 (C) == 'b' ? BREG : \ 1397 (C) == 'c' ? CREG : \ 1398 (C) == 'd' ? DREG : \ 1399 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1400 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1401 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1402 (C) == 'A' ? AD_REGS : \ 1403 (C) == 'D' ? DIREG : \ 1404 (C) == 'S' ? SIREG : NO_REGS) 1405 1406/* The letters I, J, K, L and M in a register constraint string 1407 can be used to stand for particular ranges of immediate operands. 1408 This macro defines what the ranges are. 1409 C is the letter, and VALUE is a constant value. 1410 Return 1 if VALUE is in the range specified by C. 1411 1412 I is for non-DImode shifts. 1413 J is for DImode shifts. 1414 K is for signed imm8 operands. 1415 L is for andsi as zero-extending move. 1416 M is for shifts that can be executed by the "lea" opcode. 1417 N is for immedaite operands for out/in instructions (0-255) 1418 */ 1419 1420#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1421 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1422 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1423 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1424 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1425 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1426 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1427 : 0) 1428 1429/* Similar, but for floating constants, and defining letters G and H. 1430 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1431 TARGET_387 isn't set, because the stack register converter may need to 1432 load 0.0 into the function value register. */ 1433 1434#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1435 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1436 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0)) 1437 1438/* A C expression that defines the optional machine-dependent 1439 constraint letters that can be used to segregate specific types of 1440 operands, usually memory references, for the target machine. Any 1441 letter that is not elsewhere defined and not matched by 1442 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1443 be defined. 1444 1445 If it is required for a particular target machine, it should 1446 return 1 if VALUE corresponds to the operand type represented by 1447 the constraint letter C. If C is not defined as an extra 1448 constraint, the value returned should be 0 regardless of VALUE. */ 1449 1450#define EXTRA_CONSTRAINT(VALUE, C) \ 1451 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \ 1452 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \ 1453 : 0) 1454 1455/* Place additional restrictions on the register class to use when it 1456 is necessary to be able to hold a value of mode MODE in a reload 1457 register for which class CLASS would ordinarily be used. */ 1458 1459#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1460 ((MODE) == QImode && !TARGET_64BIT \ 1461 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1462 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1463 ? Q_REGS : (CLASS)) 1464 1465/* Given an rtx X being reloaded into a reg required to be 1466 in class CLASS, return the class of reg to actually use. 1467 In general this is just CLASS; but on some machines 1468 in some cases it is preferable to use a more restrictive class. 1469 On the 80386 series, we prevent floating constants from being 1470 reloaded into floating registers (since no move-insn can do that) 1471 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1472 1473/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1474 QImode must go into class Q_REGS. 1475 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1476 movdf to do mem-to-mem moves through integer regs. */ 1477 1478#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1479 ix86_preferred_reload_class ((X), (CLASS)) 1480 1481/* If we are copying between general and FP registers, we need a memory 1482 location. The same is true for SSE and MMX registers. */ 1483#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1484 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1485 1486/* QImode spills from non-QI registers need a scratch. This does not 1487 happen often -- the only example so far requires an uninitialized 1488 pseudo. */ 1489 1490#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1491 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1492 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1493 ? Q_REGS : NO_REGS) 1494 1495/* Return the maximum number of consecutive registers 1496 needed to represent mode MODE in a register of class CLASS. */ 1497/* On the 80386, this is the size of MODE in words, 1498 except in the FP regs, where a single reg is always enough. 1499 The TFmodes are really just 80bit values, so we use only 3 registers 1500 to hold them, instead of 4, as the size would suggest. 1501 */ 1502#define CLASS_MAX_NREGS(CLASS, MODE) \ 1503 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1504 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1505 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ 1506 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1507 1508/* A C expression whose value is nonzero if pseudos that have been 1509 assigned to registers of class CLASS would likely be spilled 1510 because registers of CLASS are needed for spill registers. 1511 1512 The default value of this macro returns 1 if CLASS has exactly one 1513 register and zero otherwise. On most machines, this default 1514 should be used. Only define this macro to some other expression 1515 if pseudo allocated by `local-alloc.c' end up in memory because 1516 their hard registers were needed for spill registers. If this 1517 macro returns nonzero for those classes, those pseudos will only 1518 be allocated by `global.c', which knows how to reallocate the 1519 pseudo to another register. If there would not be another 1520 register available for reallocation, you should not change the 1521 definition of this macro since the only effect of such a 1522 definition would be to slow down register allocation. */ 1523 1524#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1525 (((CLASS) == AREG) \ 1526 || ((CLASS) == DREG) \ 1527 || ((CLASS) == CREG) \ 1528 || ((CLASS) == BREG) \ 1529 || ((CLASS) == AD_REGS) \ 1530 || ((CLASS) == SIREG) \ 1531 || ((CLASS) == DIREG)) 1532 1533/* A C statement that adds to CLOBBERS any hard regs the port wishes 1534 to automatically clobber for all asms. 1535 1536 We do this in the new i386 backend to maintain source compatibility 1537 with the old cc0-based compiler. */ 1538 1539#define MD_ASM_CLOBBERS(CLOBBERS) \ 1540 do { \ 1541 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ 1542 (CLOBBERS)); \ 1543 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ 1544 (CLOBBERS)); \ 1545 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ 1546 (CLOBBERS)); \ 1547 } while (0) 1548 1549/* Stack layout; function entry, exit and calling. */ 1550 1551/* Define this if pushing a word on the stack 1552 makes the stack pointer a smaller address. */ 1553#define STACK_GROWS_DOWNWARD 1554 1555/* Define this if the nominal address of the stack frame 1556 is at the high-address end of the local variables; 1557 that is, each additional local variable allocated 1558 goes at a more negative offset in the frame. */ 1559#define FRAME_GROWS_DOWNWARD 1560 1561/* Offset within stack frame to start allocating local variables at. 1562 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1563 first local allocated. Otherwise, it is the offset to the BEGINNING 1564 of the first local allocated. */ 1565#define STARTING_FRAME_OFFSET 0 1566 1567/* If we generate an insn to push BYTES bytes, 1568 this says how many the stack pointer really advances by. 1569 On 386 pushw decrements by exactly 2 no matter what the position was. 1570 On the 386 there is no pushb; we use pushw instead, and this 1571 has the effect of rounding up to 2. 1572 1573 For 64bit ABI we round up to 8 bytes. 1574 */ 1575 1576#define PUSH_ROUNDING(BYTES) \ 1577 (TARGET_64BIT \ 1578 ? (((BYTES) + 7) & (-8)) \ 1579 : (((BYTES) + 1) & (-2))) 1580 1581/* If defined, the maximum amount of space required for outgoing arguments will 1582 be computed and placed into the variable 1583 `current_function_outgoing_args_size'. No space will be pushed onto the 1584 stack for each call; instead, the function prologue should increase the stack 1585 frame size by this amount. */ 1586 1587#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1588 1589/* If defined, a C expression whose value is nonzero when we want to use PUSH 1590 instructions to pass outgoing arguments. */ 1591 1592#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1593 1594/* Offset of first parameter from the argument pointer register value. */ 1595#define FIRST_PARM_OFFSET(FNDECL) 0 1596 1597/* Define this macro if functions should assume that stack space has been 1598 allocated for arguments even when their values are passed in registers. 1599 1600 The value of this macro is the size, in bytes, of the area reserved for 1601 arguments passed in registers for the function represented by FNDECL. 1602 1603 This space can be allocated by the caller, or be a part of the 1604 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1605 which. */ 1606#define REG_PARM_STACK_SPACE(FNDECL) 0 1607 1608/* Define as a C expression that evaluates to nonzero if we do not know how 1609 to pass TYPE solely in registers. The file expr.h defines a 1610 definition that is usually appropriate, refer to expr.h for additional 1611 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be 1612 computed in the stack and then loaded into a register. */ 1613#define MUST_PASS_IN_STACK(MODE, TYPE) \ 1614 ((TYPE) != 0 \ 1615 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1616 || TREE_ADDRESSABLE (TYPE) \ 1617 || ((MODE) == TImode) \ 1618 || ((MODE) == BLKmode \ 1619 && ! ((TYPE) != 0 \ 1620 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ 1621 && 0 == (int_size_in_bytes (TYPE) \ 1622 % (PARM_BOUNDARY / BITS_PER_UNIT))) \ 1623 && (FUNCTION_ARG_PADDING (MODE, TYPE) \ 1624 == (BYTES_BIG_ENDIAN ? upward : downward))))) 1625 1626/* Value is the number of bytes of arguments automatically 1627 popped when returning from a subroutine call. 1628 FUNDECL is the declaration node of the function (as a tree), 1629 FUNTYPE is the data type of the function (as a tree), 1630 or for a library call it is an identifier node for the subroutine name. 1631 SIZE is the number of bytes of arguments passed on the stack. 1632 1633 On the 80386, the RTD insn may be used to pop them if the number 1634 of args is fixed, but if the number is variable then the caller 1635 must pop them all. RTD can't be used for library calls now 1636 because the library is compiled with the Unix compiler. 1637 Use of RTD is a selectable option, since it is incompatible with 1638 standard Unix calling sequences. If the option is not selected, 1639 the caller must always pop the args. 1640 1641 The attribute stdcall is equivalent to RTD on a per module basis. */ 1642 1643#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1644 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1645 1646/* Define how to find the value returned by a function. 1647 VALTYPE is the data type of the value (as a tree). 1648 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1649 otherwise, FUNC is 0. */ 1650#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1651 ix86_function_value (VALTYPE) 1652 1653#define FUNCTION_VALUE_REGNO_P(N) \ 1654 ix86_function_value_regno_p (N) 1655 1656/* Define how to find the value returned by a library function 1657 assuming the value has mode MODE. */ 1658 1659#define LIBCALL_VALUE(MODE) \ 1660 ix86_libcall_value (MODE) 1661 1662/* Define the size of the result block used for communication between 1663 untyped_call and untyped_return. The block contains a DImode value 1664 followed by the block used by fnsave and frstor. */ 1665 1666#define APPLY_RESULT_SIZE (8+108) 1667 1668/* 1 if N is a possible register number for function argument passing. */ 1669#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1670 1671/* Define a data type for recording info about an argument list 1672 during the scan of that argument list. This data type should 1673 hold all necessary information about the function itself 1674 and about the args processed so far, enough to enable macros 1675 such as FUNCTION_ARG to determine where the next arg should go. */ 1676 1677typedef struct ix86_args { 1678 int words; /* # words passed so far */ 1679 int nregs; /* # registers available for passing */ 1680 int regno; /* next available register number */ 1681 int sse_words; /* # sse words passed so far */ 1682 int sse_nregs; /* # sse registers available for passing */ 1683 int sse_regno; /* next available sse register number */ 1684 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1685} CUMULATIVE_ARGS; 1686 1687/* Initialize a variable CUM of type CUMULATIVE_ARGS 1688 for a call to a function whose data type is FNTYPE. 1689 For a library call, FNTYPE is 0. */ 1690 1691#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1692 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) 1693 1694/* Update the data in CUM to advance over an argument 1695 of mode MODE and data type TYPE. 1696 (TYPE is null for libcalls where that information may not be available.) */ 1697 1698#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1699 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1700 1701/* Define where to put the arguments to a function. 1702 Value is zero to push the argument on the stack, 1703 or a hard register in which to store the argument. 1704 1705 MODE is the argument's machine mode. 1706 TYPE is the data type of the argument (as a tree). 1707 This is null for libcalls where that information may 1708 not be available. 1709 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1710 the preceding args and about the function being called. 1711 NAMED is nonzero if this argument is a named parameter 1712 (otherwise it is an extra parameter matching an ellipsis). */ 1713 1714#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1715 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1716 1717/* For an arg passed partly in registers and partly in memory, 1718 this is the number of registers used. 1719 For args passed entirely in registers or entirely in memory, zero. */ 1720 1721#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1722 1723/* If PIC, we cannot make sibling calls to global functions 1724 because the PLT requires %ebx live. 1725 If we are returning floats on the register stack, we cannot make 1726 sibling calls to functions that return floats. (The stack adjust 1727 instruction will wind up after the sibcall jump, and not be executed.) */ 1728#define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1729 ((DECL) \ 1730 && (! flag_pic || ! TREE_PUBLIC (DECL)) \ 1731 && (! TARGET_FLOAT_RETURNS_IN_80387 \ 1732 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \ 1733 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl)))))) 1734 1735/* Perform any needed actions needed for a function that is receiving a 1736 variable number of arguments. 1737 1738 CUM is as above. 1739 1740 MODE and TYPE are the mode and type of the current parameter. 1741 1742 PRETEND_SIZE is a variable that should be set to the amount of stack 1743 that must be pushed by the prolog to pretend that our caller pushed 1744 it. 1745 1746 Normally, this macro will push all remaining incoming registers on the 1747 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1748 1749#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1750 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ 1751 (NO_RTL)) 1752 1753/* Define the `__builtin_va_list' type for the ABI. */ 1754#define BUILD_VA_LIST_TYPE(VALIST) \ 1755 ((VALIST) = ix86_build_va_list ()) 1756 1757/* Implement `va_start' for varargs and stdarg. */ 1758#define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \ 1759 ix86_va_start ((STDARG), (VALIST), (NEXTARG)) 1760 1761/* Implement `va_arg'. */ 1762#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ 1763 ix86_va_arg ((VALIST), (TYPE)) 1764 1765/* This macro is invoked at the end of compilation. It is used here to 1766 output code for -fpic that will load the return address into %ebx. */ 1767 1768#undef ASM_FILE_END 1769#define ASM_FILE_END(FILE) ix86_asm_file_end (FILE) 1770 1771/* Output assembler code to FILE to increment profiler label # LABELNO 1772 for profiling a function entry. */ 1773 1774#define FUNCTION_PROFILER(FILE, LABELNO) \ 1775do { \ 1776 if (flag_pic) \ 1777 { \ 1778 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \ 1779 LPREFIX, (LABELNO)); \ 1780 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \ 1781 } \ 1782 else \ 1783 { \ 1784 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ 1785 fprintf ((FILE), "\tcall\t_mcount\n"); \ 1786 } \ 1787} while (0) 1788 1789/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1790 the stack pointer does not matter. The value is tested only in 1791 functions that have frame pointers. 1792 No definition is equivalent to always zero. */ 1793/* Note on the 386 it might be more efficient not to define this since 1794 we have to restore it ourselves from the frame pointer, in order to 1795 use pop */ 1796 1797#define EXIT_IGNORE_STACK 1 1798 1799/* Output assembler code for a block containing the constant parts 1800 of a trampoline, leaving space for the variable parts. */ 1801 1802/* On the 386, the trampoline contains two instructions: 1803 mov #STATIC,ecx 1804 jmp FUNCTION 1805 The trampoline is generated entirely at runtime. The operand of JMP 1806 is the address of FUNCTION relative to the instruction following the 1807 JMP (which is 5 bytes long). */ 1808 1809/* Length in units of the trampoline for entering a nested function. */ 1810 1811#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1812 1813/* Emit RTL insns to initialize the variable parts of a trampoline. 1814 FNADDR is an RTX for the address of the function's pure code. 1815 CXT is an RTX for the static chain value for the function. */ 1816 1817#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1818 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1819 1820/* Definitions for register eliminations. 1821 1822 This is an array of structures. Each structure initializes one pair 1823 of eliminable registers. The "from" register number is given first, 1824 followed by "to". Eliminations of the same "from" register are listed 1825 in order of preference. 1826 1827 There are two registers that can always be eliminated on the i386. 1828 The frame pointer and the arg pointer can be replaced by either the 1829 hard frame pointer or to the stack pointer, depending upon the 1830 circumstances. The hard frame pointer is not used before reload and 1831 so it is not eligible for elimination. */ 1832 1833#define ELIMINABLE_REGS \ 1834{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1835 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1836 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1837 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1838 1839/* Given FROM and TO register numbers, say whether this elimination is 1840 allowed. Frame pointer elimination is automatically handled. 1841 1842 All other eliminations are valid. */ 1843 1844#define CAN_ELIMINATE(FROM, TO) \ 1845 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1846 1847/* Define the offset between two registers, one to be eliminated, and the other 1848 its replacement, at the start of a routine. */ 1849 1850#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1851 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1852 1853/* Addressing modes, and classification of registers for them. */ 1854 1855/* #define HAVE_POST_INCREMENT 0 */ 1856/* #define HAVE_POST_DECREMENT 0 */ 1857 1858/* #define HAVE_PRE_DECREMENT 0 */ 1859/* #define HAVE_PRE_INCREMENT 0 */ 1860 1861/* Macros to check register numbers against specific register classes. */ 1862 1863/* These assume that REGNO is a hard or pseudo reg number. 1864 They give nonzero only if REGNO is a hard reg of the suitable class 1865 or a pseudo reg currently allocated to a suitable hard reg. 1866 Since they use reg_renumber, they are safe only once reg_renumber 1867 has been allocated, which happens in local-alloc.c. */ 1868 1869#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1870 ((REGNO) < STACK_POINTER_REGNUM \ 1871 || (REGNO >= FIRST_REX_INT_REG \ 1872 && (REGNO) <= LAST_REX_INT_REG) \ 1873 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1874 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1875 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1876 1877#define REGNO_OK_FOR_BASE_P(REGNO) \ 1878 ((REGNO) <= STACK_POINTER_REGNUM \ 1879 || (REGNO) == ARG_POINTER_REGNUM \ 1880 || (REGNO) == FRAME_POINTER_REGNUM \ 1881 || (REGNO >= FIRST_REX_INT_REG \ 1882 && (REGNO) <= LAST_REX_INT_REG) \ 1883 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1884 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1885 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1886 1887#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1888 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1889#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1890 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1891 1892/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1893 and check its validity for a certain class. 1894 We have two alternate definitions for each of them. 1895 The usual definition accepts all pseudo regs; the other rejects 1896 them unless they have been allocated suitable hard regs. 1897 The symbol REG_OK_STRICT causes the latter definition to be used. 1898 1899 Most source files want to accept pseudo regs in the hope that 1900 they will get allocated to the class that the insn wants them to be in. 1901 Source files for reload pass need to be strict. 1902 After reload, it makes no difference, since pseudo regs have 1903 been eliminated by then. */ 1904 1905 1906/* Non strict versions, pseudos are ok */ 1907#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1908 (REGNO (X) < STACK_POINTER_REGNUM \ 1909 || (REGNO (X) >= FIRST_REX_INT_REG \ 1910 && REGNO (X) <= LAST_REX_INT_REG) \ 1911 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1912 1913#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1914 (REGNO (X) <= STACK_POINTER_REGNUM \ 1915 || REGNO (X) == ARG_POINTER_REGNUM \ 1916 || REGNO (X) == FRAME_POINTER_REGNUM \ 1917 || (REGNO (X) >= FIRST_REX_INT_REG \ 1918 && REGNO (X) <= LAST_REX_INT_REG) \ 1919 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1920 1921/* Strict versions, hard registers only */ 1922#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1923#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1924 1925#ifndef REG_OK_STRICT 1926#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1927#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1928 1929#else 1930#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1931#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1932#endif 1933 1934/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1935 that is a valid memory address for an instruction. 1936 The MODE argument is the machine mode for the MEM expression 1937 that wants to use this address. 1938 1939 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1940 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1941 1942 See legitimize_pic_address in i386.c for details as to what 1943 constitutes a legitimate address when -fpic is used. */ 1944 1945#define MAX_REGS_PER_ADDRESS 2 1946 1947#define CONSTANT_ADDRESS_P(X) \ 1948 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1949 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1950 || GET_CODE (X) == CONST_DOUBLE) 1951 1952/* Nonzero if the constant value X is a legitimate general operand. 1953 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1954 1955#define LEGITIMATE_CONSTANT_P(X) 1 1956 1957#ifdef REG_OK_STRICT 1958#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1959do { \ 1960 if (legitimate_address_p ((MODE), (X), 1)) \ 1961 goto ADDR; \ 1962} while (0) 1963 1964#else 1965#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1966do { \ 1967 if (legitimate_address_p ((MODE), (X), 0)) \ 1968 goto ADDR; \ 1969} while (0) 1970 1971#endif 1972 1973/* If defined, a C expression to determine the base term of address X. 1974 This macro is used in only one place: `find_base_term' in alias.c. 1975 1976 It is always safe for this macro to not be defined. It exists so 1977 that alias analysis can understand machine-dependent addresses. 1978 1979 The typical use of this macro is to handle addresses containing 1980 a label_ref or symbol_ref within an UNSPEC. */ 1981 1982#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1983 1984/* Try machine-dependent ways of modifying an illegitimate address 1985 to be legitimate. If we find one, return the new, valid address. 1986 This macro is used in only one place: `memory_address' in explow.c. 1987 1988 OLDX is the address as it was before break_out_memory_refs was called. 1989 In some cases it is useful to look at this to decide what needs to be done. 1990 1991 MODE and WIN are passed so that this macro can use 1992 GO_IF_LEGITIMATE_ADDRESS. 1993 1994 It is always safe for this macro to do nothing. It exists to recognize 1995 opportunities to optimize the output. 1996 1997 For the 80386, we handle X+REG by loading X into a register R and 1998 using R+REG. R will go in a general reg and indexing will be used. 1999 However, if REG is a broken-out memory address or multiplication, 2000 nothing needs to be done because REG can certainly go in a general reg. 2001 2002 When -fpic is used, special handling is needed for symbolic references. 2003 See comments by legitimize_pic_address in i386.c for details. */ 2004 2005#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2006do { \ 2007 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 2008 if (memory_address_p ((MODE), (X))) \ 2009 goto WIN; \ 2010} while (0) 2011 2012#define REWRITE_ADDRESS(X) rewrite_address (X) 2013 2014/* Nonzero if the constant value X is a legitimate general operand 2015 when generating PIC code. It is given that flag_pic is on and 2016 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2017 2018#define LEGITIMATE_PIC_OPERAND_P(X) \ 2019 (! SYMBOLIC_CONST (X) \ 2020 || legitimate_pic_address_disp_p (X)) 2021 2022#define SYMBOLIC_CONST(X) \ 2023 (GET_CODE (X) == SYMBOL_REF \ 2024 || GET_CODE (X) == LABEL_REF \ 2025 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 2026 2027/* Go to LABEL if ADDR (a legitimate address expression) 2028 has an effect that depends on the machine mode it is used for. 2029 On the 80386, only postdecrement and postincrement address depend thus 2030 (the amount of decrement or increment being the length of the operand). */ 2031#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2032do { \ 2033 if (GET_CODE (ADDR) == POST_INC \ 2034 || GET_CODE (ADDR) == POST_DEC) \ 2035 goto LABEL; \ 2036} while (0) 2037 2038/* Codes for all the SSE/MMX builtins. */ 2039enum ix86_builtins 2040{ 2041 IX86_BUILTIN_ADDPS, 2042 IX86_BUILTIN_ADDSS, 2043 IX86_BUILTIN_DIVPS, 2044 IX86_BUILTIN_DIVSS, 2045 IX86_BUILTIN_MULPS, 2046 IX86_BUILTIN_MULSS, 2047 IX86_BUILTIN_SUBPS, 2048 IX86_BUILTIN_SUBSS, 2049 2050 IX86_BUILTIN_CMPEQPS, 2051 IX86_BUILTIN_CMPLTPS, 2052 IX86_BUILTIN_CMPLEPS, 2053 IX86_BUILTIN_CMPGTPS, 2054 IX86_BUILTIN_CMPGEPS, 2055 IX86_BUILTIN_CMPNEQPS, 2056 IX86_BUILTIN_CMPNLTPS, 2057 IX86_BUILTIN_CMPNLEPS, 2058 IX86_BUILTIN_CMPNGTPS, 2059 IX86_BUILTIN_CMPNGEPS, 2060 IX86_BUILTIN_CMPORDPS, 2061 IX86_BUILTIN_CMPUNORDPS, 2062 IX86_BUILTIN_CMPNEPS, 2063 IX86_BUILTIN_CMPEQSS, 2064 IX86_BUILTIN_CMPLTSS, 2065 IX86_BUILTIN_CMPLESS, 2066 IX86_BUILTIN_CMPGTSS, 2067 IX86_BUILTIN_CMPGESS, 2068 IX86_BUILTIN_CMPNEQSS, 2069 IX86_BUILTIN_CMPNLTSS, 2070 IX86_BUILTIN_CMPNLESS, 2071 IX86_BUILTIN_CMPNGTSS, 2072 IX86_BUILTIN_CMPNGESS, 2073 IX86_BUILTIN_CMPORDSS, 2074 IX86_BUILTIN_CMPUNORDSS, 2075 IX86_BUILTIN_CMPNESS, 2076 2077 IX86_BUILTIN_COMIEQSS, 2078 IX86_BUILTIN_COMILTSS, 2079 IX86_BUILTIN_COMILESS, 2080 IX86_BUILTIN_COMIGTSS, 2081 IX86_BUILTIN_COMIGESS, 2082 IX86_BUILTIN_COMINEQSS, 2083 IX86_BUILTIN_UCOMIEQSS, 2084 IX86_BUILTIN_UCOMILTSS, 2085 IX86_BUILTIN_UCOMILESS, 2086 IX86_BUILTIN_UCOMIGTSS, 2087 IX86_BUILTIN_UCOMIGESS, 2088 IX86_BUILTIN_UCOMINEQSS, 2089 2090 IX86_BUILTIN_CVTPI2PS, 2091 IX86_BUILTIN_CVTPS2PI, 2092 IX86_BUILTIN_CVTSI2SS, 2093 IX86_BUILTIN_CVTSS2SI, 2094 IX86_BUILTIN_CVTTPS2PI, 2095 IX86_BUILTIN_CVTTSS2SI, 2096 2097 IX86_BUILTIN_MAXPS, 2098 IX86_BUILTIN_MAXSS, 2099 IX86_BUILTIN_MINPS, 2100 IX86_BUILTIN_MINSS, 2101 2102 IX86_BUILTIN_LOADAPS, 2103 IX86_BUILTIN_LOADUPS, 2104 IX86_BUILTIN_STOREAPS, 2105 IX86_BUILTIN_STOREUPS, 2106 IX86_BUILTIN_LOADSS, 2107 IX86_BUILTIN_STORESS, 2108 IX86_BUILTIN_MOVSS, 2109 2110 IX86_BUILTIN_MOVHLPS, 2111 IX86_BUILTIN_MOVLHPS, 2112 IX86_BUILTIN_LOADHPS, 2113 IX86_BUILTIN_LOADLPS, 2114 IX86_BUILTIN_STOREHPS, 2115 IX86_BUILTIN_STORELPS, 2116 2117 IX86_BUILTIN_MASKMOVQ, 2118 IX86_BUILTIN_MOVMSKPS, 2119 IX86_BUILTIN_PMOVMSKB, 2120 2121 IX86_BUILTIN_MOVNTPS, 2122 IX86_BUILTIN_MOVNTQ, 2123 2124 IX86_BUILTIN_PACKSSWB, 2125 IX86_BUILTIN_PACKSSDW, 2126 IX86_BUILTIN_PACKUSWB, 2127 2128 IX86_BUILTIN_PADDB, 2129 IX86_BUILTIN_PADDW, 2130 IX86_BUILTIN_PADDD, 2131 IX86_BUILTIN_PADDSB, 2132 IX86_BUILTIN_PADDSW, 2133 IX86_BUILTIN_PADDUSB, 2134 IX86_BUILTIN_PADDUSW, 2135 IX86_BUILTIN_PSUBB, 2136 IX86_BUILTIN_PSUBW, 2137 IX86_BUILTIN_PSUBD, 2138 IX86_BUILTIN_PSUBSB, 2139 IX86_BUILTIN_PSUBSW, 2140 IX86_BUILTIN_PSUBUSB, 2141 IX86_BUILTIN_PSUBUSW, 2142 2143 IX86_BUILTIN_PAND, 2144 IX86_BUILTIN_PANDN, 2145 IX86_BUILTIN_POR, 2146 IX86_BUILTIN_PXOR, 2147 2148 IX86_BUILTIN_PAVGB, 2149 IX86_BUILTIN_PAVGW, 2150 2151 IX86_BUILTIN_PCMPEQB, 2152 IX86_BUILTIN_PCMPEQW, 2153 IX86_BUILTIN_PCMPEQD, 2154 IX86_BUILTIN_PCMPGTB, 2155 IX86_BUILTIN_PCMPGTW, 2156 IX86_BUILTIN_PCMPGTD, 2157 2158 IX86_BUILTIN_PEXTRW, 2159 IX86_BUILTIN_PINSRW, 2160 2161 IX86_BUILTIN_PMADDWD, 2162 2163 IX86_BUILTIN_PMAXSW, 2164 IX86_BUILTIN_PMAXUB, 2165 IX86_BUILTIN_PMINSW, 2166 IX86_BUILTIN_PMINUB, 2167 2168 IX86_BUILTIN_PMULHUW, 2169 IX86_BUILTIN_PMULHW, 2170 IX86_BUILTIN_PMULLW, 2171 2172 IX86_BUILTIN_PSADBW, 2173 IX86_BUILTIN_PSHUFW, 2174 2175 IX86_BUILTIN_PSLLW, 2176 IX86_BUILTIN_PSLLD, 2177 IX86_BUILTIN_PSLLQ, 2178 IX86_BUILTIN_PSRAW, 2179 IX86_BUILTIN_PSRAD, 2180 IX86_BUILTIN_PSRLW, 2181 IX86_BUILTIN_PSRLD, 2182 IX86_BUILTIN_PSRLQ, 2183 IX86_BUILTIN_PSLLWI, 2184 IX86_BUILTIN_PSLLDI, 2185 IX86_BUILTIN_PSLLQI, 2186 IX86_BUILTIN_PSRAWI, 2187 IX86_BUILTIN_PSRADI, 2188 IX86_BUILTIN_PSRLWI, 2189 IX86_BUILTIN_PSRLDI, 2190 IX86_BUILTIN_PSRLQI, 2191 2192 IX86_BUILTIN_PUNPCKHBW, 2193 IX86_BUILTIN_PUNPCKHWD, 2194 IX86_BUILTIN_PUNPCKHDQ, 2195 IX86_BUILTIN_PUNPCKLBW, 2196 IX86_BUILTIN_PUNPCKLWD, 2197 IX86_BUILTIN_PUNPCKLDQ, 2198 2199 IX86_BUILTIN_SHUFPS, 2200 2201 IX86_BUILTIN_RCPPS, 2202 IX86_BUILTIN_RCPSS, 2203 IX86_BUILTIN_RSQRTPS, 2204 IX86_BUILTIN_RSQRTSS, 2205 IX86_BUILTIN_SQRTPS, 2206 IX86_BUILTIN_SQRTSS, 2207 2208 IX86_BUILTIN_UNPCKHPS, 2209 IX86_BUILTIN_UNPCKLPS, 2210 2211 IX86_BUILTIN_ANDPS, 2212 IX86_BUILTIN_ANDNPS, 2213 IX86_BUILTIN_ORPS, 2214 IX86_BUILTIN_XORPS, 2215 2216 IX86_BUILTIN_EMMS, 2217 IX86_BUILTIN_LDMXCSR, 2218 IX86_BUILTIN_STMXCSR, 2219 IX86_BUILTIN_SFENCE, 2220 2221 /* 3DNow! Original */ 2222 IX86_BUILTIN_FEMMS, 2223 IX86_BUILTIN_PAVGUSB, 2224 IX86_BUILTIN_PF2ID, 2225 IX86_BUILTIN_PFACC, 2226 IX86_BUILTIN_PFADD, 2227 IX86_BUILTIN_PFCMPEQ, 2228 IX86_BUILTIN_PFCMPGE, 2229 IX86_BUILTIN_PFCMPGT, 2230 IX86_BUILTIN_PFMAX, 2231 IX86_BUILTIN_PFMIN, 2232 IX86_BUILTIN_PFMUL, 2233 IX86_BUILTIN_PFRCP, 2234 IX86_BUILTIN_PFRCPIT1, 2235 IX86_BUILTIN_PFRCPIT2, 2236 IX86_BUILTIN_PFRSQIT1, 2237 IX86_BUILTIN_PFRSQRT, 2238 IX86_BUILTIN_PFSUB, 2239 IX86_BUILTIN_PFSUBR, 2240 IX86_BUILTIN_PI2FD, 2241 IX86_BUILTIN_PMULHRW, 2242 2243 /* 3DNow! Athlon Extensions */ 2244 IX86_BUILTIN_PF2IW, 2245 IX86_BUILTIN_PFNACC, 2246 IX86_BUILTIN_PFPNACC, 2247 IX86_BUILTIN_PI2FW, 2248 IX86_BUILTIN_PSWAPDSI, 2249 IX86_BUILTIN_PSWAPDSF, 2250 2251 IX86_BUILTIN_SSE_ZERO, 2252 IX86_BUILTIN_MMX_ZERO, 2253 2254 IX86_BUILTIN_MAX 2255}; 2256 2257/* Define this macro if references to a symbol must be treated 2258 differently depending on something about the variable or 2259 function named by the symbol (such as what section it is in). 2260 2261 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol 2262 so that we may access it directly in the GOT. */ 2263 2264#define ENCODE_SECTION_INFO(DECL) \ 2265do { \ 2266 if (flag_pic) \ 2267 { \ 2268 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2269 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ 2270 \ 2271 if (GET_CODE (rtl) == MEM) \ 2272 { \ 2273 if (TARGET_DEBUG_ADDR \ 2274 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \ 2275 { \ 2276 fprintf (stderr, "Encode %s, public = %d\n", \ 2277 IDENTIFIER_POINTER (DECL_NAME (DECL)), \ 2278 TREE_PUBLIC (DECL)); \ 2279 } \ 2280 \ 2281 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ 2282 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2283 || ! TREE_PUBLIC (DECL)); \ 2284 } \ 2285 } \ 2286} while (0) 2287 2288/* The `FINALIZE_PIC' macro serves as a hook to emit these special 2289 codes once the function is being compiled into assembly code, but 2290 not before. (It is not done before, because in the case of 2291 compiling an inline function, it would lead to multiple PIC 2292 prologues being included in functions which used inline functions 2293 and were compiled to assembly language.) */ 2294 2295#define FINALIZE_PIC \ 2296 (current_function_uses_pic_offset_table |= current_function_profile) 2297 2298 2299/* Max number of args passed in registers. If this is more than 3, we will 2300 have problems with ebx (register #4), since it is a caller save register and 2301 is also used as the pic register in ELF. So for now, don't allow more than 2302 3 registers to be passed in registers. */ 2303 2304#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 2305 2306#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0) 2307 2308 2309/* Specify the machine mode that this machine uses 2310 for the index in the tablejump instruction. */ 2311#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 2312 2313/* Define as C expression which evaluates to nonzero if the tablejump 2314 instruction expects the table to contain offsets from the address of the 2315 table. 2316 Do not define this if the table should contain absolute addresses. */ 2317/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2318 2319/* Define this as 1 if `char' should by default be signed; else as 0. */ 2320#define DEFAULT_SIGNED_CHAR 1 2321 2322/* Number of bytes moved into a data cache for a single prefetch operation. */ 2323#define PREFETCH_BLOCK ix86_cost->prefetch_block 2324 2325/* Number of prefetch operations that can be done in parallel. */ 2326#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 2327 2328/* Max number of bytes we can move from memory to memory 2329 in one reasonably fast instruction. */ 2330#define MOVE_MAX 16 2331 2332/* MOVE_MAX_PIECES is the number of bytes at a time which we can 2333 move efficiently, as opposed to MOVE_MAX which is the maximum 2334 number of bytes we can move with a single instruction. */ 2335#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 2336 2337/* If a memory-to-memory move would take MOVE_RATIO or more simple 2338 move-instruction pairs, we will do a movstr or libcall instead. 2339 Increasing the value will always make code faster, but eventually 2340 incurs high cost in increased code size. 2341 2342 If you don't define this, a reasonable default is used. */ 2343 2344#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 2345 2346/* Define if shifts truncate the shift count 2347 which implies one can omit a sign-extension or zero-extension 2348 of a shift count. */ 2349/* On i386, shifts do truncate the count. But bit opcodes don't. */ 2350 2351/* #define SHIFT_COUNT_TRUNCATED */ 2352 2353/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2354 is done just by pretending it is already truncated. */ 2355#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2356 2357/* We assume that the store-condition-codes instructions store 0 for false 2358 and some other value for true. This is the value stored for true. */ 2359 2360#define STORE_FLAG_VALUE 1 2361 2362/* When a prototype says `char' or `short', really pass an `int'. 2363 (The 386 can't easily push less than an int.) */ 2364 2365#define PROMOTE_PROTOTYPES (!TARGET_64BIT) 2366 2367/* A macro to update M and UNSIGNEDP when an object whose type is 2368 TYPE and which has the specified mode and signedness is to be 2369 stored in a register. This macro is only called when TYPE is a 2370 scalar type. 2371 2372 On i386 it is sometimes useful to promote HImode and QImode 2373 quantities to SImode. The choice depends on target type. */ 2374 2375#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2376do { \ 2377 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 2378 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 2379 (MODE) = SImode; \ 2380} while (0) 2381 2382/* Specify the machine mode that pointers have. 2383 After generation of rtl, the compiler makes no further distinction 2384 between pointers and any other objects of this machine mode. */ 2385#define Pmode (TARGET_64BIT ? DImode : SImode) 2386 2387/* A function address in a call instruction 2388 is a byte address (for indexing purposes) 2389 so give the MEM rtx a byte's mode. */ 2390#define FUNCTION_MODE QImode 2391 2392/* A part of a C `switch' statement that describes the relative costs 2393 of constant RTL expressions. It must contain `case' labels for 2394 expression codes `const_int', `const', `symbol_ref', `label_ref' 2395 and `const_double'. Each case must ultimately reach a `return' 2396 statement to return the relative cost of the use of that kind of 2397 constant value in an expression. The cost may depend on the 2398 precise value of the constant, which is available for examination 2399 in X, and the rtx code of the expression in which it is contained, 2400 found in OUTER_CODE. 2401 2402 CODE is the expression code--redundant, since it can be obtained 2403 with `GET_CODE (X)'. */ 2404 2405#define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 2406 case CONST_INT: \ 2407 case CONST: \ 2408 case LABEL_REF: \ 2409 case SYMBOL_REF: \ 2410 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \ 2411 return 3; \ 2412 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \ 2413 return 2; \ 2414 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \ 2415 \ 2416 case CONST_DOUBLE: \ 2417 { \ 2418 int code; \ 2419 if (GET_MODE (RTX) == VOIDmode) \ 2420 return 0; \ 2421 \ 2422 code = standard_80387_constant_p (RTX); \ 2423 return code == 1 ? 1 : \ 2424 code == 2 ? 2 : \ 2425 3; \ 2426 } 2427 2428/* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ 2429#define TOPLEVEL_COSTS_N_INSNS(N) \ 2430 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) 2431 2432/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. 2433 This can be used, for example, to indicate how costly a multiply 2434 instruction is. In writing this macro, you can use the construct 2435 `COSTS_N_INSNS (N)' to specify a cost equal to N fast 2436 instructions. OUTER_CODE is the code of the expression in which X 2437 is contained. 2438 2439 This macro is optional; do not define it if the default cost 2440 assumptions are adequate for the target machine. */ 2441 2442#define RTX_COSTS(X, CODE, OUTER_CODE) \ 2443 case ZERO_EXTEND: \ 2444 /* The zero extensions is often completely free on x86_64, so make \ 2445 it as cheap as possible. */ \ 2446 if (TARGET_64BIT && GET_MODE (X) == DImode \ 2447 && GET_MODE (XEXP (X, 0)) == SImode) \ 2448 { \ 2449 total = 1; goto egress_rtx_costs; \ 2450 } \ 2451 else \ 2452 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \ 2453 ix86_cost->add : ix86_cost->movzx); \ 2454 break; \ 2455 case SIGN_EXTEND: \ 2456 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \ 2457 break; \ 2458 case ASHIFT: \ 2459 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 2460 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \ 2461 { \ 2462 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2463 if (value == 1) \ 2464 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2465 if ((value == 2 || value == 3) \ 2466 && !TARGET_DECOMPOSE_LEA \ 2467 && ix86_cost->lea <= ix86_cost->shift_const) \ 2468 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ 2469 } \ 2470 /* fall through */ \ 2471 \ 2472 case ROTATE: \ 2473 case ASHIFTRT: \ 2474 case LSHIFTRT: \ 2475 case ROTATERT: \ 2476 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \ 2477 { \ 2478 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2479 { \ 2480 if (INTVAL (XEXP (X, 1)) > 32) \ 2481 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ 2482 else \ 2483 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ 2484 } \ 2485 else \ 2486 { \ 2487 if (GET_CODE (XEXP (X, 1)) == AND) \ 2488 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ 2489 else \ 2490 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ 2491 } \ 2492 } \ 2493 else \ 2494 { \ 2495 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2496 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ 2497 else \ 2498 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ 2499 } \ 2500 break; \ 2501 \ 2502 case MULT: \ 2503 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2504 { \ 2505 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2506 int nbits = 0; \ 2507 \ 2508 while (value != 0) \ 2509 { \ 2510 nbits++; \ 2511 value >>= 1; \ 2512 } \ 2513 \ 2514 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2515 + nbits * ix86_cost->mult_bit); \ 2516 } \ 2517 else /* This is arbitrary */ \ 2518 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2519 + 7 * ix86_cost->mult_bit); \ 2520 \ 2521 case DIV: \ 2522 case UDIV: \ 2523 case MOD: \ 2524 case UMOD: \ 2525 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ 2526 \ 2527 case PLUS: \ 2528 if (!TARGET_DECOMPOSE_LEA \ 2529 && INTEGRAL_MODE_P (GET_MODE (X)) \ 2530 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \ 2531 { \ 2532 if (GET_CODE (XEXP (X, 0)) == PLUS \ 2533 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ 2534 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ 2535 && CONSTANT_P (XEXP (X, 1))) \ 2536 { \ 2537 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\ 2538 if (val == 2 || val == 4 || val == 8) \ 2539 { \ 2540 return (COSTS_N_INSNS (ix86_cost->lea) \ 2541 + rtx_cost (XEXP (XEXP (X, 0), 1), \ 2542 (OUTER_CODE)) \ 2543 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \ 2544 (OUTER_CODE)) \ 2545 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2546 } \ 2547 } \ 2548 else if (GET_CODE (XEXP (X, 0)) == MULT \ 2549 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ 2550 { \ 2551 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ 2552 if (val == 2 || val == 4 || val == 8) \ 2553 { \ 2554 return (COSTS_N_INSNS (ix86_cost->lea) \ 2555 + rtx_cost (XEXP (XEXP (X, 0), 0), \ 2556 (OUTER_CODE)) \ 2557 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2558 } \ 2559 } \ 2560 else if (GET_CODE (XEXP (X, 0)) == PLUS) \ 2561 { \ 2562 return (COSTS_N_INSNS (ix86_cost->lea) \ 2563 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \ 2564 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \ 2565 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2566 } \ 2567 } \ 2568 \ 2569 /* fall through */ \ 2570 case AND: \ 2571 case IOR: \ 2572 case XOR: \ 2573 case MINUS: \ 2574 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2575 return (COSTS_N_INSNS (ix86_cost->add) * 2 \ 2576 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \ 2577 << (GET_MODE (XEXP (X, 0)) != DImode)) \ 2578 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \ 2579 << (GET_MODE (XEXP (X, 1)) != DImode))); \ 2580 \ 2581 /* fall through */ \ 2582 case NEG: \ 2583 case NOT: \ 2584 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2585 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ 2586 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2587 \ 2588 egress_rtx_costs: \ 2589 break; 2590 2591 2592/* An expression giving the cost of an addressing mode that contains 2593 ADDRESS. If not defined, the cost is computed from the ADDRESS 2594 expression and the `CONST_COSTS' values. 2595 2596 For most CISC machines, the default cost is a good approximation 2597 of the true cost of the addressing mode. However, on RISC 2598 machines, all instructions normally have the same length and 2599 execution time. Hence all addresses will have equal costs. 2600 2601 In cases where more than one form of an address is known, the form 2602 with the lowest cost will be used. If multiple forms have the 2603 same, lowest, cost, the one that is the most complex will be used. 2604 2605 For example, suppose an address that is equal to the sum of a 2606 register and a constant is used twice in the same basic block. 2607 When this macro is not defined, the address will be computed in a 2608 register and memory references will be indirect through that 2609 register. On machines where the cost of the addressing mode 2610 containing the sum is no higher than that of a simple indirect 2611 reference, this will produce an additional instruction and 2612 possibly require an additional register. Proper specification of 2613 this macro eliminates this overhead for such machines. 2614 2615 Similar use of this macro is made in strength reduction of loops. 2616 2617 ADDRESS need not be valid as an address. In such a case, the cost 2618 is not relevant and can be any value; invalid addresses need not be 2619 assigned a different cost. 2620 2621 On machines where an address involving more than one register is as 2622 cheap as an address computation involving only one register, 2623 defining `ADDRESS_COST' to reflect this can cause two registers to 2624 be live over a region of code where only one would have been if 2625 `ADDRESS_COST' were not defined in that manner. This effect should 2626 be considered in the definition of this macro. Equivalent costs 2627 should probably only be given to addresses with different numbers 2628 of registers on machines with lots of registers. 2629 2630 This macro will normally either not be defined or be defined as a 2631 constant. 2632 2633 For i386, it is better to use a complex address than let gcc copy 2634 the address into a reg and make a new pseudo. But not if the address 2635 requires to two regs - that would mean more pseudos with longer 2636 lifetimes. */ 2637 2638#define ADDRESS_COST(RTX) \ 2639 ix86_address_cost (RTX) 2640 2641/* A C expression for the cost of moving data from a register in class FROM to 2642 one in class TO. The classes are expressed using the enumeration values 2643 such as `GENERAL_REGS'. A value of 2 is the default; other values are 2644 interpreted relative to that. 2645 2646 It is not required that the cost always equal 2 when FROM is the same as TO; 2647 on some machines it is expensive to move between registers if they are not 2648 general registers. */ 2649 2650#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2651 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 2652 2653/* A C expression for the cost of moving data of mode M between a 2654 register and memory. A value of 2 is the default; this cost is 2655 relative to those in `REGISTER_MOVE_COST'. 2656 2657 If moving between registers and memory is more expensive than 2658 between two registers, you should define this macro to express the 2659 relative cost. */ 2660 2661#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 2662 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 2663 2664/* A C expression for the cost of a branch instruction. A value of 1 2665 is the default; other values are interpreted relative to that. */ 2666 2667#define BRANCH_COST ix86_branch_cost 2668 2669/* Define this macro as a C expression which is nonzero if accessing 2670 less than a word of memory (i.e. a `char' or a `short') is no 2671 faster than accessing a word of memory, i.e., if such access 2672 require more than one instruction or if there is no difference in 2673 cost between byte and (aligned) word loads. 2674 2675 When this macro is not defined, the compiler will access a field by 2676 finding the smallest containing object; when it is defined, a 2677 fullword load will be used if alignment permits. Unless bytes 2678 accesses are faster than word accesses, using word accesses is 2679 preferable since it may eliminate subsequent memory access if 2680 subsequent accesses occur to other fields in the same word of the 2681 structure, but to different bytes. */ 2682 2683#define SLOW_BYTE_ACCESS 0 2684 2685/* Nonzero if access to memory by shorts is slow and undesirable. */ 2686#define SLOW_SHORT_ACCESS 0 2687 2688/* Define this macro to be the value 1 if unaligned accesses have a 2689 cost many times greater than aligned accesses, for example if they 2690 are emulated in a trap handler. 2691 2692 When this macro is non-zero, the compiler will act as if 2693 `STRICT_ALIGNMENT' were non-zero when generating code for block 2694 moves. This can cause significantly more instructions to be 2695 produced. Therefore, do not set this macro non-zero if unaligned 2696 accesses only add a cycle or two to the time for a memory access. 2697 2698 If the value of this macro is always zero, it need not be defined. */ 2699 2700/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2701 2702/* Define this macro to inhibit strength reduction of memory 2703 addresses. (On some machines, such strength reduction seems to do 2704 harm rather than good.) */ 2705 2706/* #define DONT_REDUCE_ADDR */ 2707 2708/* Define this macro if it is as good or better to call a constant 2709 function address than to call an address kept in a register. 2710 2711 Desirable on the 386 because a CALL with a constant address is 2712 faster than one with a register address. */ 2713 2714#define NO_FUNCTION_CSE 2715 2716/* Define this macro if it is as good or better for a function to call 2717 itself with an explicit address than to call an address kept in a 2718 register. */ 2719 2720#define NO_RECURSIVE_FUNCTION_CSE 2721 2722/* Add any extra modes needed to represent the condition code. 2723 2724 For the i386, we need separate modes when floating-point 2725 equality comparisons are being done. 2726 2727 Add CCNO to indicate comparisons against zero that requires 2728 Overflow flag to be unset. Sign bit test is used instead and 2729 thus can be used to form "a&b>0" type of tests. 2730 2731 Add CCGC to indicate comparisons agains zero that allows 2732 unspecified garbage in the Carry flag. This mode is used 2733 by inc/dec instructions. 2734 2735 Add CCGOC to indicate comparisons agains zero that allows 2736 unspecified garbage in the Carry and Overflow flag. This 2737 mode is used to simulate comparisons of (a-b) and (a+b) 2738 against zero using sub/cmp/add operations. 2739 2740 Add CCZ to indicate that only the Zero flag is valid. */ 2741 2742#define EXTRA_CC_MODES \ 2743 CC (CCGCmode, "CCGC") \ 2744 CC (CCGOCmode, "CCGOC") \ 2745 CC (CCNOmode, "CCNO") \ 2746 CC (CCZmode, "CCZ") \ 2747 CC (CCFPmode, "CCFP") \ 2748 CC (CCFPUmode, "CCFPU") 2749 2750/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2751 return the mode to be used for the comparison. 2752 2753 For floating-point equality comparisons, CCFPEQmode should be used. 2754 VOIDmode should be used in all other cases. 2755 2756 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2757 possible, to allow for more combinations. */ 2758 2759#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2760 2761/* Return non-zero if MODE implies a floating point inequality can be 2762 reversed. */ 2763 2764#define REVERSIBLE_CC_MODE(MODE) 1 2765 2766/* A C expression whose value is reversed condition code of the CODE for 2767 comparison done in CC_MODE mode. */ 2768#define REVERSE_CONDITION(CODE, MODE) \ 2769 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ 2770 : reverse_condition_maybe_unordered (CODE)) 2771 2772 2773/* Control the assembler format that we output, to the extent 2774 this does not vary between assemblers. */ 2775 2776/* How to refer to registers in assembler output. 2777 This sequence is indexed by compiler's hard-register-number (see above). */ 2778 2779/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" 2780 For non floating point regs, the following are the HImode names. 2781 2782 For float regs, the stack top is sometimes referred to as "%st(0)" 2783 instead of just "%st". PRINT_REG handles this with the "y" code. */ 2784 2785#undef HI_REGISTER_NAMES 2786#define HI_REGISTER_NAMES \ 2787{"ax","dx","cx","bx","si","di","bp","sp", \ 2788 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ 2789 "flags","fpsr", "dirflag", "frame", \ 2790 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2791 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 2792 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2793 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 2794 2795#define REGISTER_NAMES HI_REGISTER_NAMES 2796 2797/* Table of additional register names to use in user input. */ 2798 2799#define ADDITIONAL_REGISTER_NAMES \ 2800{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2801 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2802 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2803 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2804 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2805 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2806 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ 2807 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } 2808 2809/* Note we are omitting these since currently I don't know how 2810to get gcc to use these, since they want the same but different 2811number as al, and ax. 2812*/ 2813 2814#define QI_REGISTER_NAMES \ 2815{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2816 2817/* These parallel the array above, and can be used to access bits 8:15 2818 of regs 0 through 3. */ 2819 2820#define QI_HIGH_REGISTER_NAMES \ 2821{"ah", "dh", "ch", "bh", } 2822 2823/* How to renumber registers for dbx and gdb. */ 2824 2825#define DBX_REGISTER_NUMBER(N) \ 2826 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2827 2828extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2829extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2830extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2831 2832/* Before the prologue, RA is at 0(%esp). */ 2833#define INCOMING_RETURN_ADDR_RTX \ 2834 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2835 2836/* After the prologue, RA is at -4(AP) in the current frame. */ 2837#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2838 ((COUNT) == 0 \ 2839 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2840 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2841 2842/* PC is dbx register 8; let's use that column for RA. */ 2843#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2844 2845/* Before the prologue, the top of the frame is at 4(%esp). */ 2846#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2847 2848/* Describe how we implement __builtin_eh_return. */ 2849#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2850#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2851 2852 2853/* Select a format to encode pointers in exception handling data. CODE 2854 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2855 true if the symbol may be affected by dynamic relocations. 2856 2857 ??? All x86 object file formats are capable of representing this. 2858 After all, the relocation needed is the same as for the call insn. 2859 Whether or not a particular assembler allows us to enter such, I 2860 guess we'll have to see. */ 2861#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2862 (flag_pic \ 2863 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 2864 : DW_EH_PE_absptr) 2865 2866/* This is how to output the definition of a user-level label named NAME, 2867 such as the label on a static function or variable NAME. */ 2868 2869#define ASM_OUTPUT_LABEL(FILE, NAME) \ 2870 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE))) 2871 2872/* Store in OUTPUT a string (made with alloca) containing 2873 an assembler-name for a local static variable named NAME. 2874 LABELNO is an integer which is different for each call. */ 2875 2876#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2877( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2878 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2879 2880/* This is how to output an insn to push a register on the stack. 2881 It need not be very fast code. */ 2882 2883#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2884 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]) 2885 2886/* This is how to output an insn to pop a register from the stack. 2887 It need not be very fast code. */ 2888 2889#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2890 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]) 2891 2892/* This is how to output an element of a case-vector that is absolute. */ 2893 2894#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2895 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2896 2897/* This is how to output an element of a case-vector that is relative. */ 2898 2899#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2900 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2901 2902/* Under some conditions we need jump tables in the text section, because 2903 the assembler cannot handle label differences between sections. */ 2904 2905#define JUMP_TABLES_IN_TEXT_SECTION \ 2906 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 2907 2908/* A C statement that outputs an address constant appropriate to 2909 for DWARF debugging. */ 2910 2911#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ 2912 i386_dwarf_output_addr_const ((FILE), (X)) 2913 2914/* Either simplify a location expression, or return the original. */ 2915 2916#define ASM_SIMPLIFY_DWARF_ADDR(X) \ 2917 i386_simplify_dwarf_addr (X) 2918 2919/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2920 and switch back. For x86 we do this only to save a few bytes that 2921 would otherwise be unused in the text section. */ 2922#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2923 asm (SECTION_OP "\n\t" \ 2924 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2925 TEXT_SECTION_ASM_OP); 2926 2927/* Print operand X (an rtx) in assembler syntax to file FILE. 2928 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2929 Effect of various CODE letters is described in i386.c near 2930 print_operand function. */ 2931 2932#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2933 ((CODE) == '*' || (CODE) == '+') 2934 2935/* Print the name of a register based on its machine mode and number. 2936 If CODE is 'w', pretend the mode is HImode. 2937 If CODE is 'b', pretend the mode is QImode. 2938 If CODE is 'k', pretend the mode is SImode. 2939 If CODE is 'q', pretend the mode is DImode. 2940 If CODE is 'h', pretend the reg is the `high' byte register. 2941 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ 2942 2943#define PRINT_REG(X, CODE, FILE) \ 2944 print_reg ((X), (CODE), (FILE)) 2945 2946#define PRINT_OPERAND(FILE, X, CODE) \ 2947 print_operand ((FILE), (X), (CODE)) 2948 2949#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2950 print_operand_address ((FILE), (ADDR)) 2951 2952/* Print the name of a register for based on its machine mode and number. 2953 This macro is used to print debugging output. 2954 This macro is different from PRINT_REG in that it may be used in 2955 programs that are not linked with aux-output.o. */ 2956 2957#define DEBUG_PRINT_REG(X, CODE, FILE) \ 2958 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ 2959 static const char * const qi_name[] = QI_REGISTER_NAMES; \ 2960 fprintf ((FILE), "%d ", REGNO (X)); \ 2961 if (REGNO (X) == FLAGS_REG) \ 2962 { fputs ("flags", (FILE)); break; } \ 2963 if (REGNO (X) == DIRFLAG_REG) \ 2964 { fputs ("dirflag", (FILE)); break; } \ 2965 if (REGNO (X) == FPSR_REG) \ 2966 { fputs ("fpsr", (FILE)); break; } \ 2967 if (REGNO (X) == ARG_POINTER_REGNUM) \ 2968 { fputs ("argp", (FILE)); break; } \ 2969 if (REGNO (X) == FRAME_POINTER_REGNUM) \ 2970 { fputs ("frame", (FILE)); break; } \ 2971 if (STACK_TOP_P (X)) \ 2972 { fputs ("st(0)", (FILE)); break; } \ 2973 if (FP_REG_P (X)) \ 2974 { fputs (hi_name[REGNO(X)], (FILE)); break; } \ 2975 if (REX_INT_REG_P (X)) \ 2976 { \ 2977 switch (GET_MODE_SIZE (GET_MODE (X))) \ 2978 { \ 2979 default: \ 2980 case 8: \ 2981 fprintf ((FILE), "r%i", REGNO (X) \ 2982 - FIRST_REX_INT_REG + 8); \ 2983 break; \ 2984 case 4: \ 2985 fprintf ((FILE), "r%id", REGNO (X) \ 2986 - FIRST_REX_INT_REG + 8); \ 2987 break; \ 2988 case 2: \ 2989 fprintf ((FILE), "r%iw", REGNO (X) \ 2990 - FIRST_REX_INT_REG + 8); \ 2991 break; \ 2992 case 1: \ 2993 fprintf ((FILE), "r%ib", REGNO (X) \ 2994 - FIRST_REX_INT_REG + 8); \ 2995 break; \ 2996 } \ 2997 break; \ 2998 } \ 2999 switch (GET_MODE_SIZE (GET_MODE (X))) \ 3000 { \ 3001 case 8: \ 3002 fputs ("r", (FILE)); \ 3003 fputs (hi_name[REGNO (X)], (FILE)); \ 3004 break; \ 3005 default: \ 3006 fputs ("e", (FILE)); \ 3007 case 2: \ 3008 fputs (hi_name[REGNO (X)], (FILE)); \ 3009 break; \ 3010 case 1: \ 3011 fputs (qi_name[REGNO (X)], (FILE)); \ 3012 break; \ 3013 } \ 3014 } while (0) 3015 3016/* a letter which is not needed by the normal asm syntax, which 3017 we can use for operand syntax in the extended asm */ 3018 3019#define ASM_OPERAND_LETTER '#' 3020#define RET return "" 3021#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 3022 3023/* Define the codes that are matched by predicates in i386.c. */ 3024 3025#define PREDICATE_CODES \ 3026 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ 3027 SYMBOL_REF, LABEL_REF, CONST}}, \ 3028 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3029 SYMBOL_REF, LABEL_REF, CONST}}, \ 3030 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ 3031 SYMBOL_REF, LABEL_REF, CONST}}, \ 3032 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3033 SYMBOL_REF, LABEL_REF, CONST}}, \ 3034 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3035 SYMBOL_REF, LABEL_REF, CONST}}, \ 3036 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3037 SYMBOL_REF, LABEL_REF, CONST}}, \ 3038 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3039 SYMBOL_REF, LABEL_REF}}, \ 3040 {"shiftdi_operand", {SUBREG, REG, MEM}}, \ 3041 {"const_int_1_operand", {CONST_INT}}, \ 3042 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 3043 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3044 LABEL_REF, SUBREG, REG, MEM}}, \ 3045 {"pic_symbolic_operand", {CONST}}, \ 3046 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ 3047 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ 3048 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ 3049 {"const1_operand", {CONST_INT}}, \ 3050 {"const248_operand", {CONST_INT}}, \ 3051 {"incdec_operand", {CONST_INT}}, \ 3052 {"mmx_reg_operand", {REG}}, \ 3053 {"reg_no_sp_operand", {SUBREG, REG}}, \ 3054 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3055 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ 3056 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ 3057 {"q_regs_operand", {SUBREG, REG}}, \ 3058 {"non_q_regs_operand", {SUBREG, REG}}, \ 3059 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ 3060 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ 3061 GE, UNGE, LTGT, UNEQ}}, \ 3062 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ 3063 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ 3064 }}, \ 3065 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ 3066 GTU, UNORDERED, ORDERED, UNLE, UNLT, \ 3067 UNGE, UNGT, LTGT, UNEQ }}, \ 3068 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ 3069 {"ext_register_operand", {SUBREG, REG}}, \ 3070 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ 3071 {"mult_operator", {MULT}}, \ 3072 {"div_operator", {DIV}}, \ 3073 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ 3074 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ 3075 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ 3076 LSHIFTRT, ROTATERT}}, \ 3077 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ 3078 {"memory_displacement_operand", {MEM}}, \ 3079 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3080 LABEL_REF, SUBREG, REG, MEM, AND}}, \ 3081 {"long_memory_operand", {MEM}}, 3082 3083/* A list of predicates that do special things with modes, and so 3084 should not elicit warnings for VOIDmode match_operand. */ 3085 3086#define SPECIAL_MODE_PREDICATES \ 3087 "ext_register_operand", 3088 3089/* CM_32 is used by 32bit ABI 3090 CM_SMALL is small model assuming that all code and data fits in the first 3091 31bits of address space. 3092 CM_KERNEL is model assuming that all code and data fits in the negative 3093 31bits of address space. 3094 CM_MEDIUM is model assuming that code fits in the first 31bits of address 3095 space. Size of data is unlimited. 3096 CM_LARGE is model making no assumptions about size of particular sections. 3097 3098 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt 3099 tables first in 31bits of address space. 3100 */ 3101enum cmodel { 3102 CM_32, 3103 CM_SMALL, 3104 CM_KERNEL, 3105 CM_MEDIUM, 3106 CM_LARGE, 3107 CM_SMALL_PIC 3108}; 3109 3110/* Size of the RED_ZONE area. */ 3111#define RED_ZONE_SIZE 128 3112/* Reserved area of the red zone for temporaries. */ 3113#define RED_ZONE_RESERVE 8 3114extern const char *ix86_debug_arg_string, *ix86_debug_addr_string; 3115 3116enum asm_dialect { 3117 ASM_ATT, 3118 ASM_INTEL 3119}; 3120extern const char *ix86_asm_string; 3121extern enum asm_dialect ix86_asm_dialect; 3122/* Value of -mcmodel specified by user. */ 3123extern const char *ix86_cmodel_string; 3124extern enum cmodel ix86_cmodel; 3125 3126/* Variables in i386.c */ 3127extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */ 3128extern const char *ix86_arch_string; /* for -march=<xxx> */ 3129extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */ 3130extern const char *ix86_regparm_string; /* # registers to use to pass args */ 3131extern const char *ix86_align_loops_string; /* power of two alignment for loops */ 3132extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */ 3133extern const char *ix86_align_funcs_string; /* power of two alignment for functions */ 3134extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */ 3135extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */ 3136extern int ix86_regparm; /* ix86_regparm_string as a number */ 3137extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */ 3138extern int ix86_branch_cost; /* values 1-5: see jump.c */ 3139extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */ 3140extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 3141extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 3142 3143/* To properly truncate FP values into integers, we need to set i387 control 3144 word. We can't emit proper mode switching code before reload, as spills 3145 generated by reload may truncate values incorrectly, but we still can avoid 3146 redundant computation of new control word by the mode switching pass. 3147 The fldcw instructions are still emitted redundantly, but this is probably 3148 not going to be noticeable problem, as most CPUs do have fast path for 3149 the sequence. 3150 3151 The machinery is to emit simple truncation instructions and split them 3152 before reload to instructions having USEs of two memory locations that 3153 are filled by this code to old and new control word. 3154 3155 Post-reload pass may be later used to eliminate the redundant fildcw if 3156 needed. */ 3157 3158enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; 3159 3160/* Define this macro if the port needs extra instructions inserted 3161 for mode switching in an optimizing compilation. */ 3162 3163#define OPTIMIZE_MODE_SWITCHING(ENTITY) 1 3164 3165/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 3166 initializer for an array of integers. Each initializer element N 3167 refers to an entity that needs mode switching, and specifies the 3168 number of different modes that might need to be set for this 3169 entity. The position of the initializer in the initializer - 3170 starting counting at zero - determines the integer that is used to 3171 refer to the mode-switched entity in question. */ 3172 3173#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } 3174 3175/* ENTITY is an integer specifying a mode-switched entity. If 3176 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 3177 return an integer value not larger than the corresponding element 3178 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 3179 must be switched into prior to the execution of INSN. */ 3180 3181#define MODE_NEEDED(ENTITY, I) \ 3182 (GET_CODE (I) == CALL_INSN \ 3183 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ 3184 || GET_CODE (PATTERN (I)) == ASM_INPUT))\ 3185 ? FP_CW_UNINITIALIZED \ 3186 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ 3187 ? FP_CW_ANY \ 3188 : FP_CW_STORED) 3189 3190/* This macro specifies the order in which modes for ENTITY are 3191 processed. 0 is the highest priority. */ 3192 3193#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 3194 3195/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 3196 is the set of hard registers live at the point where the insn(s) 3197 are to be inserted. */ 3198 3199#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3200 ((MODE) == FP_CW_STORED \ 3201 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ 3202 assign_386_stack_local (HImode, 2)), 0\ 3203 : 0) 3204 3205/* Avoid renaming of stack registers, as doing so in combination with 3206 scheduling just increases amount of live registers at time and in 3207 the turn amount of fxch instructions needed. 3208 3209 ??? Maybe Pentium chips benefits from renaming, someone can try... */ 3210 3211#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 3212 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 3213 3214 3215/* 3216Local variables: 3217version-control: t 3218End: 3219*/ 3220