i386.h revision 97911
121240Swosch/* Definitions of target machine for GNU compiler for IA-32. 221240Swosch Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 321240Swosch 2001, 2002 Free Software Foundation, Inc. 421240Swosch 521240SwoschThis file is part of GNU CC. 621240Swosch 721240SwoschGNU CC is free software; you can redistribute it and/or modify 821240Swoschit under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GNU CC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GNU CC; see the file COPYING. If not, write to 19the Free Software Foundation, 59 Temple Place - Suite 330, 20Boston, MA 02111-1307, USA. */ 21 22/* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37 38/* $FreeBSD: head/contrib/gcc/config/i386/i386.h 97911 2002-06-06 03:36:32Z obrien $ */ 39 40 41/* Stubs for half-pic support if not OSF/1 reference platform. */ 42 43#ifndef HALF_PIC_P 44#define HALF_PIC_P() 0 45#define HALF_PIC_NUMBER_PTRS 0 46#define HALF_PIC_NUMBER_REFS 0 47#define HALF_PIC_ENCODE(DECL) 48#define HALF_PIC_DECLARE(NAME) 49#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it") 50#define HALF_PIC_ADDRESS_P(X) 0 51#define HALF_PIC_PTR(X) (X) 52#define HALF_PIC_FINISH(STREAM) 53#endif 54 55/* Define the specific costs for a given cpu */ 56 57struct processor_costs { 58 const int add; /* cost of an add instruction */ 59 const int lea; /* cost of a lea instruction */ 60 const int shift_var; /* variable shift costs */ 61 const int shift_const; /* constant shift costs */ 62 const int mult_init; /* cost of starting a multiply */ 63 const int mult_bit; /* cost of multiply per each bit set */ 64 const int divide; /* cost of a divide/mod */ 65 int movsx; /* The cost of movsx operation. */ 66 int movzx; /* The cost of movzx operation. */ 67 const int large_insn; /* insns larger than this cost more */ 68 const int move_ratio; /* The threshold of number of scalar 69 memory-to-memory move insns. */ 70 const int movzbl_load; /* cost of loading using movzbl */ 71 const int int_load[3]; /* cost of loading integer registers 72 in QImode, HImode and SImode relative 73 to reg-reg move (2). */ 74 const int int_store[3]; /* cost of storing integer register 75 in QImode, HImode and SImode */ 76 const int fp_move; /* cost of reg,reg fld/fst */ 77 const int fp_load[3]; /* cost of loading FP register 78 in SFmode, DFmode and XFmode */ 79 const int fp_store[3]; /* cost of storing FP register 80 in SFmode, DFmode and XFmode */ 81 const int mmx_move; /* cost of moving MMX register. */ 82 const int mmx_load[2]; /* cost of loading MMX register 83 in SImode and DImode */ 84 const int mmx_store[2]; /* cost of storing MMX register 85 in SImode and DImode */ 86 const int sse_move; /* cost of moving SSE register. */ 87 const int sse_load[3]; /* cost of loading SSE register 88 in SImode, DImode and TImode*/ 89 const int sse_store[3]; /* cost of storing SSE register 90 in SImode, DImode and TImode*/ 91 const int mmxsse_to_integer; /* cost of moving mmxsse register to 92 integer and vice versa. */ 93 const int prefetch_block; /* bytes moved to cache for prefetch. */ 94 const int simultaneous_prefetches; /* number of parallel prefetch 95 operations. */ 96}; 97 98extern const struct processor_costs *ix86_cost; 99 100/* Run-time compilation parameters selecting different hardware subsets. */ 101 102extern int target_flags; 103 104/* Macros used in the machine description to test the flags. */ 105 106/* configure can arrange to make this 2, to force a 486. */ 107 108#ifndef TARGET_CPU_DEFAULT 109#define TARGET_CPU_DEFAULT 0 110#endif 111 112/* Masks for the -m switches */ 113#define MASK_80387 0x00000001 /* Hardware floating point */ 114#define MASK_RTD 0x00000002 /* Use ret that pops args */ 115#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ 116#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ 117#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ 118#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ 119#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ 120#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ 121#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ 122#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ 123#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ 124#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ 125#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ 126#define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000 127#define MASK_MMX 0x00004000 /* Support MMX regs/builtins */ 128#define MASK_MMX_SET 0x00008000 129#define MASK_SSE 0x00010000 /* Support SSE regs/builtins */ 130#define MASK_SSE_SET 0x00020000 131#define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */ 132#define MASK_SSE2_SET 0x00080000 133#define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */ 134#define MASK_3DNOW_SET 0x00200000 135#define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */ 136#define MASK_3DNOW_A_SET 0x00800000 137#define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */ 138#define MASK_64BIT 0x02000000 /* Produce 64bit code */ 139/* ... overlap with subtarget options starts by 0x04000000. */ 140#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ 141#define MASK_NO_ALIGN_LONG_STRINGS 0x08000000 /* Do not align long strings specially */ 142 143/* Use the floating point instructions */ 144#define TARGET_80387 (target_flags & MASK_80387) 145 146/* Compile using ret insn that pops args. 147 This will not work unless you use prototypes at least 148 for all functions that can take varying numbers of args. */ 149#define TARGET_RTD (target_flags & MASK_RTD) 150 151/* Align doubles to a two word boundary. This breaks compatibility with 152 the published ABI's for structures containing doubles, but produces 153 faster code on the pentium. */ 154#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) 155 156/* Use push instructions to save outgoing args. */ 157#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) 158 159/* Accumulate stack adjustments to prologue/epilogue. */ 160#define TARGET_ACCUMULATE_OUTGOING_ARGS \ 161 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) 162 163/* Put uninitialized locals into bss, not data. 164 Meaningful only on svr3. */ 165#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) 166 167/* Use IEEE floating point comparisons. These handle correctly the cases 168 where the result of a comparison is unordered. Normally SIGFPE is 169 generated in such cases, in which case this isn't needed. */ 170#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) 171 172/* Functions that return a floating point value may return that value 173 in the 387 FPU or in 386 integer registers. If set, this flag causes 174 the 387 to be used, which is compatible with most calling conventions. */ 175#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) 176 177/* Long double is 128bit instead of 96bit, even when only 80bits are used. 178 This mode wastes cache, but avoid misaligned data accesses and simplifies 179 address calculations. */ 180#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) 181 182/* Disable generation of FP sin, cos and sqrt operations for 387. 183 This is because FreeBSD lacks these in the math-emulator-code */ 184#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) 185 186/* Don't create frame pointers for leaf functions */ 187#define TARGET_OMIT_LEAF_FRAME_POINTER \ 188 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) 189 190/* Debug GO_IF_LEGITIMATE_ADDRESS */ 191#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) 192 193/* Debug FUNCTION_ARG macros */ 194#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) 195 196/* 64bit Sledgehammer mode */ 197#ifdef TARGET_BI_ARCH 198#define TARGET_64BIT (target_flags & MASK_64BIT) 199#else 200#ifdef TARGET_64BIT_DEFAULT 201#define TARGET_64BIT 1 202#else 203#define TARGET_64BIT 0 204#endif 205#endif 206 207#define TARGET_386 (ix86_cpu == PROCESSOR_I386) 208#define TARGET_486 (ix86_cpu == PROCESSOR_I486) 209#define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) 210#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) 211#define TARGET_K6 (ix86_cpu == PROCESSOR_K6) 212#define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) 213#define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4) 214 215#define CPUMASK (1 << ix86_cpu) 216extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 217extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 218extern const int x86_branch_hints, x86_unroll_strlen; 219extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 220extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; 221extern const int x86_use_cltd, x86_read_modify_write; 222extern const int x86_read_modify, x86_split_long_moves; 223extern const int x86_promote_QImode, x86_single_stringop; 224extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 225extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 226extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 227extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 228extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 229extern const int x86_epilogue_using_move, x86_decompose_lea; 230extern const int x86_arch_always_fancy_math_387; 231extern int x86_prefetch_sse; 232 233#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) 234#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) 235#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) 236#define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) 237#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) 238/* For sane SSE instruction set generation we need fcomi instruction. It is 239 safe to enable all CMOVE instructions. */ 240#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 241#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) 242#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK) 243#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) 244#define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT) 245#define TARGET_MOVX (x86_movx & CPUMASK) 246#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) 247#define TARGET_USE_LOOP (x86_use_loop & CPUMASK) 248#define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) 249#define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) 250#define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) 251#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) 252#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) 253#define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) 254#define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) 255#define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) 256#define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) 257#define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) 258#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) 259#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) 260#define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK) 261#define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK) 262#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK) 263#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK) 264#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK) 265#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK) 266#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK) 267#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK) 268#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK) 269#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK) 270#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 271 272#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) 273 274#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) 275#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) 276 277#define ASSEMBLER_DIALECT (ix86_asm_dialect) 278 279#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0) 280#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) 281#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 282#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 283 && (ix86_fpmath & FPMATH_387)) 284#define TARGET_MMX ((target_flags & MASK_MMX) != 0) 285#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) 286#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) 287 288#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) 289 290#define TARGET_NO_ALIGN_LONG_STRINGS (target_flags & MASK_NO_ALIGN_LONG_STRINGS) 291 292/* WARNING: Do not mark empty strings for translation, as calling 293 gettext on an empty string does NOT return an empty 294 string. */ 295 296 297#define TARGET_SWITCHES \ 298{ { "80387", MASK_80387, N_("Use hardware fp") }, \ 299 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ 300 { "hard-float", MASK_80387, N_("Use hardware fp") }, \ 301 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ 302 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ 303 { "386", 0, "" /*Deprecated.*/}, \ 304 { "486", 0, "" /*Deprecated.*/}, \ 305 { "pentium", 0, "" /*Deprecated.*/}, \ 306 { "pentiumpro", 0, "" /*Deprecated.*/}, \ 307 { "intel-syntax", 0, "" /*Deprecated.*/}, \ 308 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ 309 { "rtd", MASK_RTD, \ 310 N_("Alternate calling convention") }, \ 311 { "no-rtd", -MASK_RTD, \ 312 N_("Use normal calling convention") }, \ 313 { "align-double", MASK_ALIGN_DOUBLE, \ 314 N_("Align some doubles on dword boundary") }, \ 315 { "no-align-double", -MASK_ALIGN_DOUBLE, \ 316 N_("Align doubles on word boundary") }, \ 317 { "svr3-shlib", MASK_SVR3_SHLIB, \ 318 N_("Uninitialized locals in .bss") }, \ 319 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ 320 N_("Uninitialized locals in .data") }, \ 321 { "ieee-fp", MASK_IEEE_FP, \ 322 N_("Use IEEE math for fp comparisons") }, \ 323 { "no-ieee-fp", -MASK_IEEE_FP, \ 324 N_("Do not use IEEE math for fp comparisons") }, \ 325 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ 326 N_("Return values of functions in FPU registers") }, \ 327 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ 328 N_("Do not return values of functions in FPU registers")}, \ 329 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ 330 N_("Do not generate sin, cos, sqrt for FPU") }, \ 331 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ 332 N_("Generate sin, cos, sqrt for FPU")}, \ 333 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ 334 N_("Omit the frame pointer in leaf functions") }, \ 335 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ 336 { "stack-arg-probe", MASK_STACK_PROBE, \ 337 N_("Enable stack probing") }, \ 338 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ 339 { "windows", 0, 0 /* undocumented */ }, \ 340 { "dll", 0, 0 /* undocumented */ }, \ 341 { "align-stringops", -MASK_NO_ALIGN_STROPS, \ 342 N_("Align destination of the string operations") }, \ 343 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ 344 N_("Do not align destination of the string operations") }, \ 345 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ 346 N_("Inline all known string operations") }, \ 347 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ 348 N_("Do not inline all known string operations") }, \ 349 { "push-args", -MASK_NO_PUSH_ARGS, \ 350 N_("Use push instructions to save outgoing arguments") }, \ 351 { "no-push-args", MASK_NO_PUSH_ARGS, \ 352 N_("Do not use push instructions to save outgoing arguments") }, \ 353 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \ 354 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \ 355 N_("Use push instructions to save outgoing arguments") }, \ 356 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \ 357 N_("Do not use push instructions to save outgoing arguments") }, \ 358 { "mmx", MASK_MMX | MASK_MMX_SET, \ 359 N_("Support MMX built-in functions") }, \ 360 { "no-mmx", -MASK_MMX, \ 361 N_("Do not support MMX built-in functions") }, \ 362 { "no-mmx", MASK_MMX_SET, "" }, \ 363 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \ 364 N_("Support 3DNow! built-in functions") }, \ 365 { "no-3dnow", -MASK_3DNOW, "" }, \ 366 { "no-3dnow", MASK_3DNOW_SET, \ 367 N_("Do not support 3DNow! built-in functions") }, \ 368 { "sse", MASK_SSE | MASK_SSE_SET, \ 369 N_("Support MMX and SSE built-in functions and code generation") }, \ 370 { "no-sse", -MASK_SSE, "" }, \ 371 { "no-sse", MASK_SSE_SET, \ 372 N_("Do not support MMX and SSE built-in functions and code generation") },\ 373 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \ 374 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ 375 { "no-sse2", -MASK_SSE2, "" }, \ 376 { "no-sse2", MASK_SSE2_SET, \ 377 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ 378 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ 379 N_("sizeof(long double) is 16") }, \ 380 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ 381 N_("sizeof(long double) is 12") }, \ 382 { "64", MASK_64BIT, \ 383 N_("Generate 64bit x86-64 code") }, \ 384 { "32", -MASK_64BIT, \ 385 N_("Generate 32bit i386 code") }, \ 386 { "red-zone", -MASK_NO_RED_ZONE, \ 387 N_("Use red-zone in the x86-64 code") }, \ 388 { "no-red-zone", MASK_NO_RED_ZONE, \ 389 N_("Do not use red-zone in the x86-64 code") }, \ 390 { "no-align-long-strings", MASK_NO_ALIGN_LONG_STRINGS, \ 391 N_("Do not align long strings specially") }, \ 392 { "align-long-strings", -MASK_NO_ALIGN_LONG_STRINGS, \ 393 N_("Align strings longer than 30 on a 32-byte boundary") }, \ 394 SUBTARGET_SWITCHES \ 395 { "", TARGET_DEFAULT, 0 }} 396 397#ifdef TARGET_64BIT_DEFAULT 398#define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT) 399#else 400#define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT 401#endif 402 403/* Which processor to schedule for. The cpu attribute defines a list that 404 mirrors this list, so changes to i386.md must be made at the same time. */ 405 406enum processor_type 407{ 408 PROCESSOR_I386, /* 80386 */ 409 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 410 PROCESSOR_PENTIUM, 411 PROCESSOR_PENTIUMPRO, 412 PROCESSOR_K6, 413 PROCESSOR_ATHLON, 414 PROCESSOR_PENTIUM4, 415 PROCESSOR_max 416}; 417enum fpmath_unit 418{ 419 FPMATH_387 = 1, 420 FPMATH_SSE = 2 421}; 422 423extern enum processor_type ix86_cpu; 424extern enum fpmath_unit ix86_fpmath; 425 426extern int ix86_arch; 427 428/* This macro is similar to `TARGET_SWITCHES' but defines names of 429 command options that have values. Its definition is an 430 initializer with a subgrouping for each command option. 431 432 Each subgrouping contains a string constant, that defines the 433 fixed part of the option name, and the address of a variable. The 434 variable, type `char *', is set to the variable part of the given 435 option if the fixed part matches. The actual option name is made 436 by appending `-m' to the specified name. */ 437#define TARGET_OPTIONS \ 438{ { "cpu=", &ix86_cpu_string, \ 439 N_("Schedule code for given CPU")}, \ 440 { "fpmath=", &ix86_fpmath_string, \ 441 N_("Generate floating point mathematics using given instruction set")},\ 442 { "arch=", &ix86_arch_string, \ 443 N_("Generate code for given CPU")}, \ 444 { "regparm=", &ix86_regparm_string, \ 445 N_("Number of registers used to pass integer arguments") }, \ 446 { "align-loops=", &ix86_align_loops_string, \ 447 N_("Loop code aligned to this power of 2") }, \ 448 { "align-jumps=", &ix86_align_jumps_string, \ 449 N_("Jump targets are aligned to this power of 2") }, \ 450 { "align-functions=", &ix86_align_funcs_string, \ 451 N_("Function starts are aligned to this power of 2") }, \ 452 { "preferred-stack-boundary=", \ 453 &ix86_preferred_stack_boundary_string, \ 454 N_("Attempt to keep stack aligned to this power of 2") }, \ 455 { "branch-cost=", &ix86_branch_cost_string, \ 456 N_("Branches are this expensive (1-5, arbitrary units)") }, \ 457 { "cmodel=", &ix86_cmodel_string, \ 458 N_("Use given x86-64 code model") }, \ 459 { "debug-arg", &ix86_debug_arg_string, \ 460 "" /* Undocumented. */ }, \ 461 { "debug-addr", &ix86_debug_addr_string, \ 462 "" /* Undocumented. */ }, \ 463 { "asm=", &ix86_asm_string, \ 464 N_("Use given assembler dialect") }, \ 465 SUBTARGET_OPTIONS \ 466} 467 468/* Sometimes certain combinations of command options do not make 469 sense on a particular target machine. You can define a macro 470 `OVERRIDE_OPTIONS' to take account of this. This macro, if 471 defined, is executed once just after all the command options have 472 been parsed. 473 474 Don't use this macro to turn on various extra optimizations for 475 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 476 477#define OVERRIDE_OPTIONS override_options () 478 479/* These are meant to be redefined in the host dependent files */ 480#define SUBTARGET_SWITCHES 481#define SUBTARGET_OPTIONS 482 483/* Define this to change the optimizations performed by default. */ 484#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 485 optimization_options ((LEVEL), (SIZE)) 486 487/* Specs for the compiler proper */ 488 489#ifndef CC1_CPU_SPEC 490#define CC1_CPU_SPEC "\ 491%{!mcpu*: \ 492%{m386:-mcpu=i386 \ 493%n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \ 494%{m486:-mcpu=i486 \ 495%n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \ 496%{mpentium:-mcpu=pentium \ 497%n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \ 498%{mpentiumpro:-mcpu=pentiumpro \ 499%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \ 500%{mintel-syntax:-masm=intel \ 501%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 502%{mno-intel-syntax:-masm=att \ 503%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 504#endif 505 506#define TARGET_CPU_DEFAULT_i386 0 507#define TARGET_CPU_DEFAULT_i486 1 508#define TARGET_CPU_DEFAULT_pentium 2 509#define TARGET_CPU_DEFAULT_pentium_mmx 3 510#define TARGET_CPU_DEFAULT_pentiumpro 4 511#define TARGET_CPU_DEFAULT_pentium2 5 512#define TARGET_CPU_DEFAULT_pentium3 6 513#define TARGET_CPU_DEFAULT_pentium4 7 514#define TARGET_CPU_DEFAULT_k6 8 515#define TARGET_CPU_DEFAULT_k6_2 9 516#define TARGET_CPU_DEFAULT_k6_3 10 517#define TARGET_CPU_DEFAULT_athlon 11 518#define TARGET_CPU_DEFAULT_athlon_sse 12 519 520#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 521 "pentiumpro", "pentium2", "pentium3", \ 522 "pentium4", "k6", "k6-2", "k6-3",\ 523 "athlon", "athlon-4"} 524#ifndef CPP_CPU_DEFAULT_SPEC 525#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486 526#define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__" 527#endif 528#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium 529#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__" 530#endif 531#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx 532#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__" 533#endif 534#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro 535#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__" 536#endif 537#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2 538#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 539-D__tune_pentium2__" 540#endif 541#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3 542#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 543-D__tune_pentium2__ -D__tune_pentium3__" 544#endif 545#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4 546#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__" 547#endif 548#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6 549#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__" 550#endif 551#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2 552#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__" 553#endif 554#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3 555#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__" 556#endif 557#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon 558#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__" 559#endif 560#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse 561#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__" 562#endif 563#ifndef CPP_CPU_DEFAULT_SPEC 564#define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__" 565#endif 566#endif /* CPP_CPU_DEFAULT_SPEC */ 567 568#ifdef TARGET_BI_ARCH 569#define NO_BUILTIN_SIZE_TYPE 570#define NO_BUILTIN_PTRDIFF_TYPE 571#endif 572 573#ifdef NO_BUILTIN_SIZE_TYPE 574#define CPP_CPU32_SIZE_TYPE_SPEC \ 575 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int" 576#define CPP_CPU64_SIZE_TYPE_SPEC \ 577 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int" 578#else 579#define CPP_CPU32_SIZE_TYPE_SPEC "" 580#define CPP_CPU64_SIZE_TYPE_SPEC "" 581#endif 582 583#define CPP_CPU32_SPEC \ 584 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \ 585-D__i386__ %(cpp_cpu32sizet)" 586 587#define CPP_CPU64_SPEC \ 588 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)" 589 590#define CPP_CPUCOMMON_SPEC "\ 591%{march=i386:%{!mcpu*:-D__tune_i386__ }}\ 592%{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\ 593%{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 594 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\ 595%{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 596 -D__pentium__mmx__ \ 597 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\ 598%{march=pentiumpro|march=i686:-D__i686 -D__i686__ \ 599 -D__pentiumpro -D__pentiumpro__ \ 600 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\ 601%{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\ 602%{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \ 603 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\ 604%{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \ 605 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\ 606%{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \ 607 %{!mcpu*:-D__tune_athlon__ }}\ 608%{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \ 609 -D__athlon_sse__ \ 610 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\ 611%{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\ 612%{m386|mcpu=i386:-D__tune_i386__ }\ 613%{m486|mcpu=i486:-D__tune_i486__ }\ 614%{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\ 615%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \ 616-D__tune_pentiumpro__ }\ 617%{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\ 618%{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 619-D__tune_athlon__ }\ 620%{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 621-D__tune_athlon_sse__ }\ 622%{mcpu=pentium4:-D__tune_pentium4__ }\ 623%{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\ 624-D__SSE__ }\ 625%{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\ 626|march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 627|march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\ 628%{march=k6-2|march=k6-3\ 629|march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 630|march=athlon-mp: -D__3dNOW__ }\ 631%{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 632|march=athlon-mp: -D__3dNOW_A__ }\ 633%{march=pentium4: -D__SSE2__ }\ 634%{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}" 635 636#ifndef CPP_CPU_SPEC 637#ifdef TARGET_BI_ARCH 638#ifdef TARGET_64BIT_DEFAULT 639#define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)" 640#else 641#define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)" 642#endif 643#else 644#ifdef TARGET_64BIT_DEFAULT 645#define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)" 646#else 647#define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)" 648#endif 649#endif 650#endif 651 652#ifndef CC1_SPEC 653#define CC1_SPEC "%(cc1_cpu) " 654#endif 655 656/* This macro defines names of additional specifications to put in the 657 specs that can be used in various specifications like CC1_SPEC. Its 658 definition is an initializer with a subgrouping for each command option. 659 660 Each subgrouping contains a string constant, that defines the 661 specification name, and a string constant that used by the GNU CC driver 662 program. 663 664 Do not define this macro if it does not need to do anything. */ 665 666#ifndef SUBTARGET_EXTRA_SPECS 667#define SUBTARGET_EXTRA_SPECS 668#endif 669 670#define EXTRA_SPECS \ 671 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 672 { "cpp_cpu", CPP_CPU_SPEC }, \ 673 { "cpp_cpu32", CPP_CPU32_SPEC }, \ 674 { "cpp_cpu64", CPP_CPU64_SPEC }, \ 675 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \ 676 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \ 677 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \ 678 { "cc1_cpu", CC1_CPU_SPEC }, \ 679 SUBTARGET_EXTRA_SPECS 680 681/* target machine storage layout */ 682 683/* Define for XFmode or TFmode extended real floating point support. 684 This will automatically cause REAL_ARITHMETIC to be defined. 685 686 The XFmode is specified by i386 ABI, while TFmode may be faster 687 due to alignment and simplifications in the address calculations. 688 */ 689#define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96) 690#define MAX_LONG_DOUBLE_TYPE_SIZE 128 691#ifdef __x86_64__ 692#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 693#else 694#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 695#endif 696/* Tell real.c that this is the 80-bit Intel extended float format 697 packaged in a 128-bit or 96bit entity. */ 698#define INTEL_EXTENDED_IEEE_FORMAT 1 699 700 701#define SHORT_TYPE_SIZE 16 702#define INT_TYPE_SIZE 32 703#define FLOAT_TYPE_SIZE 32 704#define LONG_TYPE_SIZE BITS_PER_WORD 705#define MAX_WCHAR_TYPE_SIZE 32 706#define DOUBLE_TYPE_SIZE 64 707#define LONG_LONG_TYPE_SIZE 64 708 709#if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT) 710#define MAX_BITS_PER_WORD 64 711#define MAX_LONG_TYPE_SIZE 64 712#else 713#define MAX_BITS_PER_WORD 32 714#define MAX_LONG_TYPE_SIZE 32 715#endif 716 717/* Define if you don't want extended real, but do want to use the 718 software floating point emulator for REAL_ARITHMETIC and 719 decimal <-> binary conversion. */ 720/* #define REAL_ARITHMETIC */ 721 722/* Define this if most significant byte of a word is the lowest numbered. */ 723/* That is true on the 80386. */ 724 725#define BITS_BIG_ENDIAN 0 726 727/* Define this if most significant byte of a word is the lowest numbered. */ 728/* That is not true on the 80386. */ 729#define BYTES_BIG_ENDIAN 0 730 731/* Define this if most significant word of a multiword number is the lowest 732 numbered. */ 733/* Not true for 80386 */ 734#define WORDS_BIG_ENDIAN 0 735 736/* number of bits in an addressable storage unit */ 737#define BITS_PER_UNIT 8 738 739/* Width in bits of a "word", which is the contents of a machine register. 740 Note that this is not necessarily the width of data type `int'; 741 if using 16-bit ints on a 80386, this would still be 32. 742 But on a machine with 16-bit registers, this would be 16. */ 743#define BITS_PER_WORD (TARGET_64BIT ? 64 : 32) 744 745/* Width of a word, in units (bytes). */ 746#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 747#define MIN_UNITS_PER_WORD 4 748 749/* Width in bits of a pointer. 750 See also the macro `Pmode' defined below. */ 751#define POINTER_SIZE BITS_PER_WORD 752 753/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 754#define PARM_BOUNDARY BITS_PER_WORD 755 756/* Boundary (in *bits*) on which stack pointer should be aligned. */ 757#define STACK_BOUNDARY BITS_PER_WORD 758 759/* Boundary (in *bits*) on which the stack pointer preferrs to be 760 aligned; the compiler cannot rely on having this alignment. */ 761#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 762 763/* As of July 2001, many runtimes to not align the stack properly when 764 entering main. This causes expand_main_function to forcably align 765 the stack, which results in aligned frames for functions called from 766 main, though it does nothing for the alignment of main itself. */ 767#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 768 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 769 770/* Allocation boundary for the code of a function. */ 771#define FUNCTION_BOUNDARY 16 772 773/* Alignment of field after `int : 0' in a structure. */ 774 775#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 776 777/* Minimum size in bits of the largest boundary to which any 778 and all fundamental data types supported by the hardware 779 might need to be aligned. No data type wants to be aligned 780 rounder than this. 781 782 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary 783 and Pentium Pro XFmode values at 128 bit boundaries. */ 784 785#define BIGGEST_ALIGNMENT 128 786 787/* Decide whether a variable of mode MODE must be 128 bit aligned. */ 788#define ALIGN_MODE_128(MODE) \ 789 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \ 790 || (MODE) == V4SFmode || (MODE) == V4SImode) 791 792/* The published ABIs say that doubles should be aligned on word 793 boundaries, so lower the aligment for structure fields unless 794 -malign-double is set. */ 795/* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be 796 constant. Use the smaller value in that context. */ 797#ifndef IN_TARGET_LIBS 798#define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32)) 799#else 800#define BIGGEST_FIELD_ALIGNMENT 32 801#endif 802 803/* If defined, a C expression to compute the alignment given to a 804 constant that is being placed in memory. EXP is the constant 805 and ALIGN is the alignment that the object would ordinarily have. 806 The value of this macro is used instead of that alignment to align 807 the object. 808 809 If this macro is not defined, then ALIGN is used. 810 811 The typical use of this macro is to increase alignment for string 812 constants to be word aligned so that `strcpy' calls that copy 813 constants can be done inline. */ 814 815#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 816 817/* If defined, a C expression to compute the alignment for a static 818 variable. TYPE is the data type, and ALIGN is the alignment that 819 the object would ordinarily have. The value of this macro is used 820 instead of that alignment to align the object. 821 822 If this macro is not defined, then ALIGN is used. 823 824 One use of this macro is to increase alignment of medium-size 825 data to make it all fit in fewer cache lines. Another is to 826 cause character arrays to be word-aligned so that `strcpy' calls 827 that copy constants to character arrays can be done inline. */ 828 829#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 830 831/* If defined, a C expression to compute the alignment for a local 832 variable. TYPE is the data type, and ALIGN is the alignment that 833 the object would ordinarily have. The value of this macro is used 834 instead of that alignment to align the object. 835 836 If this macro is not defined, then ALIGN is used. 837 838 One use of this macro is to increase alignment of medium-size 839 data to make it all fit in fewer cache lines. */ 840 841#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 842 843/* If defined, a C expression that gives the alignment boundary, in 844 bits, of an argument with the specified mode and type. If it is 845 not defined, `PARM_BOUNDARY' is used for all arguments. */ 846 847#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 848 ix86_function_arg_boundary ((MODE), (TYPE)) 849 850/* Set this non-zero if move instructions will actually fail to work 851 when given unaligned data. */ 852#define STRICT_ALIGNMENT 0 853 854/* If bit field type is int, don't let it cross an int, 855 and give entire struct the alignment of an int. */ 856/* Required on the 386 since it doesn't have bitfield insns. */ 857#define PCC_BITFIELD_TYPE_MATTERS 1 858 859/* Standard register usage. */ 860 861/* This processor has special stack-like registers. See reg-stack.c 862 for details. */ 863 864#define STACK_REGS 865#define IS_STACK_MODE(MODE) \ 866 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ 867 || (MODE) == TFmode) 868 869/* Number of actual hardware registers. 870 The hardware registers are assigned numbers for the compiler 871 from 0 to just below FIRST_PSEUDO_REGISTER. 872 All registers that the compiler knows about must be given numbers, 873 even those that are not normally considered general registers. 874 875 In the 80386 we give the 8 general purpose registers the numbers 0-7. 876 We number the floating point registers 8-15. 877 Note that registers 0-7 can be accessed as a short or int, 878 while only 0-3 may be used with byte `mov' instructions. 879 880 Reg 16 does not correspond to any hardware register, but instead 881 appears in the RTL as an argument pointer prior to reload, and is 882 eliminated during reloading in favor of either the stack or frame 883 pointer. */ 884 885#define FIRST_PSEUDO_REGISTER 53 886 887/* Number of hardware registers that go into the DWARF-2 unwind info. 888 If not defined, equals FIRST_PSEUDO_REGISTER. */ 889 890#define DWARF_FRAME_REGISTERS 17 891 892/* 1 for registers that have pervasive standard uses 893 and are not available for the register allocator. 894 On the 80386, the stack pointer is such, as is the arg pointer. 895 896 The value is an mask - bit 1 is set for fixed registers 897 for 32bit target, while 2 is set for fixed registers for 64bit. 898 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 899 */ 900#define FIXED_REGISTERS \ 901/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 902{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ 903/*arg,flags,fpsr,dir,frame*/ \ 904 3, 3, 3, 3, 3, \ 905/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 906 0, 0, 0, 0, 0, 0, 0, 0, \ 907/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 908 0, 0, 0, 0, 0, 0, 0, 0, \ 909/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 910 1, 1, 1, 1, 1, 1, 1, 1, \ 911/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 912 1, 1, 1, 1, 1, 1, 1, 1} 913 914 915/* 1 for registers not available across function calls. 916 These must include the FIXED_REGISTERS and also any 917 registers that can be used without being saved. 918 The latter must include the registers where values are returned 919 and the register where structure-value addresses are passed. 920 Aside from that, you can include as many other registers as you like. 921 922 The value is an mask - bit 1 is set for call used 923 for 32bit target, while 2 is set for call used for 64bit. 924 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 925*/ 926#define CALL_USED_REGISTERS \ 927/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 928{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 929/*arg,flags,fpsr,dir,frame*/ \ 930 3, 3, 3, 3, 3, \ 931/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 932 3, 3, 3, 3, 3, 3, 3, 3, \ 933/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 934 3, 3, 3, 3, 3, 3, 3, 3, \ 935/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 936 3, 3, 3, 3, 1, 1, 1, 1, \ 937/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 938 3, 3, 3, 3, 3, 3, 3, 3} \ 939 940/* Order in which to allocate registers. Each register must be 941 listed once, even those in FIXED_REGISTERS. List frame pointer 942 late and fixed registers last. Note that, in general, we prefer 943 registers listed in CALL_USED_REGISTERS, keeping the others 944 available for storage of persistent values. 945 946 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 947 so this is just empty initializer for array. */ 948 949#define REG_ALLOC_ORDER \ 950{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 951 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 952 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 953 48, 49, 50, 51, 52 } 954 955/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 956 to be rearranged based on a particular function. When using sse math, 957 we want to allocase SSE before x87 registers and vice vera. */ 958 959#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 960 961 962/* Macro to conditionally modify fixed_regs/call_used_regs. */ 963#define CONDITIONAL_REGISTER_USAGE \ 964do { \ 965 int i; \ 966 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 967 { \ 968 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ 969 call_used_regs[i] = (call_used_regs[i] \ 970 & (TARGET_64BIT ? 2 : 1)) != 0; \ 971 } \ 972 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 973 { \ 974 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 975 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 976 } \ 977 if (! TARGET_MMX) \ 978 { \ 979 int i; \ 980 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 981 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 982 fixed_regs[i] = call_used_regs[i] = 1; \ 983 } \ 984 if (! TARGET_SSE) \ 985 { \ 986 int i; \ 987 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 988 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 989 fixed_regs[i] = call_used_regs[i] = 1; \ 990 } \ 991 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 992 { \ 993 int i; \ 994 HARD_REG_SET x; \ 995 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 996 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 997 if (TEST_HARD_REG_BIT (x, i)) \ 998 fixed_regs[i] = call_used_regs[i] = 1; \ 999 } \ 1000 } while (0) 1001 1002/* Return number of consecutive hard regs needed starting at reg REGNO 1003 to hold something of mode MODE. 1004 This is ordinarily the length in words of a value of mode MODE 1005 but can be less for certain modes in special long registers. 1006 1007 Actually there are no two word move instructions for consecutive 1008 registers. And only registers 0-3 may have mov byte instructions 1009 applied to them. 1010 */ 1011 1012#define HARD_REGNO_NREGS(REGNO, MODE) \ 1013 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1014 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1015 : ((MODE) == TFmode \ 1016 ? (TARGET_64BIT ? 2 : 3) \ 1017 : (MODE) == TCmode \ 1018 ? (TARGET_64BIT ? 4 : 6) \ 1019 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1020 1021#define VALID_SSE_REG_MODE(MODE) \ 1022 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1023 || (MODE) == SFmode \ 1024 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) 1025 1026#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1027 ((MODE) == V2SFmode || (MODE) == SFmode) 1028 1029#define VALID_MMX_REG_MODE(MODE) \ 1030 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 1031 || (MODE) == V2SImode || (MODE) == SImode) 1032 1033#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1034 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ 1035 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ 1036 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) 1037 1038#define VALID_FP_MODE_P(MODE) \ 1039 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 1040 || (!TARGET_64BIT && (MODE) == XFmode) \ 1041 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \ 1042 || (!TARGET_64BIT && (MODE) == XCmode)) 1043 1044#define VALID_INT_MODE_P(MODE) \ 1045 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1046 || (MODE) == DImode \ 1047 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1048 || (MODE) == CDImode \ 1049 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) 1050 1051/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1052 1053#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1054 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1055 1056/* Value is 1 if it is a good idea to tie two pseudo registers 1057 when one has mode MODE1 and one has mode MODE2. 1058 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1059 for any hard reg, then this must be 0 for correct output. */ 1060 1061#define MODES_TIEABLE_P(MODE1, MODE2) \ 1062 ((MODE1) == (MODE2) \ 1063 || (((MODE1) == HImode || (MODE1) == SImode \ 1064 || ((MODE1) == QImode \ 1065 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1066 || ((MODE1) == DImode && TARGET_64BIT)) \ 1067 && ((MODE2) == HImode || (MODE2) == SImode \ 1068 || ((MODE1) == QImode \ 1069 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1070 || ((MODE2) == DImode && TARGET_64BIT)))) 1071 1072 1073/* Specify the modes required to caller save a given hard regno. 1074 We do this on i386 to prevent flags from being saved at all. 1075 1076 Kill any attempts to combine saving of modes. */ 1077 1078#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1079 (CC_REGNO_P (REGNO) ? VOIDmode \ 1080 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1081 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \ 1082 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1083 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 1084 : (MODE)) 1085/* Specify the registers used for certain standard purposes. 1086 The values of these macros are register numbers. */ 1087 1088/* on the 386 the pc register is %eip, and is not usable as a general 1089 register. The ordinary mov instructions won't work */ 1090/* #define PC_REGNUM */ 1091 1092/* Register to use for pushing function arguments. */ 1093#define STACK_POINTER_REGNUM 7 1094 1095/* Base register for access to local variables of the function. */ 1096#define HARD_FRAME_POINTER_REGNUM 6 1097 1098/* Base register for access to local variables of the function. */ 1099#define FRAME_POINTER_REGNUM 20 1100 1101/* First floating point reg */ 1102#define FIRST_FLOAT_REG 8 1103 1104/* First & last stack-like regs */ 1105#define FIRST_STACK_REG FIRST_FLOAT_REG 1106#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1107 1108#define FLAGS_REG 17 1109#define FPSR_REG 18 1110#define DIRFLAG_REG 19 1111 1112#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1113#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1114 1115#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1116#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1117 1118#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1119#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1120 1121#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1122#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1123 1124/* Value should be nonzero if functions must have frame pointers. 1125 Zero means the frame pointer need not be set up (and parms 1126 may be accessed via the stack pointer) in functions that seem suitable. 1127 This is computed in `reload', in reload1.c. */ 1128#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1129 1130/* Override this in other tm.h files to cope with various OS losage 1131 requiring a frame pointer. */ 1132#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1133#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1134#endif 1135 1136/* Make sure we can access arbitrary call frames. */ 1137#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1138 1139/* Base register for access to arguments of the function. */ 1140#define ARG_POINTER_REGNUM 16 1141 1142/* Register in which static-chain is passed to a function. 1143 We do use ECX as static chain register for 32 bit ABI. On the 1144 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1145#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1146 1147/* Register to hold the addressing base for position independent 1148 code access to data items. We don't use PIC pointer for 64bit 1149 mode. Define the regnum to dummy value to prevent gcc from 1150 pessimizing code dealing with EBX. */ 1151#define PIC_OFFSET_TABLE_REGNUM \ 1152 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM : 3) 1153 1154/* Register in which address to store a structure value 1155 arrives in the function. On the 386, the prologue 1156 copies this from the stack to register %eax. */ 1157#define STRUCT_VALUE_INCOMING 0 1158 1159/* Place in which caller passes the structure value address. 1160 0 means push the value on the stack like an argument. */ 1161#define STRUCT_VALUE 0 1162 1163/* A C expression which can inhibit the returning of certain function 1164 values in registers, based on the type of value. A nonzero value 1165 says to return the function value in memory, just as large 1166 structures are always returned. Here TYPE will be a C expression 1167 of type `tree', representing the data type of the value. 1168 1169 Note that values of mode `BLKmode' must be explicitly handled by 1170 this macro. Also, the option `-fpcc-struct-return' takes effect 1171 regardless of this macro. On most systems, it is possible to 1172 leave the macro undefined; this causes a default definition to be 1173 used, whose value is the constant 1 for `BLKmode' values, and 0 1174 otherwise. 1175 1176 Do not use this macro to indicate that structures and unions 1177 should always be returned in memory. You should instead use 1178 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1179 1180#define RETURN_IN_MEMORY(TYPE) \ 1181 ix86_return_in_memory (TYPE) 1182 1183 1184/* Define the classes of registers for register constraints in the 1185 machine description. Also define ranges of constants. 1186 1187 One of the classes must always be named ALL_REGS and include all hard regs. 1188 If there is more than one class, another class must be named NO_REGS 1189 and contain no registers. 1190 1191 The name GENERAL_REGS must be the name of a class (or an alias for 1192 another name such as ALL_REGS). This is the class of registers 1193 that is allowed by "g" or "r" in a register constraint. 1194 Also, registers outside this class are allocated only when 1195 instructions express preferences for them. 1196 1197 The classes must be numbered in nondecreasing order; that is, 1198 a larger-numbered class must never be contained completely 1199 in a smaller-numbered class. 1200 1201 For any two classes, it is very desirable that there be another 1202 class that represents their union. 1203 1204 It might seem that class BREG is unnecessary, since no useful 386 1205 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1206 and the "b" register constraint is useful in asms for syscalls. 1207 1208 The flags and fpsr registers are in no class. */ 1209 1210enum reg_class 1211{ 1212 NO_REGS, 1213 AREG, DREG, CREG, BREG, SIREG, DIREG, 1214 AD_REGS, /* %eax/%edx for DImode */ 1215 Q_REGS, /* %eax %ebx %ecx %edx */ 1216 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1217 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1218 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1219 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1220 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1221 FLOAT_REGS, 1222 SSE_REGS, 1223 MMX_REGS, 1224 FP_TOP_SSE_REGS, 1225 FP_SECOND_SSE_REGS, 1226 FLOAT_SSE_REGS, 1227 FLOAT_INT_REGS, 1228 INT_SSE_REGS, 1229 FLOAT_INT_SSE_REGS, 1230 ALL_REGS, LIM_REG_CLASSES 1231}; 1232 1233#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1234 1235#define INTEGER_CLASS_P(CLASS) \ 1236 reg_class_subset_p ((CLASS), GENERAL_REGS) 1237#define FLOAT_CLASS_P(CLASS) \ 1238 reg_class_subset_p ((CLASS), FLOAT_REGS) 1239#define SSE_CLASS_P(CLASS) \ 1240 reg_class_subset_p ((CLASS), SSE_REGS) 1241#define MMX_CLASS_P(CLASS) \ 1242 reg_class_subset_p ((CLASS), MMX_REGS) 1243#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1244 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1245#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1246 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1247#define MAYBE_SSE_CLASS_P(CLASS) \ 1248 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1249#define MAYBE_MMX_CLASS_P(CLASS) \ 1250 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1251 1252#define Q_CLASS_P(CLASS) \ 1253 reg_class_subset_p ((CLASS), Q_REGS) 1254 1255/* Give names of register classes as strings for dump file. */ 1256 1257#define REG_CLASS_NAMES \ 1258{ "NO_REGS", \ 1259 "AREG", "DREG", "CREG", "BREG", \ 1260 "SIREG", "DIREG", \ 1261 "AD_REGS", \ 1262 "Q_REGS", "NON_Q_REGS", \ 1263 "INDEX_REGS", \ 1264 "LEGACY_REGS", \ 1265 "GENERAL_REGS", \ 1266 "FP_TOP_REG", "FP_SECOND_REG", \ 1267 "FLOAT_REGS", \ 1268 "SSE_REGS", \ 1269 "MMX_REGS", \ 1270 "FP_TOP_SSE_REGS", \ 1271 "FP_SECOND_SSE_REGS", \ 1272 "FLOAT_SSE_REGS", \ 1273 "FLOAT_INT_REGS", \ 1274 "INT_SSE_REGS", \ 1275 "FLOAT_INT_SSE_REGS", \ 1276 "ALL_REGS" } 1277 1278/* Define which registers fit in which classes. 1279 This is an initializer for a vector of HARD_REG_SET 1280 of length N_REG_CLASSES. */ 1281 1282#define REG_CLASS_CONTENTS \ 1283{ { 0x00, 0x0 }, \ 1284 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1285 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1286 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1287 { 0x03, 0x0 }, /* AD_REGS */ \ 1288 { 0x0f, 0x0 }, /* Q_REGS */ \ 1289 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1290 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1291 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1292 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1293 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1294 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1295{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1296{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1297{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1298{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1299{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1300 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1301{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1302{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1303{ 0xffffffff,0x1fffff } \ 1304} 1305 1306/* The same information, inverted: 1307 Return the class number of the smallest class containing 1308 reg number REGNO. This could be a conditional expression 1309 or could index an array. */ 1310 1311#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1312 1313/* When defined, the compiler allows registers explicitly used in the 1314 rtl to be used as spill registers but prevents the compiler from 1315 extending the lifetime of these registers. */ 1316 1317#define SMALL_REGISTER_CLASSES 1 1318 1319#define QI_REG_P(X) \ 1320 (REG_P (X) && REGNO (X) < 4) 1321 1322#define GENERAL_REGNO_P(N) \ 1323 ((N) < 8 || REX_INT_REGNO_P (N)) 1324 1325#define GENERAL_REG_P(X) \ 1326 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1327 1328#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1329 1330#define NON_QI_REG_P(X) \ 1331 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1332 1333#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1334#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1335 1336#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1337#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1338#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1339#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1340 1341#define SSE_REGNO_P(N) \ 1342 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1343 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1344 1345#define SSE_REGNO(N) \ 1346 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1347#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1348 1349#define SSE_FLOAT_MODE_P(MODE) \ 1350 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1351 1352#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1353#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1354 1355#define STACK_REG_P(XOP) \ 1356 (REG_P (XOP) && \ 1357 REGNO (XOP) >= FIRST_STACK_REG && \ 1358 REGNO (XOP) <= LAST_STACK_REG) 1359 1360#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1361 1362#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1363 1364#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1365#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1366 1367/* Indicate whether hard register numbered REG_NO should be converted 1368 to SSA form. */ 1369#define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \ 1370 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM) 1371 1372/* The class value for index registers, and the one for base regs. */ 1373 1374#define INDEX_REG_CLASS INDEX_REGS 1375#define BASE_REG_CLASS GENERAL_REGS 1376 1377/* Get reg_class from a letter such as appears in the machine description. */ 1378 1379#define REG_CLASS_FROM_LETTER(C) \ 1380 ((C) == 'r' ? GENERAL_REGS : \ 1381 (C) == 'R' ? LEGACY_REGS : \ 1382 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1383 (C) == 'Q' ? Q_REGS : \ 1384 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1385 ? FLOAT_REGS \ 1386 : NO_REGS) : \ 1387 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1388 ? FP_TOP_REG \ 1389 : NO_REGS) : \ 1390 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1391 ? FP_SECOND_REG \ 1392 : NO_REGS) : \ 1393 (C) == 'a' ? AREG : \ 1394 (C) == 'b' ? BREG : \ 1395 (C) == 'c' ? CREG : \ 1396 (C) == 'd' ? DREG : \ 1397 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1398 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1399 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1400 (C) == 'A' ? AD_REGS : \ 1401 (C) == 'D' ? DIREG : \ 1402 (C) == 'S' ? SIREG : NO_REGS) 1403 1404/* The letters I, J, K, L and M in a register constraint string 1405 can be used to stand for particular ranges of immediate operands. 1406 This macro defines what the ranges are. 1407 C is the letter, and VALUE is a constant value. 1408 Return 1 if VALUE is in the range specified by C. 1409 1410 I is for non-DImode shifts. 1411 J is for DImode shifts. 1412 K is for signed imm8 operands. 1413 L is for andsi as zero-extending move. 1414 M is for shifts that can be executed by the "lea" opcode. 1415 N is for immedaite operands for out/in instructions (0-255) 1416 */ 1417 1418#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1419 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1420 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1421 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1422 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1423 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1424 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1425 : 0) 1426 1427/* Similar, but for floating constants, and defining letters G and H. 1428 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1429 TARGET_387 isn't set, because the stack register converter may need to 1430 load 0.0 into the function value register. */ 1431 1432#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1433 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1434 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0)) 1435 1436/* A C expression that defines the optional machine-dependent 1437 constraint letters that can be used to segregate specific types of 1438 operands, usually memory references, for the target machine. Any 1439 letter that is not elsewhere defined and not matched by 1440 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1441 be defined. 1442 1443 If it is required for a particular target machine, it should 1444 return 1 if VALUE corresponds to the operand type represented by 1445 the constraint letter C. If C is not defined as an extra 1446 constraint, the value returned should be 0 regardless of VALUE. */ 1447 1448#define EXTRA_CONSTRAINT(VALUE, C) \ 1449 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \ 1450 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \ 1451 : 0) 1452 1453/* Place additional restrictions on the register class to use when it 1454 is necessary to be able to hold a value of mode MODE in a reload 1455 register for which class CLASS would ordinarily be used. */ 1456 1457#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1458 ((MODE) == QImode && !TARGET_64BIT \ 1459 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1460 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1461 ? Q_REGS : (CLASS)) 1462 1463/* Given an rtx X being reloaded into a reg required to be 1464 in class CLASS, return the class of reg to actually use. 1465 In general this is just CLASS; but on some machines 1466 in some cases it is preferable to use a more restrictive class. 1467 On the 80386 series, we prevent floating constants from being 1468 reloaded into floating registers (since no move-insn can do that) 1469 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1470 1471/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1472 QImode must go into class Q_REGS. 1473 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1474 movdf to do mem-to-mem moves through integer regs. */ 1475 1476#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1477 ix86_preferred_reload_class ((X), (CLASS)) 1478 1479/* If we are copying between general and FP registers, we need a memory 1480 location. The same is true for SSE and MMX registers. */ 1481#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1482 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1483 1484/* QImode spills from non-QI registers need a scratch. This does not 1485 happen often -- the only example so far requires an uninitialized 1486 pseudo. */ 1487 1488#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1489 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1490 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1491 ? Q_REGS : NO_REGS) 1492 1493/* Return the maximum number of consecutive registers 1494 needed to represent mode MODE in a register of class CLASS. */ 1495/* On the 80386, this is the size of MODE in words, 1496 except in the FP regs, where a single reg is always enough. 1497 The TFmodes are really just 80bit values, so we use only 3 registers 1498 to hold them, instead of 4, as the size would suggest. 1499 */ 1500#define CLASS_MAX_NREGS(CLASS, MODE) \ 1501 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1502 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1503 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ 1504 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1505 1506/* A C expression whose value is nonzero if pseudos that have been 1507 assigned to registers of class CLASS would likely be spilled 1508 because registers of CLASS are needed for spill registers. 1509 1510 The default value of this macro returns 1 if CLASS has exactly one 1511 register and zero otherwise. On most machines, this default 1512 should be used. Only define this macro to some other expression 1513 if pseudo allocated by `local-alloc.c' end up in memory because 1514 their hard registers were needed for spill registers. If this 1515 macro returns nonzero for those classes, those pseudos will only 1516 be allocated by `global.c', which knows how to reallocate the 1517 pseudo to another register. If there would not be another 1518 register available for reallocation, you should not change the 1519 definition of this macro since the only effect of such a 1520 definition would be to slow down register allocation. */ 1521 1522#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1523 (((CLASS) == AREG) \ 1524 || ((CLASS) == DREG) \ 1525 || ((CLASS) == CREG) \ 1526 || ((CLASS) == BREG) \ 1527 || ((CLASS) == AD_REGS) \ 1528 || ((CLASS) == SIREG) \ 1529 || ((CLASS) == DIREG)) 1530 1531/* A C statement that adds to CLOBBERS any hard regs the port wishes 1532 to automatically clobber for all asms. 1533 1534 We do this in the new i386 backend to maintain source compatibility 1535 with the old cc0-based compiler. */ 1536 1537#define MD_ASM_CLOBBERS(CLOBBERS) \ 1538 do { \ 1539 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ 1540 (CLOBBERS)); \ 1541 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ 1542 (CLOBBERS)); \ 1543 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ 1544 (CLOBBERS)); \ 1545 } while (0) 1546 1547/* Stack layout; function entry, exit and calling. */ 1548 1549/* Define this if pushing a word on the stack 1550 makes the stack pointer a smaller address. */ 1551#define STACK_GROWS_DOWNWARD 1552 1553/* Define this if the nominal address of the stack frame 1554 is at the high-address end of the local variables; 1555 that is, each additional local variable allocated 1556 goes at a more negative offset in the frame. */ 1557#define FRAME_GROWS_DOWNWARD 1558 1559/* Offset within stack frame to start allocating local variables at. 1560 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1561 first local allocated. Otherwise, it is the offset to the BEGINNING 1562 of the first local allocated. */ 1563#define STARTING_FRAME_OFFSET 0 1564 1565/* If we generate an insn to push BYTES bytes, 1566 this says how many the stack pointer really advances by. 1567 On 386 pushw decrements by exactly 2 no matter what the position was. 1568 On the 386 there is no pushb; we use pushw instead, and this 1569 has the effect of rounding up to 2. 1570 1571 For 64bit ABI we round up to 8 bytes. 1572 */ 1573 1574#define PUSH_ROUNDING(BYTES) \ 1575 (TARGET_64BIT \ 1576 ? (((BYTES) + 7) & (-8)) \ 1577 : (((BYTES) + 1) & (-2))) 1578 1579/* If defined, the maximum amount of space required for outgoing arguments will 1580 be computed and placed into the variable 1581 `current_function_outgoing_args_size'. No space will be pushed onto the 1582 stack for each call; instead, the function prologue should increase the stack 1583 frame size by this amount. */ 1584 1585#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1586 1587/* If defined, a C expression whose value is nonzero when we want to use PUSH 1588 instructions to pass outgoing arguments. */ 1589 1590#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1591 1592/* Offset of first parameter from the argument pointer register value. */ 1593#define FIRST_PARM_OFFSET(FNDECL) 0 1594 1595/* Define this macro if functions should assume that stack space has been 1596 allocated for arguments even when their values are passed in registers. 1597 1598 The value of this macro is the size, in bytes, of the area reserved for 1599 arguments passed in registers for the function represented by FNDECL. 1600 1601 This space can be allocated by the caller, or be a part of the 1602 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1603 which. */ 1604#define REG_PARM_STACK_SPACE(FNDECL) 0 1605 1606/* Define as a C expression that evaluates to nonzero if we do not know how 1607 to pass TYPE solely in registers. The file expr.h defines a 1608 definition that is usually appropriate, refer to expr.h for additional 1609 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be 1610 computed in the stack and then loaded into a register. */ 1611#define MUST_PASS_IN_STACK(MODE, TYPE) \ 1612 ((TYPE) != 0 \ 1613 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1614 || TREE_ADDRESSABLE (TYPE) \ 1615 || ((MODE) == TImode) \ 1616 || ((MODE) == BLKmode \ 1617 && ! ((TYPE) != 0 \ 1618 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ 1619 && 0 == (int_size_in_bytes (TYPE) \ 1620 % (PARM_BOUNDARY / BITS_PER_UNIT))) \ 1621 && (FUNCTION_ARG_PADDING (MODE, TYPE) \ 1622 == (BYTES_BIG_ENDIAN ? upward : downward))))) 1623 1624/* Value is the number of bytes of arguments automatically 1625 popped when returning from a subroutine call. 1626 FUNDECL is the declaration node of the function (as a tree), 1627 FUNTYPE is the data type of the function (as a tree), 1628 or for a library call it is an identifier node for the subroutine name. 1629 SIZE is the number of bytes of arguments passed on the stack. 1630 1631 On the 80386, the RTD insn may be used to pop them if the number 1632 of args is fixed, but if the number is variable then the caller 1633 must pop them all. RTD can't be used for library calls now 1634 because the library is compiled with the Unix compiler. 1635 Use of RTD is a selectable option, since it is incompatible with 1636 standard Unix calling sequences. If the option is not selected, 1637 the caller must always pop the args. 1638 1639 The attribute stdcall is equivalent to RTD on a per module basis. */ 1640 1641#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1642 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1643 1644/* Define how to find the value returned by a function. 1645 VALTYPE is the data type of the value (as a tree). 1646 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1647 otherwise, FUNC is 0. */ 1648#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1649 ix86_function_value (VALTYPE) 1650 1651#define FUNCTION_VALUE_REGNO_P(N) \ 1652 ix86_function_value_regno_p (N) 1653 1654/* Define how to find the value returned by a library function 1655 assuming the value has mode MODE. */ 1656 1657#define LIBCALL_VALUE(MODE) \ 1658 ix86_libcall_value (MODE) 1659 1660/* Define the size of the result block used for communication between 1661 untyped_call and untyped_return. The block contains a DImode value 1662 followed by the block used by fnsave and frstor. */ 1663 1664#define APPLY_RESULT_SIZE (8+108) 1665 1666/* 1 if N is a possible register number for function argument passing. */ 1667#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1668 1669/* Define a data type for recording info about an argument list 1670 during the scan of that argument list. This data type should 1671 hold all necessary information about the function itself 1672 and about the args processed so far, enough to enable macros 1673 such as FUNCTION_ARG to determine where the next arg should go. */ 1674 1675typedef struct ix86_args { 1676 int words; /* # words passed so far */ 1677 int nregs; /* # registers available for passing */ 1678 int regno; /* next available register number */ 1679 int sse_words; /* # sse words passed so far */ 1680 int sse_nregs; /* # sse registers available for passing */ 1681 int sse_regno; /* next available sse register number */ 1682 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1683} CUMULATIVE_ARGS; 1684 1685/* Initialize a variable CUM of type CUMULATIVE_ARGS 1686 for a call to a function whose data type is FNTYPE. 1687 For a library call, FNTYPE is 0. */ 1688 1689#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1690 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) 1691 1692/* Update the data in CUM to advance over an argument 1693 of mode MODE and data type TYPE. 1694 (TYPE is null for libcalls where that information may not be available.) */ 1695 1696#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1697 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1698 1699/* Define where to put the arguments to a function. 1700 Value is zero to push the argument on the stack, 1701 or a hard register in which to store the argument. 1702 1703 MODE is the argument's machine mode. 1704 TYPE is the data type of the argument (as a tree). 1705 This is null for libcalls where that information may 1706 not be available. 1707 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1708 the preceding args and about the function being called. 1709 NAMED is nonzero if this argument is a named parameter 1710 (otherwise it is an extra parameter matching an ellipsis). */ 1711 1712#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1713 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1714 1715/* For an arg passed partly in registers and partly in memory, 1716 this is the number of registers used. 1717 For args passed entirely in registers or entirely in memory, zero. */ 1718 1719#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1720 1721/* If PIC, we cannot make sibling calls to global functions 1722 because the PLT requires %ebx live. 1723 If we are returning floats on the register stack, we cannot make 1724 sibling calls to functions that return floats. (The stack adjust 1725 instruction will wind up after the sibcall jump, and not be executed.) */ 1726#define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1727 ((DECL) \ 1728 && (! flag_pic || ! TREE_PUBLIC (DECL)) \ 1729 && (! TARGET_FLOAT_RETURNS_IN_80387 \ 1730 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \ 1731 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl)))))) 1732 1733/* Perform any needed actions needed for a function that is receiving a 1734 variable number of arguments. 1735 1736 CUM is as above. 1737 1738 MODE and TYPE are the mode and type of the current parameter. 1739 1740 PRETEND_SIZE is a variable that should be set to the amount of stack 1741 that must be pushed by the prolog to pretend that our caller pushed 1742 it. 1743 1744 Normally, this macro will push all remaining incoming registers on the 1745 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1746 1747#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1748 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ 1749 (NO_RTL)) 1750 1751/* Define the `__builtin_va_list' type for the ABI. */ 1752#define BUILD_VA_LIST_TYPE(VALIST) \ 1753 ((VALIST) = ix86_build_va_list ()) 1754 1755/* Implement `va_start' for varargs and stdarg. */ 1756#define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \ 1757 ix86_va_start ((STDARG), (VALIST), (NEXTARG)) 1758 1759/* Implement `va_arg'. */ 1760#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ 1761 ix86_va_arg ((VALIST), (TYPE)) 1762 1763/* This macro is invoked at the end of compilation. It is used here to 1764 output code for -fpic that will load the return address into %ebx. */ 1765 1766#undef ASM_FILE_END 1767#define ASM_FILE_END(FILE) ix86_asm_file_end (FILE) 1768 1769/* Output assembler code to FILE to increment profiler label # LABELNO 1770 for profiling a function entry. */ 1771 1772#define FUNCTION_PROFILER(FILE, LABELNO) \ 1773do { \ 1774 if (flag_pic) \ 1775 { \ 1776 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \ 1777 LPREFIX, (LABELNO)); \ 1778 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \ 1779 } \ 1780 else \ 1781 { \ 1782 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ 1783 fprintf ((FILE), "\tcall\t_mcount\n"); \ 1784 } \ 1785} while (0) 1786 1787/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1788 the stack pointer does not matter. The value is tested only in 1789 functions that have frame pointers. 1790 No definition is equivalent to always zero. */ 1791/* Note on the 386 it might be more efficient not to define this since 1792 we have to restore it ourselves from the frame pointer, in order to 1793 use pop */ 1794 1795#define EXIT_IGNORE_STACK 1 1796 1797/* Output assembler code for a block containing the constant parts 1798 of a trampoline, leaving space for the variable parts. */ 1799 1800/* On the 386, the trampoline contains two instructions: 1801 mov #STATIC,ecx 1802 jmp FUNCTION 1803 The trampoline is generated entirely at runtime. The operand of JMP 1804 is the address of FUNCTION relative to the instruction following the 1805 JMP (which is 5 bytes long). */ 1806 1807/* Length in units of the trampoline for entering a nested function. */ 1808 1809#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1810 1811/* Emit RTL insns to initialize the variable parts of a trampoline. 1812 FNADDR is an RTX for the address of the function's pure code. 1813 CXT is an RTX for the static chain value for the function. */ 1814 1815#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1816 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1817 1818/* Definitions for register eliminations. 1819 1820 This is an array of structures. Each structure initializes one pair 1821 of eliminable registers. The "from" register number is given first, 1822 followed by "to". Eliminations of the same "from" register are listed 1823 in order of preference. 1824 1825 There are two registers that can always be eliminated on the i386. 1826 The frame pointer and the arg pointer can be replaced by either the 1827 hard frame pointer or to the stack pointer, depending upon the 1828 circumstances. The hard frame pointer is not used before reload and 1829 so it is not eligible for elimination. */ 1830 1831#define ELIMINABLE_REGS \ 1832{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1833 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1834 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1835 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1836 1837/* Given FROM and TO register numbers, say whether this elimination is 1838 allowed. Frame pointer elimination is automatically handled. 1839 1840 All other eliminations are valid. */ 1841 1842#define CAN_ELIMINATE(FROM, TO) \ 1843 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1844 1845/* Define the offset between two registers, one to be eliminated, and the other 1846 its replacement, at the start of a routine. */ 1847 1848#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1849 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1850 1851/* Addressing modes, and classification of registers for them. */ 1852 1853/* #define HAVE_POST_INCREMENT 0 */ 1854/* #define HAVE_POST_DECREMENT 0 */ 1855 1856/* #define HAVE_PRE_DECREMENT 0 */ 1857/* #define HAVE_PRE_INCREMENT 0 */ 1858 1859/* Macros to check register numbers against specific register classes. */ 1860 1861/* These assume that REGNO is a hard or pseudo reg number. 1862 They give nonzero only if REGNO is a hard reg of the suitable class 1863 or a pseudo reg currently allocated to a suitable hard reg. 1864 Since they use reg_renumber, they are safe only once reg_renumber 1865 has been allocated, which happens in local-alloc.c. */ 1866 1867#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1868 ((REGNO) < STACK_POINTER_REGNUM \ 1869 || (REGNO >= FIRST_REX_INT_REG \ 1870 && (REGNO) <= LAST_REX_INT_REG) \ 1871 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1872 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1873 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1874 1875#define REGNO_OK_FOR_BASE_P(REGNO) \ 1876 ((REGNO) <= STACK_POINTER_REGNUM \ 1877 || (REGNO) == ARG_POINTER_REGNUM \ 1878 || (REGNO) == FRAME_POINTER_REGNUM \ 1879 || (REGNO >= FIRST_REX_INT_REG \ 1880 && (REGNO) <= LAST_REX_INT_REG) \ 1881 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1882 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1883 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1884 1885#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1886 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1887#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1888 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1889 1890/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1891 and check its validity for a certain class. 1892 We have two alternate definitions for each of them. 1893 The usual definition accepts all pseudo regs; the other rejects 1894 them unless they have been allocated suitable hard regs. 1895 The symbol REG_OK_STRICT causes the latter definition to be used. 1896 1897 Most source files want to accept pseudo regs in the hope that 1898 they will get allocated to the class that the insn wants them to be in. 1899 Source files for reload pass need to be strict. 1900 After reload, it makes no difference, since pseudo regs have 1901 been eliminated by then. */ 1902 1903 1904/* Non strict versions, pseudos are ok */ 1905#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1906 (REGNO (X) < STACK_POINTER_REGNUM \ 1907 || (REGNO (X) >= FIRST_REX_INT_REG \ 1908 && REGNO (X) <= LAST_REX_INT_REG) \ 1909 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1910 1911#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1912 (REGNO (X) <= STACK_POINTER_REGNUM \ 1913 || REGNO (X) == ARG_POINTER_REGNUM \ 1914 || REGNO (X) == FRAME_POINTER_REGNUM \ 1915 || (REGNO (X) >= FIRST_REX_INT_REG \ 1916 && REGNO (X) <= LAST_REX_INT_REG) \ 1917 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1918 1919/* Strict versions, hard registers only */ 1920#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1921#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1922 1923#ifndef REG_OK_STRICT 1924#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1925#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1926 1927#else 1928#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1929#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1930#endif 1931 1932/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1933 that is a valid memory address for an instruction. 1934 The MODE argument is the machine mode for the MEM expression 1935 that wants to use this address. 1936 1937 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1938 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1939 1940 See legitimize_pic_address in i386.c for details as to what 1941 constitutes a legitimate address when -fpic is used. */ 1942 1943#define MAX_REGS_PER_ADDRESS 2 1944 1945#define CONSTANT_ADDRESS_P(X) \ 1946 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1947 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1948 || GET_CODE (X) == CONST_DOUBLE) 1949 1950/* Nonzero if the constant value X is a legitimate general operand. 1951 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1952 1953#define LEGITIMATE_CONSTANT_P(X) 1 1954 1955#ifdef REG_OK_STRICT 1956#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1957do { \ 1958 if (legitimate_address_p ((MODE), (X), 1)) \ 1959 goto ADDR; \ 1960} while (0) 1961 1962#else 1963#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1964do { \ 1965 if (legitimate_address_p ((MODE), (X), 0)) \ 1966 goto ADDR; \ 1967} while (0) 1968 1969#endif 1970 1971/* If defined, a C expression to determine the base term of address X. 1972 This macro is used in only one place: `find_base_term' in alias.c. 1973 1974 It is always safe for this macro to not be defined. It exists so 1975 that alias analysis can understand machine-dependent addresses. 1976 1977 The typical use of this macro is to handle addresses containing 1978 a label_ref or symbol_ref within an UNSPEC. */ 1979 1980#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1981 1982/* Try machine-dependent ways of modifying an illegitimate address 1983 to be legitimate. If we find one, return the new, valid address. 1984 This macro is used in only one place: `memory_address' in explow.c. 1985 1986 OLDX is the address as it was before break_out_memory_refs was called. 1987 In some cases it is useful to look at this to decide what needs to be done. 1988 1989 MODE and WIN are passed so that this macro can use 1990 GO_IF_LEGITIMATE_ADDRESS. 1991 1992 It is always safe for this macro to do nothing. It exists to recognize 1993 opportunities to optimize the output. 1994 1995 For the 80386, we handle X+REG by loading X into a register R and 1996 using R+REG. R will go in a general reg and indexing will be used. 1997 However, if REG is a broken-out memory address or multiplication, 1998 nothing needs to be done because REG can certainly go in a general reg. 1999 2000 When -fpic is used, special handling is needed for symbolic references. 2001 See comments by legitimize_pic_address in i386.c for details. */ 2002 2003#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2004do { \ 2005 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 2006 if (memory_address_p ((MODE), (X))) \ 2007 goto WIN; \ 2008} while (0) 2009 2010#define REWRITE_ADDRESS(X) rewrite_address (X) 2011 2012/* Nonzero if the constant value X is a legitimate general operand 2013 when generating PIC code. It is given that flag_pic is on and 2014 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2015 2016#define LEGITIMATE_PIC_OPERAND_P(X) \ 2017 (! SYMBOLIC_CONST (X) \ 2018 || legitimate_pic_address_disp_p (X)) 2019 2020#define SYMBOLIC_CONST(X) \ 2021 (GET_CODE (X) == SYMBOL_REF \ 2022 || GET_CODE (X) == LABEL_REF \ 2023 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 2024 2025/* Go to LABEL if ADDR (a legitimate address expression) 2026 has an effect that depends on the machine mode it is used for. 2027 On the 80386, only postdecrement and postincrement address depend thus 2028 (the amount of decrement or increment being the length of the operand). */ 2029#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2030do { \ 2031 if (GET_CODE (ADDR) == POST_INC \ 2032 || GET_CODE (ADDR) == POST_DEC) \ 2033 goto LABEL; \ 2034} while (0) 2035 2036/* Codes for all the SSE/MMX builtins. */ 2037enum ix86_builtins 2038{ 2039 IX86_BUILTIN_ADDPS, 2040 IX86_BUILTIN_ADDSS, 2041 IX86_BUILTIN_DIVPS, 2042 IX86_BUILTIN_DIVSS, 2043 IX86_BUILTIN_MULPS, 2044 IX86_BUILTIN_MULSS, 2045 IX86_BUILTIN_SUBPS, 2046 IX86_BUILTIN_SUBSS, 2047 2048 IX86_BUILTIN_CMPEQPS, 2049 IX86_BUILTIN_CMPLTPS, 2050 IX86_BUILTIN_CMPLEPS, 2051 IX86_BUILTIN_CMPGTPS, 2052 IX86_BUILTIN_CMPGEPS, 2053 IX86_BUILTIN_CMPNEQPS, 2054 IX86_BUILTIN_CMPNLTPS, 2055 IX86_BUILTIN_CMPNLEPS, 2056 IX86_BUILTIN_CMPNGTPS, 2057 IX86_BUILTIN_CMPNGEPS, 2058 IX86_BUILTIN_CMPORDPS, 2059 IX86_BUILTIN_CMPUNORDPS, 2060 IX86_BUILTIN_CMPNEPS, 2061 IX86_BUILTIN_CMPEQSS, 2062 IX86_BUILTIN_CMPLTSS, 2063 IX86_BUILTIN_CMPLESS, 2064 IX86_BUILTIN_CMPGTSS, 2065 IX86_BUILTIN_CMPGESS, 2066 IX86_BUILTIN_CMPNEQSS, 2067 IX86_BUILTIN_CMPNLTSS, 2068 IX86_BUILTIN_CMPNLESS, 2069 IX86_BUILTIN_CMPNGTSS, 2070 IX86_BUILTIN_CMPNGESS, 2071 IX86_BUILTIN_CMPORDSS, 2072 IX86_BUILTIN_CMPUNORDSS, 2073 IX86_BUILTIN_CMPNESS, 2074 2075 IX86_BUILTIN_COMIEQSS, 2076 IX86_BUILTIN_COMILTSS, 2077 IX86_BUILTIN_COMILESS, 2078 IX86_BUILTIN_COMIGTSS, 2079 IX86_BUILTIN_COMIGESS, 2080 IX86_BUILTIN_COMINEQSS, 2081 IX86_BUILTIN_UCOMIEQSS, 2082 IX86_BUILTIN_UCOMILTSS, 2083 IX86_BUILTIN_UCOMILESS, 2084 IX86_BUILTIN_UCOMIGTSS, 2085 IX86_BUILTIN_UCOMIGESS, 2086 IX86_BUILTIN_UCOMINEQSS, 2087 2088 IX86_BUILTIN_CVTPI2PS, 2089 IX86_BUILTIN_CVTPS2PI, 2090 IX86_BUILTIN_CVTSI2SS, 2091 IX86_BUILTIN_CVTSS2SI, 2092 IX86_BUILTIN_CVTTPS2PI, 2093 IX86_BUILTIN_CVTTSS2SI, 2094 2095 IX86_BUILTIN_MAXPS, 2096 IX86_BUILTIN_MAXSS, 2097 IX86_BUILTIN_MINPS, 2098 IX86_BUILTIN_MINSS, 2099 2100 IX86_BUILTIN_LOADAPS, 2101 IX86_BUILTIN_LOADUPS, 2102 IX86_BUILTIN_STOREAPS, 2103 IX86_BUILTIN_STOREUPS, 2104 IX86_BUILTIN_LOADSS, 2105 IX86_BUILTIN_STORESS, 2106 IX86_BUILTIN_MOVSS, 2107 2108 IX86_BUILTIN_MOVHLPS, 2109 IX86_BUILTIN_MOVLHPS, 2110 IX86_BUILTIN_LOADHPS, 2111 IX86_BUILTIN_LOADLPS, 2112 IX86_BUILTIN_STOREHPS, 2113 IX86_BUILTIN_STORELPS, 2114 2115 IX86_BUILTIN_MASKMOVQ, 2116 IX86_BUILTIN_MOVMSKPS, 2117 IX86_BUILTIN_PMOVMSKB, 2118 2119 IX86_BUILTIN_MOVNTPS, 2120 IX86_BUILTIN_MOVNTQ, 2121 2122 IX86_BUILTIN_PACKSSWB, 2123 IX86_BUILTIN_PACKSSDW, 2124 IX86_BUILTIN_PACKUSWB, 2125 2126 IX86_BUILTIN_PADDB, 2127 IX86_BUILTIN_PADDW, 2128 IX86_BUILTIN_PADDD, 2129 IX86_BUILTIN_PADDSB, 2130 IX86_BUILTIN_PADDSW, 2131 IX86_BUILTIN_PADDUSB, 2132 IX86_BUILTIN_PADDUSW, 2133 IX86_BUILTIN_PSUBB, 2134 IX86_BUILTIN_PSUBW, 2135 IX86_BUILTIN_PSUBD, 2136 IX86_BUILTIN_PSUBSB, 2137 IX86_BUILTIN_PSUBSW, 2138 IX86_BUILTIN_PSUBUSB, 2139 IX86_BUILTIN_PSUBUSW, 2140 2141 IX86_BUILTIN_PAND, 2142 IX86_BUILTIN_PANDN, 2143 IX86_BUILTIN_POR, 2144 IX86_BUILTIN_PXOR, 2145 2146 IX86_BUILTIN_PAVGB, 2147 IX86_BUILTIN_PAVGW, 2148 2149 IX86_BUILTIN_PCMPEQB, 2150 IX86_BUILTIN_PCMPEQW, 2151 IX86_BUILTIN_PCMPEQD, 2152 IX86_BUILTIN_PCMPGTB, 2153 IX86_BUILTIN_PCMPGTW, 2154 IX86_BUILTIN_PCMPGTD, 2155 2156 IX86_BUILTIN_PEXTRW, 2157 IX86_BUILTIN_PINSRW, 2158 2159 IX86_BUILTIN_PMADDWD, 2160 2161 IX86_BUILTIN_PMAXSW, 2162 IX86_BUILTIN_PMAXUB, 2163 IX86_BUILTIN_PMINSW, 2164 IX86_BUILTIN_PMINUB, 2165 2166 IX86_BUILTIN_PMULHUW, 2167 IX86_BUILTIN_PMULHW, 2168 IX86_BUILTIN_PMULLW, 2169 2170 IX86_BUILTIN_PSADBW, 2171 IX86_BUILTIN_PSHUFW, 2172 2173 IX86_BUILTIN_PSLLW, 2174 IX86_BUILTIN_PSLLD, 2175 IX86_BUILTIN_PSLLQ, 2176 IX86_BUILTIN_PSRAW, 2177 IX86_BUILTIN_PSRAD, 2178 IX86_BUILTIN_PSRLW, 2179 IX86_BUILTIN_PSRLD, 2180 IX86_BUILTIN_PSRLQ, 2181 IX86_BUILTIN_PSLLWI, 2182 IX86_BUILTIN_PSLLDI, 2183 IX86_BUILTIN_PSLLQI, 2184 IX86_BUILTIN_PSRAWI, 2185 IX86_BUILTIN_PSRADI, 2186 IX86_BUILTIN_PSRLWI, 2187 IX86_BUILTIN_PSRLDI, 2188 IX86_BUILTIN_PSRLQI, 2189 2190 IX86_BUILTIN_PUNPCKHBW, 2191 IX86_BUILTIN_PUNPCKHWD, 2192 IX86_BUILTIN_PUNPCKHDQ, 2193 IX86_BUILTIN_PUNPCKLBW, 2194 IX86_BUILTIN_PUNPCKLWD, 2195 IX86_BUILTIN_PUNPCKLDQ, 2196 2197 IX86_BUILTIN_SHUFPS, 2198 2199 IX86_BUILTIN_RCPPS, 2200 IX86_BUILTIN_RCPSS, 2201 IX86_BUILTIN_RSQRTPS, 2202 IX86_BUILTIN_RSQRTSS, 2203 IX86_BUILTIN_SQRTPS, 2204 IX86_BUILTIN_SQRTSS, 2205 2206 IX86_BUILTIN_UNPCKHPS, 2207 IX86_BUILTIN_UNPCKLPS, 2208 2209 IX86_BUILTIN_ANDPS, 2210 IX86_BUILTIN_ANDNPS, 2211 IX86_BUILTIN_ORPS, 2212 IX86_BUILTIN_XORPS, 2213 2214 IX86_BUILTIN_EMMS, 2215 IX86_BUILTIN_LDMXCSR, 2216 IX86_BUILTIN_STMXCSR, 2217 IX86_BUILTIN_SFENCE, 2218 2219 /* 3DNow! Original */ 2220 IX86_BUILTIN_FEMMS, 2221 IX86_BUILTIN_PAVGUSB, 2222 IX86_BUILTIN_PF2ID, 2223 IX86_BUILTIN_PFACC, 2224 IX86_BUILTIN_PFADD, 2225 IX86_BUILTIN_PFCMPEQ, 2226 IX86_BUILTIN_PFCMPGE, 2227 IX86_BUILTIN_PFCMPGT, 2228 IX86_BUILTIN_PFMAX, 2229 IX86_BUILTIN_PFMIN, 2230 IX86_BUILTIN_PFMUL, 2231 IX86_BUILTIN_PFRCP, 2232 IX86_BUILTIN_PFRCPIT1, 2233 IX86_BUILTIN_PFRCPIT2, 2234 IX86_BUILTIN_PFRSQIT1, 2235 IX86_BUILTIN_PFRSQRT, 2236 IX86_BUILTIN_PFSUB, 2237 IX86_BUILTIN_PFSUBR, 2238 IX86_BUILTIN_PI2FD, 2239 IX86_BUILTIN_PMULHRW, 2240 2241 /* 3DNow! Athlon Extensions */ 2242 IX86_BUILTIN_PF2IW, 2243 IX86_BUILTIN_PFNACC, 2244 IX86_BUILTIN_PFPNACC, 2245 IX86_BUILTIN_PI2FW, 2246 IX86_BUILTIN_PSWAPDSI, 2247 IX86_BUILTIN_PSWAPDSF, 2248 2249 IX86_BUILTIN_SSE_ZERO, 2250 IX86_BUILTIN_MMX_ZERO, 2251 2252 IX86_BUILTIN_MAX 2253}; 2254 2255/* Define this macro if references to a symbol must be treated 2256 differently depending on something about the variable or 2257 function named by the symbol (such as what section it is in). 2258 2259 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol 2260 so that we may access it directly in the GOT. */ 2261 2262#define ENCODE_SECTION_INFO(DECL) \ 2263do { \ 2264 if (flag_pic) \ 2265 { \ 2266 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2267 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ 2268 \ 2269 if (GET_CODE (rtl) == MEM) \ 2270 { \ 2271 if (TARGET_DEBUG_ADDR \ 2272 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \ 2273 { \ 2274 fprintf (stderr, "Encode %s, public = %d\n", \ 2275 IDENTIFIER_POINTER (DECL_NAME (DECL)), \ 2276 TREE_PUBLIC (DECL)); \ 2277 } \ 2278 \ 2279 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ 2280 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2281 || ! TREE_PUBLIC (DECL)); \ 2282 } \ 2283 } \ 2284} while (0) 2285 2286/* The `FINALIZE_PIC' macro serves as a hook to emit these special 2287 codes once the function is being compiled into assembly code, but 2288 not before. (It is not done before, because in the case of 2289 compiling an inline function, it would lead to multiple PIC 2290 prologues being included in functions which used inline functions 2291 and were compiled to assembly language.) */ 2292 2293#define FINALIZE_PIC \ 2294 (current_function_uses_pic_offset_table |= current_function_profile) 2295 2296 2297/* Max number of args passed in registers. If this is more than 3, we will 2298 have problems with ebx (register #4), since it is a caller save register and 2299 is also used as the pic register in ELF. So for now, don't allow more than 2300 3 registers to be passed in registers. */ 2301 2302#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 2303 2304#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0) 2305 2306 2307/* Specify the machine mode that this machine uses 2308 for the index in the tablejump instruction. */ 2309#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 2310 2311/* Define as C expression which evaluates to nonzero if the tablejump 2312 instruction expects the table to contain offsets from the address of the 2313 table. 2314 Do not define this if the table should contain absolute addresses. */ 2315/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2316 2317/* Define this as 1 if `char' should by default be signed; else as 0. */ 2318#define DEFAULT_SIGNED_CHAR 1 2319 2320/* Number of bytes moved into a data cache for a single prefetch operation. */ 2321#define PREFETCH_BLOCK ix86_cost->prefetch_block 2322 2323/* Number of prefetch operations that can be done in parallel. */ 2324#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 2325 2326/* Max number of bytes we can move from memory to memory 2327 in one reasonably fast instruction. */ 2328#define MOVE_MAX 16 2329 2330/* MOVE_MAX_PIECES is the number of bytes at a time which we can 2331 move efficiently, as opposed to MOVE_MAX which is the maximum 2332 number of bytes we can move with a single instruction. */ 2333#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 2334 2335/* If a memory-to-memory move would take MOVE_RATIO or more simple 2336 move-instruction pairs, we will do a movstr or libcall instead. 2337 Increasing the value will always make code faster, but eventually 2338 incurs high cost in increased code size. 2339 2340 If you don't define this, a reasonable default is used. */ 2341 2342#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 2343 2344/* Define if shifts truncate the shift count 2345 which implies one can omit a sign-extension or zero-extension 2346 of a shift count. */ 2347/* On i386, shifts do truncate the count. But bit opcodes don't. */ 2348 2349/* #define SHIFT_COUNT_TRUNCATED */ 2350 2351/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2352 is done just by pretending it is already truncated. */ 2353#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2354 2355/* We assume that the store-condition-codes instructions store 0 for false 2356 and some other value for true. This is the value stored for true. */ 2357 2358#define STORE_FLAG_VALUE 1 2359 2360/* When a prototype says `char' or `short', really pass an `int'. 2361 (The 386 can't easily push less than an int.) */ 2362 2363#define PROMOTE_PROTOTYPES (!TARGET_64BIT) 2364 2365/* A macro to update M and UNSIGNEDP when an object whose type is 2366 TYPE and which has the specified mode and signedness is to be 2367 stored in a register. This macro is only called when TYPE is a 2368 scalar type. 2369 2370 On i386 it is sometimes useful to promote HImode and QImode 2371 quantities to SImode. The choice depends on target type. */ 2372 2373#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2374do { \ 2375 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 2376 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 2377 (MODE) = SImode; \ 2378} while (0) 2379 2380/* Specify the machine mode that pointers have. 2381 After generation of rtl, the compiler makes no further distinction 2382 between pointers and any other objects of this machine mode. */ 2383#define Pmode (TARGET_64BIT ? DImode : SImode) 2384 2385/* A function address in a call instruction 2386 is a byte address (for indexing purposes) 2387 so give the MEM rtx a byte's mode. */ 2388#define FUNCTION_MODE QImode 2389 2390/* A part of a C `switch' statement that describes the relative costs 2391 of constant RTL expressions. It must contain `case' labels for 2392 expression codes `const_int', `const', `symbol_ref', `label_ref' 2393 and `const_double'. Each case must ultimately reach a `return' 2394 statement to return the relative cost of the use of that kind of 2395 constant value in an expression. The cost may depend on the 2396 precise value of the constant, which is available for examination 2397 in X, and the rtx code of the expression in which it is contained, 2398 found in OUTER_CODE. 2399 2400 CODE is the expression code--redundant, since it can be obtained 2401 with `GET_CODE (X)'. */ 2402 2403#define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 2404 case CONST_INT: \ 2405 case CONST: \ 2406 case LABEL_REF: \ 2407 case SYMBOL_REF: \ 2408 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \ 2409 return 3; \ 2410 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \ 2411 return 2; \ 2412 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \ 2413 \ 2414 case CONST_DOUBLE: \ 2415 { \ 2416 int code; \ 2417 if (GET_MODE (RTX) == VOIDmode) \ 2418 return 0; \ 2419 \ 2420 code = standard_80387_constant_p (RTX); \ 2421 return code == 1 ? 1 : \ 2422 code == 2 ? 2 : \ 2423 3; \ 2424 } 2425 2426/* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ 2427#define TOPLEVEL_COSTS_N_INSNS(N) \ 2428 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) 2429 2430/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. 2431 This can be used, for example, to indicate how costly a multiply 2432 instruction is. In writing this macro, you can use the construct 2433 `COSTS_N_INSNS (N)' to specify a cost equal to N fast 2434 instructions. OUTER_CODE is the code of the expression in which X 2435 is contained. 2436 2437 This macro is optional; do not define it if the default cost 2438 assumptions are adequate for the target machine. */ 2439 2440#define RTX_COSTS(X, CODE, OUTER_CODE) \ 2441 case ZERO_EXTEND: \ 2442 /* The zero extensions is often completely free on x86_64, so make \ 2443 it as cheap as possible. */ \ 2444 if (TARGET_64BIT && GET_MODE (X) == DImode \ 2445 && GET_MODE (XEXP (X, 0)) == SImode) \ 2446 { \ 2447 total = 1; goto egress_rtx_costs; \ 2448 } \ 2449 else \ 2450 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \ 2451 ix86_cost->add : ix86_cost->movzx); \ 2452 break; \ 2453 case SIGN_EXTEND: \ 2454 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \ 2455 break; \ 2456 case ASHIFT: \ 2457 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 2458 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \ 2459 { \ 2460 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2461 if (value == 1) \ 2462 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2463 if ((value == 2 || value == 3) \ 2464 && !TARGET_DECOMPOSE_LEA \ 2465 && ix86_cost->lea <= ix86_cost->shift_const) \ 2466 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ 2467 } \ 2468 /* fall through */ \ 2469 \ 2470 case ROTATE: \ 2471 case ASHIFTRT: \ 2472 case LSHIFTRT: \ 2473 case ROTATERT: \ 2474 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \ 2475 { \ 2476 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2477 { \ 2478 if (INTVAL (XEXP (X, 1)) > 32) \ 2479 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ 2480 else \ 2481 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ 2482 } \ 2483 else \ 2484 { \ 2485 if (GET_CODE (XEXP (X, 1)) == AND) \ 2486 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ 2487 else \ 2488 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ 2489 } \ 2490 } \ 2491 else \ 2492 { \ 2493 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2494 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ 2495 else \ 2496 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ 2497 } \ 2498 break; \ 2499 \ 2500 case MULT: \ 2501 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2502 { \ 2503 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2504 int nbits = 0; \ 2505 \ 2506 while (value != 0) \ 2507 { \ 2508 nbits++; \ 2509 value >>= 1; \ 2510 } \ 2511 \ 2512 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2513 + nbits * ix86_cost->mult_bit); \ 2514 } \ 2515 else /* This is arbitrary */ \ 2516 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2517 + 7 * ix86_cost->mult_bit); \ 2518 \ 2519 case DIV: \ 2520 case UDIV: \ 2521 case MOD: \ 2522 case UMOD: \ 2523 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ 2524 \ 2525 case PLUS: \ 2526 if (!TARGET_DECOMPOSE_LEA \ 2527 && INTEGRAL_MODE_P (GET_MODE (X)) \ 2528 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \ 2529 { \ 2530 if (GET_CODE (XEXP (X, 0)) == PLUS \ 2531 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ 2532 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ 2533 && CONSTANT_P (XEXP (X, 1))) \ 2534 { \ 2535 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\ 2536 if (val == 2 || val == 4 || val == 8) \ 2537 { \ 2538 return (COSTS_N_INSNS (ix86_cost->lea) \ 2539 + rtx_cost (XEXP (XEXP (X, 0), 1), \ 2540 (OUTER_CODE)) \ 2541 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \ 2542 (OUTER_CODE)) \ 2543 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2544 } \ 2545 } \ 2546 else if (GET_CODE (XEXP (X, 0)) == MULT \ 2547 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ 2548 { \ 2549 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ 2550 if (val == 2 || val == 4 || val == 8) \ 2551 { \ 2552 return (COSTS_N_INSNS (ix86_cost->lea) \ 2553 + rtx_cost (XEXP (XEXP (X, 0), 0), \ 2554 (OUTER_CODE)) \ 2555 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2556 } \ 2557 } \ 2558 else if (GET_CODE (XEXP (X, 0)) == PLUS) \ 2559 { \ 2560 return (COSTS_N_INSNS (ix86_cost->lea) \ 2561 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \ 2562 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \ 2563 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2564 } \ 2565 } \ 2566 \ 2567 /* fall through */ \ 2568 case AND: \ 2569 case IOR: \ 2570 case XOR: \ 2571 case MINUS: \ 2572 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2573 return (COSTS_N_INSNS (ix86_cost->add) * 2 \ 2574 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \ 2575 << (GET_MODE (XEXP (X, 0)) != DImode)) \ 2576 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \ 2577 << (GET_MODE (XEXP (X, 1)) != DImode))); \ 2578 \ 2579 /* fall through */ \ 2580 case NEG: \ 2581 case NOT: \ 2582 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2583 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ 2584 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2585 \ 2586 egress_rtx_costs: \ 2587 break; 2588 2589 2590/* An expression giving the cost of an addressing mode that contains 2591 ADDRESS. If not defined, the cost is computed from the ADDRESS 2592 expression and the `CONST_COSTS' values. 2593 2594 For most CISC machines, the default cost is a good approximation 2595 of the true cost of the addressing mode. However, on RISC 2596 machines, all instructions normally have the same length and 2597 execution time. Hence all addresses will have equal costs. 2598 2599 In cases where more than one form of an address is known, the form 2600 with the lowest cost will be used. If multiple forms have the 2601 same, lowest, cost, the one that is the most complex will be used. 2602 2603 For example, suppose an address that is equal to the sum of a 2604 register and a constant is used twice in the same basic block. 2605 When this macro is not defined, the address will be computed in a 2606 register and memory references will be indirect through that 2607 register. On machines where the cost of the addressing mode 2608 containing the sum is no higher than that of a simple indirect 2609 reference, this will produce an additional instruction and 2610 possibly require an additional register. Proper specification of 2611 this macro eliminates this overhead for such machines. 2612 2613 Similar use of this macro is made in strength reduction of loops. 2614 2615 ADDRESS need not be valid as an address. In such a case, the cost 2616 is not relevant and can be any value; invalid addresses need not be 2617 assigned a different cost. 2618 2619 On machines where an address involving more than one register is as 2620 cheap as an address computation involving only one register, 2621 defining `ADDRESS_COST' to reflect this can cause two registers to 2622 be live over a region of code where only one would have been if 2623 `ADDRESS_COST' were not defined in that manner. This effect should 2624 be considered in the definition of this macro. Equivalent costs 2625 should probably only be given to addresses with different numbers 2626 of registers on machines with lots of registers. 2627 2628 This macro will normally either not be defined or be defined as a 2629 constant. 2630 2631 For i386, it is better to use a complex address than let gcc copy 2632 the address into a reg and make a new pseudo. But not if the address 2633 requires to two regs - that would mean more pseudos with longer 2634 lifetimes. */ 2635 2636#define ADDRESS_COST(RTX) \ 2637 ix86_address_cost (RTX) 2638 2639/* A C expression for the cost of moving data from a register in class FROM to 2640 one in class TO. The classes are expressed using the enumeration values 2641 such as `GENERAL_REGS'. A value of 2 is the default; other values are 2642 interpreted relative to that. 2643 2644 It is not required that the cost always equal 2 when FROM is the same as TO; 2645 on some machines it is expensive to move between registers if they are not 2646 general registers. */ 2647 2648#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2649 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 2650 2651/* A C expression for the cost of moving data of mode M between a 2652 register and memory. A value of 2 is the default; this cost is 2653 relative to those in `REGISTER_MOVE_COST'. 2654 2655 If moving between registers and memory is more expensive than 2656 between two registers, you should define this macro to express the 2657 relative cost. */ 2658 2659#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 2660 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 2661 2662/* A C expression for the cost of a branch instruction. A value of 1 2663 is the default; other values are interpreted relative to that. */ 2664 2665#define BRANCH_COST ix86_branch_cost 2666 2667/* Define this macro as a C expression which is nonzero if accessing 2668 less than a word of memory (i.e. a `char' or a `short') is no 2669 faster than accessing a word of memory, i.e., if such access 2670 require more than one instruction or if there is no difference in 2671 cost between byte and (aligned) word loads. 2672 2673 When this macro is not defined, the compiler will access a field by 2674 finding the smallest containing object; when it is defined, a 2675 fullword load will be used if alignment permits. Unless bytes 2676 accesses are faster than word accesses, using word accesses is 2677 preferable since it may eliminate subsequent memory access if 2678 subsequent accesses occur to other fields in the same word of the 2679 structure, but to different bytes. */ 2680 2681#define SLOW_BYTE_ACCESS 0 2682 2683/* Nonzero if access to memory by shorts is slow and undesirable. */ 2684#define SLOW_SHORT_ACCESS 0 2685 2686/* Define this macro to be the value 1 if unaligned accesses have a 2687 cost many times greater than aligned accesses, for example if they 2688 are emulated in a trap handler. 2689 2690 When this macro is non-zero, the compiler will act as if 2691 `STRICT_ALIGNMENT' were non-zero when generating code for block 2692 moves. This can cause significantly more instructions to be 2693 produced. Therefore, do not set this macro non-zero if unaligned 2694 accesses only add a cycle or two to the time for a memory access. 2695 2696 If the value of this macro is always zero, it need not be defined. */ 2697 2698/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2699 2700/* Define this macro to inhibit strength reduction of memory 2701 addresses. (On some machines, such strength reduction seems to do 2702 harm rather than good.) */ 2703 2704/* #define DONT_REDUCE_ADDR */ 2705 2706/* Define this macro if it is as good or better to call a constant 2707 function address than to call an address kept in a register. 2708 2709 Desirable on the 386 because a CALL with a constant address is 2710 faster than one with a register address. */ 2711 2712#define NO_FUNCTION_CSE 2713 2714/* Define this macro if it is as good or better for a function to call 2715 itself with an explicit address than to call an address kept in a 2716 register. */ 2717 2718#define NO_RECURSIVE_FUNCTION_CSE 2719 2720/* Add any extra modes needed to represent the condition code. 2721 2722 For the i386, we need separate modes when floating-point 2723 equality comparisons are being done. 2724 2725 Add CCNO to indicate comparisons against zero that requires 2726 Overflow flag to be unset. Sign bit test is used instead and 2727 thus can be used to form "a&b>0" type of tests. 2728 2729 Add CCGC to indicate comparisons agains zero that allows 2730 unspecified garbage in the Carry flag. This mode is used 2731 by inc/dec instructions. 2732 2733 Add CCGOC to indicate comparisons agains zero that allows 2734 unspecified garbage in the Carry and Overflow flag. This 2735 mode is used to simulate comparisons of (a-b) and (a+b) 2736 against zero using sub/cmp/add operations. 2737 2738 Add CCZ to indicate that only the Zero flag is valid. */ 2739 2740#define EXTRA_CC_MODES \ 2741 CC (CCGCmode, "CCGC") \ 2742 CC (CCGOCmode, "CCGOC") \ 2743 CC (CCNOmode, "CCNO") \ 2744 CC (CCZmode, "CCZ") \ 2745 CC (CCFPmode, "CCFP") \ 2746 CC (CCFPUmode, "CCFPU") 2747 2748/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2749 return the mode to be used for the comparison. 2750 2751 For floating-point equality comparisons, CCFPEQmode should be used. 2752 VOIDmode should be used in all other cases. 2753 2754 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2755 possible, to allow for more combinations. */ 2756 2757#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2758 2759/* Return non-zero if MODE implies a floating point inequality can be 2760 reversed. */ 2761 2762#define REVERSIBLE_CC_MODE(MODE) 1 2763 2764/* A C expression whose value is reversed condition code of the CODE for 2765 comparison done in CC_MODE mode. */ 2766#define REVERSE_CONDITION(CODE, MODE) \ 2767 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ 2768 : reverse_condition_maybe_unordered (CODE)) 2769 2770 2771/* Control the assembler format that we output, to the extent 2772 this does not vary between assemblers. */ 2773 2774/* How to refer to registers in assembler output. 2775 This sequence is indexed by compiler's hard-register-number (see above). */ 2776 2777/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" 2778 For non floating point regs, the following are the HImode names. 2779 2780 For float regs, the stack top is sometimes referred to as "%st(0)" 2781 instead of just "%st". PRINT_REG handles this with the "y" code. */ 2782 2783#undef HI_REGISTER_NAMES 2784#define HI_REGISTER_NAMES \ 2785{"ax","dx","cx","bx","si","di","bp","sp", \ 2786 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ 2787 "flags","fpsr", "dirflag", "frame", \ 2788 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2789 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 2790 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2791 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 2792 2793#define REGISTER_NAMES HI_REGISTER_NAMES 2794 2795/* Table of additional register names to use in user input. */ 2796 2797#define ADDITIONAL_REGISTER_NAMES \ 2798{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2799 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2800 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2801 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2802 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2803 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2804 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ 2805 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } 2806 2807/* Note we are omitting these since currently I don't know how 2808to get gcc to use these, since they want the same but different 2809number as al, and ax. 2810*/ 2811 2812#define QI_REGISTER_NAMES \ 2813{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2814 2815/* These parallel the array above, and can be used to access bits 8:15 2816 of regs 0 through 3. */ 2817 2818#define QI_HIGH_REGISTER_NAMES \ 2819{"ah", "dh", "ch", "bh", } 2820 2821/* How to renumber registers for dbx and gdb. */ 2822 2823#define DBX_REGISTER_NUMBER(N) \ 2824 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2825 2826extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2827extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2828extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2829 2830/* Before the prologue, RA is at 0(%esp). */ 2831#define INCOMING_RETURN_ADDR_RTX \ 2832 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2833 2834/* After the prologue, RA is at -4(AP) in the current frame. */ 2835#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2836 ((COUNT) == 0 \ 2837 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2838 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2839 2840/* PC is dbx register 8; let's use that column for RA. */ 2841#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2842 2843/* Before the prologue, the top of the frame is at 4(%esp). */ 2844#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2845 2846/* Describe how we implement __builtin_eh_return. */ 2847#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2848#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2849 2850 2851/* Select a format to encode pointers in exception handling data. CODE 2852 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2853 true if the symbol may be affected by dynamic relocations. 2854 2855 ??? All x86 object file formats are capable of representing this. 2856 After all, the relocation needed is the same as for the call insn. 2857 Whether or not a particular assembler allows us to enter such, I 2858 guess we'll have to see. */ 2859#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2860 (flag_pic \ 2861 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 2862 : DW_EH_PE_absptr) 2863 2864/* This is how to output the definition of a user-level label named NAME, 2865 such as the label on a static function or variable NAME. */ 2866 2867#define ASM_OUTPUT_LABEL(FILE, NAME) \ 2868 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE))) 2869 2870/* Store in OUTPUT a string (made with alloca) containing 2871 an assembler-name for a local static variable named NAME. 2872 LABELNO is an integer which is different for each call. */ 2873 2874#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2875( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2876 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2877 2878/* This is how to output an insn to push a register on the stack. 2879 It need not be very fast code. */ 2880 2881#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2882 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]) 2883 2884/* This is how to output an insn to pop a register from the stack. 2885 It need not be very fast code. */ 2886 2887#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2888 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]) 2889 2890/* This is how to output an element of a case-vector that is absolute. */ 2891 2892#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2893 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2894 2895/* This is how to output an element of a case-vector that is relative. */ 2896 2897#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2898 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2899 2900/* Under some conditions we need jump tables in the text section, because 2901 the assembler cannot handle label differences between sections. */ 2902 2903#define JUMP_TABLES_IN_TEXT_SECTION \ 2904 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 2905 2906/* A C statement that outputs an address constant appropriate to 2907 for DWARF debugging. */ 2908 2909#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ 2910 i386_dwarf_output_addr_const ((FILE), (X)) 2911 2912/* Either simplify a location expression, or return the original. */ 2913 2914#define ASM_SIMPLIFY_DWARF_ADDR(X) \ 2915 i386_simplify_dwarf_addr (X) 2916 2917/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2918 and switch back. For x86 we do this only to save a few bytes that 2919 would otherwise be unused in the text section. */ 2920#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2921 asm (SECTION_OP "\n\t" \ 2922 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2923 TEXT_SECTION_ASM_OP); 2924 2925/* Print operand X (an rtx) in assembler syntax to file FILE. 2926 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2927 Effect of various CODE letters is described in i386.c near 2928 print_operand function. */ 2929 2930#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2931 ((CODE) == '*' || (CODE) == '+') 2932 2933/* Print the name of a register based on its machine mode and number. 2934 If CODE is 'w', pretend the mode is HImode. 2935 If CODE is 'b', pretend the mode is QImode. 2936 If CODE is 'k', pretend the mode is SImode. 2937 If CODE is 'q', pretend the mode is DImode. 2938 If CODE is 'h', pretend the reg is the `high' byte register. 2939 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ 2940 2941#define PRINT_REG(X, CODE, FILE) \ 2942 print_reg ((X), (CODE), (FILE)) 2943 2944#define PRINT_OPERAND(FILE, X, CODE) \ 2945 print_operand ((FILE), (X), (CODE)) 2946 2947#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2948 print_operand_address ((FILE), (ADDR)) 2949 2950/* Print the name of a register for based on its machine mode and number. 2951 This macro is used to print debugging output. 2952 This macro is different from PRINT_REG in that it may be used in 2953 programs that are not linked with aux-output.o. */ 2954 2955#define DEBUG_PRINT_REG(X, CODE, FILE) \ 2956 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ 2957 static const char * const qi_name[] = QI_REGISTER_NAMES; \ 2958 fprintf ((FILE), "%d ", REGNO (X)); \ 2959 if (REGNO (X) == FLAGS_REG) \ 2960 { fputs ("flags", (FILE)); break; } \ 2961 if (REGNO (X) == DIRFLAG_REG) \ 2962 { fputs ("dirflag", (FILE)); break; } \ 2963 if (REGNO (X) == FPSR_REG) \ 2964 { fputs ("fpsr", (FILE)); break; } \ 2965 if (REGNO (X) == ARG_POINTER_REGNUM) \ 2966 { fputs ("argp", (FILE)); break; } \ 2967 if (REGNO (X) == FRAME_POINTER_REGNUM) \ 2968 { fputs ("frame", (FILE)); break; } \ 2969 if (STACK_TOP_P (X)) \ 2970 { fputs ("st(0)", (FILE)); break; } \ 2971 if (FP_REG_P (X)) \ 2972 { fputs (hi_name[REGNO(X)], (FILE)); break; } \ 2973 if (REX_INT_REG_P (X)) \ 2974 { \ 2975 switch (GET_MODE_SIZE (GET_MODE (X))) \ 2976 { \ 2977 default: \ 2978 case 8: \ 2979 fprintf ((FILE), "r%i", REGNO (X) \ 2980 - FIRST_REX_INT_REG + 8); \ 2981 break; \ 2982 case 4: \ 2983 fprintf ((FILE), "r%id", REGNO (X) \ 2984 - FIRST_REX_INT_REG + 8); \ 2985 break; \ 2986 case 2: \ 2987 fprintf ((FILE), "r%iw", REGNO (X) \ 2988 - FIRST_REX_INT_REG + 8); \ 2989 break; \ 2990 case 1: \ 2991 fprintf ((FILE), "r%ib", REGNO (X) \ 2992 - FIRST_REX_INT_REG + 8); \ 2993 break; \ 2994 } \ 2995 break; \ 2996 } \ 2997 switch (GET_MODE_SIZE (GET_MODE (X))) \ 2998 { \ 2999 case 8: \ 3000 fputs ("r", (FILE)); \ 3001 fputs (hi_name[REGNO (X)], (FILE)); \ 3002 break; \ 3003 default: \ 3004 fputs ("e", (FILE)); \ 3005 case 2: \ 3006 fputs (hi_name[REGNO (X)], (FILE)); \ 3007 break; \ 3008 case 1: \ 3009 fputs (qi_name[REGNO (X)], (FILE)); \ 3010 break; \ 3011 } \ 3012 } while (0) 3013 3014/* a letter which is not needed by the normal asm syntax, which 3015 we can use for operand syntax in the extended asm */ 3016 3017#define ASM_OPERAND_LETTER '#' 3018#define RET return "" 3019#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 3020 3021/* Define the codes that are matched by predicates in i386.c. */ 3022 3023#define PREDICATE_CODES \ 3024 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ 3025 SYMBOL_REF, LABEL_REF, CONST}}, \ 3026 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3027 SYMBOL_REF, LABEL_REF, CONST}}, \ 3028 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ 3029 SYMBOL_REF, LABEL_REF, CONST}}, \ 3030 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3031 SYMBOL_REF, LABEL_REF, CONST}}, \ 3032 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3033 SYMBOL_REF, LABEL_REF, CONST}}, \ 3034 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3035 SYMBOL_REF, LABEL_REF, CONST}}, \ 3036 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3037 SYMBOL_REF, LABEL_REF}}, \ 3038 {"shiftdi_operand", {SUBREG, REG, MEM}}, \ 3039 {"const_int_1_operand", {CONST_INT}}, \ 3040 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 3041 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3042 LABEL_REF, SUBREG, REG, MEM}}, \ 3043 {"pic_symbolic_operand", {CONST}}, \ 3044 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ 3045 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ 3046 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ 3047 {"const1_operand", {CONST_INT}}, \ 3048 {"const248_operand", {CONST_INT}}, \ 3049 {"incdec_operand", {CONST_INT}}, \ 3050 {"mmx_reg_operand", {REG}}, \ 3051 {"reg_no_sp_operand", {SUBREG, REG}}, \ 3052 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3053 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ 3054 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ 3055 {"q_regs_operand", {SUBREG, REG}}, \ 3056 {"non_q_regs_operand", {SUBREG, REG}}, \ 3057 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ 3058 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ 3059 GE, UNGE, LTGT, UNEQ}}, \ 3060 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ 3061 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ 3062 }}, \ 3063 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ 3064 GTU, UNORDERED, ORDERED, UNLE, UNLT, \ 3065 UNGE, UNGT, LTGT, UNEQ }}, \ 3066 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ 3067 {"ext_register_operand", {SUBREG, REG}}, \ 3068 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ 3069 {"mult_operator", {MULT}}, \ 3070 {"div_operator", {DIV}}, \ 3071 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ 3072 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ 3073 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ 3074 LSHIFTRT, ROTATERT}}, \ 3075 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ 3076 {"memory_displacement_operand", {MEM}}, \ 3077 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3078 LABEL_REF, SUBREG, REG, MEM, AND}}, \ 3079 {"long_memory_operand", {MEM}}, 3080 3081/* A list of predicates that do special things with modes, and so 3082 should not elicit warnings for VOIDmode match_operand. */ 3083 3084#define SPECIAL_MODE_PREDICATES \ 3085 "ext_register_operand", 3086 3087/* CM_32 is used by 32bit ABI 3088 CM_SMALL is small model assuming that all code and data fits in the first 3089 31bits of address space. 3090 CM_KERNEL is model assuming that all code and data fits in the negative 3091 31bits of address space. 3092 CM_MEDIUM is model assuming that code fits in the first 31bits of address 3093 space. Size of data is unlimited. 3094 CM_LARGE is model making no assumptions about size of particular sections. 3095 3096 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt 3097 tables first in 31bits of address space. 3098 */ 3099enum cmodel { 3100 CM_32, 3101 CM_SMALL, 3102 CM_KERNEL, 3103 CM_MEDIUM, 3104 CM_LARGE, 3105 CM_SMALL_PIC 3106}; 3107 3108/* Size of the RED_ZONE area. */ 3109#define RED_ZONE_SIZE 128 3110/* Reserved area of the red zone for temporaries. */ 3111#define RED_ZONE_RESERVE 8 3112extern const char *ix86_debug_arg_string, *ix86_debug_addr_string; 3113 3114enum asm_dialect { 3115 ASM_ATT, 3116 ASM_INTEL 3117}; 3118extern const char *ix86_asm_string; 3119extern enum asm_dialect ix86_asm_dialect; 3120/* Value of -mcmodel specified by user. */ 3121extern const char *ix86_cmodel_string; 3122extern enum cmodel ix86_cmodel; 3123 3124/* Variables in i386.c */ 3125extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */ 3126extern const char *ix86_arch_string; /* for -march=<xxx> */ 3127extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */ 3128extern const char *ix86_regparm_string; /* # registers to use to pass args */ 3129extern const char *ix86_align_loops_string; /* power of two alignment for loops */ 3130extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */ 3131extern const char *ix86_align_funcs_string; /* power of two alignment for functions */ 3132extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */ 3133extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */ 3134extern int ix86_regparm; /* ix86_regparm_string as a number */ 3135extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */ 3136extern int ix86_branch_cost; /* values 1-5: see jump.c */ 3137extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */ 3138extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 3139extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 3140 3141/* To properly truncate FP values into integers, we need to set i387 control 3142 word. We can't emit proper mode switching code before reload, as spills 3143 generated by reload may truncate values incorrectly, but we still can avoid 3144 redundant computation of new control word by the mode switching pass. 3145 The fldcw instructions are still emitted redundantly, but this is probably 3146 not going to be noticeable problem, as most CPUs do have fast path for 3147 the sequence. 3148 3149 The machinery is to emit simple truncation instructions and split them 3150 before reload to instructions having USEs of two memory locations that 3151 are filled by this code to old and new control word. 3152 3153 Post-reload pass may be later used to eliminate the redundant fildcw if 3154 needed. */ 3155 3156enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; 3157 3158/* Define this macro if the port needs extra instructions inserted 3159 for mode switching in an optimizing compilation. */ 3160 3161#define OPTIMIZE_MODE_SWITCHING(ENTITY) 1 3162 3163/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 3164 initializer for an array of integers. Each initializer element N 3165 refers to an entity that needs mode switching, and specifies the 3166 number of different modes that might need to be set for this 3167 entity. The position of the initializer in the initializer - 3168 starting counting at zero - determines the integer that is used to 3169 refer to the mode-switched entity in question. */ 3170 3171#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } 3172 3173/* ENTITY is an integer specifying a mode-switched entity. If 3174 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 3175 return an integer value not larger than the corresponding element 3176 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 3177 must be switched into prior to the execution of INSN. */ 3178 3179#define MODE_NEEDED(ENTITY, I) \ 3180 (GET_CODE (I) == CALL_INSN \ 3181 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ 3182 || GET_CODE (PATTERN (I)) == ASM_INPUT))\ 3183 ? FP_CW_UNINITIALIZED \ 3184 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ 3185 ? FP_CW_ANY \ 3186 : FP_CW_STORED) 3187 3188/* This macro specifies the order in which modes for ENTITY are 3189 processed. 0 is the highest priority. */ 3190 3191#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 3192 3193/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 3194 is the set of hard registers live at the point where the insn(s) 3195 are to be inserted. */ 3196 3197#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3198 ((MODE) == FP_CW_STORED \ 3199 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ 3200 assign_386_stack_local (HImode, 2)), 0\ 3201 : 0) 3202 3203/* Avoid renaming of stack registers, as doing so in combination with 3204 scheduling just increases amount of live registers at time and in 3205 the turn amount of fxch instructions needed. 3206 3207 ??? Maybe Pentium chips benefits from renaming, someone can try... */ 3208 3209#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 3210 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 3211 3212 3213/* 3214Local variables: 3215version-control: t 3216End: 3217*/ 3218