i386.h revision 90285
1251607Sdim/* Definitions of target machine for GNU compiler for IA-32. 2251607Sdim Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3251607Sdim 2001, 2002 Free Software Foundation, Inc. 4251607Sdim 5251607SdimThis file is part of GNU CC. 6251607Sdim 7251607SdimGNU CC is free software; you can redistribute it and/or modify 8251607Sdimit under the terms of the GNU General Public License as published by 9251607Sdimthe Free Software Foundation; either version 2, or (at your option) 10251607Sdimany later version. 11251607Sdim 12251607SdimGNU CC is distributed in the hope that it will be useful, 13251607Sdimbut WITHOUT ANY WARRANTY; without even the implied warranty of 14251607SdimMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15251607SdimGNU General Public License for more details. 16251607Sdim 17251607SdimYou should have received a copy of the GNU General Public License 18251607Sdimalong with GNU CC; see the file COPYING. If not, write to 19251607Sdimthe Free Software Foundation, 59 Temple Place - Suite 330, 20276479SdimBoston, MA 02111-1307, USA. */ 21251607Sdim 22251607Sdim/* The purpose of this file is to define the characteristics of the i386, 23276479Sdim independent of assembler syntax or operating system. 24276479Sdim 25251607Sdim Three other files build on this one to describe a specific assembler syntax: 26251607Sdim bsd386.h, att386.h, and sun386.h. 27261991Sdim 28251607Sdim The actual tm.h file for a particular system should include 29251607Sdim this file, and then the file for the appropriate assembler syntax. 30251607Sdim 31251607Sdim Many macros that specify assembler syntax are omitted entirely from 32251607Sdim this file because they really belong in the files for particular 33251607Sdim assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34251607Sdim ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35251607Sdim that start with ASM_ or end in ASM_OP. */ 36251607Sdim 37251607Sdim 38251607Sdim/* $FreeBSD: head/contrib/gcc/config/i386/i386.h 90285 2002-02-06 05:01:51Z obrien $ */ 39251607Sdim 40251607Sdim 41251607Sdim/* Stubs for half-pic support if not OSF/1 reference platform. */ 42251607Sdim 43251607Sdim#ifndef HALF_PIC_P 44251607Sdim#define HALF_PIC_P() 0 45251607Sdim#define HALF_PIC_NUMBER_PTRS 0 46251607Sdim#define HALF_PIC_NUMBER_REFS 0 47251607Sdim#define HALF_PIC_ENCODE(DECL) 48251607Sdim#define HALF_PIC_DECLARE(NAME) 49251607Sdim#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it") 50251607Sdim#define HALF_PIC_ADDRESS_P(X) 0 51276479Sdim#define HALF_PIC_PTR(X) (X) 52251607Sdim#define HALF_PIC_FINISH(STREAM) 53251607Sdim#endif 54251607Sdim 55251607Sdim/* Define the specific costs for a given cpu */ 56251607Sdim 57251607Sdimstruct processor_costs { 58251607Sdim const int add; /* cost of an add instruction */ 59251607Sdim const int lea; /* cost of a lea instruction */ 60251607Sdim const int shift_var; /* variable shift costs */ 61251607Sdim const int shift_const; /* constant shift costs */ 62251607Sdim const int mult_init; /* cost of starting a multiply */ 63251607Sdim const int mult_bit; /* cost of multiply per each bit set */ 64251607Sdim const int divide; /* cost of a divide/mod */ 65251607Sdim int movsx; /* The cost of movsx operation. */ 66251607Sdim int movzx; /* The cost of movzx operation. */ 67251607Sdim const int large_insn; /* insns larger than this cost more */ 68251607Sdim const int move_ratio; /* The threshold of number of scalar 69251607Sdim memory-to-memory move insns. */ 70251607Sdim const int movzbl_load; /* cost of loading using movzbl */ 71251607Sdim const int int_load[3]; /* cost of loading integer registers 72251607Sdim in QImode, HImode and SImode relative 73251607Sdim to reg-reg move (2). */ 74251607Sdim const int int_store[3]; /* cost of storing integer register 75251607Sdim in QImode, HImode and SImode */ 76251607Sdim const int fp_move; /* cost of reg,reg fld/fst */ 77261991Sdim const int fp_load[3]; /* cost of loading FP register 78261991Sdim in SFmode, DFmode and XFmode */ 79261991Sdim const int fp_store[3]; /* cost of storing FP register 80261991Sdim in SFmode, DFmode and XFmode */ 81261991Sdim const int mmx_move; /* cost of moving MMX register. */ 82261991Sdim const int mmx_load[2]; /* cost of loading MMX register 83261991Sdim in SImode and DImode */ 84261991Sdim const int mmx_store[2]; /* cost of storing MMX register 85288943Sdim in SImode and DImode */ 86288943Sdim const int sse_move; /* cost of moving SSE register. */ 87288943Sdim const int sse_load[3]; /* cost of loading SSE register 88261991Sdim in SImode, DImode and TImode*/ 89261991Sdim const int sse_store[3]; /* cost of storing SSE register 90261991Sdim in SImode, DImode and TImode*/ 91261991Sdim const int mmxsse_to_integer; /* cost of moving mmxsse register to 92261991Sdim integer and vice versa. */ 93261991Sdim const int prefetch_block; /* bytes moved to cache for prefetch. */ 94261991Sdim const int simultaneous_prefetches; /* number of parallel prefetch 95261991Sdim operations. */ 96261991Sdim}; 97261991Sdim 98261991Sdimextern const struct processor_costs *ix86_cost; 99261991Sdim 100261991Sdim/* Run-time compilation parameters selecting different hardware subsets. */ 101261991Sdim 102261991Sdimextern int target_flags; 103261991Sdim 104261991Sdim/* Macros used in the machine description to test the flags. */ 105261991Sdim 106261991Sdim/* configure can arrange to make this 2, to force a 486. */ 107261991Sdim 108261991Sdim#ifndef TARGET_CPU_DEFAULT 109261991Sdim#define TARGET_CPU_DEFAULT 0 110261991Sdim#endif 111261991Sdim 112261991Sdim/* Masks for the -m switches */ 113261991Sdim#define MASK_80387 0x00000001 /* Hardware floating point */ 114261991Sdim#define MASK_RTD 0x00000002 /* Use ret that pops args */ 115261991Sdim#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ 116261991Sdim#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ 117261991Sdim#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ 118261991Sdim#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ 119261991Sdim#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ 120261991Sdim#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ 121261991Sdim#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ 122261991Sdim#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ 123261991Sdim#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ 124261991Sdim#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ 125261991Sdim#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ 126261991Sdim#define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000 127261991Sdim#define MASK_MMX 0x00004000 /* Support MMX regs/builtins */ 128251607Sdim#define MASK_MMX_SET 0x00008000 129261991Sdim#define MASK_SSE 0x00010000 /* Support SSE regs/builtins */ 130261991Sdim#define MASK_SSE_SET 0x00020000 131276479Sdim#define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */ 132261991Sdim#define MASK_SSE2_SET 0x00080000 133261991Sdim#define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */ 134261991Sdim#define MASK_3DNOW_SET 0x00200000 135261991Sdim#define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */ 136261991Sdim#define MASK_3DNOW_A_SET 0x00800000 137261991Sdim#define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */ 138261991Sdim#define MASK_64BIT 0x02000000 /* Produce 64bit code */ 139261991Sdim/* ... overlap with subtarget options starts by 0x04000000. */ 140261991Sdim#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ 141288943Sdim 142261991Sdim/* Use the floating point instructions */ 143261991Sdim#define TARGET_80387 (target_flags & MASK_80387) 144261991Sdim 145261991Sdim/* Compile using ret insn that pops args. 146261991Sdim This will not work unless you use prototypes at least 147261991Sdim for all functions that can take varying numbers of args. */ 148261991Sdim#define TARGET_RTD (target_flags & MASK_RTD) 149261991Sdim 150261991Sdim/* Align doubles to a two word boundary. This breaks compatibility with 151261991Sdim the published ABI's for structures containing doubles, but produces 152261991Sdim faster code on the pentium. */ 153261991Sdim#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) 154261991Sdim 155276479Sdim/* Use push instructions to save outgoing args. */ 156276479Sdim#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) 157261991Sdim 158261991Sdim/* Accumulate stack adjustments to prologue/epilogue. */ 159251607Sdim#define TARGET_ACCUMULATE_OUTGOING_ARGS \ 160251607Sdim (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) 161261991Sdim 162261991Sdim/* Put uninitialized locals into bss, not data. 163276479Sdim Meaningful only on svr3. */ 164276479Sdim#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) 165276479Sdim 166261991Sdim/* Use IEEE floating point comparisons. These handle correctly the cases 167261991Sdim where the result of a comparison is unordered. Normally SIGFPE is 168261991Sdim generated in such cases, in which case this isn't needed. */ 169261991Sdim#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) 170261991Sdim 171261991Sdim/* Functions that return a floating point value may return that value 172261991Sdim in the 387 FPU or in 386 integer registers. If set, this flag causes 173261991Sdim the 387 to be used, which is compatible with most calling conventions. */ 174261991Sdim#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) 175251607Sdim 176251607Sdim/* Long double is 128bit instead of 96bit, even when only 80bits are used. 177251607Sdim This mode wastes cache, but avoid misaligned data accesses and simplifies 178251607Sdim address calculations. */ 179251607Sdim#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) 180251607Sdim 181251607Sdim/* Disable generation of FP sin, cos and sqrt operations for 387. 182251607Sdim This is because FreeBSD lacks these in the math-emulator-code */ 183251607Sdim#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) 184251607Sdim 185251607Sdim/* Don't create frame pointers for leaf functions */ 186251607Sdim#define TARGET_OMIT_LEAF_FRAME_POINTER \ 187261991Sdim (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) 188251607Sdim 189251607Sdim/* Debug GO_IF_LEGITIMATE_ADDRESS */ 190251607Sdim#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) 191251607Sdim 192251607Sdim/* Debug FUNCTION_ARG macros */ 193276479Sdim#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) 194261991Sdim 195261991Sdim/* 64bit Sledgehammer mode */ 196261991Sdim#ifdef TARGET_BI_ARCH 197251607Sdim#define TARGET_64BIT (target_flags & MASK_64BIT) 198251607Sdim#else 199276479Sdim#ifdef TARGET_64BIT_DEFAULT 200276479Sdim#define TARGET_64BIT 1 201251607Sdim#else 202251607Sdim#define TARGET_64BIT 0 203251607Sdim#endif 204251607Sdim#endif 205276479Sdim 206251607Sdim#define TARGET_386 (ix86_cpu == PROCESSOR_I386) 207251607Sdim#define TARGET_486 (ix86_cpu == PROCESSOR_I486) 208251607Sdim#define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) 209251607Sdim#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) 210251607Sdim#define TARGET_K6 (ix86_cpu == PROCESSOR_K6) 211251607Sdim#define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) 212288943Sdim#define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4) 213251607Sdim 214251607Sdim#define CPUMASK (1 << ix86_cpu) 215251607Sdimextern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 216288943Sdimextern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 217288943Sdimextern const int x86_branch_hints, x86_unroll_strlen; 218251607Sdimextern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 219251607Sdimextern const int x86_use_loop, x86_use_fiop, x86_use_mov0; 220251607Sdimextern const int x86_use_cltd, x86_read_modify_write; 221251607Sdimextern const int x86_read_modify, x86_split_long_moves; 222251607Sdimextern const int x86_promote_QImode, x86_single_stringop; 223251607Sdimextern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 224251607Sdimextern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 225251607Sdimextern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 226251607Sdimextern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 227251607Sdimextern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 228251607Sdimextern const int x86_epilogue_using_move, x86_decompose_lea; 229251607Sdimextern int x86_prefetch_sse; 230251607Sdim 231251607Sdim#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) 232251607Sdim#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) 233251607Sdim#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) 234251607Sdim#define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) 235251607Sdim#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) 236251607Sdim/* For sane SSE instruction set generation we need fcomi instruction. It is 237251607Sdim safe to enable all CMOVE instructions. */ 238251607Sdim#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 239251607Sdim#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) 240251607Sdim#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK) 241251607Sdim#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) 242#define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT) 243#define TARGET_MOVX (x86_movx & CPUMASK) 244#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) 245#define TARGET_USE_LOOP (x86_use_loop & CPUMASK) 246#define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) 247#define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) 248#define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) 249#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) 250#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) 251#define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) 252#define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) 253#define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) 254#define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) 255#define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) 256#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) 257#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) 258#define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK) 259#define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK) 260#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK) 261#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK) 262#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK) 263#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK) 264#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK) 265#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK) 266#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK) 267#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK) 268#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 269 270#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) 271 272#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) 273#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) 274 275#define ASSEMBLER_DIALECT (ix86_asm_dialect) 276 277#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0) 278#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) 279#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 280#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 281 && (ix86_fpmath & FPMATH_387)) 282#define TARGET_MMX ((target_flags & MASK_MMX) != 0) 283#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) 284#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) 285 286#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) 287 288#define TARGET_SWITCHES \ 289{ { "80387", MASK_80387, N_("Use hardware fp") }, \ 290 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ 291 { "hard-float", MASK_80387, N_("Use hardware fp") }, \ 292 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ 293 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ 294 { "386", 0, N_("") /*Deprecated.*/}, \ 295 { "486", 0, N_("") /*Deprecated.*/}, \ 296 { "pentium", 0, N_("") /*Deprecated.*/}, \ 297 { "pentiumpro", 0, N_("") /*Deprecated.*/}, \ 298 { "intel-syntax", 0, N_("") /*Deprecated.*/}, \ 299 { "no-intel-syntax", 0, N_("") /*Deprecated.*/}, \ 300 { "rtd", MASK_RTD, \ 301 N_("Alternate calling convention") }, \ 302 { "no-rtd", -MASK_RTD, \ 303 N_("Use normal calling convention") }, \ 304 { "align-double", MASK_ALIGN_DOUBLE, \ 305 N_("Align some doubles on dword boundary") }, \ 306 { "no-align-double", -MASK_ALIGN_DOUBLE, \ 307 N_("Align doubles on word boundary") }, \ 308 { "svr3-shlib", MASK_SVR3_SHLIB, \ 309 N_("Uninitialized locals in .bss") }, \ 310 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ 311 N_("Uninitialized locals in .data") }, \ 312 { "ieee-fp", MASK_IEEE_FP, \ 313 N_("Use IEEE math for fp comparisons") }, \ 314 { "no-ieee-fp", -MASK_IEEE_FP, \ 315 N_("Do not use IEEE math for fp comparisons") }, \ 316 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ 317 N_("Return values of functions in FPU registers") }, \ 318 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ 319 N_("Do not return values of functions in FPU registers")}, \ 320 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ 321 N_("Do not generate sin, cos, sqrt for FPU") }, \ 322 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ 323 N_("Generate sin, cos, sqrt for FPU")}, \ 324 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ 325 N_("Omit the frame pointer in leaf functions") }, \ 326 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ 327 { "stack-arg-probe", MASK_STACK_PROBE, \ 328 N_("Enable stack probing") }, \ 329 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ 330 { "windows", 0, 0 /* undocumented */ }, \ 331 { "dll", 0, 0 /* undocumented */ }, \ 332 { "align-stringops", -MASK_NO_ALIGN_STROPS, \ 333 N_("Align destination of the string operations") }, \ 334 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ 335 N_("Do not align destination of the string operations") }, \ 336 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ 337 N_("Inline all known string operations") }, \ 338 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ 339 N_("Do not inline all known string operations") }, \ 340 { "push-args", -MASK_NO_PUSH_ARGS, \ 341 N_("Use push instructions to save outgoing arguments") }, \ 342 { "no-push-args", MASK_NO_PUSH_ARGS, \ 343 N_("Do not use push instructions to save outgoing arguments") }, \ 344 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \ 345 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \ 346 N_("Use push instructions to save outgoing arguments") }, \ 347 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \ 348 N_("Do not use push instructions to save outgoing arguments") }, \ 349 { "mmx", MASK_MMX | MASK_MMX_SET, \ 350 N_("Support MMX built-in functions") }, \ 351 { "no-mmx", -MASK_MMX, \ 352 N_("Do not support MMX built-in functions") }, \ 353 { "no-mmx", MASK_MMX_SET, N_("") }, \ 354 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \ 355 N_("Support 3DNow! built-in functions") }, \ 356 { "no-3dnow", -MASK_3DNOW, N_("") }, \ 357 { "no-3dnow", MASK_3DNOW_SET, \ 358 N_("Do not support 3DNow! built-in functions") }, \ 359 { "sse", MASK_SSE | MASK_SSE_SET, \ 360 N_("Support MMX and SSE built-in functions and code generation") }, \ 361 { "no-sse", -MASK_SSE, N_("") }, \ 362 { "no-sse", MASK_SSE_SET, \ 363 N_("Do not support MMX and SSE built-in functions and code generation") },\ 364 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \ 365 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ 366 { "no-sse2", -MASK_SSE2, N_("") }, \ 367 { "no-sse2", MASK_SSE2_SET, \ 368 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ 369 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ 370 N_("sizeof(long double) is 16") }, \ 371 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ 372 N_("sizeof(long double) is 12") }, \ 373 { "64", MASK_64BIT, \ 374 N_("Generate 64bit x86-64 code") }, \ 375 { "32", -MASK_64BIT, \ 376 N_("Generate 32bit i386 code") }, \ 377 { "red-zone", -MASK_NO_RED_ZONE, \ 378 N_("Use red-zone in the x86-64 code") }, \ 379 { "no-red-zone", MASK_NO_RED_ZONE, \ 380 N_("Do not use red-zone in the x86-64 code") }, \ 381 SUBTARGET_SWITCHES \ 382 { "", TARGET_DEFAULT, 0 }} 383 384#ifdef TARGET_64BIT_DEFAULT 385#define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT) 386#else 387#define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT 388#endif 389 390/* Which processor to schedule for. The cpu attribute defines a list that 391 mirrors this list, so changes to i386.md must be made at the same time. */ 392 393enum processor_type 394{ 395 PROCESSOR_I386, /* 80386 */ 396 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 397 PROCESSOR_PENTIUM, 398 PROCESSOR_PENTIUMPRO, 399 PROCESSOR_K6, 400 PROCESSOR_ATHLON, 401 PROCESSOR_PENTIUM4, 402 PROCESSOR_max 403}; 404enum fpmath_unit 405{ 406 FPMATH_387 = 1, 407 FPMATH_SSE = 2 408}; 409 410extern enum processor_type ix86_cpu; 411extern enum fpmath_unit ix86_fpmath; 412 413extern int ix86_arch; 414 415/* This macro is similar to `TARGET_SWITCHES' but defines names of 416 command options that have values. Its definition is an 417 initializer with a subgrouping for each command option. 418 419 Each subgrouping contains a string constant, that defines the 420 fixed part of the option name, and the address of a variable. The 421 variable, type `char *', is set to the variable part of the given 422 option if the fixed part matches. The actual option name is made 423 by appending `-m' to the specified name. */ 424#define TARGET_OPTIONS \ 425{ { "cpu=", &ix86_cpu_string, \ 426 N_("Schedule code for given CPU")}, \ 427 { "fpmath=", &ix86_fpmath_string, \ 428 N_("Generate floating point mathematics using given instruction set")},\ 429 { "arch=", &ix86_arch_string, \ 430 N_("Generate code for given CPU")}, \ 431 { "regparm=", &ix86_regparm_string, \ 432 N_("Number of registers used to pass integer arguments") }, \ 433 { "align-loops=", &ix86_align_loops_string, \ 434 N_("Loop code aligned to this power of 2") }, \ 435 { "align-jumps=", &ix86_align_jumps_string, \ 436 N_("Jump targets are aligned to this power of 2") }, \ 437 { "align-functions=", &ix86_align_funcs_string, \ 438 N_("Function starts are aligned to this power of 2") }, \ 439 { "preferred-stack-boundary=", \ 440 &ix86_preferred_stack_boundary_string, \ 441 N_("Attempt to keep stack aligned to this power of 2") }, \ 442 { "branch-cost=", &ix86_branch_cost_string, \ 443 N_("Branches are this expensive (1-5, arbitrary units)") }, \ 444 { "cmodel=", &ix86_cmodel_string, \ 445 N_("Use given x86-64 code model") }, \ 446 { "debug-arg", &ix86_debug_arg_string, \ 447 N_("" /* Undocumented. */) }, \ 448 { "debug-addr", &ix86_debug_addr_string, \ 449 N_("" /* Undocumented. */) }, \ 450 { "asm=", &ix86_asm_string, \ 451 N_("Use given assembler dialect") }, \ 452 SUBTARGET_OPTIONS \ 453} 454 455/* Sometimes certain combinations of command options do not make 456 sense on a particular target machine. You can define a macro 457 `OVERRIDE_OPTIONS' to take account of this. This macro, if 458 defined, is executed once just after all the command options have 459 been parsed. 460 461 Don't use this macro to turn on various extra optimizations for 462 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 463 464#define OVERRIDE_OPTIONS override_options () 465 466/* These are meant to be redefined in the host dependent files */ 467#define SUBTARGET_SWITCHES 468#define SUBTARGET_OPTIONS 469 470/* Define this to change the optimizations performed by default. */ 471#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 472 optimization_options ((LEVEL), (SIZE)) 473 474/* Specs for the compiler proper */ 475 476#ifndef CC1_CPU_SPEC 477#define CC1_CPU_SPEC "\ 478%{!mcpu*: \ 479%{m386:-mcpu=i386 \ 480%n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \ 481%{m486:-mcpu=i486 \ 482%n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \ 483%{mpentium:-mcpu=pentium \ 484%n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \ 485%{mpentiumpro:-mcpu=pentiumpro \ 486%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \ 487%{mintel-syntax:-masm=intel \ 488%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 489%{mno-intel-syntax:-masm=att \ 490%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 491#endif 492 493#define TARGET_CPU_DEFAULT_i386 0 494#define TARGET_CPU_DEFAULT_i486 1 495#define TARGET_CPU_DEFAULT_pentium 2 496#define TARGET_CPU_DEFAULT_pentium_mmx 3 497#define TARGET_CPU_DEFAULT_pentiumpro 4 498#define TARGET_CPU_DEFAULT_pentium2 5 499#define TARGET_CPU_DEFAULT_pentium3 6 500#define TARGET_CPU_DEFAULT_pentium4 7 501#define TARGET_CPU_DEFAULT_k6 8 502#define TARGET_CPU_DEFAULT_k6_2 9 503#define TARGET_CPU_DEFAULT_k6_3 10 504#define TARGET_CPU_DEFAULT_athlon 11 505#define TARGET_CPU_DEFAULT_athlon_sse 12 506 507#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 508 "pentiumpro", "pentium2", "pentium3", \ 509 "pentium4", "k6", "k6-2", "k6-3",\ 510 "athlon", "athlon-4"} 511#ifndef CPP_CPU_DEFAULT_SPEC 512#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486 513#define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__" 514#endif 515#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium 516#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__" 517#endif 518#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx 519#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__" 520#endif 521#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro 522#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__" 523#endif 524#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2 525#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 526-D__tune_pentium2__" 527#endif 528#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3 529#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 530-D__tune_pentium2__ -D__tune_pentium3__" 531#endif 532#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4 533#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__" 534#endif 535#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6 536#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__" 537#endif 538#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2 539#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__" 540#endif 541#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3 542#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__" 543#endif 544#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon 545#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__" 546#endif 547#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse 548#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__" 549#endif 550#ifndef CPP_CPU_DEFAULT_SPEC 551#define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__" 552#endif 553#endif /* CPP_CPU_DEFAULT_SPEC */ 554 555#ifdef TARGET_BI_ARCH 556#define NO_BUILTIN_SIZE_TYPE 557#define NO_BUILTIN_PTRDIFF_TYPE 558#endif 559 560#ifdef NO_BUILTIN_SIZE_TYPE 561#define CPP_CPU32_SIZE_TYPE_SPEC \ 562 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int" 563#define CPP_CPU64_SIZE_TYPE_SPEC \ 564 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int" 565#else 566#define CPP_CPU32_SIZE_TYPE_SPEC "" 567#define CPP_CPU64_SIZE_TYPE_SPEC "" 568#endif 569 570#define CPP_CPU32_SPEC \ 571 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \ 572-D__i386__ %(cpp_cpu32sizet)" 573 574#define CPP_CPU64_SPEC \ 575 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)" 576 577#define CPP_CPUCOMMON_SPEC "\ 578%{march=i386:%{!mcpu*:-D__tune_i386__ }}\ 579%{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\ 580%{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 581 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\ 582%{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 583 -D__pentium__mmx__ \ 584 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\ 585%{march=pentiumpro|march=i686:-D__i686 -D__i686__ \ 586 -D__pentiumpro -D__pentiumpro__ \ 587 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\ 588%{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\ 589%{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \ 590 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\ 591%{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \ 592 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\ 593%{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \ 594 %{!mcpu*:-D__tune_athlon__ }}\ 595%{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \ 596 -D__athlon_sse__ \ 597 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\ 598%{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\ 599%{m386|mcpu=i386:-D__tune_i386__ }\ 600%{m486|mcpu=i486:-D__tune_i486__ }\ 601%{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\ 602%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \ 603-D__tune_pentiumpro__ }\ 604%{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\ 605%{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 606-D__tune_athlon__ }\ 607%{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 608-D__tune_athlon_sse__ }\ 609%{mcpu=pentium4:-D__tune_pentium4__ }\ 610%{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\ 611-D__SSE__ }\ 612%{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\ 613march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 614|march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\ 615%{march=k6-2|march=k6-3\ 616march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 617|march=athlon-mp: -D__3dNOW__ }\ 618%{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 619|march=athlon-mp: -D__3dNOW_A__ }\ 620%{march=pentium4: -D__SSE2__ }\ 621%{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}" 622 623#ifndef CPP_CPU_SPEC 624#ifdef TARGET_BI_ARCH 625#ifdef TARGET_64BIT_DEFAULT 626#define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)" 627#else 628#define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)" 629#endif 630#else 631#ifdef TARGET_64BIT_DEFAULT 632#define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)" 633#else 634#define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)" 635#endif 636#endif 637#endif 638 639#ifndef CC1_SPEC 640#define CC1_SPEC "%(cc1_cpu) " 641#endif 642 643/* This macro defines names of additional specifications to put in the 644 specs that can be used in various specifications like CC1_SPEC. Its 645 definition is an initializer with a subgrouping for each command option. 646 647 Each subgrouping contains a string constant, that defines the 648 specification name, and a string constant that used by the GNU CC driver 649 program. 650 651 Do not define this macro if it does not need to do anything. */ 652 653#ifndef SUBTARGET_EXTRA_SPECS 654#define SUBTARGET_EXTRA_SPECS 655#endif 656 657#define EXTRA_SPECS \ 658 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 659 { "cpp_cpu", CPP_CPU_SPEC }, \ 660 { "cpp_cpu32", CPP_CPU32_SPEC }, \ 661 { "cpp_cpu64", CPP_CPU64_SPEC }, \ 662 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \ 663 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \ 664 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \ 665 { "cc1_cpu", CC1_CPU_SPEC }, \ 666 SUBTARGET_EXTRA_SPECS 667 668/* target machine storage layout */ 669 670/* Define for XFmode or TFmode extended real floating point support. 671 This will automatically cause REAL_ARITHMETIC to be defined. 672 673 The XFmode is specified by i386 ABI, while TFmode may be faster 674 due to alignment and simplifications in the address calculations. 675 */ 676#define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96) 677#define MAX_LONG_DOUBLE_TYPE_SIZE 128 678#ifdef __x86_64__ 679#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 680#else 681#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 682#endif 683/* Tell real.c that this is the 80-bit Intel extended float format 684 packaged in a 128-bit or 96bit entity. */ 685#define INTEL_EXTENDED_IEEE_FORMAT 1 686 687 688#define SHORT_TYPE_SIZE 16 689#define INT_TYPE_SIZE 32 690#define FLOAT_TYPE_SIZE 32 691#define LONG_TYPE_SIZE BITS_PER_WORD 692#define MAX_WCHAR_TYPE_SIZE 32 693#define DOUBLE_TYPE_SIZE 64 694#define LONG_LONG_TYPE_SIZE 64 695 696#if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT) 697#define MAX_BITS_PER_WORD 64 698#define MAX_LONG_TYPE_SIZE 64 699#else 700#define MAX_BITS_PER_WORD 32 701#define MAX_LONG_TYPE_SIZE 32 702#endif 703 704/* Define if you don't want extended real, but do want to use the 705 software floating point emulator for REAL_ARITHMETIC and 706 decimal <-> binary conversion. */ 707/* #define REAL_ARITHMETIC */ 708 709/* Define this if most significant byte of a word is the lowest numbered. */ 710/* That is true on the 80386. */ 711 712#define BITS_BIG_ENDIAN 0 713 714/* Define this if most significant byte of a word is the lowest numbered. */ 715/* That is not true on the 80386. */ 716#define BYTES_BIG_ENDIAN 0 717 718/* Define this if most significant word of a multiword number is the lowest 719 numbered. */ 720/* Not true for 80386 */ 721#define WORDS_BIG_ENDIAN 0 722 723/* number of bits in an addressable storage unit */ 724#define BITS_PER_UNIT 8 725 726/* Width in bits of a "word", which is the contents of a machine register. 727 Note that this is not necessarily the width of data type `int'; 728 if using 16-bit ints on a 80386, this would still be 32. 729 But on a machine with 16-bit registers, this would be 16. */ 730#define BITS_PER_WORD (TARGET_64BIT ? 64 : 32) 731 732/* Width of a word, in units (bytes). */ 733#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 734#define MIN_UNITS_PER_WORD 4 735 736/* Width in bits of a pointer. 737 See also the macro `Pmode' defined below. */ 738#define POINTER_SIZE BITS_PER_WORD 739 740/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 741#define PARM_BOUNDARY BITS_PER_WORD 742 743/* Boundary (in *bits*) on which stack pointer should be aligned. */ 744#define STACK_BOUNDARY BITS_PER_WORD 745 746/* Boundary (in *bits*) on which the stack pointer preferrs to be 747 aligned; the compiler cannot rely on having this alignment. */ 748#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 749 750/* As of July 2001, many runtimes to not align the stack properly when 751 entering main. This causes expand_main_function to forcably align 752 the stack, which results in aligned frames for functions called from 753 main, though it does nothing for the alignment of main itself. */ 754#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 755 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 756 757/* Allocation boundary for the code of a function. */ 758#define FUNCTION_BOUNDARY 16 759 760/* Alignment of field after `int : 0' in a structure. */ 761 762#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 763 764/* Minimum size in bits of the largest boundary to which any 765 and all fundamental data types supported by the hardware 766 might need to be aligned. No data type wants to be aligned 767 rounder than this. 768 769 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary 770 and Pentium Pro XFmode values at 128 bit boundaries. */ 771 772#define BIGGEST_ALIGNMENT 128 773 774/* Decide whether a variable of mode MODE must be 128 bit aligned. */ 775#define ALIGN_MODE_128(MODE) \ 776 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \ 777 || (MODE) == V4SFmode || (MODE) == V4SImode) 778 779/* The published ABIs say that doubles should be aligned on word 780 boundaries, so lower the aligment for structure fields unless 781 -malign-double is set. */ 782/* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be 783 constant. Use the smaller value in that context. */ 784#ifndef IN_TARGET_LIBS 785#define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32)) 786#else 787#define BIGGEST_FIELD_ALIGNMENT 32 788#endif 789 790/* If defined, a C expression to compute the alignment given to a 791 constant that is being placed in memory. EXP is the constant 792 and ALIGN is the alignment that the object would ordinarily have. 793 The value of this macro is used instead of that alignment to align 794 the object. 795 796 If this macro is not defined, then ALIGN is used. 797 798 The typical use of this macro is to increase alignment for string 799 constants to be word aligned so that `strcpy' calls that copy 800 constants can be done inline. */ 801 802#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 803 804/* If defined, a C expression to compute the alignment for a static 805 variable. TYPE is the data type, and ALIGN is the alignment that 806 the object would ordinarily have. The value of this macro is used 807 instead of that alignment to align the object. 808 809 If this macro is not defined, then ALIGN is used. 810 811 One use of this macro is to increase alignment of medium-size 812 data to make it all fit in fewer cache lines. Another is to 813 cause character arrays to be word-aligned so that `strcpy' calls 814 that copy constants to character arrays can be done inline. */ 815 816#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 817 818/* If defined, a C expression to compute the alignment for a local 819 variable. TYPE is the data type, and ALIGN is the alignment that 820 the object would ordinarily have. The value of this macro is used 821 instead of that alignment to align the object. 822 823 If this macro is not defined, then ALIGN is used. 824 825 One use of this macro is to increase alignment of medium-size 826 data to make it all fit in fewer cache lines. */ 827 828#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 829 830/* If defined, a C expression that gives the alignment boundary, in 831 bits, of an argument with the specified mode and type. If it is 832 not defined, `PARM_BOUNDARY' is used for all arguments. */ 833 834#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 835 ix86_function_arg_boundary ((MODE), (TYPE)) 836 837/* Set this non-zero if move instructions will actually fail to work 838 when given unaligned data. */ 839#define STRICT_ALIGNMENT 0 840 841/* If bit field type is int, don't let it cross an int, 842 and give entire struct the alignment of an int. */ 843/* Required on the 386 since it doesn't have bitfield insns. */ 844#define PCC_BITFIELD_TYPE_MATTERS 1 845 846/* Standard register usage. */ 847 848/* This processor has special stack-like registers. See reg-stack.c 849 for details. */ 850 851#define STACK_REGS 852#define IS_STACK_MODE(MODE) \ 853 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ 854 || (MODE) == TFmode) 855 856/* Number of actual hardware registers. 857 The hardware registers are assigned numbers for the compiler 858 from 0 to just below FIRST_PSEUDO_REGISTER. 859 All registers that the compiler knows about must be given numbers, 860 even those that are not normally considered general registers. 861 862 In the 80386 we give the 8 general purpose registers the numbers 0-7. 863 We number the floating point registers 8-15. 864 Note that registers 0-7 can be accessed as a short or int, 865 while only 0-3 may be used with byte `mov' instructions. 866 867 Reg 16 does not correspond to any hardware register, but instead 868 appears in the RTL as an argument pointer prior to reload, and is 869 eliminated during reloading in favor of either the stack or frame 870 pointer. */ 871 872#define FIRST_PSEUDO_REGISTER 53 873 874/* Number of hardware registers that go into the DWARF-2 unwind info. 875 If not defined, equals FIRST_PSEUDO_REGISTER. */ 876 877#define DWARF_FRAME_REGISTERS 17 878 879/* 1 for registers that have pervasive standard uses 880 and are not available for the register allocator. 881 On the 80386, the stack pointer is such, as is the arg pointer. 882 883 The value is an mask - bit 1 is set for fixed registers 884 for 32bit target, while 2 is set for fixed registers for 64bit. 885 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 886 */ 887#define FIXED_REGISTERS \ 888/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 889{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ 890/*arg,flags,fpsr,dir,frame*/ \ 891 3, 3, 3, 3, 3, \ 892/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 893 0, 0, 0, 0, 0, 0, 0, 0, \ 894/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 895 0, 0, 0, 0, 0, 0, 0, 0, \ 896/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 897 1, 1, 1, 1, 1, 1, 1, 1, \ 898/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 899 1, 1, 1, 1, 1, 1, 1, 1} 900 901 902/* 1 for registers not available across function calls. 903 These must include the FIXED_REGISTERS and also any 904 registers that can be used without being saved. 905 The latter must include the registers where values are returned 906 and the register where structure-value addresses are passed. 907 Aside from that, you can include as many other registers as you like. 908 909 The value is an mask - bit 1 is set for call used 910 for 32bit target, while 2 is set for call used for 64bit. 911 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 912*/ 913#define CALL_USED_REGISTERS \ 914/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 915{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 916/*arg,flags,fpsr,dir,frame*/ \ 917 3, 3, 3, 3, 3, \ 918/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 919 3, 3, 3, 3, 3, 3, 3, 3, \ 920/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 921 3, 3, 3, 3, 3, 3, 3, 3, \ 922/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 923 3, 3, 3, 3, 1, 1, 1, 1, \ 924/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 925 3, 3, 3, 3, 3, 3, 3, 3} \ 926 927/* Order in which to allocate registers. Each register must be 928 listed once, even those in FIXED_REGISTERS. List frame pointer 929 late and fixed registers last. Note that, in general, we prefer 930 registers listed in CALL_USED_REGISTERS, keeping the others 931 available for storage of persistent values. 932 933 Three different versions of REG_ALLOC_ORDER have been tried: 934 935 If the order is edx, ecx, eax, ... it produces a slightly faster compiler, 936 but slower code on simple functions returning values in eax. 937 938 If the order is eax, ecx, edx, ... it causes reload to abort when compiling 939 perl 4.036 due to not being able to create a DImode register (to hold a 2 940 word union). 941 942 If the order is eax, edx, ecx, ... it produces better code for simple 943 functions, and a slightly slower compiler. Users complained about the code 944 generated by allocating edx first, so restore the 'natural' order of things. */ 945 946#define REG_ALLOC_ORDER \ 947/*ax,dx,cx,*/ \ 948{ 0, 1, 2, \ 949/* bx,si,di,bp,sp,*/ \ 950 3, 4, 5, 6, 7, \ 951/*r8,r9,r10,r11,*/ \ 952 37,38, 39, 40, \ 953/*r12,r15,r14,r13*/ \ 954 41, 44, 43, 42, \ 955/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 956 21, 22, 23, 24, 25, 26, 27, 28, \ 957/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 958 45, 46, 47, 48, 49, 50, 51, 52, \ 959/*st,st1,st2,st3,st4,st5,st6,st7*/ \ 960 8, 9, 10, 11, 12, 13, 14, 15, \ 961/*,arg,cc,fpsr,dir,frame*/ \ 962 16,17, 18, 19, 20, \ 963/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 964 29, 30, 31, 32, 33, 34, 35, 36 } 965 966/* Macro to conditionally modify fixed_regs/call_used_regs. */ 967#define CONDITIONAL_REGISTER_USAGE \ 968do { \ 969 int i; \ 970 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 971 { \ 972 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ 973 call_used_regs[i] = (call_used_regs[i] \ 974 & (TARGET_64BIT ? 2 : 1)) != 0; \ 975 } \ 976 if (flag_pic) \ 977 { \ 978 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 979 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 980 } \ 981 if (! TARGET_MMX) \ 982 { \ 983 int i; \ 984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 985 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 986 fixed_regs[i] = call_used_regs[i] = 1; \ 987 } \ 988 if (! TARGET_SSE) \ 989 { \ 990 int i; \ 991 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 992 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 993 fixed_regs[i] = call_used_regs[i] = 1; \ 994 } \ 995 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 996 { \ 997 int i; \ 998 HARD_REG_SET x; \ 999 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 1000 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1001 if (TEST_HARD_REG_BIT (x, i)) \ 1002 fixed_regs[i] = call_used_regs[i] = 1; \ 1003 } \ 1004 } while (0) 1005 1006/* Return number of consecutive hard regs needed starting at reg REGNO 1007 to hold something of mode MODE. 1008 This is ordinarily the length in words of a value of mode MODE 1009 but can be less for certain modes in special long registers. 1010 1011 Actually there are no two word move instructions for consecutive 1012 registers. And only registers 0-3 may have mov byte instructions 1013 applied to them. 1014 */ 1015 1016#define HARD_REGNO_NREGS(REGNO, MODE) \ 1017 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1018 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1019 : ((MODE) == TFmode \ 1020 ? (TARGET_64BIT ? 2 : 3) \ 1021 : (MODE) == TCmode \ 1022 ? (TARGET_64BIT ? 4 : 6) \ 1023 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1024 1025#define VALID_SSE_REG_MODE(MODE) \ 1026 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1027 || (MODE) == SFmode \ 1028 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) 1029 1030#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1031 ((MODE) == V2SFmode || (MODE) == SFmode) 1032 1033#define VALID_MMX_REG_MODE(MODE) \ 1034 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 1035 || (MODE) == V2SImode || (MODE) == SImode) 1036 1037#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1038 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ 1039 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ 1040 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) 1041 1042#define VALID_FP_MODE_P(MODE) \ 1043 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 1044 || (!TARGET_64BIT && (MODE) == XFmode) \ 1045 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \ 1046 || (!TARGET_64BIT && (MODE) == XCmode)) 1047 1048#define VALID_INT_MODE_P(MODE) \ 1049 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1050 || (MODE) == DImode \ 1051 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1052 || (MODE) == CDImode \ 1053 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) 1054 1055/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1056 1057#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1058 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1059 1060/* Value is 1 if it is a good idea to tie two pseudo registers 1061 when one has mode MODE1 and one has mode MODE2. 1062 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1063 for any hard reg, then this must be 0 for correct output. */ 1064 1065#define MODES_TIEABLE_P(MODE1, MODE2) \ 1066 ((MODE1) == (MODE2) \ 1067 || (((MODE1) == HImode || (MODE1) == SImode \ 1068 || ((MODE1) == QImode \ 1069 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1070 || ((MODE1) == DImode && TARGET_64BIT)) \ 1071 && ((MODE2) == HImode || (MODE2) == SImode \ 1072 || ((MODE1) == QImode \ 1073 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1074 || ((MODE2) == DImode && TARGET_64BIT)))) 1075 1076 1077/* Specify the modes required to caller save a given hard regno. 1078 We do this on i386 to prevent flags from being saved at all. 1079 1080 Kill any attempts to combine saving of modes. */ 1081 1082#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1083 (CC_REGNO_P (REGNO) ? VOIDmode \ 1084 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1085 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \ 1086 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1087 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 1088 : (MODE)) 1089/* Specify the registers used for certain standard purposes. 1090 The values of these macros are register numbers. */ 1091 1092/* on the 386 the pc register is %eip, and is not usable as a general 1093 register. The ordinary mov instructions won't work */ 1094/* #define PC_REGNUM */ 1095 1096/* Register to use for pushing function arguments. */ 1097#define STACK_POINTER_REGNUM 7 1098 1099/* Base register for access to local variables of the function. */ 1100#define HARD_FRAME_POINTER_REGNUM 6 1101 1102/* Base register for access to local variables of the function. */ 1103#define FRAME_POINTER_REGNUM 20 1104 1105/* First floating point reg */ 1106#define FIRST_FLOAT_REG 8 1107 1108/* First & last stack-like regs */ 1109#define FIRST_STACK_REG FIRST_FLOAT_REG 1110#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1111 1112#define FLAGS_REG 17 1113#define FPSR_REG 18 1114#define DIRFLAG_REG 19 1115 1116#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1117#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1118 1119#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1120#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1121 1122#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1123#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1124 1125#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1126#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1127 1128/* Value should be nonzero if functions must have frame pointers. 1129 Zero means the frame pointer need not be set up (and parms 1130 may be accessed via the stack pointer) in functions that seem suitable. 1131 This is computed in `reload', in reload1.c. */ 1132#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1133 1134/* Override this in other tm.h files to cope with various OS losage 1135 requiring a frame pointer. */ 1136#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1137#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1138#endif 1139 1140/* Make sure we can access arbitrary call frames. */ 1141#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1142 1143/* Base register for access to arguments of the function. */ 1144#define ARG_POINTER_REGNUM 16 1145 1146/* Register in which static-chain is passed to a function. 1147 We do use ECX as static chain register for 32 bit ABI. On the 1148 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1149#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1150 1151/* Register to hold the addressing base for position independent 1152 code access to data items. 1153 We don't use PIC pointer for 64bit mode. Define the regnum to 1154 dummy value to prevent gcc from pessimizing code dealing with EBX. 1155 */ 1156#define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3) 1157 1158/* Register in which address to store a structure value 1159 arrives in the function. On the 386, the prologue 1160 copies this from the stack to register %eax. */ 1161#define STRUCT_VALUE_INCOMING 0 1162 1163/* Place in which caller passes the structure value address. 1164 0 means push the value on the stack like an argument. */ 1165#define STRUCT_VALUE 0 1166 1167/* A C expression which can inhibit the returning of certain function 1168 values in registers, based on the type of value. A nonzero value 1169 says to return the function value in memory, just as large 1170 structures are always returned. Here TYPE will be a C expression 1171 of type `tree', representing the data type of the value. 1172 1173 Note that values of mode `BLKmode' must be explicitly handled by 1174 this macro. Also, the option `-fpcc-struct-return' takes effect 1175 regardless of this macro. On most systems, it is possible to 1176 leave the macro undefined; this causes a default definition to be 1177 used, whose value is the constant 1 for `BLKmode' values, and 0 1178 otherwise. 1179 1180 Do not use this macro to indicate that structures and unions 1181 should always be returned in memory. You should instead use 1182 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1183 1184#define RETURN_IN_MEMORY(TYPE) \ 1185 ix86_return_in_memory (TYPE) 1186 1187 1188/* Define the classes of registers for register constraints in the 1189 machine description. Also define ranges of constants. 1190 1191 One of the classes must always be named ALL_REGS and include all hard regs. 1192 If there is more than one class, another class must be named NO_REGS 1193 and contain no registers. 1194 1195 The name GENERAL_REGS must be the name of a class (or an alias for 1196 another name such as ALL_REGS). This is the class of registers 1197 that is allowed by "g" or "r" in a register constraint. 1198 Also, registers outside this class are allocated only when 1199 instructions express preferences for them. 1200 1201 The classes must be numbered in nondecreasing order; that is, 1202 a larger-numbered class must never be contained completely 1203 in a smaller-numbered class. 1204 1205 For any two classes, it is very desirable that there be another 1206 class that represents their union. 1207 1208 It might seem that class BREG is unnecessary, since no useful 386 1209 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1210 and the "b" register constraint is useful in asms for syscalls. 1211 1212 The flags and fpsr registers are in no class. */ 1213 1214enum reg_class 1215{ 1216 NO_REGS, 1217 AREG, DREG, CREG, BREG, SIREG, DIREG, 1218 AD_REGS, /* %eax/%edx for DImode */ 1219 Q_REGS, /* %eax %ebx %ecx %edx */ 1220 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1221 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1222 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1223 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1224 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1225 FLOAT_REGS, 1226 SSE_REGS, 1227 MMX_REGS, 1228 FP_TOP_SSE_REGS, 1229 FP_SECOND_SSE_REGS, 1230 FLOAT_SSE_REGS, 1231 FLOAT_INT_REGS, 1232 INT_SSE_REGS, 1233 FLOAT_INT_SSE_REGS, 1234 ALL_REGS, LIM_REG_CLASSES 1235}; 1236 1237#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1238 1239#define INTEGER_CLASS_P(CLASS) \ 1240 reg_class_subset_p ((CLASS), GENERAL_REGS) 1241#define FLOAT_CLASS_P(CLASS) \ 1242 reg_class_subset_p ((CLASS), FLOAT_REGS) 1243#define SSE_CLASS_P(CLASS) \ 1244 reg_class_subset_p ((CLASS), SSE_REGS) 1245#define MMX_CLASS_P(CLASS) \ 1246 reg_class_subset_p ((CLASS), MMX_REGS) 1247#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1248 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1249#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1250 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1251#define MAYBE_SSE_CLASS_P(CLASS) \ 1252 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1253#define MAYBE_MMX_CLASS_P(CLASS) \ 1254 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1255 1256#define Q_CLASS_P(CLASS) \ 1257 reg_class_subset_p ((CLASS), Q_REGS) 1258 1259/* Give names of register classes as strings for dump file. */ 1260 1261#define REG_CLASS_NAMES \ 1262{ "NO_REGS", \ 1263 "AREG", "DREG", "CREG", "BREG", \ 1264 "SIREG", "DIREG", \ 1265 "AD_REGS", \ 1266 "Q_REGS", "NON_Q_REGS", \ 1267 "INDEX_REGS", \ 1268 "LEGACY_REGS", \ 1269 "GENERAL_REGS", \ 1270 "FP_TOP_REG", "FP_SECOND_REG", \ 1271 "FLOAT_REGS", \ 1272 "SSE_REGS", \ 1273 "MMX_REGS", \ 1274 "FP_TOP_SSE_REGS", \ 1275 "FP_SECOND_SSE_REGS", \ 1276 "FLOAT_SSE_REGS", \ 1277 "FLOAT_INT_REGS", \ 1278 "INT_SSE_REGS", \ 1279 "FLOAT_INT_SSE_REGS", \ 1280 "ALL_REGS" } 1281 1282/* Define which registers fit in which classes. 1283 This is an initializer for a vector of HARD_REG_SET 1284 of length N_REG_CLASSES. */ 1285 1286#define REG_CLASS_CONTENTS \ 1287{ { 0x00, 0x0 }, \ 1288 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1289 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1290 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1291 { 0x03, 0x0 }, /* AD_REGS */ \ 1292 { 0x0f, 0x0 }, /* Q_REGS */ \ 1293 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1294 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1295 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1296 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1297 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1298 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1299{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1300{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1301{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1302{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1303{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1304 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1305{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1306{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1307{ 0xffffffff,0x1fffff } \ 1308} 1309 1310/* The same information, inverted: 1311 Return the class number of the smallest class containing 1312 reg number REGNO. This could be a conditional expression 1313 or could index an array. */ 1314 1315#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1316 1317/* When defined, the compiler allows registers explicitly used in the 1318 rtl to be used as spill registers but prevents the compiler from 1319 extending the lifetime of these registers. */ 1320 1321#define SMALL_REGISTER_CLASSES 1 1322 1323#define QI_REG_P(X) \ 1324 (REG_P (X) && REGNO (X) < 4) 1325 1326#define GENERAL_REGNO_P(N) \ 1327 ((N) < 8 || REX_INT_REGNO_P (N)) 1328 1329#define GENERAL_REG_P(X) \ 1330 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1331 1332#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1333 1334#define NON_QI_REG_P(X) \ 1335 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1336 1337#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1338#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1339 1340#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1341#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1342#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1343#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1344 1345#define SSE_REGNO_P(N) \ 1346 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1347 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1348 1349#define SSE_REGNO(N) \ 1350 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1351#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1352 1353#define SSE_FLOAT_MODE_P(MODE) \ 1354 ((TARGET_SSE_MATH && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1355 1356#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1357#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1358 1359#define STACK_REG_P(XOP) \ 1360 (REG_P (XOP) && \ 1361 REGNO (XOP) >= FIRST_STACK_REG && \ 1362 REGNO (XOP) <= LAST_STACK_REG) 1363 1364#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1365 1366#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1367 1368#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1369#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1370 1371/* Indicate whether hard register numbered REG_NO should be converted 1372 to SSA form. */ 1373#define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \ 1374 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM) 1375 1376/* The class value for index registers, and the one for base regs. */ 1377 1378#define INDEX_REG_CLASS INDEX_REGS 1379#define BASE_REG_CLASS GENERAL_REGS 1380 1381/* Get reg_class from a letter such as appears in the machine description. */ 1382 1383#define REG_CLASS_FROM_LETTER(C) \ 1384 ((C) == 'r' ? GENERAL_REGS : \ 1385 (C) == 'R' ? LEGACY_REGS : \ 1386 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1387 (C) == 'Q' ? Q_REGS : \ 1388 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1389 ? FLOAT_REGS \ 1390 : NO_REGS) : \ 1391 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1392 ? FP_TOP_REG \ 1393 : NO_REGS) : \ 1394 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1395 ? FP_SECOND_REG \ 1396 : NO_REGS) : \ 1397 (C) == 'a' ? AREG : \ 1398 (C) == 'b' ? BREG : \ 1399 (C) == 'c' ? CREG : \ 1400 (C) == 'd' ? DREG : \ 1401 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1402 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1403 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1404 (C) == 'A' ? AD_REGS : \ 1405 (C) == 'D' ? DIREG : \ 1406 (C) == 'S' ? SIREG : NO_REGS) 1407 1408/* The letters I, J, K, L and M in a register constraint string 1409 can be used to stand for particular ranges of immediate operands. 1410 This macro defines what the ranges are. 1411 C is the letter, and VALUE is a constant value. 1412 Return 1 if VALUE is in the range specified by C. 1413 1414 I is for non-DImode shifts. 1415 J is for DImode shifts. 1416 K is for signed imm8 operands. 1417 L is for andsi as zero-extending move. 1418 M is for shifts that can be executed by the "lea" opcode. 1419 N is for immedaite operands for out/in instructions (0-255) 1420 */ 1421 1422#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1423 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1424 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1425 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1426 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1427 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1428 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1429 : 0) 1430 1431/* Similar, but for floating constants, and defining letters G and H. 1432 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1433 TARGET_387 isn't set, because the stack register converter may need to 1434 load 0.0 into the function value register. */ 1435 1436#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1437 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1438 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0)) 1439 1440/* A C expression that defines the optional machine-dependent 1441 constraint letters that can be used to segregate specific types of 1442 operands, usually memory references, for the target machine. Any 1443 letter that is not elsewhere defined and not matched by 1444 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1445 be defined. 1446 1447 If it is required for a particular target machine, it should 1448 return 1 if VALUE corresponds to the operand type represented by 1449 the constraint letter C. If C is not defined as an extra 1450 constraint, the value returned should be 0 regardless of VALUE. */ 1451 1452#define EXTRA_CONSTRAINT(VALUE, C) \ 1453 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \ 1454 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \ 1455 : 0) 1456 1457/* Place additional restrictions on the register class to use when it 1458 is necessary to be able to hold a value of mode MODE in a reload 1459 register for which class CLASS would ordinarily be used. */ 1460 1461#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1462 ((MODE) == QImode && !TARGET_64BIT \ 1463 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1464 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1465 ? Q_REGS : (CLASS)) 1466 1467/* Given an rtx X being reloaded into a reg required to be 1468 in class CLASS, return the class of reg to actually use. 1469 In general this is just CLASS; but on some machines 1470 in some cases it is preferable to use a more restrictive class. 1471 On the 80386 series, we prevent floating constants from being 1472 reloaded into floating registers (since no move-insn can do that) 1473 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1474 1475/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1476 QImode must go into class Q_REGS. 1477 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1478 movdf to do mem-to-mem moves through integer regs. */ 1479 1480#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1481 ix86_preferred_reload_class ((X), (CLASS)) 1482 1483/* If we are copying between general and FP registers, we need a memory 1484 location. The same is true for SSE and MMX registers. */ 1485#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1486 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1487 1488/* QImode spills from non-QI registers need a scratch. This does not 1489 happen often -- the only example so far requires an uninitialized 1490 pseudo. */ 1491 1492#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1493 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1494 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1495 ? Q_REGS : NO_REGS) 1496 1497/* Return the maximum number of consecutive registers 1498 needed to represent mode MODE in a register of class CLASS. */ 1499/* On the 80386, this is the size of MODE in words, 1500 except in the FP regs, where a single reg is always enough. 1501 The TFmodes are really just 80bit values, so we use only 3 registers 1502 to hold them, instead of 4, as the size would suggest. 1503 */ 1504#define CLASS_MAX_NREGS(CLASS, MODE) \ 1505 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1506 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1507 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ 1508 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1509 1510/* A C expression whose value is nonzero if pseudos that have been 1511 assigned to registers of class CLASS would likely be spilled 1512 because registers of CLASS are needed for spill registers. 1513 1514 The default value of this macro returns 1 if CLASS has exactly one 1515 register and zero otherwise. On most machines, this default 1516 should be used. Only define this macro to some other expression 1517 if pseudo allocated by `local-alloc.c' end up in memory because 1518 their hard registers were needed for spill registers. If this 1519 macro returns nonzero for those classes, those pseudos will only 1520 be allocated by `global.c', which knows how to reallocate the 1521 pseudo to another register. If there would not be another 1522 register available for reallocation, you should not change the 1523 definition of this macro since the only effect of such a 1524 definition would be to slow down register allocation. */ 1525 1526#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1527 (((CLASS) == AREG) \ 1528 || ((CLASS) == DREG) \ 1529 || ((CLASS) == CREG) \ 1530 || ((CLASS) == BREG) \ 1531 || ((CLASS) == AD_REGS) \ 1532 || ((CLASS) == SIREG) \ 1533 || ((CLASS) == DIREG)) 1534 1535/* A C statement that adds to CLOBBERS any hard regs the port wishes 1536 to automatically clobber for all asms. 1537 1538 We do this in the new i386 backend to maintain source compatibility 1539 with the old cc0-based compiler. */ 1540 1541#define MD_ASM_CLOBBERS(CLOBBERS) \ 1542 do { \ 1543 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ 1544 (CLOBBERS)); \ 1545 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ 1546 (CLOBBERS)); \ 1547 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ 1548 (CLOBBERS)); \ 1549 } while (0) 1550 1551/* Stack layout; function entry, exit and calling. */ 1552 1553/* Define this if pushing a word on the stack 1554 makes the stack pointer a smaller address. */ 1555#define STACK_GROWS_DOWNWARD 1556 1557/* Define this if the nominal address of the stack frame 1558 is at the high-address end of the local variables; 1559 that is, each additional local variable allocated 1560 goes at a more negative offset in the frame. */ 1561#define FRAME_GROWS_DOWNWARD 1562 1563/* Offset within stack frame to start allocating local variables at. 1564 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1565 first local allocated. Otherwise, it is the offset to the BEGINNING 1566 of the first local allocated. */ 1567#define STARTING_FRAME_OFFSET 0 1568 1569/* If we generate an insn to push BYTES bytes, 1570 this says how many the stack pointer really advances by. 1571 On 386 pushw decrements by exactly 2 no matter what the position was. 1572 On the 386 there is no pushb; we use pushw instead, and this 1573 has the effect of rounding up to 2. 1574 1575 For 64bit ABI we round up to 8 bytes. 1576 */ 1577 1578#define PUSH_ROUNDING(BYTES) \ 1579 (TARGET_64BIT \ 1580 ? (((BYTES) + 7) & (-8)) \ 1581 : (((BYTES) + 1) & (-2))) 1582 1583/* If defined, the maximum amount of space required for outgoing arguments will 1584 be computed and placed into the variable 1585 `current_function_outgoing_args_size'. No space will be pushed onto the 1586 stack for each call; instead, the function prologue should increase the stack 1587 frame size by this amount. */ 1588 1589#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1590 1591/* If defined, a C expression whose value is nonzero when we want to use PUSH 1592 instructions to pass outgoing arguments. */ 1593 1594#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1595 1596/* Offset of first parameter from the argument pointer register value. */ 1597#define FIRST_PARM_OFFSET(FNDECL) 0 1598 1599/* Define this macro if functions should assume that stack space has been 1600 allocated for arguments even when their values are passed in registers. 1601 1602 The value of this macro is the size, in bytes, of the area reserved for 1603 arguments passed in registers for the function represented by FNDECL. 1604 1605 This space can be allocated by the caller, or be a part of the 1606 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1607 which. */ 1608#define REG_PARM_STACK_SPACE(FNDECL) 0 1609 1610/* Define as a C expression that evaluates to nonzero if we do not know how 1611 to pass TYPE solely in registers. The file expr.h defines a 1612 definition that is usually appropriate, refer to expr.h for additional 1613 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be 1614 computed in the stack and then loaded into a register. */ 1615#define MUST_PASS_IN_STACK(MODE, TYPE) \ 1616 ((TYPE) != 0 \ 1617 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1618 || TREE_ADDRESSABLE (TYPE) \ 1619 || ((MODE) == TImode) \ 1620 || ((MODE) == BLKmode \ 1621 && ! ((TYPE) != 0 \ 1622 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ 1623 && 0 == (int_size_in_bytes (TYPE) \ 1624 % (PARM_BOUNDARY / BITS_PER_UNIT))) \ 1625 && (FUNCTION_ARG_PADDING (MODE, TYPE) \ 1626 == (BYTES_BIG_ENDIAN ? upward : downward))))) 1627 1628/* Value is the number of bytes of arguments automatically 1629 popped when returning from a subroutine call. 1630 FUNDECL is the declaration node of the function (as a tree), 1631 FUNTYPE is the data type of the function (as a tree), 1632 or for a library call it is an identifier node for the subroutine name. 1633 SIZE is the number of bytes of arguments passed on the stack. 1634 1635 On the 80386, the RTD insn may be used to pop them if the number 1636 of args is fixed, but if the number is variable then the caller 1637 must pop them all. RTD can't be used for library calls now 1638 because the library is compiled with the Unix compiler. 1639 Use of RTD is a selectable option, since it is incompatible with 1640 standard Unix calling sequences. If the option is not selected, 1641 the caller must always pop the args. 1642 1643 The attribute stdcall is equivalent to RTD on a per module basis. */ 1644 1645#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1646 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1647 1648/* Define how to find the value returned by a function. 1649 VALTYPE is the data type of the value (as a tree). 1650 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1651 otherwise, FUNC is 0. */ 1652#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1653 ix86_function_value (VALTYPE) 1654 1655#define FUNCTION_VALUE_REGNO_P(N) \ 1656 ix86_function_value_regno_p (N) 1657 1658/* Define how to find the value returned by a library function 1659 assuming the value has mode MODE. */ 1660 1661#define LIBCALL_VALUE(MODE) \ 1662 ix86_libcall_value (MODE) 1663 1664/* Define the size of the result block used for communication between 1665 untyped_call and untyped_return. The block contains a DImode value 1666 followed by the block used by fnsave and frstor. */ 1667 1668#define APPLY_RESULT_SIZE (8+108) 1669 1670/* 1 if N is a possible register number for function argument passing. */ 1671#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1672 1673/* Define a data type for recording info about an argument list 1674 during the scan of that argument list. This data type should 1675 hold all necessary information about the function itself 1676 and about the args processed so far, enough to enable macros 1677 such as FUNCTION_ARG to determine where the next arg should go. */ 1678 1679typedef struct ix86_args { 1680 int words; /* # words passed so far */ 1681 int nregs; /* # registers available for passing */ 1682 int regno; /* next available register number */ 1683 int sse_words; /* # sse words passed so far */ 1684 int sse_nregs; /* # sse registers available for passing */ 1685 int sse_regno; /* next available sse register number */ 1686 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1687} CUMULATIVE_ARGS; 1688 1689/* Initialize a variable CUM of type CUMULATIVE_ARGS 1690 for a call to a function whose data type is FNTYPE. 1691 For a library call, FNTYPE is 0. */ 1692 1693#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1694 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) 1695 1696/* Update the data in CUM to advance over an argument 1697 of mode MODE and data type TYPE. 1698 (TYPE is null for libcalls where that information may not be available.) */ 1699 1700#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1701 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1702 1703/* Define where to put the arguments to a function. 1704 Value is zero to push the argument on the stack, 1705 or a hard register in which to store the argument. 1706 1707 MODE is the argument's machine mode. 1708 TYPE is the data type of the argument (as a tree). 1709 This is null for libcalls where that information may 1710 not be available. 1711 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1712 the preceding args and about the function being called. 1713 NAMED is nonzero if this argument is a named parameter 1714 (otherwise it is an extra parameter matching an ellipsis). */ 1715 1716#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1717 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1718 1719/* For an arg passed partly in registers and partly in memory, 1720 this is the number of registers used. 1721 For args passed entirely in registers or entirely in memory, zero. */ 1722 1723#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1724 1725/* If PIC, we cannot make sibling calls to global functions 1726 because the PLT requires %ebx live. 1727 If we are returning floats on the register stack, we cannot make 1728 sibling calls to functions that return floats. (The stack adjust 1729 instruction will wind up after the sibcall jump, and not be executed.) */ 1730#define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1731 ((DECL) \ 1732 && (! flag_pic || ! TREE_PUBLIC (DECL)) \ 1733 && (! TARGET_FLOAT_RETURNS_IN_80387 \ 1734 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \ 1735 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl)))))) 1736 1737/* Perform any needed actions needed for a function that is receiving a 1738 variable number of arguments. 1739 1740 CUM is as above. 1741 1742 MODE and TYPE are the mode and type of the current parameter. 1743 1744 PRETEND_SIZE is a variable that should be set to the amount of stack 1745 that must be pushed by the prolog to pretend that our caller pushed 1746 it. 1747 1748 Normally, this macro will push all remaining incoming registers on the 1749 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1750 1751#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1752 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ 1753 (NO_RTL)) 1754 1755/* Define the `__builtin_va_list' type for the ABI. */ 1756#define BUILD_VA_LIST_TYPE(VALIST) \ 1757 ((VALIST) = ix86_build_va_list ()) 1758 1759/* Implement `va_start' for varargs and stdarg. */ 1760#define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \ 1761 ix86_va_start ((STDARG), (VALIST), (NEXTARG)) 1762 1763/* Implement `va_arg'. */ 1764#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ 1765 ix86_va_arg ((VALIST), (TYPE)) 1766 1767/* This macro is invoked at the end of compilation. It is used here to 1768 output code for -fpic that will load the return address into %ebx. */ 1769 1770#undef ASM_FILE_END 1771#define ASM_FILE_END(FILE) ix86_asm_file_end (FILE) 1772 1773/* Output assembler code to FILE to increment profiler label # LABELNO 1774 for profiling a function entry. */ 1775 1776#define FUNCTION_PROFILER(FILE, LABELNO) \ 1777do { \ 1778 if (flag_pic) \ 1779 { \ 1780 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \ 1781 LPREFIX, (LABELNO)); \ 1782 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \ 1783 } \ 1784 else \ 1785 { \ 1786 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ 1787 fprintf ((FILE), "\tcall\t_mcount\n"); \ 1788 } \ 1789} while (0) 1790 1791/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1792 the stack pointer does not matter. The value is tested only in 1793 functions that have frame pointers. 1794 No definition is equivalent to always zero. */ 1795/* Note on the 386 it might be more efficient not to define this since 1796 we have to restore it ourselves from the frame pointer, in order to 1797 use pop */ 1798 1799#define EXIT_IGNORE_STACK 1 1800 1801/* Output assembler code for a block containing the constant parts 1802 of a trampoline, leaving space for the variable parts. */ 1803 1804/* On the 386, the trampoline contains two instructions: 1805 mov #STATIC,ecx 1806 jmp FUNCTION 1807 The trampoline is generated entirely at runtime. The operand of JMP 1808 is the address of FUNCTION relative to the instruction following the 1809 JMP (which is 5 bytes long). */ 1810 1811/* Length in units of the trampoline for entering a nested function. */ 1812 1813#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1814 1815/* Emit RTL insns to initialize the variable parts of a trampoline. 1816 FNADDR is an RTX for the address of the function's pure code. 1817 CXT is an RTX for the static chain value for the function. */ 1818 1819#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1820 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1821 1822/* Definitions for register eliminations. 1823 1824 This is an array of structures. Each structure initializes one pair 1825 of eliminable registers. The "from" register number is given first, 1826 followed by "to". Eliminations of the same "from" register are listed 1827 in order of preference. 1828 1829 There are two registers that can always be eliminated on the i386. 1830 The frame pointer and the arg pointer can be replaced by either the 1831 hard frame pointer or to the stack pointer, depending upon the 1832 circumstances. The hard frame pointer is not used before reload and 1833 so it is not eligible for elimination. */ 1834 1835#define ELIMINABLE_REGS \ 1836{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1837 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1838 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1839 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1840 1841/* Given FROM and TO register numbers, say whether this elimination is 1842 allowed. Frame pointer elimination is automatically handled. 1843 1844 All other eliminations are valid. */ 1845 1846#define CAN_ELIMINATE(FROM, TO) \ 1847 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1848 1849/* Define the offset between two registers, one to be eliminated, and the other 1850 its replacement, at the start of a routine. */ 1851 1852#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1853 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1854 1855/* Addressing modes, and classification of registers for them. */ 1856 1857/* #define HAVE_POST_INCREMENT 0 */ 1858/* #define HAVE_POST_DECREMENT 0 */ 1859 1860/* #define HAVE_PRE_DECREMENT 0 */ 1861/* #define HAVE_PRE_INCREMENT 0 */ 1862 1863/* Macros to check register numbers against specific register classes. */ 1864 1865/* These assume that REGNO is a hard or pseudo reg number. 1866 They give nonzero only if REGNO is a hard reg of the suitable class 1867 or a pseudo reg currently allocated to a suitable hard reg. 1868 Since they use reg_renumber, they are safe only once reg_renumber 1869 has been allocated, which happens in local-alloc.c. */ 1870 1871#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1872 ((REGNO) < STACK_POINTER_REGNUM \ 1873 || (REGNO >= FIRST_REX_INT_REG \ 1874 && (REGNO) <= LAST_REX_INT_REG) \ 1875 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1876 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1877 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1878 1879#define REGNO_OK_FOR_BASE_P(REGNO) \ 1880 ((REGNO) <= STACK_POINTER_REGNUM \ 1881 || (REGNO) == ARG_POINTER_REGNUM \ 1882 || (REGNO) == FRAME_POINTER_REGNUM \ 1883 || (REGNO >= FIRST_REX_INT_REG \ 1884 && (REGNO) <= LAST_REX_INT_REG) \ 1885 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1886 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1887 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1888 1889#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1890 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1891#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1892 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1893 1894/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1895 and check its validity for a certain class. 1896 We have two alternate definitions for each of them. 1897 The usual definition accepts all pseudo regs; the other rejects 1898 them unless they have been allocated suitable hard regs. 1899 The symbol REG_OK_STRICT causes the latter definition to be used. 1900 1901 Most source files want to accept pseudo regs in the hope that 1902 they will get allocated to the class that the insn wants them to be in. 1903 Source files for reload pass need to be strict. 1904 After reload, it makes no difference, since pseudo regs have 1905 been eliminated by then. */ 1906 1907 1908/* Non strict versions, pseudos are ok */ 1909#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1910 (REGNO (X) < STACK_POINTER_REGNUM \ 1911 || (REGNO (X) >= FIRST_REX_INT_REG \ 1912 && REGNO (X) <= LAST_REX_INT_REG) \ 1913 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1914 1915#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1916 (REGNO (X) <= STACK_POINTER_REGNUM \ 1917 || REGNO (X) == ARG_POINTER_REGNUM \ 1918 || REGNO (X) == FRAME_POINTER_REGNUM \ 1919 || (REGNO (X) >= FIRST_REX_INT_REG \ 1920 && REGNO (X) <= LAST_REX_INT_REG) \ 1921 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1922 1923/* Strict versions, hard registers only */ 1924#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1925#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1926 1927#ifndef REG_OK_STRICT 1928#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1929#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1930 1931#else 1932#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1933#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1934#endif 1935 1936/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1937 that is a valid memory address for an instruction. 1938 The MODE argument is the machine mode for the MEM expression 1939 that wants to use this address. 1940 1941 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1942 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1943 1944 See legitimize_pic_address in i386.c for details as to what 1945 constitutes a legitimate address when -fpic is used. */ 1946 1947#define MAX_REGS_PER_ADDRESS 2 1948 1949#define CONSTANT_ADDRESS_P(X) \ 1950 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1951 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1952 || GET_CODE (X) == CONST_DOUBLE) 1953 1954/* Nonzero if the constant value X is a legitimate general operand. 1955 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1956 1957#define LEGITIMATE_CONSTANT_P(X) 1 1958 1959#ifdef REG_OK_STRICT 1960#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1961do { \ 1962 if (legitimate_address_p ((MODE), (X), 1)) \ 1963 goto ADDR; \ 1964} while (0) 1965 1966#else 1967#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1968do { \ 1969 if (legitimate_address_p ((MODE), (X), 0)) \ 1970 goto ADDR; \ 1971} while (0) 1972 1973#endif 1974 1975/* If defined, a C expression to determine the base term of address X. 1976 This macro is used in only one place: `find_base_term' in alias.c. 1977 1978 It is always safe for this macro to not be defined. It exists so 1979 that alias analysis can understand machine-dependent addresses. 1980 1981 The typical use of this macro is to handle addresses containing 1982 a label_ref or symbol_ref within an UNSPEC. */ 1983 1984#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1985 1986/* Try machine-dependent ways of modifying an illegitimate address 1987 to be legitimate. If we find one, return the new, valid address. 1988 This macro is used in only one place: `memory_address' in explow.c. 1989 1990 OLDX is the address as it was before break_out_memory_refs was called. 1991 In some cases it is useful to look at this to decide what needs to be done. 1992 1993 MODE and WIN are passed so that this macro can use 1994 GO_IF_LEGITIMATE_ADDRESS. 1995 1996 It is always safe for this macro to do nothing. It exists to recognize 1997 opportunities to optimize the output. 1998 1999 For the 80386, we handle X+REG by loading X into a register R and 2000 using R+REG. R will go in a general reg and indexing will be used. 2001 However, if REG is a broken-out memory address or multiplication, 2002 nothing needs to be done because REG can certainly go in a general reg. 2003 2004 When -fpic is used, special handling is needed for symbolic references. 2005 See comments by legitimize_pic_address in i386.c for details. */ 2006 2007#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2008do { \ 2009 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 2010 if (memory_address_p ((MODE), (X))) \ 2011 goto WIN; \ 2012} while (0) 2013 2014#define REWRITE_ADDRESS(X) rewrite_address (X) 2015 2016/* Nonzero if the constant value X is a legitimate general operand 2017 when generating PIC code. It is given that flag_pic is on and 2018 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2019 2020#define LEGITIMATE_PIC_OPERAND_P(X) \ 2021 (! SYMBOLIC_CONST (X) \ 2022 || legitimate_pic_address_disp_p (X)) 2023 2024#define SYMBOLIC_CONST(X) \ 2025 (GET_CODE (X) == SYMBOL_REF \ 2026 || GET_CODE (X) == LABEL_REF \ 2027 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 2028 2029/* Go to LABEL if ADDR (a legitimate address expression) 2030 has an effect that depends on the machine mode it is used for. 2031 On the 80386, only postdecrement and postincrement address depend thus 2032 (the amount of decrement or increment being the length of the operand). */ 2033#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2034do { \ 2035 if (GET_CODE (ADDR) == POST_INC \ 2036 || GET_CODE (ADDR) == POST_DEC) \ 2037 goto LABEL; \ 2038} while (0) 2039 2040/* Codes for all the SSE/MMX builtins. */ 2041enum ix86_builtins 2042{ 2043 IX86_BUILTIN_ADDPS, 2044 IX86_BUILTIN_ADDSS, 2045 IX86_BUILTIN_DIVPS, 2046 IX86_BUILTIN_DIVSS, 2047 IX86_BUILTIN_MULPS, 2048 IX86_BUILTIN_MULSS, 2049 IX86_BUILTIN_SUBPS, 2050 IX86_BUILTIN_SUBSS, 2051 2052 IX86_BUILTIN_CMPEQPS, 2053 IX86_BUILTIN_CMPLTPS, 2054 IX86_BUILTIN_CMPLEPS, 2055 IX86_BUILTIN_CMPGTPS, 2056 IX86_BUILTIN_CMPGEPS, 2057 IX86_BUILTIN_CMPNEQPS, 2058 IX86_BUILTIN_CMPNLTPS, 2059 IX86_BUILTIN_CMPNLEPS, 2060 IX86_BUILTIN_CMPNGTPS, 2061 IX86_BUILTIN_CMPNGEPS, 2062 IX86_BUILTIN_CMPORDPS, 2063 IX86_BUILTIN_CMPUNORDPS, 2064 IX86_BUILTIN_CMPNEPS, 2065 IX86_BUILTIN_CMPEQSS, 2066 IX86_BUILTIN_CMPLTSS, 2067 IX86_BUILTIN_CMPLESS, 2068 IX86_BUILTIN_CMPGTSS, 2069 IX86_BUILTIN_CMPGESS, 2070 IX86_BUILTIN_CMPNEQSS, 2071 IX86_BUILTIN_CMPNLTSS, 2072 IX86_BUILTIN_CMPNLESS, 2073 IX86_BUILTIN_CMPNGTSS, 2074 IX86_BUILTIN_CMPNGESS, 2075 IX86_BUILTIN_CMPORDSS, 2076 IX86_BUILTIN_CMPUNORDSS, 2077 IX86_BUILTIN_CMPNESS, 2078 2079 IX86_BUILTIN_COMIEQSS, 2080 IX86_BUILTIN_COMILTSS, 2081 IX86_BUILTIN_COMILESS, 2082 IX86_BUILTIN_COMIGTSS, 2083 IX86_BUILTIN_COMIGESS, 2084 IX86_BUILTIN_COMINEQSS, 2085 IX86_BUILTIN_UCOMIEQSS, 2086 IX86_BUILTIN_UCOMILTSS, 2087 IX86_BUILTIN_UCOMILESS, 2088 IX86_BUILTIN_UCOMIGTSS, 2089 IX86_BUILTIN_UCOMIGESS, 2090 IX86_BUILTIN_UCOMINEQSS, 2091 2092 IX86_BUILTIN_CVTPI2PS, 2093 IX86_BUILTIN_CVTPS2PI, 2094 IX86_BUILTIN_CVTSI2SS, 2095 IX86_BUILTIN_CVTSS2SI, 2096 IX86_BUILTIN_CVTTPS2PI, 2097 IX86_BUILTIN_CVTTSS2SI, 2098 2099 IX86_BUILTIN_MAXPS, 2100 IX86_BUILTIN_MAXSS, 2101 IX86_BUILTIN_MINPS, 2102 IX86_BUILTIN_MINSS, 2103 2104 IX86_BUILTIN_LOADAPS, 2105 IX86_BUILTIN_LOADUPS, 2106 IX86_BUILTIN_STOREAPS, 2107 IX86_BUILTIN_STOREUPS, 2108 IX86_BUILTIN_LOADSS, 2109 IX86_BUILTIN_STORESS, 2110 IX86_BUILTIN_MOVSS, 2111 2112 IX86_BUILTIN_MOVHLPS, 2113 IX86_BUILTIN_MOVLHPS, 2114 IX86_BUILTIN_LOADHPS, 2115 IX86_BUILTIN_LOADLPS, 2116 IX86_BUILTIN_STOREHPS, 2117 IX86_BUILTIN_STORELPS, 2118 2119 IX86_BUILTIN_MASKMOVQ, 2120 IX86_BUILTIN_MOVMSKPS, 2121 IX86_BUILTIN_PMOVMSKB, 2122 2123 IX86_BUILTIN_MOVNTPS, 2124 IX86_BUILTIN_MOVNTQ, 2125 2126 IX86_BUILTIN_PACKSSWB, 2127 IX86_BUILTIN_PACKSSDW, 2128 IX86_BUILTIN_PACKUSWB, 2129 2130 IX86_BUILTIN_PADDB, 2131 IX86_BUILTIN_PADDW, 2132 IX86_BUILTIN_PADDD, 2133 IX86_BUILTIN_PADDSB, 2134 IX86_BUILTIN_PADDSW, 2135 IX86_BUILTIN_PADDUSB, 2136 IX86_BUILTIN_PADDUSW, 2137 IX86_BUILTIN_PSUBB, 2138 IX86_BUILTIN_PSUBW, 2139 IX86_BUILTIN_PSUBD, 2140 IX86_BUILTIN_PSUBSB, 2141 IX86_BUILTIN_PSUBSW, 2142 IX86_BUILTIN_PSUBUSB, 2143 IX86_BUILTIN_PSUBUSW, 2144 2145 IX86_BUILTIN_PAND, 2146 IX86_BUILTIN_PANDN, 2147 IX86_BUILTIN_POR, 2148 IX86_BUILTIN_PXOR, 2149 2150 IX86_BUILTIN_PAVGB, 2151 IX86_BUILTIN_PAVGW, 2152 2153 IX86_BUILTIN_PCMPEQB, 2154 IX86_BUILTIN_PCMPEQW, 2155 IX86_BUILTIN_PCMPEQD, 2156 IX86_BUILTIN_PCMPGTB, 2157 IX86_BUILTIN_PCMPGTW, 2158 IX86_BUILTIN_PCMPGTD, 2159 2160 IX86_BUILTIN_PEXTRW, 2161 IX86_BUILTIN_PINSRW, 2162 2163 IX86_BUILTIN_PMADDWD, 2164 2165 IX86_BUILTIN_PMAXSW, 2166 IX86_BUILTIN_PMAXUB, 2167 IX86_BUILTIN_PMINSW, 2168 IX86_BUILTIN_PMINUB, 2169 2170 IX86_BUILTIN_PMULHUW, 2171 IX86_BUILTIN_PMULHW, 2172 IX86_BUILTIN_PMULLW, 2173 2174 IX86_BUILTIN_PSADBW, 2175 IX86_BUILTIN_PSHUFW, 2176 2177 IX86_BUILTIN_PSLLW, 2178 IX86_BUILTIN_PSLLD, 2179 IX86_BUILTIN_PSLLQ, 2180 IX86_BUILTIN_PSRAW, 2181 IX86_BUILTIN_PSRAD, 2182 IX86_BUILTIN_PSRLW, 2183 IX86_BUILTIN_PSRLD, 2184 IX86_BUILTIN_PSRLQ, 2185 IX86_BUILTIN_PSLLWI, 2186 IX86_BUILTIN_PSLLDI, 2187 IX86_BUILTIN_PSLLQI, 2188 IX86_BUILTIN_PSRAWI, 2189 IX86_BUILTIN_PSRADI, 2190 IX86_BUILTIN_PSRLWI, 2191 IX86_BUILTIN_PSRLDI, 2192 IX86_BUILTIN_PSRLQI, 2193 2194 IX86_BUILTIN_PUNPCKHBW, 2195 IX86_BUILTIN_PUNPCKHWD, 2196 IX86_BUILTIN_PUNPCKHDQ, 2197 IX86_BUILTIN_PUNPCKLBW, 2198 IX86_BUILTIN_PUNPCKLWD, 2199 IX86_BUILTIN_PUNPCKLDQ, 2200 2201 IX86_BUILTIN_SHUFPS, 2202 2203 IX86_BUILTIN_RCPPS, 2204 IX86_BUILTIN_RCPSS, 2205 IX86_BUILTIN_RSQRTPS, 2206 IX86_BUILTIN_RSQRTSS, 2207 IX86_BUILTIN_SQRTPS, 2208 IX86_BUILTIN_SQRTSS, 2209 2210 IX86_BUILTIN_UNPCKHPS, 2211 IX86_BUILTIN_UNPCKLPS, 2212 2213 IX86_BUILTIN_ANDPS, 2214 IX86_BUILTIN_ANDNPS, 2215 IX86_BUILTIN_ORPS, 2216 IX86_BUILTIN_XORPS, 2217 2218 IX86_BUILTIN_EMMS, 2219 IX86_BUILTIN_LDMXCSR, 2220 IX86_BUILTIN_STMXCSR, 2221 IX86_BUILTIN_SFENCE, 2222 2223 /* 3DNow! Original */ 2224 IX86_BUILTIN_FEMMS, 2225 IX86_BUILTIN_PAVGUSB, 2226 IX86_BUILTIN_PF2ID, 2227 IX86_BUILTIN_PFACC, 2228 IX86_BUILTIN_PFADD, 2229 IX86_BUILTIN_PFCMPEQ, 2230 IX86_BUILTIN_PFCMPGE, 2231 IX86_BUILTIN_PFCMPGT, 2232 IX86_BUILTIN_PFMAX, 2233 IX86_BUILTIN_PFMIN, 2234 IX86_BUILTIN_PFMUL, 2235 IX86_BUILTIN_PFRCP, 2236 IX86_BUILTIN_PFRCPIT1, 2237 IX86_BUILTIN_PFRCPIT2, 2238 IX86_BUILTIN_PFRSQIT1, 2239 IX86_BUILTIN_PFRSQRT, 2240 IX86_BUILTIN_PFSUB, 2241 IX86_BUILTIN_PFSUBR, 2242 IX86_BUILTIN_PI2FD, 2243 IX86_BUILTIN_PMULHRW, 2244 2245 /* 3DNow! Athlon Extensions */ 2246 IX86_BUILTIN_PF2IW, 2247 IX86_BUILTIN_PFNACC, 2248 IX86_BUILTIN_PFPNACC, 2249 IX86_BUILTIN_PI2FW, 2250 IX86_BUILTIN_PSWAPDSI, 2251 IX86_BUILTIN_PSWAPDSF, 2252 2253 IX86_BUILTIN_SSE_ZERO, 2254 IX86_BUILTIN_MMX_ZERO, 2255 2256 IX86_BUILTIN_MAX 2257}; 2258 2259/* Define this macro if references to a symbol must be treated 2260 differently depending on something about the variable or 2261 function named by the symbol (such as what section it is in). 2262 2263 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol 2264 so that we may access it directly in the GOT. */ 2265 2266#define ENCODE_SECTION_INFO(DECL) \ 2267do { \ 2268 if (flag_pic) \ 2269 { \ 2270 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2271 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ 2272 \ 2273 if (GET_CODE (rtl) == MEM) \ 2274 { \ 2275 if (TARGET_DEBUG_ADDR \ 2276 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \ 2277 { \ 2278 fprintf (stderr, "Encode %s, public = %d\n", \ 2279 IDENTIFIER_POINTER (DECL_NAME (DECL)), \ 2280 TREE_PUBLIC (DECL)); \ 2281 } \ 2282 \ 2283 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ 2284 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2285 || ! TREE_PUBLIC (DECL)); \ 2286 } \ 2287 } \ 2288} while (0) 2289 2290/* The `FINALIZE_PIC' macro serves as a hook to emit these special 2291 codes once the function is being compiled into assembly code, but 2292 not before. (It is not done before, because in the case of 2293 compiling an inline function, it would lead to multiple PIC 2294 prologues being included in functions which used inline functions 2295 and were compiled to assembly language.) */ 2296 2297#define FINALIZE_PIC \ 2298 (current_function_uses_pic_offset_table |= current_function_profile) 2299 2300 2301/* Max number of args passed in registers. If this is more than 3, we will 2302 have problems with ebx (register #4), since it is a caller save register and 2303 is also used as the pic register in ELF. So for now, don't allow more than 2304 3 registers to be passed in registers. */ 2305 2306#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 2307 2308#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0) 2309 2310 2311/* Specify the machine mode that this machine uses 2312 for the index in the tablejump instruction. */ 2313#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 2314 2315/* Define as C expression which evaluates to nonzero if the tablejump 2316 instruction expects the table to contain offsets from the address of the 2317 table. 2318 Do not define this if the table should contain absolute addresses. */ 2319/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2320 2321/* Define this as 1 if `char' should by default be signed; else as 0. */ 2322#define DEFAULT_SIGNED_CHAR 1 2323 2324/* Number of bytes moved into a data cache for a single prefetch operation. */ 2325#define PREFETCH_BLOCK ix86_cost->prefetch_block 2326 2327/* Number of prefetch operations that can be done in parallel. */ 2328#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 2329 2330/* Max number of bytes we can move from memory to memory 2331 in one reasonably fast instruction. */ 2332#define MOVE_MAX 16 2333 2334/* MOVE_MAX_PIECES is the number of bytes at a time which we can 2335 move efficiently, as opposed to MOVE_MAX which is the maximum 2336 number of bytes we can move with a single instruction. */ 2337#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 2338 2339/* If a memory-to-memory move would take MOVE_RATIO or more simple 2340 move-instruction pairs, we will do a movstr or libcall instead. 2341 Increasing the value will always make code faster, but eventually 2342 incurs high cost in increased code size. 2343 2344 If you don't define this, a reasonable default is used. */ 2345 2346#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 2347 2348/* Define if shifts truncate the shift count 2349 which implies one can omit a sign-extension or zero-extension 2350 of a shift count. */ 2351/* On i386, shifts do truncate the count. But bit opcodes don't. */ 2352 2353/* #define SHIFT_COUNT_TRUNCATED */ 2354 2355/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2356 is done just by pretending it is already truncated. */ 2357#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2358 2359/* We assume that the store-condition-codes instructions store 0 for false 2360 and some other value for true. This is the value stored for true. */ 2361 2362#define STORE_FLAG_VALUE 1 2363 2364/* When a prototype says `char' or `short', really pass an `int'. 2365 (The 386 can't easily push less than an int.) */ 2366 2367#define PROMOTE_PROTOTYPES 1 2368 2369/* A macro to update M and UNSIGNEDP when an object whose type is 2370 TYPE and which has the specified mode and signedness is to be 2371 stored in a register. This macro is only called when TYPE is a 2372 scalar type. 2373 2374 On i386 it is sometimes useful to promote HImode and QImode 2375 quantities to SImode. The choice depends on target type. */ 2376 2377#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2378do { \ 2379 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 2380 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 2381 (MODE) = SImode; \ 2382} while (0) 2383 2384/* Specify the machine mode that pointers have. 2385 After generation of rtl, the compiler makes no further distinction 2386 between pointers and any other objects of this machine mode. */ 2387#define Pmode (TARGET_64BIT ? DImode : SImode) 2388 2389/* A function address in a call instruction 2390 is a byte address (for indexing purposes) 2391 so give the MEM rtx a byte's mode. */ 2392#define FUNCTION_MODE QImode 2393 2394/* A part of a C `switch' statement that describes the relative costs 2395 of constant RTL expressions. It must contain `case' labels for 2396 expression codes `const_int', `const', `symbol_ref', `label_ref' 2397 and `const_double'. Each case must ultimately reach a `return' 2398 statement to return the relative cost of the use of that kind of 2399 constant value in an expression. The cost may depend on the 2400 precise value of the constant, which is available for examination 2401 in X, and the rtx code of the expression in which it is contained, 2402 found in OUTER_CODE. 2403 2404 CODE is the expression code--redundant, since it can be obtained 2405 with `GET_CODE (X)'. */ 2406 2407#define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 2408 case CONST_INT: \ 2409 case CONST: \ 2410 case LABEL_REF: \ 2411 case SYMBOL_REF: \ 2412 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \ 2413 return 3; \ 2414 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \ 2415 return 2; \ 2416 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \ 2417 \ 2418 case CONST_DOUBLE: \ 2419 { \ 2420 int code; \ 2421 if (GET_MODE (RTX) == VOIDmode) \ 2422 return 0; \ 2423 \ 2424 code = standard_80387_constant_p (RTX); \ 2425 return code == 1 ? 1 : \ 2426 code == 2 ? 2 : \ 2427 3; \ 2428 } 2429 2430/* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ 2431#define TOPLEVEL_COSTS_N_INSNS(N) \ 2432 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) 2433 2434/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. 2435 This can be used, for example, to indicate how costly a multiply 2436 instruction is. In writing this macro, you can use the construct 2437 `COSTS_N_INSNS (N)' to specify a cost equal to N fast 2438 instructions. OUTER_CODE is the code of the expression in which X 2439 is contained. 2440 2441 This macro is optional; do not define it if the default cost 2442 assumptions are adequate for the target machine. */ 2443 2444#define RTX_COSTS(X, CODE, OUTER_CODE) \ 2445 case ZERO_EXTEND: \ 2446 /* The zero extensions is often completely free on x86_64, so make \ 2447 it as cheap as possible. */ \ 2448 if (TARGET_64BIT && GET_MODE (X) == DImode \ 2449 && GET_MODE (XEXP (X, 0)) == SImode) \ 2450 { \ 2451 total = 1; goto egress_rtx_costs; \ 2452 } \ 2453 else \ 2454 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \ 2455 ix86_cost->add : ix86_cost->movzx); \ 2456 break; \ 2457 case SIGN_EXTEND: \ 2458 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \ 2459 break; \ 2460 case ASHIFT: \ 2461 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 2462 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \ 2463 { \ 2464 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2465 if (value == 1) \ 2466 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2467 if ((value == 2 || value == 3) \ 2468 && !TARGET_DECOMPOSE_LEA \ 2469 && ix86_cost->lea <= ix86_cost->shift_const) \ 2470 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ 2471 } \ 2472 /* fall through */ \ 2473 \ 2474 case ROTATE: \ 2475 case ASHIFTRT: \ 2476 case LSHIFTRT: \ 2477 case ROTATERT: \ 2478 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \ 2479 { \ 2480 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2481 { \ 2482 if (INTVAL (XEXP (X, 1)) > 32) \ 2483 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ 2484 else \ 2485 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ 2486 } \ 2487 else \ 2488 { \ 2489 if (GET_CODE (XEXP (X, 1)) == AND) \ 2490 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ 2491 else \ 2492 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ 2493 } \ 2494 } \ 2495 else \ 2496 { \ 2497 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2498 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ 2499 else \ 2500 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ 2501 } \ 2502 break; \ 2503 \ 2504 case MULT: \ 2505 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2506 { \ 2507 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2508 int nbits = 0; \ 2509 \ 2510 while (value != 0) \ 2511 { \ 2512 nbits++; \ 2513 value >>= 1; \ 2514 } \ 2515 \ 2516 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2517 + nbits * ix86_cost->mult_bit); \ 2518 } \ 2519 else /* This is arbitrary */ \ 2520 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2521 + 7 * ix86_cost->mult_bit); \ 2522 \ 2523 case DIV: \ 2524 case UDIV: \ 2525 case MOD: \ 2526 case UMOD: \ 2527 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ 2528 \ 2529 case PLUS: \ 2530 if (!TARGET_DECOMPOSE_LEA \ 2531 && INTEGRAL_MODE_P (GET_MODE (X)) \ 2532 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \ 2533 { \ 2534 if (GET_CODE (XEXP (X, 0)) == PLUS \ 2535 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ 2536 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ 2537 && CONSTANT_P (XEXP (X, 1))) \ 2538 { \ 2539 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\ 2540 if (val == 2 || val == 4 || val == 8) \ 2541 { \ 2542 return (COSTS_N_INSNS (ix86_cost->lea) \ 2543 + rtx_cost (XEXP (XEXP (X, 0), 1), \ 2544 (OUTER_CODE)) \ 2545 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \ 2546 (OUTER_CODE)) \ 2547 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2548 } \ 2549 } \ 2550 else if (GET_CODE (XEXP (X, 0)) == MULT \ 2551 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ 2552 { \ 2553 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ 2554 if (val == 2 || val == 4 || val == 8) \ 2555 { \ 2556 return (COSTS_N_INSNS (ix86_cost->lea) \ 2557 + rtx_cost (XEXP (XEXP (X, 0), 0), \ 2558 (OUTER_CODE)) \ 2559 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2560 } \ 2561 } \ 2562 else if (GET_CODE (XEXP (X, 0)) == PLUS) \ 2563 { \ 2564 return (COSTS_N_INSNS (ix86_cost->lea) \ 2565 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \ 2566 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \ 2567 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2568 } \ 2569 } \ 2570 \ 2571 /* fall through */ \ 2572 case AND: \ 2573 case IOR: \ 2574 case XOR: \ 2575 case MINUS: \ 2576 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2577 return (COSTS_N_INSNS (ix86_cost->add) * 2 \ 2578 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \ 2579 << (GET_MODE (XEXP (X, 0)) != DImode)) \ 2580 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \ 2581 << (GET_MODE (XEXP (X, 1)) != DImode))); \ 2582 \ 2583 /* fall through */ \ 2584 case NEG: \ 2585 case NOT: \ 2586 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2587 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ 2588 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2589 \ 2590 egress_rtx_costs: \ 2591 break; 2592 2593 2594/* An expression giving the cost of an addressing mode that contains 2595 ADDRESS. If not defined, the cost is computed from the ADDRESS 2596 expression and the `CONST_COSTS' values. 2597 2598 For most CISC machines, the default cost is a good approximation 2599 of the true cost of the addressing mode. However, on RISC 2600 machines, all instructions normally have the same length and 2601 execution time. Hence all addresses will have equal costs. 2602 2603 In cases where more than one form of an address is known, the form 2604 with the lowest cost will be used. If multiple forms have the 2605 same, lowest, cost, the one that is the most complex will be used. 2606 2607 For example, suppose an address that is equal to the sum of a 2608 register and a constant is used twice in the same basic block. 2609 When this macro is not defined, the address will be computed in a 2610 register and memory references will be indirect through that 2611 register. On machines where the cost of the addressing mode 2612 containing the sum is no higher than that of a simple indirect 2613 reference, this will produce an additional instruction and 2614 possibly require an additional register. Proper specification of 2615 this macro eliminates this overhead for such machines. 2616 2617 Similar use of this macro is made in strength reduction of loops. 2618 2619 ADDRESS need not be valid as an address. In such a case, the cost 2620 is not relevant and can be any value; invalid addresses need not be 2621 assigned a different cost. 2622 2623 On machines where an address involving more than one register is as 2624 cheap as an address computation involving only one register, 2625 defining `ADDRESS_COST' to reflect this can cause two registers to 2626 be live over a region of code where only one would have been if 2627 `ADDRESS_COST' were not defined in that manner. This effect should 2628 be considered in the definition of this macro. Equivalent costs 2629 should probably only be given to addresses with different numbers 2630 of registers on machines with lots of registers. 2631 2632 This macro will normally either not be defined or be defined as a 2633 constant. 2634 2635 For i386, it is better to use a complex address than let gcc copy 2636 the address into a reg and make a new pseudo. But not if the address 2637 requires to two regs - that would mean more pseudos with longer 2638 lifetimes. */ 2639 2640#define ADDRESS_COST(RTX) \ 2641 ix86_address_cost (RTX) 2642 2643/* A C expression for the cost of moving data from a register in class FROM to 2644 one in class TO. The classes are expressed using the enumeration values 2645 such as `GENERAL_REGS'. A value of 2 is the default; other values are 2646 interpreted relative to that. 2647 2648 It is not required that the cost always equal 2 when FROM is the same as TO; 2649 on some machines it is expensive to move between registers if they are not 2650 general registers. */ 2651 2652#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2653 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 2654 2655/* A C expression for the cost of moving data of mode M between a 2656 register and memory. A value of 2 is the default; this cost is 2657 relative to those in `REGISTER_MOVE_COST'. 2658 2659 If moving between registers and memory is more expensive than 2660 between two registers, you should define this macro to express the 2661 relative cost. */ 2662 2663#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 2664 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 2665 2666/* A C expression for the cost of a branch instruction. A value of 1 2667 is the default; other values are interpreted relative to that. */ 2668 2669#define BRANCH_COST ix86_branch_cost 2670 2671/* Define this macro as a C expression which is nonzero if accessing 2672 less than a word of memory (i.e. a `char' or a `short') is no 2673 faster than accessing a word of memory, i.e., if such access 2674 require more than one instruction or if there is no difference in 2675 cost between byte and (aligned) word loads. 2676 2677 When this macro is not defined, the compiler will access a field by 2678 finding the smallest containing object; when it is defined, a 2679 fullword load will be used if alignment permits. Unless bytes 2680 accesses are faster than word accesses, using word accesses is 2681 preferable since it may eliminate subsequent memory access if 2682 subsequent accesses occur to other fields in the same word of the 2683 structure, but to different bytes. */ 2684 2685#define SLOW_BYTE_ACCESS 0 2686 2687/* Nonzero if access to memory by shorts is slow and undesirable. */ 2688#define SLOW_SHORT_ACCESS 0 2689 2690/* Define this macro to be the value 1 if unaligned accesses have a 2691 cost many times greater than aligned accesses, for example if they 2692 are emulated in a trap handler. 2693 2694 When this macro is non-zero, the compiler will act as if 2695 `STRICT_ALIGNMENT' were non-zero when generating code for block 2696 moves. This can cause significantly more instructions to be 2697 produced. Therefore, do not set this macro non-zero if unaligned 2698 accesses only add a cycle or two to the time for a memory access. 2699 2700 If the value of this macro is always zero, it need not be defined. */ 2701 2702/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2703 2704/* Define this macro to inhibit strength reduction of memory 2705 addresses. (On some machines, such strength reduction seems to do 2706 harm rather than good.) */ 2707 2708/* #define DONT_REDUCE_ADDR */ 2709 2710/* Define this macro if it is as good or better to call a constant 2711 function address than to call an address kept in a register. 2712 2713 Desirable on the 386 because a CALL with a constant address is 2714 faster than one with a register address. */ 2715 2716#define NO_FUNCTION_CSE 2717 2718/* Define this macro if it is as good or better for a function to call 2719 itself with an explicit address than to call an address kept in a 2720 register. */ 2721 2722#define NO_RECURSIVE_FUNCTION_CSE 2723 2724/* Add any extra modes needed to represent the condition code. 2725 2726 For the i386, we need separate modes when floating-point 2727 equality comparisons are being done. 2728 2729 Add CCNO to indicate comparisons against zero that requires 2730 Overflow flag to be unset. Sign bit test is used instead and 2731 thus can be used to form "a&b>0" type of tests. 2732 2733 Add CCGC to indicate comparisons agains zero that allows 2734 unspecified garbage in the Carry flag. This mode is used 2735 by inc/dec instructions. 2736 2737 Add CCGOC to indicate comparisons agains zero that allows 2738 unspecified garbage in the Carry and Overflow flag. This 2739 mode is used to simulate comparisons of (a-b) and (a+b) 2740 against zero using sub/cmp/add operations. 2741 2742 Add CCZ to indicate that only the Zero flag is valid. */ 2743 2744#define EXTRA_CC_MODES \ 2745 CC (CCGCmode, "CCGC") \ 2746 CC (CCGOCmode, "CCGOC") \ 2747 CC (CCNOmode, "CCNO") \ 2748 CC (CCZmode, "CCZ") \ 2749 CC (CCFPmode, "CCFP") \ 2750 CC (CCFPUmode, "CCFPU") 2751 2752/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2753 return the mode to be used for the comparison. 2754 2755 For floating-point equality comparisons, CCFPEQmode should be used. 2756 VOIDmode should be used in all other cases. 2757 2758 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2759 possible, to allow for more combinations. */ 2760 2761#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2762 2763/* Return non-zero if MODE implies a floating point inequality can be 2764 reversed. */ 2765 2766#define REVERSIBLE_CC_MODE(MODE) 1 2767 2768/* A C expression whose value is reversed condition code of the CODE for 2769 comparison done in CC_MODE mode. */ 2770#define REVERSE_CONDITION(CODE, MODE) \ 2771 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ 2772 : reverse_condition_maybe_unordered (CODE)) 2773 2774 2775/* Control the assembler format that we output, to the extent 2776 this does not vary between assemblers. */ 2777 2778/* How to refer to registers in assembler output. 2779 This sequence is indexed by compiler's hard-register-number (see above). */ 2780 2781/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" 2782 For non floating point regs, the following are the HImode names. 2783 2784 For float regs, the stack top is sometimes referred to as "%st(0)" 2785 instead of just "%st". PRINT_REG handles this with the "y" code. */ 2786 2787#undef HI_REGISTER_NAMES 2788#define HI_REGISTER_NAMES \ 2789{"ax","dx","cx","bx","si","di","bp","sp", \ 2790 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ 2791 "flags","fpsr", "dirflag", "frame", \ 2792 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2793 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 2794 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2795 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 2796 2797#define REGISTER_NAMES HI_REGISTER_NAMES 2798 2799/* Table of additional register names to use in user input. */ 2800 2801#define ADDITIONAL_REGISTER_NAMES \ 2802{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2803 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2804 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2805 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2806 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2807 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2808 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ 2809 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } 2810 2811/* Note we are omitting these since currently I don't know how 2812to get gcc to use these, since they want the same but different 2813number as al, and ax. 2814*/ 2815 2816#define QI_REGISTER_NAMES \ 2817{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2818 2819/* These parallel the array above, and can be used to access bits 8:15 2820 of regs 0 through 3. */ 2821 2822#define QI_HIGH_REGISTER_NAMES \ 2823{"ah", "dh", "ch", "bh", } 2824 2825/* How to renumber registers for dbx and gdb. */ 2826 2827#define DBX_REGISTER_NUMBER(N) \ 2828 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2829 2830extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2831extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2832extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2833 2834/* Before the prologue, RA is at 0(%esp). */ 2835#define INCOMING_RETURN_ADDR_RTX \ 2836 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2837 2838/* After the prologue, RA is at -4(AP) in the current frame. */ 2839#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2840 ((COUNT) == 0 \ 2841 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2842 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2843 2844/* PC is dbx register 8; let's use that column for RA. */ 2845#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2846 2847/* Before the prologue, the top of the frame is at 4(%esp). */ 2848#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2849 2850/* Describe how we implement __builtin_eh_return. */ 2851#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2852#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2853 2854 2855/* Select a format to encode pointers in exception handling data. CODE 2856 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2857 true if the symbol may be affected by dynamic relocations. 2858 2859 ??? All x86 object file formats are capable of representing this. 2860 After all, the relocation needed is the same as for the call insn. 2861 Whether or not a particular assembler allows us to enter such, I 2862 guess we'll have to see. */ 2863#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2864 (flag_pic \ 2865 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 2866 : DW_EH_PE_absptr) 2867 2868/* This is how to output the definition of a user-level label named NAME, 2869 such as the label on a static function or variable NAME. */ 2870 2871#define ASM_OUTPUT_LABEL(FILE, NAME) \ 2872 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE))) 2873 2874/* Store in OUTPUT a string (made with alloca) containing 2875 an assembler-name for a local static variable named NAME. 2876 LABELNO is an integer which is different for each call. */ 2877 2878#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2879( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2880 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2881 2882/* This is how to output an insn to push a register on the stack. 2883 It need not be very fast code. */ 2884 2885#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2886 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]) 2887 2888/* This is how to output an insn to pop a register from the stack. 2889 It need not be very fast code. */ 2890 2891#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2892 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]) 2893 2894/* This is how to output an element of a case-vector that is absolute. */ 2895 2896#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2897 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2898 2899/* This is how to output an element of a case-vector that is relative. */ 2900 2901#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2902 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2903 2904/* Under some conditions we need jump tables in the text section, because 2905 the assembler cannot handle label differences between sections. */ 2906 2907#define JUMP_TABLES_IN_TEXT_SECTION \ 2908 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 2909 2910/* A C statement that outputs an address constant appropriate to 2911 for DWARF debugging. */ 2912 2913#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ 2914 i386_dwarf_output_addr_const ((FILE), (X)) 2915 2916/* Either simplify a location expression, or return the original. */ 2917 2918#define ASM_SIMPLIFY_DWARF_ADDR(X) \ 2919 i386_simplify_dwarf_addr (X) 2920 2921/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2922 and switch back. For x86 we do this only to save a few bytes that 2923 would otherwise be unused in the text section. */ 2924#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2925 asm (SECTION_OP "\n\t" \ 2926 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2927 TEXT_SECTION_ASM_OP); 2928 2929/* Print operand X (an rtx) in assembler syntax to file FILE. 2930 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2931 Effect of various CODE letters is described in i386.c near 2932 print_operand function. */ 2933 2934#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2935 ((CODE) == '*' || (CODE) == '+') 2936 2937/* Print the name of a register based on its machine mode and number. 2938 If CODE is 'w', pretend the mode is HImode. 2939 If CODE is 'b', pretend the mode is QImode. 2940 If CODE is 'k', pretend the mode is SImode. 2941 If CODE is 'q', pretend the mode is DImode. 2942 If CODE is 'h', pretend the reg is the `high' byte register. 2943 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ 2944 2945#define PRINT_REG(X, CODE, FILE) \ 2946 print_reg ((X), (CODE), (FILE)) 2947 2948#define PRINT_OPERAND(FILE, X, CODE) \ 2949 print_operand ((FILE), (X), (CODE)) 2950 2951#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2952 print_operand_address ((FILE), (ADDR)) 2953 2954/* Print the name of a register for based on its machine mode and number. 2955 This macro is used to print debugging output. 2956 This macro is different from PRINT_REG in that it may be used in 2957 programs that are not linked with aux-output.o. */ 2958 2959#define DEBUG_PRINT_REG(X, CODE, FILE) \ 2960 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ 2961 static const char * const qi_name[] = QI_REGISTER_NAMES; \ 2962 fprintf ((FILE), "%d ", REGNO (X)); \ 2963 if (REGNO (X) == FLAGS_REG) \ 2964 { fputs ("flags", (FILE)); break; } \ 2965 if (REGNO (X) == DIRFLAG_REG) \ 2966 { fputs ("dirflag", (FILE)); break; } \ 2967 if (REGNO (X) == FPSR_REG) \ 2968 { fputs ("fpsr", (FILE)); break; } \ 2969 if (REGNO (X) == ARG_POINTER_REGNUM) \ 2970 { fputs ("argp", (FILE)); break; } \ 2971 if (REGNO (X) == FRAME_POINTER_REGNUM) \ 2972 { fputs ("frame", (FILE)); break; } \ 2973 if (STACK_TOP_P (X)) \ 2974 { fputs ("st(0)", (FILE)); break; } \ 2975 if (FP_REG_P (X)) \ 2976 { fputs (hi_name[REGNO(X)], (FILE)); break; } \ 2977 if (REX_INT_REG_P (X)) \ 2978 { \ 2979 switch (GET_MODE_SIZE (GET_MODE (X))) \ 2980 { \ 2981 default: \ 2982 case 8: \ 2983 fprintf ((FILE), "r%i", REGNO (X) \ 2984 - FIRST_REX_INT_REG + 8); \ 2985 break; \ 2986 case 4: \ 2987 fprintf ((FILE), "r%id", REGNO (X) \ 2988 - FIRST_REX_INT_REG + 8); \ 2989 break; \ 2990 case 2: \ 2991 fprintf ((FILE), "r%iw", REGNO (X) \ 2992 - FIRST_REX_INT_REG + 8); \ 2993 break; \ 2994 case 1: \ 2995 fprintf ((FILE), "r%ib", REGNO (X) \ 2996 - FIRST_REX_INT_REG + 8); \ 2997 break; \ 2998 } \ 2999 break; \ 3000 } \ 3001 switch (GET_MODE_SIZE (GET_MODE (X))) \ 3002 { \ 3003 case 8: \ 3004 fputs ("r", (FILE)); \ 3005 fputs (hi_name[REGNO (X)], (FILE)); \ 3006 break; \ 3007 default: \ 3008 fputs ("e", (FILE)); \ 3009 case 2: \ 3010 fputs (hi_name[REGNO (X)], (FILE)); \ 3011 break; \ 3012 case 1: \ 3013 fputs (qi_name[REGNO (X)], (FILE)); \ 3014 break; \ 3015 } \ 3016 } while (0) 3017 3018/* a letter which is not needed by the normal asm syntax, which 3019 we can use for operand syntax in the extended asm */ 3020 3021#define ASM_OPERAND_LETTER '#' 3022#define RET return "" 3023#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 3024 3025/* Define the codes that are matched by predicates in i386.c. */ 3026 3027#define PREDICATE_CODES \ 3028 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ 3029 SYMBOL_REF, LABEL_REF, CONST}}, \ 3030 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3031 SYMBOL_REF, LABEL_REF, CONST}}, \ 3032 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ 3033 SYMBOL_REF, LABEL_REF, CONST}}, \ 3034 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3035 SYMBOL_REF, LABEL_REF, CONST}}, \ 3036 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3037 SYMBOL_REF, LABEL_REF, CONST}}, \ 3038 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3039 SYMBOL_REF, LABEL_REF, CONST}}, \ 3040 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3041 SYMBOL_REF, LABEL_REF}}, \ 3042 {"shiftdi_operand", {SUBREG, REG, MEM}}, \ 3043 {"const_int_1_operand", {CONST_INT}}, \ 3044 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 3045 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3046 LABEL_REF, SUBREG, REG, MEM}}, \ 3047 {"pic_symbolic_operand", {CONST}}, \ 3048 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ 3049 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ 3050 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ 3051 {"const1_operand", {CONST_INT}}, \ 3052 {"const248_operand", {CONST_INT}}, \ 3053 {"incdec_operand", {CONST_INT}}, \ 3054 {"mmx_reg_operand", {REG}}, \ 3055 {"reg_no_sp_operand", {SUBREG, REG}}, \ 3056 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3057 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ 3058 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ 3059 {"q_regs_operand", {SUBREG, REG}}, \ 3060 {"non_q_regs_operand", {SUBREG, REG}}, \ 3061 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ 3062 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ 3063 GE, UNGE, LTGT, UNEQ}}, \ 3064 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ 3065 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ 3066 }}, \ 3067 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ 3068 GTU, UNORDERED, ORDERED, UNLE, UNLT, \ 3069 UNGE, UNGT, LTGT, UNEQ }}, \ 3070 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ 3071 {"ext_register_operand", {SUBREG, REG}}, \ 3072 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ 3073 {"mult_operator", {MULT}}, \ 3074 {"div_operator", {DIV}}, \ 3075 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ 3076 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ 3077 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ 3078 LSHIFTRT, ROTATERT}}, \ 3079 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ 3080 {"memory_displacement_operand", {MEM}}, \ 3081 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3082 LABEL_REF, SUBREG, REG, MEM, AND}}, \ 3083 {"long_memory_operand", {MEM}}, 3084 3085/* A list of predicates that do special things with modes, and so 3086 should not elicit warnings for VOIDmode match_operand. */ 3087 3088#define SPECIAL_MODE_PREDICATES \ 3089 "ext_register_operand", 3090 3091/* CM_32 is used by 32bit ABI 3092 CM_SMALL is small model assuming that all code and data fits in the first 3093 31bits of address space. 3094 CM_KERNEL is model assuming that all code and data fits in the negative 3095 31bits of address space. 3096 CM_MEDIUM is model assuming that code fits in the first 31bits of address 3097 space. Size of data is unlimited. 3098 CM_LARGE is model making no assumptions about size of particular sections. 3099 3100 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt 3101 tables first in 31bits of address space. 3102 */ 3103enum cmodel { 3104 CM_32, 3105 CM_SMALL, 3106 CM_KERNEL, 3107 CM_MEDIUM, 3108 CM_LARGE, 3109 CM_SMALL_PIC 3110}; 3111 3112/* Size of the RED_ZONE area. */ 3113#define RED_ZONE_SIZE 128 3114/* Reserved area of the red zone for temporaries. */ 3115#define RED_ZONE_RESERVE 8 3116extern const char *ix86_debug_arg_string, *ix86_debug_addr_string; 3117 3118enum asm_dialect { 3119 ASM_ATT, 3120 ASM_INTEL 3121}; 3122extern const char *ix86_asm_string; 3123extern enum asm_dialect ix86_asm_dialect; 3124/* Value of -mcmodel specified by user. */ 3125extern const char *ix86_cmodel_string; 3126extern enum cmodel ix86_cmodel; 3127 3128/* Variables in i386.c */ 3129extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */ 3130extern const char *ix86_arch_string; /* for -march=<xxx> */ 3131extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */ 3132extern const char *ix86_regparm_string; /* # registers to use to pass args */ 3133extern const char *ix86_align_loops_string; /* power of two alignment for loops */ 3134extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */ 3135extern const char *ix86_align_funcs_string; /* power of two alignment for functions */ 3136extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */ 3137extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */ 3138extern int ix86_regparm; /* ix86_regparm_string as a number */ 3139extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */ 3140extern int ix86_branch_cost; /* values 1-5: see jump.c */ 3141extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */ 3142extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 3143extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 3144 3145/* To properly truncate FP values into integers, we need to set i387 control 3146 word. We can't emit proper mode switching code before reload, as spills 3147 generated by reload may truncate values incorrectly, but we still can avoid 3148 redundant computation of new control word by the mode switching pass. 3149 The fldcw instructions are still emitted redundantly, but this is probably 3150 not going to be noticeable problem, as most CPUs do have fast path for 3151 the sequence. 3152 3153 The machinery is to emit simple truncation instructions and split them 3154 before reload to instructions having USEs of two memory locations that 3155 are filled by this code to old and new control word. 3156 3157 Post-reload pass may be later used to eliminate the redundant fildcw if 3158 needed. */ 3159 3160enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; 3161 3162/* Define this macro if the port needs extra instructions inserted 3163 for mode switching in an optimizing compilation. */ 3164 3165#define OPTIMIZE_MODE_SWITCHING(ENTITY) 1 3166 3167/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 3168 initializer for an array of integers. Each initializer element N 3169 refers to an entity that needs mode switching, and specifies the 3170 number of different modes that might need to be set for this 3171 entity. The position of the initializer in the initializer - 3172 starting counting at zero - determines the integer that is used to 3173 refer to the mode-switched entity in question. */ 3174 3175#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } 3176 3177/* ENTITY is an integer specifying a mode-switched entity. If 3178 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 3179 return an integer value not larger than the corresponding element 3180 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 3181 must be switched into prior to the execution of INSN. */ 3182 3183#define MODE_NEEDED(ENTITY, I) \ 3184 (GET_CODE (I) == CALL_INSN \ 3185 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ 3186 || GET_CODE (PATTERN (I)) == ASM_INPUT))\ 3187 ? FP_CW_UNINITIALIZED \ 3188 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ 3189 ? FP_CW_ANY \ 3190 : FP_CW_STORED) 3191 3192/* This macro specifies the order in which modes for ENTITY are 3193 processed. 0 is the highest priority. */ 3194 3195#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 3196 3197/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 3198 is the set of hard registers live at the point where the insn(s) 3199 are to be inserted. */ 3200 3201#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3202 ((MODE) == FP_CW_STORED \ 3203 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ 3204 assign_386_stack_local (HImode, 2)), 0\ 3205 : 0) 3206 3207/* Avoid renaming of stack registers, as doing so in combination with 3208 scheduling just increases amount of live registers at time and in 3209 the turn amount of fxch instructions needed. 3210 3211 ??? Maybe Pentium chips benefits from renaming, someone can try... */ 3212 3213#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 3214 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 3215 3216 3217/* 3218Local variables: 3219version-control: t 3220End: 3221*/ 3222