i386.h revision 302408
1/* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GCC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to 19the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20Boston, MA 02110-1301, USA. */ 21 22/* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37/* Define the specific costs for a given cpu */ 38 39struct processor_costs { 40 const int add; /* cost of an add instruction */ 41 const int lea; /* cost of a lea instruction */ 42 const int shift_var; /* variable shift costs */ 43 const int shift_const; /* constant shift costs */ 44 const int mult_init[5]; /* cost of starting a multiply 45 in QImode, HImode, SImode, DImode, TImode*/ 46 const int mult_bit; /* cost of multiply per each bit set */ 47 const int divide[5]; /* cost of a divide/mod 48 in QImode, HImode, SImode, DImode, TImode*/ 49 int movsx; /* The cost of movsx operation. */ 50 int movzx; /* The cost of movzx operation. */ 51 const int large_insn; /* insns larger than this cost more */ 52 const int move_ratio; /* The threshold of number of scalar 53 memory-to-memory move insns. */ 54 const int movzbl_load; /* cost of loading using movzbl */ 55 const int int_load[3]; /* cost of loading integer registers 56 in QImode, HImode and SImode relative 57 to reg-reg move (2). */ 58 const int int_store[3]; /* cost of storing integer register 59 in QImode, HImode and SImode */ 60 const int fp_move; /* cost of reg,reg fld/fst */ 61 const int fp_load[3]; /* cost of loading FP register 62 in SFmode, DFmode and XFmode */ 63 const int fp_store[3]; /* cost of storing FP register 64 in SFmode, DFmode and XFmode */ 65 const int mmx_move; /* cost of moving MMX register. */ 66 const int mmx_load[2]; /* cost of loading MMX register 67 in SImode and DImode */ 68 const int mmx_store[2]; /* cost of storing MMX register 69 in SImode and DImode */ 70 const int sse_move; /* cost of moving SSE register. */ 71 const int sse_load[3]; /* cost of loading SSE register 72 in SImode, DImode and TImode*/ 73 const int sse_store[3]; /* cost of storing SSE register 74 in SImode, DImode and TImode*/ 75 const int mmxsse_to_integer; /* cost of moving mmxsse register to 76 integer and vice versa. */ 77 const int prefetch_block; /* bytes moved to cache for prefetch. */ 78 const int simultaneous_prefetches; /* number of parallel prefetch 79 operations. */ 80 const int branch_cost; /* Default value for BRANCH_COST. */ 81 const int fadd; /* cost of FADD and FSUB instructions. */ 82 const int fmul; /* cost of FMUL instruction. */ 83 const int fdiv; /* cost of FDIV instruction. */ 84 const int fabs; /* cost of FABS instruction. */ 85 const int fchs; /* cost of FCHS instruction. */ 86 const int fsqrt; /* cost of FSQRT instruction. */ 87}; 88 89extern const struct processor_costs *ix86_cost; 90 91/* Macros used in the machine description to test the flags. */ 92 93/* configure can arrange to make this 2, to force a 486. */ 94 95#ifndef TARGET_CPU_DEFAULT 96#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic 97#endif 98 99#ifndef TARGET_FPMATH_DEFAULT 100#define TARGET_FPMATH_DEFAULT \ 101 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 102#endif 103 104#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 105 106/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 107 compile-time constant. */ 108#ifdef IN_LIBGCC2 109#undef TARGET_64BIT 110#ifdef __x86_64__ 111#define TARGET_64BIT 1 112#else 113#define TARGET_64BIT 0 114#endif 115#else 116#ifndef TARGET_BI_ARCH 117#undef TARGET_64BIT 118#if TARGET_64BIT_DEFAULT 119#define TARGET_64BIT 1 120#else 121#define TARGET_64BIT 0 122#endif 123#endif 124#endif 125 126#define HAS_LONG_COND_BRANCH 1 127#define HAS_LONG_UNCOND_BRANCH 1 128 129#define TARGET_386 (ix86_tune == PROCESSOR_I386) 130#define TARGET_486 (ix86_tune == PROCESSOR_I486) 131#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 132#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 133#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 134#define TARGET_K6 (ix86_tune == PROCESSOR_K6) 135#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 136#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 137#define TARGET_K8 (ix86_tune == PROCESSOR_K8) 138#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 139#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 140#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 141#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) 142#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) 143#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) 144#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 145 146#define TUNEMASK (1 << ix86_tune) 147extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 148extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 149extern const int x86_branch_hints, x86_unroll_strlen; 150extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 151extern const int x86_use_himode_fiop, x86_use_simode_fiop; 152extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write; 153extern const int x86_read_modify, x86_split_long_moves; 154extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; 155extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 156extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 157extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 158extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 159extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 160extern const int x86_epilogue_using_move, x86_decompose_lea; 161extern const int x86_arch_always_fancy_math_387, x86_shift1; 162extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs; 163extern const int x86_sse_unaligned_move_optimal; 164extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; 165extern const int x86_use_ffreep; 166extern const int x86_inter_unit_moves, x86_schedule; 167extern const int x86_use_bt; 168extern const int x86_cmpxchg, x86_cmpxchg8b, x86_xadd; 169extern const int x86_use_incdec; 170extern const int x86_pad_returns; 171extern const int x86_bswap; 172extern const int x86_partial_flag_reg_stall; 173extern int x86_prefetch_sse, x86_cmpxchg16b; 174 175#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) 176#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) 177#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK) 178#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK) 179#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK) 180/* For sane SSE instruction set generation we need fcomi instruction. It is 181 safe to enable all CMOVE instructions. */ 182#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 183#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 184#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK) 185#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK) 186#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK) 187#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) 188#define TARGET_MOVX (x86_movx & TUNEMASK) 189#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) 190#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK) 191#define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK) 192#define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK) 193#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) 194#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK) 195#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK) 196#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK) 197#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK) 198#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK) 199#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK) 200#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK) 201#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK) 202#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK) 203#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK) 204#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK) 205#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK) 206#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK) 207#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK) 208#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK) 209#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK) 210#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) 211#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 212 (x86_sse_partial_reg_dependency & TUNEMASK) 213#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \ 214 (x86_sse_unaligned_move_optimal & TUNEMASK) 215#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK) 216#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) 217#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) 218#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) 219#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK) 220#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK) 221#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 222#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK) 223#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK) 224#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK) 225#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK) 226#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK) 227#define TARGET_SCHEDULE (x86_schedule & TUNEMASK) 228#define TARGET_USE_BT (x86_use_bt & TUNEMASK) 229#define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK) 230#define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK) 231 232#define ASSEMBLER_DIALECT (ix86_asm_dialect) 233 234#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 235#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 236 && (ix86_fpmath & FPMATH_387)) 237 238#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 239#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 240#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 241#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) 242 243#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch)) 244#define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch)) 245#define TARGET_CMPXCHG16B (x86_cmpxchg16b) 246#define TARGET_XADD (x86_xadd & (1 << ix86_arch)) 247#define TARGET_BSWAP (x86_bswap & (1 << ix86_arch)) 248 249#ifndef TARGET_64BIT_DEFAULT 250#define TARGET_64BIT_DEFAULT 0 251#endif 252#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 253#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 254#endif 255 256/* Once GDB has been enhanced to deal with functions without frame 257 pointers, we can change this to allow for elimination of 258 the frame pointer in leaf functions. */ 259#define TARGET_DEFAULT 0 260 261/* This is not really a target flag, but is done this way so that 262 it's analogous to similar code for Mach-O on PowerPC. darwin.h 263 redefines this to 1. */ 264#define TARGET_MACHO 0 265 266/* Subtargets may reset this to 1 in order to enable 96-bit long double 267 with the rounding mode forced to 53 bits. */ 268#define TARGET_96_ROUND_53_LONG_DOUBLE 0 269 270/* Sometimes certain combinations of command options do not make 271 sense on a particular target machine. You can define a macro 272 `OVERRIDE_OPTIONS' to take account of this. This macro, if 273 defined, is executed once just after all the command options have 274 been parsed. 275 276 Don't use this macro to turn on various extra optimizations for 277 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 278 279#define OVERRIDE_OPTIONS override_options () 280 281/* Define this to change the optimizations performed by default. */ 282#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 283 optimization_options ((LEVEL), (SIZE)) 284 285/* -march=native handling only makes sense with compiler running on 286 an x86 or x86_64 chip. If changing this condition, also change 287 the condition in driver-i386.c. */ 288#if defined(__i386__) || defined(__x86_64__) 289/* In driver-i386.c. */ 290extern const char *host_detect_local_cpu (int argc, const char **argv); 291#define EXTRA_SPEC_FUNCTIONS \ 292 { "local_cpu_detect", host_detect_local_cpu }, 293#define HAVE_LOCAL_CPU_DETECT 294#endif 295 296/* Support for configure-time defaults of some command line options. 297 The order here is important so that -march doesn't squash the 298 tune or cpu values. */ 299#define OPTION_DEFAULT_SPECS \ 300 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 301 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 302 {"arch", "%{!march=*:-march=%(VALUE)}"} 303 304/* Specs for the compiler proper */ 305 306#ifndef CC1_CPU_SPEC 307#define CC1_CPU_SPEC_1 "\ 308%{!mtune*: \ 309%{m386:mtune=i386 \ 310%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \ 311%{m486:-mtune=i486 \ 312%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \ 313%{mpentium:-mtune=pentium \ 314%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \ 315%{mpentiumpro:-mtune=pentiumpro \ 316%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \ 317%{mcpu=*:-mtune=%* \ 318%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \ 319%<mcpu=* \ 320%{mintel-syntax:-masm=intel \ 321%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 322%{mno-intel-syntax:-masm=att \ 323%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 324 325#ifndef HAVE_LOCAL_CPU_DETECT 326#define CC1_CPU_SPEC CC1_CPU_SPEC_1 327#else 328#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 329"%{march=native:%<march=native %:local_cpu_detect(arch) \ 330 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ 331%{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 332#endif 333#endif 334 335/* Target CPU builtins. */ 336#define TARGET_CPU_CPP_BUILTINS() \ 337 do \ 338 { \ 339 size_t arch_len = strlen (ix86_arch_string); \ 340 size_t tune_len = strlen (ix86_tune_string); \ 341 int last_arch_char = ix86_arch_string[arch_len - 1]; \ 342 int last_tune_char = ix86_tune_string[tune_len - 1]; \ 343 \ 344 if (TARGET_64BIT) \ 345 { \ 346 builtin_assert ("cpu=x86_64"); \ 347 builtin_assert ("machine=x86_64"); \ 348 builtin_define ("__amd64"); \ 349 builtin_define ("__amd64__"); \ 350 builtin_define ("__x86_64"); \ 351 builtin_define ("__x86_64__"); \ 352 } \ 353 else \ 354 { \ 355 builtin_assert ("cpu=i386"); \ 356 builtin_assert ("machine=i386"); \ 357 builtin_define_std ("i386"); \ 358 } \ 359 \ 360 /* Built-ins based on -mtune= (or -march= if no \ 361 -mtune= given). */ \ 362 if (TARGET_386) \ 363 builtin_define ("__tune_i386__"); \ 364 else if (TARGET_486) \ 365 builtin_define ("__tune_i486__"); \ 366 else if (TARGET_PENTIUM) \ 367 { \ 368 builtin_define ("__tune_i586__"); \ 369 builtin_define ("__tune_pentium__"); \ 370 if (last_tune_char == 'x') \ 371 builtin_define ("__tune_pentium_mmx__"); \ 372 } \ 373 else if (TARGET_PENTIUMPRO) \ 374 { \ 375 builtin_define ("__tune_i686__"); \ 376 builtin_define ("__tune_pentiumpro__"); \ 377 switch (last_tune_char) \ 378 { \ 379 case '3': \ 380 builtin_define ("__tune_pentium3__"); \ 381 /* FALLTHRU */ \ 382 case '2': \ 383 builtin_define ("__tune_pentium2__"); \ 384 break; \ 385 } \ 386 } \ 387 else if (TARGET_GEODE) \ 388 { \ 389 builtin_define ("__tune_geode__"); \ 390 } \ 391 else if (TARGET_K6) \ 392 { \ 393 builtin_define ("__tune_k6__"); \ 394 if (last_tune_char == '2') \ 395 builtin_define ("__tune_k6_2__"); \ 396 else if (last_tune_char == '3') \ 397 builtin_define ("__tune_k6_3__"); \ 398 } \ 399 else if (TARGET_ATHLON) \ 400 { \ 401 builtin_define ("__tune_athlon__"); \ 402 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \ 403 if (last_tune_char != 'n' && last_tune_char != 'd') \ 404 builtin_define ("__tune_athlon_sse__"); \ 405 } \ 406 else if (TARGET_K8) \ 407 builtin_define ("__tune_k8__"); \ 408 else if (TARGET_AMDFAM10) \ 409 builtin_define ("__tune_amdfam10__"); \ 410 else if (TARGET_PENTIUM4) \ 411 builtin_define ("__tune_pentium4__"); \ 412 else if (TARGET_NOCONA) \ 413 builtin_define ("__tune_nocona__"); \ 414 else if (TARGET_CORE2) \ 415 builtin_define ("__tune_core2__"); \ 416 \ 417 if (TARGET_MMX) \ 418 builtin_define ("__MMX__"); \ 419 if (TARGET_3DNOW) \ 420 builtin_define ("__3dNOW__"); \ 421 if (TARGET_3DNOW_A) \ 422 builtin_define ("__3dNOW_A__"); \ 423 if (TARGET_SSE) \ 424 builtin_define ("__SSE__"); \ 425 if (TARGET_SSE2) \ 426 builtin_define ("__SSE2__"); \ 427 if (TARGET_SSE3) \ 428 builtin_define ("__SSE3__"); \ 429 if (TARGET_SSSE3) \ 430 builtin_define ("__SSSE3__"); \ 431 if (TARGET_SSE4A) \ 432 builtin_define ("__SSE4A__"); \ 433 if (TARGET_AES) \ 434 builtin_define ("__AES__"); \ 435 if (TARGET_SSE_MATH && TARGET_SSE) \ 436 builtin_define ("__SSE_MATH__"); \ 437 if (TARGET_SSE_MATH && TARGET_SSE2) \ 438 builtin_define ("__SSE2_MATH__"); \ 439 \ 440 /* Built-ins based on -march=. */ \ 441 if (ix86_arch == PROCESSOR_I486) \ 442 { \ 443 builtin_define ("__i486"); \ 444 builtin_define ("__i486__"); \ 445 } \ 446 else if (ix86_arch == PROCESSOR_PENTIUM) \ 447 { \ 448 builtin_define ("__i586"); \ 449 builtin_define ("__i586__"); \ 450 builtin_define ("__pentium"); \ 451 builtin_define ("__pentium__"); \ 452 if (last_arch_char == 'x') \ 453 builtin_define ("__pentium_mmx__"); \ 454 } \ 455 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ 456 { \ 457 builtin_define ("__i686"); \ 458 builtin_define ("__i686__"); \ 459 builtin_define ("__pentiumpro"); \ 460 builtin_define ("__pentiumpro__"); \ 461 } \ 462 else if (ix86_arch == PROCESSOR_GEODE) \ 463 { \ 464 builtin_define ("__geode"); \ 465 builtin_define ("__geode__"); \ 466 } \ 467 else if (ix86_arch == PROCESSOR_K6) \ 468 { \ 469 \ 470 builtin_define ("__k6"); \ 471 builtin_define ("__k6__"); \ 472 if (last_arch_char == '2') \ 473 builtin_define ("__k6_2__"); \ 474 else if (last_arch_char == '3') \ 475 builtin_define ("__k6_3__"); \ 476 } \ 477 else if (ix86_arch == PROCESSOR_ATHLON) \ 478 { \ 479 builtin_define ("__athlon"); \ 480 builtin_define ("__athlon__"); \ 481 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \ 482 if (last_tune_char != 'n' && last_tune_char != 'd') \ 483 builtin_define ("__athlon_sse__"); \ 484 } \ 485 else if (ix86_arch == PROCESSOR_K8) \ 486 { \ 487 builtin_define ("__k8"); \ 488 builtin_define ("__k8__"); \ 489 } \ 490 else if (ix86_arch == PROCESSOR_AMDFAM10) \ 491 { \ 492 builtin_define ("__amdfam10"); \ 493 builtin_define ("__amdfam10__"); \ 494 } \ 495 else if (ix86_arch == PROCESSOR_PENTIUM4) \ 496 { \ 497 builtin_define ("__pentium4"); \ 498 builtin_define ("__pentium4__"); \ 499 } \ 500 else if (ix86_arch == PROCESSOR_NOCONA) \ 501 { \ 502 builtin_define ("__nocona"); \ 503 builtin_define ("__nocona__"); \ 504 } \ 505 else if (ix86_arch == PROCESSOR_CORE2) \ 506 { \ 507 builtin_define ("__core2"); \ 508 builtin_define ("__core2__"); \ 509 } \ 510 } \ 511 while (0) 512 513#define TARGET_CPU_DEFAULT_i386 0 514#define TARGET_CPU_DEFAULT_i486 1 515#define TARGET_CPU_DEFAULT_pentium 2 516#define TARGET_CPU_DEFAULT_pentium_mmx 3 517#define TARGET_CPU_DEFAULT_pentiumpro 4 518#define TARGET_CPU_DEFAULT_pentium2 5 519#define TARGET_CPU_DEFAULT_pentium3 6 520#define TARGET_CPU_DEFAULT_pentium4 7 521#define TARGET_CPU_DEFAULT_geode 8 522#define TARGET_CPU_DEFAULT_k6 9 523#define TARGET_CPU_DEFAULT_k6_2 10 524#define TARGET_CPU_DEFAULT_k6_3 11 525#define TARGET_CPU_DEFAULT_athlon 12 526#define TARGET_CPU_DEFAULT_athlon_sse 13 527#define TARGET_CPU_DEFAULT_k8 14 528#define TARGET_CPU_DEFAULT_pentium_m 15 529#define TARGET_CPU_DEFAULT_prescott 16 530#define TARGET_CPU_DEFAULT_nocona 17 531#define TARGET_CPU_DEFAULT_core2 18 532#define TARGET_CPU_DEFAULT_generic 19 533#define TARGET_CPU_DEFAULT_amdfam10 20 534 535#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 536 "pentiumpro", "pentium2", "pentium3", \ 537 "pentium4", "geode", "k6", "k6-2", "k6-3", \ 538 "athlon", "athlon-4", "k8", \ 539 "pentium-m", "prescott", "nocona", \ 540 "core2", "generic", "amdfam10"} 541 542#ifndef CC1_SPEC 543#define CC1_SPEC "%(cc1_cpu) " 544#endif 545 546/* This macro defines names of additional specifications to put in the 547 specs that can be used in various specifications like CC1_SPEC. Its 548 definition is an initializer with a subgrouping for each command option. 549 550 Each subgrouping contains a string constant, that defines the 551 specification name, and a string constant that used by the GCC driver 552 program. 553 554 Do not define this macro if it does not need to do anything. */ 555 556#ifndef SUBTARGET_EXTRA_SPECS 557#define SUBTARGET_EXTRA_SPECS 558#endif 559 560#define EXTRA_SPECS \ 561 { "cc1_cpu", CC1_CPU_SPEC }, \ 562 SUBTARGET_EXTRA_SPECS 563 564/* target machine storage layout */ 565 566#define LONG_DOUBLE_TYPE_SIZE 80 567 568/* Set the value of FLT_EVAL_METHOD in float.h. When using only the 569 FPU, assume that the fpcw is set to extended precision; when using 570 only SSE, rounding is correct; when using both SSE and the FPU, 571 the rounding precision is indeterminate, since either may be chosen 572 apparently at random. */ 573#define TARGET_FLT_EVAL_METHOD \ 574 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 575 576#define SHORT_TYPE_SIZE 16 577#define INT_TYPE_SIZE 32 578#define FLOAT_TYPE_SIZE 32 579#ifndef LONG_TYPE_SIZE 580#define LONG_TYPE_SIZE BITS_PER_WORD 581#endif 582#define DOUBLE_TYPE_SIZE 64 583#define LONG_LONG_TYPE_SIZE 64 584 585#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 586#define MAX_BITS_PER_WORD 64 587#else 588#define MAX_BITS_PER_WORD 32 589#endif 590 591/* Define this if most significant byte of a word is the lowest numbered. */ 592/* That is true on the 80386. */ 593 594#define BITS_BIG_ENDIAN 0 595 596/* Define this if most significant byte of a word is the lowest numbered. */ 597/* That is not true on the 80386. */ 598#define BYTES_BIG_ENDIAN 0 599 600/* Define this if most significant word of a multiword number is the lowest 601 numbered. */ 602/* Not true for 80386 */ 603#define WORDS_BIG_ENDIAN 0 604 605/* Width of a word, in units (bytes). */ 606#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 607#ifdef IN_LIBGCC2 608#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 609#else 610#define MIN_UNITS_PER_WORD 4 611#endif 612 613/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 614#define PARM_BOUNDARY BITS_PER_WORD 615 616/* Boundary (in *bits*) on which stack pointer should be aligned. */ 617#define STACK_BOUNDARY BITS_PER_WORD 618 619/* Boundary (in *bits*) on which the stack pointer prefers to be 620 aligned; the compiler cannot rely on having this alignment. */ 621#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 622 623/* As of July 2001, many runtimes do not align the stack properly when 624 entering main. This causes expand_main_function to forcibly align 625 the stack, which results in aligned frames for functions called from 626 main, though it does nothing for the alignment of main itself. */ 627#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 628 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 629 630/* Minimum allocation boundary for the code of a function. */ 631#define FUNCTION_BOUNDARY 8 632 633/* C++ stores the virtual bit in the lowest bit of function pointers. */ 634#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 635 636/* Alignment of field after `int : 0' in a structure. */ 637 638#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 639 640/* Minimum size in bits of the largest boundary to which any 641 and all fundamental data types supported by the hardware 642 might need to be aligned. No data type wants to be aligned 643 rounder than this. 644 645 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 646 and Pentium Pro XFmode values at 128 bit boundaries. */ 647 648#define BIGGEST_ALIGNMENT 128 649 650/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 651#define ALIGN_MODE_128(MODE) \ 652 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 653 654/* The published ABIs say that doubles should be aligned on word 655 boundaries, so lower the alignment for structure fields unless 656 -malign-double is set. */ 657 658/* ??? Blah -- this macro is used directly by libobjc. Since it 659 supports no vector modes, cut out the complexity and fall back 660 on BIGGEST_FIELD_ALIGNMENT. */ 661#ifdef IN_TARGET_LIBS 662#ifdef __x86_64__ 663#define BIGGEST_FIELD_ALIGNMENT 128 664#else 665#define BIGGEST_FIELD_ALIGNMENT 32 666#endif 667#else 668#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 669 x86_field_alignment (FIELD, COMPUTED) 670#endif 671 672/* If defined, a C expression to compute the alignment given to a 673 constant that is being placed in memory. EXP is the constant 674 and ALIGN is the alignment that the object would ordinarily have. 675 The value of this macro is used instead of that alignment to align 676 the object. 677 678 If this macro is not defined, then ALIGN is used. 679 680 The typical use of this macro is to increase alignment for string 681 constants to be word aligned so that `strcpy' calls that copy 682 constants can be done inline. */ 683 684#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 685 686/* If defined, a C expression to compute the alignment for a static 687 variable. TYPE is the data type, and ALIGN is the alignment that 688 the object would ordinarily have. The value of this macro is used 689 instead of that alignment to align the object. 690 691 If this macro is not defined, then ALIGN is used. 692 693 One use of this macro is to increase alignment of medium-size 694 data to make it all fit in fewer cache lines. Another is to 695 cause character arrays to be word-aligned so that `strcpy' calls 696 that copy constants to character arrays can be done inline. */ 697 698#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 699 700/* If defined, a C expression to compute the alignment for a local 701 variable. TYPE is the data type, and ALIGN is the alignment that 702 the object would ordinarily have. The value of this macro is used 703 instead of that alignment to align the object. 704 705 If this macro is not defined, then ALIGN is used. 706 707 One use of this macro is to increase alignment of medium-size 708 data to make it all fit in fewer cache lines. */ 709 710#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 711 712/* If defined, a C expression that gives the alignment boundary, in 713 bits, of an argument with the specified mode and type. If it is 714 not defined, `PARM_BOUNDARY' is used for all arguments. */ 715 716#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 717 ix86_function_arg_boundary ((MODE), (TYPE)) 718 719/* Set this nonzero if move instructions will actually fail to work 720 when given unaligned data. */ 721#define STRICT_ALIGNMENT 0 722 723/* If bit field type is int, don't let it cross an int, 724 and give entire struct the alignment of an int. */ 725/* Required on the 386 since it doesn't have bit-field insns. */ 726#define PCC_BITFIELD_TYPE_MATTERS 1 727 728/* Standard register usage. */ 729 730/* This processor has special stack-like registers. See reg-stack.c 731 for details. */ 732 733#define STACK_REGS 734#define IS_STACK_MODE(MODE) \ 735 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ 736 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ 737 || (MODE) == XFmode) 738 739/* Number of actual hardware registers. 740 The hardware registers are assigned numbers for the compiler 741 from 0 to just below FIRST_PSEUDO_REGISTER. 742 All registers that the compiler knows about must be given numbers, 743 even those that are not normally considered general registers. 744 745 In the 80386 we give the 8 general purpose registers the numbers 0-7. 746 We number the floating point registers 8-15. 747 Note that registers 0-7 can be accessed as a short or int, 748 while only 0-3 may be used with byte `mov' instructions. 749 750 Reg 16 does not correspond to any hardware register, but instead 751 appears in the RTL as an argument pointer prior to reload, and is 752 eliminated during reloading in favor of either the stack or frame 753 pointer. */ 754 755#define FIRST_PSEUDO_REGISTER 53 756 757/* Number of hardware registers that go into the DWARF-2 unwind info. 758 If not defined, equals FIRST_PSEUDO_REGISTER. */ 759 760#define DWARF_FRAME_REGISTERS 17 761 762/* 1 for registers that have pervasive standard uses 763 and are not available for the register allocator. 764 On the 80386, the stack pointer is such, as is the arg pointer. 765 766 The value is zero if the register is not fixed on either 32 or 767 64 bit targets, one if the register if fixed on both 32 and 64 768 bit targets, two if it is only fixed on 32bit targets and three 769 if its only fixed on 64bit targets. 770 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 771 */ 772#define FIXED_REGISTERS \ 773/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 774{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 775/*arg,flags,fpsr,dir,frame*/ \ 776 1, 1, 1, 1, 1, \ 777/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 778 0, 0, 0, 0, 0, 0, 0, 0, \ 779/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 780 0, 0, 0, 0, 0, 0, 0, 0, \ 781/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 782 2, 2, 2, 2, 2, 2, 2, 2, \ 783/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 784 2, 2, 2, 2, 2, 2, 2, 2} 785 786 787/* 1 for registers not available across function calls. 788 These must include the FIXED_REGISTERS and also any 789 registers that can be used without being saved. 790 The latter must include the registers where values are returned 791 and the register where structure-value addresses are passed. 792 Aside from that, you can include as many other registers as you like. 793 794 The value is zero if the register is not call used on either 32 or 795 64 bit targets, one if the register if call used on both 32 and 64 796 bit targets, two if it is only call used on 32bit targets and three 797 if its only call used on 64bit targets. 798 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 799*/ 800#define CALL_USED_REGISTERS \ 801/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 802{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 803/*arg,flags,fpsr,dir,frame*/ \ 804 1, 1, 1, 1, 1, \ 805/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 806 1, 1, 1, 1, 1, 1, 1, 1, \ 807/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 808 1, 1, 1, 1, 1, 1, 1, 1, \ 809/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 810 1, 1, 1, 1, 2, 2, 2, 2, \ 811/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 812 1, 1, 1, 1, 1, 1, 1, 1} \ 813 814/* Order in which to allocate registers. Each register must be 815 listed once, even those in FIXED_REGISTERS. List frame pointer 816 late and fixed registers last. Note that, in general, we prefer 817 registers listed in CALL_USED_REGISTERS, keeping the others 818 available for storage of persistent values. 819 820 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 821 so this is just empty initializer for array. */ 822 823#define REG_ALLOC_ORDER \ 824{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 825 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 826 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 827 48, 49, 50, 51, 52 } 828 829/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 830 to be rearranged based on a particular function. When using sse math, 831 we want to allocate SSE before x87 registers and vice vera. */ 832 833#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 834 835 836/* Macro to conditionally modify fixed_regs/call_used_regs. */ 837#define CONDITIONAL_REGISTER_USAGE \ 838do { \ 839 int i; \ 840 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 841 { \ 842 if (fixed_regs[i] > 1) \ 843 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ 844 if (call_used_regs[i] > 1) \ 845 call_used_regs[i] = (call_used_regs[i] \ 846 == (TARGET_64BIT ? 3 : 2)); \ 847 } \ 848 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 849 { \ 850 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 851 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 852 } \ 853 if (! TARGET_MMX) \ 854 { \ 855 int i; \ 856 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 857 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 858 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 859 } \ 860 if (! TARGET_SSE) \ 861 { \ 862 int i; \ 863 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 864 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 865 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 866 } \ 867 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 868 { \ 869 int i; \ 870 HARD_REG_SET x; \ 871 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 872 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 873 if (TEST_HARD_REG_BIT (x, i)) \ 874 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 875 } \ 876 if (! TARGET_64BIT) \ 877 { \ 878 int i; \ 879 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ 880 reg_names[i] = ""; \ 881 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ 882 reg_names[i] = ""; \ 883 } \ 884 } while (0) 885 886/* Return number of consecutive hard regs needed starting at reg REGNO 887 to hold something of mode MODE. 888 This is ordinarily the length in words of a value of mode MODE 889 but can be less for certain modes in special long registers. 890 891 Actually there are no two word move instructions for consecutive 892 registers. And only registers 0-3 may have mov byte instructions 893 applied to them. 894 */ 895 896#define HARD_REGNO_NREGS(REGNO, MODE) \ 897 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 898 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 899 : ((MODE) == XFmode \ 900 ? (TARGET_64BIT ? 2 : 3) \ 901 : (MODE) == XCmode \ 902 ? (TARGET_64BIT ? 4 : 6) \ 903 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 904 905#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 906 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 907 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 908 ? 0 \ 909 : ((MODE) == XFmode || (MODE) == XCmode)) \ 910 : 0) 911 912#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 913 914#define VALID_SSE2_REG_MODE(MODE) \ 915 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 916 || (MODE) == V2DImode || (MODE) == DFmode) 917 918#define VALID_SSE_REG_MODE(MODE) \ 919 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 920 || (MODE) == SFmode || (MODE) == TFmode) 921 922#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 923 ((MODE) == V2SFmode || (MODE) == SFmode) 924 925#define VALID_MMX_REG_MODE(MODE) \ 926 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 927 || (MODE) == V2SImode || (MODE) == SImode) 928 929/* ??? No autovectorization into MMX or 3DNOW until we can reliably 930 place emms and femms instructions. */ 931#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD) 932 933#define VALID_FP_MODE_P(MODE) \ 934 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 935 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 936 937#define VALID_INT_MODE_P(MODE) \ 938 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 939 || (MODE) == DImode \ 940 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 941 || (MODE) == CDImode \ 942 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 943 || (MODE) == TFmode || (MODE) == TCmode))) 944 945/* Return true for modes passed in SSE registers. */ 946#define SSE_REG_MODE_P(MODE) \ 947 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ 948 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ 949 || (MODE) == V4SFmode || (MODE) == V4SImode) 950 951/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 952 953#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 954 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 955 956/* Value is 1 if it is a good idea to tie two pseudo registers 957 when one has mode MODE1 and one has mode MODE2. 958 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 959 for any hard reg, then this must be 0 for correct output. */ 960 961#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 962 963/* It is possible to write patterns to move flags; but until someone 964 does it, */ 965#define AVOID_CCMODE_COPIES 966 967/* Specify the modes required to caller save a given hard regno. 968 We do this on i386 to prevent flags from being saved at all. 969 970 Kill any attempts to combine saving of modes. */ 971 972#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 973 (CC_REGNO_P (REGNO) ? VOIDmode \ 974 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 975 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\ 976 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 977 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 978 : (MODE)) 979/* Specify the registers used for certain standard purposes. 980 The values of these macros are register numbers. */ 981 982/* on the 386 the pc register is %eip, and is not usable as a general 983 register. The ordinary mov instructions won't work */ 984/* #define PC_REGNUM */ 985 986/* Register to use for pushing function arguments. */ 987#define STACK_POINTER_REGNUM 7 988 989/* Base register for access to local variables of the function. */ 990#define HARD_FRAME_POINTER_REGNUM 6 991 992/* Base register for access to local variables of the function. */ 993#define FRAME_POINTER_REGNUM 20 994 995/* First floating point reg */ 996#define FIRST_FLOAT_REG 8 997 998/* First & last stack-like regs */ 999#define FIRST_STACK_REG FIRST_FLOAT_REG 1000#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1001 1002#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1003#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1004 1005#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1006#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1007 1008#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1009#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1010 1011#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1012#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1013 1014/* Value should be nonzero if functions must have frame pointers. 1015 Zero means the frame pointer need not be set up (and parms 1016 may be accessed via the stack pointer) in functions that seem suitable. 1017 This is computed in `reload', in reload1.c. */ 1018#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1019 1020/* Override this in other tm.h files to cope with various OS lossage 1021 requiring a frame pointer. */ 1022#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1023#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1024#endif 1025 1026/* Make sure we can access arbitrary call frames. */ 1027#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1028 1029/* Base register for access to arguments of the function. */ 1030#define ARG_POINTER_REGNUM 16 1031 1032/* Register in which static-chain is passed to a function. 1033 We do use ECX as static chain register for 32 bit ABI. On the 1034 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1035#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1036 1037/* Register to hold the addressing base for position independent 1038 code access to data items. We don't use PIC pointer for 64bit 1039 mode. Define the regnum to dummy value to prevent gcc from 1040 pessimizing code dealing with EBX. 1041 1042 To avoid clobbering a call-saved register unnecessarily, we renumber 1043 the pic register when possible. The change is visible after the 1044 prologue has been emitted. */ 1045 1046#define REAL_PIC_OFFSET_TABLE_REGNUM 3 1047 1048#define PIC_OFFSET_TABLE_REGNUM \ 1049 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 1050 || !flag_pic ? INVALID_REGNUM \ 1051 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1052 : REAL_PIC_OFFSET_TABLE_REGNUM) 1053 1054#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1055 1056/* A C expression which can inhibit the returning of certain function 1057 values in registers, based on the type of value. A nonzero value 1058 says to return the function value in memory, just as large 1059 structures are always returned. Here TYPE will be a C expression 1060 of type `tree', representing the data type of the value. 1061 1062 Note that values of mode `BLKmode' must be explicitly handled by 1063 this macro. Also, the option `-fpcc-struct-return' takes effect 1064 regardless of this macro. On most systems, it is possible to 1065 leave the macro undefined; this causes a default definition to be 1066 used, whose value is the constant 1 for `BLKmode' values, and 0 1067 otherwise. 1068 1069 Do not use this macro to indicate that structures and unions 1070 should always be returned in memory. You should instead use 1071 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1072 1073#define RETURN_IN_MEMORY(TYPE) \ 1074 ix86_return_in_memory (TYPE) 1075 1076/* This is overridden by <cygwin.h>. */ 1077#define MS_AGGREGATE_RETURN 0 1078 1079/* This is overridden by <netware.h>. */ 1080#define KEEP_AGGREGATE_RETURN_POINTER 0 1081 1082/* Define the classes of registers for register constraints in the 1083 machine description. Also define ranges of constants. 1084 1085 One of the classes must always be named ALL_REGS and include all hard regs. 1086 If there is more than one class, another class must be named NO_REGS 1087 and contain no registers. 1088 1089 The name GENERAL_REGS must be the name of a class (or an alias for 1090 another name such as ALL_REGS). This is the class of registers 1091 that is allowed by "g" or "r" in a register constraint. 1092 Also, registers outside this class are allocated only when 1093 instructions express preferences for them. 1094 1095 The classes must be numbered in nondecreasing order; that is, 1096 a larger-numbered class must never be contained completely 1097 in a smaller-numbered class. 1098 1099 For any two classes, it is very desirable that there be another 1100 class that represents their union. 1101 1102 It might seem that class BREG is unnecessary, since no useful 386 1103 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1104 and the "b" register constraint is useful in asms for syscalls. 1105 1106 The flags and fpsr registers are in no class. */ 1107 1108enum reg_class 1109{ 1110 NO_REGS, 1111 AREG, DREG, CREG, BREG, SIREG, DIREG, 1112 AD_REGS, /* %eax/%edx for DImode */ 1113 Q_REGS, /* %eax %ebx %ecx %edx */ 1114 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1115 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1116 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1117 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1118 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1119 FLOAT_REGS, 1120 SSE_REGS, 1121 MMX_REGS, 1122 FP_TOP_SSE_REGS, 1123 FP_SECOND_SSE_REGS, 1124 FLOAT_SSE_REGS, 1125 FLOAT_INT_REGS, 1126 INT_SSE_REGS, 1127 FLOAT_INT_SSE_REGS, 1128 ALL_REGS, LIM_REG_CLASSES 1129}; 1130 1131#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1132 1133#define INTEGER_CLASS_P(CLASS) \ 1134 reg_class_subset_p ((CLASS), GENERAL_REGS) 1135#define FLOAT_CLASS_P(CLASS) \ 1136 reg_class_subset_p ((CLASS), FLOAT_REGS) 1137#define SSE_CLASS_P(CLASS) \ 1138 ((CLASS) == SSE_REGS) 1139#define MMX_CLASS_P(CLASS) \ 1140 ((CLASS) == MMX_REGS) 1141#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1142 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1143#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1144 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1145#define MAYBE_SSE_CLASS_P(CLASS) \ 1146 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1147#define MAYBE_MMX_CLASS_P(CLASS) \ 1148 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1149 1150#define Q_CLASS_P(CLASS) \ 1151 reg_class_subset_p ((CLASS), Q_REGS) 1152 1153/* Give names of register classes as strings for dump file. */ 1154 1155#define REG_CLASS_NAMES \ 1156{ "NO_REGS", \ 1157 "AREG", "DREG", "CREG", "BREG", \ 1158 "SIREG", "DIREG", \ 1159 "AD_REGS", \ 1160 "Q_REGS", "NON_Q_REGS", \ 1161 "INDEX_REGS", \ 1162 "LEGACY_REGS", \ 1163 "GENERAL_REGS", \ 1164 "FP_TOP_REG", "FP_SECOND_REG", \ 1165 "FLOAT_REGS", \ 1166 "SSE_REGS", \ 1167 "MMX_REGS", \ 1168 "FP_TOP_SSE_REGS", \ 1169 "FP_SECOND_SSE_REGS", \ 1170 "FLOAT_SSE_REGS", \ 1171 "FLOAT_INT_REGS", \ 1172 "INT_SSE_REGS", \ 1173 "FLOAT_INT_SSE_REGS", \ 1174 "ALL_REGS" } 1175 1176/* Define which registers fit in which classes. 1177 This is an initializer for a vector of HARD_REG_SET 1178 of length N_REG_CLASSES. */ 1179 1180#define REG_CLASS_CONTENTS \ 1181{ { 0x00, 0x0 }, \ 1182 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1183 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1184 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1185 { 0x03, 0x0 }, /* AD_REGS */ \ 1186 { 0x0f, 0x0 }, /* Q_REGS */ \ 1187 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1188 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1189 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1190 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1191 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1192 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1193{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1194{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1195{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1196{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1197{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1198 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1199{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1200{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1201{ 0xffffffff,0x1fffff } \ 1202} 1203 1204/* The same information, inverted: 1205 Return the class number of the smallest class containing 1206 reg number REGNO. This could be a conditional expression 1207 or could index an array. */ 1208 1209#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1210 1211/* When defined, the compiler allows registers explicitly used in the 1212 rtl to be used as spill registers but prevents the compiler from 1213 extending the lifetime of these registers. */ 1214 1215#define SMALL_REGISTER_CLASSES 1 1216 1217#define QI_REG_P(X) \ 1218 (REG_P (X) && REGNO (X) < 4) 1219 1220#define GENERAL_REGNO_P(N) \ 1221 ((N) < 8 || REX_INT_REGNO_P (N)) 1222 1223#define GENERAL_REG_P(X) \ 1224 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1225 1226#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1227 1228#define NON_QI_REG_P(X) \ 1229 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1230 1231#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1232#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1233 1234#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1235#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1236#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1237#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1238 1239#define SSE_REGNO_P(N) \ 1240 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1241 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1242 1243#define REX_SSE_REGNO_P(N) \ 1244 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG) 1245 1246#define SSE_REGNO(N) \ 1247 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1248#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1249 1250#define SSE_FLOAT_MODE_P(MODE) \ 1251 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1252 1253#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1254#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1255 1256#define STACK_REG_P(XOP) \ 1257 (REG_P (XOP) && \ 1258 REGNO (XOP) >= FIRST_STACK_REG && \ 1259 REGNO (XOP) <= LAST_STACK_REG) 1260 1261#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1262 1263#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1264 1265#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1266#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1267 1268/* The class value for index registers, and the one for base regs. */ 1269 1270#define INDEX_REG_CLASS INDEX_REGS 1271#define BASE_REG_CLASS GENERAL_REGS 1272 1273/* Place additional restrictions on the register class to use when it 1274 is necessary to be able to hold a value of mode MODE in a reload 1275 register for which class CLASS would ordinarily be used. */ 1276 1277#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1278 ((MODE) == QImode && !TARGET_64BIT \ 1279 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1280 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1281 ? Q_REGS : (CLASS)) 1282 1283/* Given an rtx X being reloaded into a reg required to be 1284 in class CLASS, return the class of reg to actually use. 1285 In general this is just CLASS; but on some machines 1286 in some cases it is preferable to use a more restrictive class. 1287 On the 80386 series, we prevent floating constants from being 1288 reloaded into floating registers (since no move-insn can do that) 1289 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1290 1291/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1292 QImode must go into class Q_REGS. 1293 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1294 movdf to do mem-to-mem moves through integer regs. */ 1295 1296#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1297 ix86_preferred_reload_class ((X), (CLASS)) 1298 1299/* Discourage putting floating-point values in SSE registers unless 1300 SSE math is being used, and likewise for the 387 registers. */ 1301 1302#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ 1303 ix86_preferred_output_reload_class ((X), (CLASS)) 1304 1305/* If we are copying between general and FP registers, we need a memory 1306 location. The same is true for SSE and MMX registers. */ 1307#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1308 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1309 1310/* QImode spills from non-QI registers need a scratch. This does not 1311 happen often -- the only example so far requires an uninitialized 1312 pseudo. */ 1313 1314#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1315 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1316 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1317 ? Q_REGS : NO_REGS) 1318 1319/* Return the maximum number of consecutive registers 1320 needed to represent mode MODE in a register of class CLASS. */ 1321/* On the 80386, this is the size of MODE in words, 1322 except in the FP regs, where a single reg is always enough. */ 1323#define CLASS_MAX_NREGS(CLASS, MODE) \ 1324 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1325 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1326 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ 1327 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1328 1329/* A C expression whose value is nonzero if pseudos that have been 1330 assigned to registers of class CLASS would likely be spilled 1331 because registers of CLASS are needed for spill registers. 1332 1333 The default value of this macro returns 1 if CLASS has exactly one 1334 register and zero otherwise. On most machines, this default 1335 should be used. Only define this macro to some other expression 1336 if pseudo allocated by `local-alloc.c' end up in memory because 1337 their hard registers were needed for spill registers. If this 1338 macro returns nonzero for those classes, those pseudos will only 1339 be allocated by `global.c', which knows how to reallocate the 1340 pseudo to another register. If there would not be another 1341 register available for reallocation, you should not change the 1342 definition of this macro since the only effect of such a 1343 definition would be to slow down register allocation. */ 1344 1345#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1346 (((CLASS) == AREG) \ 1347 || ((CLASS) == DREG) \ 1348 || ((CLASS) == CREG) \ 1349 || ((CLASS) == BREG) \ 1350 || ((CLASS) == AD_REGS) \ 1351 || ((CLASS) == SIREG) \ 1352 || ((CLASS) == DIREG) \ 1353 || ((CLASS) == FP_TOP_REG) \ 1354 || ((CLASS) == FP_SECOND_REG)) 1355 1356/* Return a class of registers that cannot change FROM mode to TO mode. */ 1357 1358#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1359 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1360 1361/* Stack layout; function entry, exit and calling. */ 1362 1363/* Define this if pushing a word on the stack 1364 makes the stack pointer a smaller address. */ 1365#define STACK_GROWS_DOWNWARD 1366 1367/* Define this to nonzero if the nominal address of the stack frame 1368 is at the high-address end of the local variables; 1369 that is, each additional local variable allocated 1370 goes at a more negative offset in the frame. */ 1371#define FRAME_GROWS_DOWNWARD 1 1372 1373/* Offset within stack frame to start allocating local variables at. 1374 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1375 first local allocated. Otherwise, it is the offset to the BEGINNING 1376 of the first local allocated. */ 1377#define STARTING_FRAME_OFFSET 0 1378 1379/* If we generate an insn to push BYTES bytes, 1380 this says how many the stack pointer really advances by. 1381 On 386, we have pushw instruction that decrements by exactly 2 no 1382 matter what the position was, there is no pushb. 1383 But as CIE data alignment factor on this arch is -4, we need to make 1384 sure all stack pointer adjustments are in multiple of 4. 1385 1386 For 64bit ABI we round up to 8 bytes. 1387 */ 1388 1389#define PUSH_ROUNDING(BYTES) \ 1390 (TARGET_64BIT \ 1391 ? (((BYTES) + 7) & (-8)) \ 1392 : (((BYTES) + 3) & (-4))) 1393 1394/* If defined, the maximum amount of space required for outgoing arguments will 1395 be computed and placed into the variable 1396 `current_function_outgoing_args_size'. No space will be pushed onto the 1397 stack for each call; instead, the function prologue should increase the stack 1398 frame size by this amount. */ 1399 1400#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1401 1402/* If defined, a C expression whose value is nonzero when we want to use PUSH 1403 instructions to pass outgoing arguments. */ 1404 1405#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1406 1407/* We want the stack and args grow in opposite directions, even if 1408 PUSH_ARGS is 0. */ 1409#define PUSH_ARGS_REVERSED 1 1410 1411/* Offset of first parameter from the argument pointer register value. */ 1412#define FIRST_PARM_OFFSET(FNDECL) 0 1413 1414/* Define this macro if functions should assume that stack space has been 1415 allocated for arguments even when their values are passed in registers. 1416 1417 The value of this macro is the size, in bytes, of the area reserved for 1418 arguments passed in registers for the function represented by FNDECL. 1419 1420 This space can be allocated by the caller, or be a part of the 1421 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1422 which. */ 1423#define REG_PARM_STACK_SPACE(FNDECL) 0 1424 1425/* Value is the number of bytes of arguments automatically 1426 popped when returning from a subroutine call. 1427 FUNDECL is the declaration node of the function (as a tree), 1428 FUNTYPE is the data type of the function (as a tree), 1429 or for a library call it is an identifier node for the subroutine name. 1430 SIZE is the number of bytes of arguments passed on the stack. 1431 1432 On the 80386, the RTD insn may be used to pop them if the number 1433 of args is fixed, but if the number is variable then the caller 1434 must pop them all. RTD can't be used for library calls now 1435 because the library is compiled with the Unix compiler. 1436 Use of RTD is a selectable option, since it is incompatible with 1437 standard Unix calling sequences. If the option is not selected, 1438 the caller must always pop the args. 1439 1440 The attribute stdcall is equivalent to RTD on a per module basis. */ 1441 1442#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1443 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1444 1445#define FUNCTION_VALUE_REGNO_P(N) \ 1446 ix86_function_value_regno_p (N) 1447 1448/* Define how to find the value returned by a library function 1449 assuming the value has mode MODE. */ 1450 1451#define LIBCALL_VALUE(MODE) \ 1452 ix86_libcall_value (MODE) 1453 1454/* Define the size of the result block used for communication between 1455 untyped_call and untyped_return. The block contains a DImode value 1456 followed by the block used by fnsave and frstor. */ 1457 1458#define APPLY_RESULT_SIZE (8+108) 1459 1460/* 1 if N is a possible register number for function argument passing. */ 1461#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1462 1463/* Define a data type for recording info about an argument list 1464 during the scan of that argument list. This data type should 1465 hold all necessary information about the function itself 1466 and about the args processed so far, enough to enable macros 1467 such as FUNCTION_ARG to determine where the next arg should go. */ 1468 1469typedef struct ix86_args { 1470 int words; /* # words passed so far */ 1471 int nregs; /* # registers available for passing */ 1472 int regno; /* next available register number */ 1473 int fastcall; /* fastcall calling convention is used */ 1474 int sse_words; /* # sse words passed so far */ 1475 int sse_nregs; /* # sse registers available for passing */ 1476 int warn_sse; /* True when we want to warn about SSE ABI. */ 1477 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1478 int sse_regno; /* next available sse register number */ 1479 int mmx_words; /* # mmx words passed so far */ 1480 int mmx_nregs; /* # mmx registers available for passing */ 1481 int mmx_regno; /* next available mmx register number */ 1482 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1483 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should 1484 be passed in SSE registers. Otherwise 0. */ 1485} CUMULATIVE_ARGS; 1486 1487/* Initialize a variable CUM of type CUMULATIVE_ARGS 1488 for a call to a function whose data type is FNTYPE. 1489 For a library call, FNTYPE is 0. */ 1490 1491#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1492 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1493 1494/* Update the data in CUM to advance over an argument 1495 of mode MODE and data type TYPE. 1496 (TYPE is null for libcalls where that information may not be available.) */ 1497 1498#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1499 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1500 1501/* Define where to put the arguments to a function. 1502 Value is zero to push the argument on the stack, 1503 or a hard register in which to store the argument. 1504 1505 MODE is the argument's machine mode. 1506 TYPE is the data type of the argument (as a tree). 1507 This is null for libcalls where that information may 1508 not be available. 1509 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1510 the preceding args and about the function being called. 1511 NAMED is nonzero if this argument is a named parameter 1512 (otherwise it is an extra parameter matching an ellipsis). */ 1513 1514#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1515 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1516 1517/* Implement `va_start' for varargs and stdarg. */ 1518#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ 1519 ix86_va_start (VALIST, NEXTARG) 1520 1521#define TARGET_ASM_FILE_END ix86_file_end 1522#define NEED_INDICATE_EXEC_STACK 0 1523 1524/* Output assembler code to FILE to increment profiler label # LABELNO 1525 for profiling a function entry. */ 1526 1527#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1528 1529#define MCOUNT_NAME "_mcount" 1530 1531#define PROFILE_COUNT_REGISTER "edx" 1532 1533/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1534 the stack pointer does not matter. The value is tested only in 1535 functions that have frame pointers. 1536 No definition is equivalent to always zero. */ 1537/* Note on the 386 it might be more efficient not to define this since 1538 we have to restore it ourselves from the frame pointer, in order to 1539 use pop */ 1540 1541#define EXIT_IGNORE_STACK 1 1542 1543/* Output assembler code for a block containing the constant parts 1544 of a trampoline, leaving space for the variable parts. */ 1545 1546/* On the 386, the trampoline contains two instructions: 1547 mov #STATIC,ecx 1548 jmp FUNCTION 1549 The trampoline is generated entirely at runtime. The operand of JMP 1550 is the address of FUNCTION relative to the instruction following the 1551 JMP (which is 5 bytes long). */ 1552 1553/* Length in units of the trampoline for entering a nested function. */ 1554 1555#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1556 1557/* Emit RTL insns to initialize the variable parts of a trampoline. 1558 FNADDR is an RTX for the address of the function's pure code. 1559 CXT is an RTX for the static chain value for the function. */ 1560 1561#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1562 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1563 1564/* Definitions for register eliminations. 1565 1566 This is an array of structures. Each structure initializes one pair 1567 of eliminable registers. The "from" register number is given first, 1568 followed by "to". Eliminations of the same "from" register are listed 1569 in order of preference. 1570 1571 There are two registers that can always be eliminated on the i386. 1572 The frame pointer and the arg pointer can be replaced by either the 1573 hard frame pointer or to the stack pointer, depending upon the 1574 circumstances. The hard frame pointer is not used before reload and 1575 so it is not eligible for elimination. */ 1576 1577#define ELIMINABLE_REGS \ 1578{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1579 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1580 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1581 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1582 1583/* Given FROM and TO register numbers, say whether this elimination is 1584 allowed. Frame pointer elimination is automatically handled. 1585 1586 All other eliminations are valid. */ 1587 1588#define CAN_ELIMINATE(FROM, TO) \ 1589 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1590 1591/* Define the offset between two registers, one to be eliminated, and the other 1592 its replacement, at the start of a routine. */ 1593 1594#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1595 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1596 1597/* Addressing modes, and classification of registers for them. */ 1598 1599/* Macros to check register numbers against specific register classes. */ 1600 1601/* These assume that REGNO is a hard or pseudo reg number. 1602 They give nonzero only if REGNO is a hard reg of the suitable class 1603 or a pseudo reg currently allocated to a suitable hard reg. 1604 Since they use reg_renumber, they are safe only once reg_renumber 1605 has been allocated, which happens in local-alloc.c. */ 1606 1607#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1608 ((REGNO) < STACK_POINTER_REGNUM \ 1609 || (REGNO >= FIRST_REX_INT_REG \ 1610 && (REGNO) <= LAST_REX_INT_REG) \ 1611 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1612 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1613 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1614 1615#define REGNO_OK_FOR_BASE_P(REGNO) \ 1616 ((REGNO) <= STACK_POINTER_REGNUM \ 1617 || (REGNO) == ARG_POINTER_REGNUM \ 1618 || (REGNO) == FRAME_POINTER_REGNUM \ 1619 || (REGNO >= FIRST_REX_INT_REG \ 1620 && (REGNO) <= LAST_REX_INT_REG) \ 1621 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1622 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1623 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1624 1625#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1626 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1627#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1628 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1629 1630/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1631 and check its validity for a certain class. 1632 We have two alternate definitions for each of them. 1633 The usual definition accepts all pseudo regs; the other rejects 1634 them unless they have been allocated suitable hard regs. 1635 The symbol REG_OK_STRICT causes the latter definition to be used. 1636 1637 Most source files want to accept pseudo regs in the hope that 1638 they will get allocated to the class that the insn wants them to be in. 1639 Source files for reload pass need to be strict. 1640 After reload, it makes no difference, since pseudo regs have 1641 been eliminated by then. */ 1642 1643 1644/* Non strict versions, pseudos are ok. */ 1645#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1646 (REGNO (X) < STACK_POINTER_REGNUM \ 1647 || (REGNO (X) >= FIRST_REX_INT_REG \ 1648 && REGNO (X) <= LAST_REX_INT_REG) \ 1649 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1650 1651#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1652 (REGNO (X) <= STACK_POINTER_REGNUM \ 1653 || REGNO (X) == ARG_POINTER_REGNUM \ 1654 || REGNO (X) == FRAME_POINTER_REGNUM \ 1655 || (REGNO (X) >= FIRST_REX_INT_REG \ 1656 && REGNO (X) <= LAST_REX_INT_REG) \ 1657 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1658 1659/* Strict versions, hard registers only */ 1660#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1661#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1662 1663#ifndef REG_OK_STRICT 1664#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1665#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1666 1667#else 1668#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1669#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1670#endif 1671 1672/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1673 that is a valid memory address for an instruction. 1674 The MODE argument is the machine mode for the MEM expression 1675 that wants to use this address. 1676 1677 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1678 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1679 1680 See legitimize_pic_address in i386.c for details as to what 1681 constitutes a legitimate address when -fpic is used. */ 1682 1683#define MAX_REGS_PER_ADDRESS 2 1684 1685#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1686 1687/* Nonzero if the constant value X is a legitimate general operand. 1688 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1689 1690#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1691 1692#ifdef REG_OK_STRICT 1693#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1694do { \ 1695 if (legitimate_address_p ((MODE), (X), 1)) \ 1696 goto ADDR; \ 1697} while (0) 1698 1699#else 1700#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1701do { \ 1702 if (legitimate_address_p ((MODE), (X), 0)) \ 1703 goto ADDR; \ 1704} while (0) 1705 1706#endif 1707 1708/* If defined, a C expression to determine the base term of address X. 1709 This macro is used in only one place: `find_base_term' in alias.c. 1710 1711 It is always safe for this macro to not be defined. It exists so 1712 that alias analysis can understand machine-dependent addresses. 1713 1714 The typical use of this macro is to handle addresses containing 1715 a label_ref or symbol_ref within an UNSPEC. */ 1716 1717#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1718 1719/* Try machine-dependent ways of modifying an illegitimate address 1720 to be legitimate. If we find one, return the new, valid address. 1721 This macro is used in only one place: `memory_address' in explow.c. 1722 1723 OLDX is the address as it was before break_out_memory_refs was called. 1724 In some cases it is useful to look at this to decide what needs to be done. 1725 1726 MODE and WIN are passed so that this macro can use 1727 GO_IF_LEGITIMATE_ADDRESS. 1728 1729 It is always safe for this macro to do nothing. It exists to recognize 1730 opportunities to optimize the output. 1731 1732 For the 80386, we handle X+REG by loading X into a register R and 1733 using R+REG. R will go in a general reg and indexing will be used. 1734 However, if REG is a broken-out memory address or multiplication, 1735 nothing needs to be done because REG can certainly go in a general reg. 1736 1737 When -fpic is used, special handling is needed for symbolic references. 1738 See comments by legitimize_pic_address in i386.c for details. */ 1739 1740#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1741do { \ 1742 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 1743 if (memory_address_p ((MODE), (X))) \ 1744 goto WIN; \ 1745} while (0) 1746 1747#define REWRITE_ADDRESS(X) rewrite_address (X) 1748 1749/* Nonzero if the constant value X is a legitimate general operand 1750 when generating PIC code. It is given that flag_pic is on and 1751 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1752 1753#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1754 1755#define SYMBOLIC_CONST(X) \ 1756 (GET_CODE (X) == SYMBOL_REF \ 1757 || GET_CODE (X) == LABEL_REF \ 1758 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1759 1760/* Go to LABEL if ADDR (a legitimate address expression) 1761 has an effect that depends on the machine mode it is used for. 1762 On the 80386, only postdecrement and postincrement address depend thus 1763 (the amount of decrement or increment being the length of the operand). */ 1764#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1765do { \ 1766 if (GET_CODE (ADDR) == POST_INC \ 1767 || GET_CODE (ADDR) == POST_DEC) \ 1768 goto LABEL; \ 1769} while (0) 1770 1771/* Max number of args passed in registers. If this is more than 3, we will 1772 have problems with ebx (register #4), since it is a caller save register and 1773 is also used as the pic register in ELF. So for now, don't allow more than 1774 3 registers to be passed in registers. */ 1775 1776#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 1777 1778#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) 1779 1780#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1781 1782 1783/* Specify the machine mode that this machine uses 1784 for the index in the tablejump instruction. */ 1785#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 1786 1787/* Define this as 1 if `char' should by default be signed; else as 0. */ 1788#define DEFAULT_SIGNED_CHAR 1 1789 1790/* Number of bytes moved into a data cache for a single prefetch operation. */ 1791#define PREFETCH_BLOCK ix86_cost->prefetch_block 1792 1793/* Number of prefetch operations that can be done in parallel. */ 1794#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 1795 1796/* Max number of bytes we can move from memory to memory 1797 in one reasonably fast instruction. */ 1798#define MOVE_MAX 16 1799 1800/* MOVE_MAX_PIECES is the number of bytes at a time which we can 1801 move efficiently, as opposed to MOVE_MAX which is the maximum 1802 number of bytes we can move with a single instruction. */ 1803#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 1804 1805/* If a memory-to-memory move would take MOVE_RATIO or more simple 1806 move-instruction pairs, we will do a movmem or libcall instead. 1807 Increasing the value will always make code faster, but eventually 1808 incurs high cost in increased code size. 1809 1810 If you don't define this, a reasonable default is used. */ 1811 1812#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 1813 1814/* If a clear memory operation would take CLEAR_RATIO or more simple 1815 move-instruction sequences, we will do a clrmem or libcall instead. */ 1816 1817#define CLEAR_RATIO (optimize_size ? 2 \ 1818 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio) 1819 1820/* Define if shifts truncate the shift count 1821 which implies one can omit a sign-extension or zero-extension 1822 of a shift count. */ 1823/* On i386, shifts do truncate the count. But bit opcodes don't. */ 1824 1825/* #define SHIFT_COUNT_TRUNCATED */ 1826 1827/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1828 is done just by pretending it is already truncated. */ 1829#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1830 1831/* A macro to update M and UNSIGNEDP when an object whose type is 1832 TYPE and which has the specified mode and signedness is to be 1833 stored in a register. This macro is only called when TYPE is a 1834 scalar type. 1835 1836 On i386 it is sometimes useful to promote HImode and QImode 1837 quantities to SImode. The choice depends on target type. */ 1838 1839#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1840do { \ 1841 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1842 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1843 (MODE) = SImode; \ 1844} while (0) 1845 1846/* Specify the machine mode that pointers have. 1847 After generation of rtl, the compiler makes no further distinction 1848 between pointers and any other objects of this machine mode. */ 1849#define Pmode (TARGET_64BIT ? DImode : SImode) 1850 1851/* A function address in a call instruction 1852 is a byte address (for indexing purposes) 1853 so give the MEM rtx a byte's mode. */ 1854#define FUNCTION_MODE QImode 1855 1856/* A C expression for the cost of moving data from a register in class FROM to 1857 one in class TO. The classes are expressed using the enumeration values 1858 such as `GENERAL_REGS'. A value of 2 is the default; other values are 1859 interpreted relative to that. 1860 1861 It is not required that the cost always equal 2 when FROM is the same as TO; 1862 on some machines it is expensive to move between registers if they are not 1863 general registers. */ 1864 1865#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1866 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1867 1868/* A C expression for the cost of moving data of mode M between a 1869 register and memory. A value of 2 is the default; this cost is 1870 relative to those in `REGISTER_MOVE_COST'. 1871 1872 If moving between registers and memory is more expensive than 1873 between two registers, you should define this macro to express the 1874 relative cost. */ 1875 1876#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1877 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 1878 1879/* A C expression for the cost of a branch instruction. A value of 1 1880 is the default; other values are interpreted relative to that. */ 1881 1882#define BRANCH_COST ix86_branch_cost 1883 1884/* Define this macro as a C expression which is nonzero if accessing 1885 less than a word of memory (i.e. a `char' or a `short') is no 1886 faster than accessing a word of memory, i.e., if such access 1887 require more than one instruction or if there is no difference in 1888 cost between byte and (aligned) word loads. 1889 1890 When this macro is not defined, the compiler will access a field by 1891 finding the smallest containing object; when it is defined, a 1892 fullword load will be used if alignment permits. Unless bytes 1893 accesses are faster than word accesses, using word accesses is 1894 preferable since it may eliminate subsequent memory access if 1895 subsequent accesses occur to other fields in the same word of the 1896 structure, but to different bytes. */ 1897 1898#define SLOW_BYTE_ACCESS 0 1899 1900/* Nonzero if access to memory by shorts is slow and undesirable. */ 1901#define SLOW_SHORT_ACCESS 0 1902 1903/* Define this macro to be the value 1 if unaligned accesses have a 1904 cost many times greater than aligned accesses, for example if they 1905 are emulated in a trap handler. 1906 1907 When this macro is nonzero, the compiler will act as if 1908 `STRICT_ALIGNMENT' were nonzero when generating code for block 1909 moves. This can cause significantly more instructions to be 1910 produced. Therefore, do not set this macro nonzero if unaligned 1911 accesses only add a cycle or two to the time for a memory access. 1912 1913 If the value of this macro is always zero, it need not be defined. */ 1914 1915/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1916 1917/* Define this macro if it is as good or better to call a constant 1918 function address than to call an address kept in a register. 1919 1920 Desirable on the 386 because a CALL with a constant address is 1921 faster than one with a register address. */ 1922 1923#define NO_FUNCTION_CSE 1924 1925/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1926 return the mode to be used for the comparison. 1927 1928 For floating-point equality comparisons, CCFPEQmode should be used. 1929 VOIDmode should be used in all other cases. 1930 1931 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1932 possible, to allow for more combinations. */ 1933 1934#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1935 1936/* Return nonzero if MODE implies a floating point inequality can be 1937 reversed. */ 1938 1939#define REVERSIBLE_CC_MODE(MODE) 1 1940 1941/* A C expression whose value is reversed condition code of the CODE for 1942 comparison done in CC_MODE mode. */ 1943#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 1944 1945 1946/* Control the assembler format that we output, to the extent 1947 this does not vary between assemblers. */ 1948 1949/* How to refer to registers in assembler output. 1950 This sequence is indexed by compiler's hard-register-number (see above). */ 1951 1952/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e". 1953 For non floating point regs, the following are the HImode names. 1954 1955 For float regs, the stack top is sometimes referred to as "%st(0)" 1956 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ 1957 1958#define HI_REGISTER_NAMES \ 1959{"ax","dx","cx","bx","si","di","bp","sp", \ 1960 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 1961 "argp", "flags", "fpsr", "dirflag", "frame", \ 1962 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 1963 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 1964 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1965 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 1966 1967#define REGISTER_NAMES HI_REGISTER_NAMES 1968 1969/* Table of additional register names to use in user input. */ 1970 1971#define ADDITIONAL_REGISTER_NAMES \ 1972{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 1973 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 1974 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 1975 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 1976 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 1977 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 1978 1979/* Note we are omitting these since currently I don't know how 1980to get gcc to use these, since they want the same but different 1981number as al, and ax. 1982*/ 1983 1984#define QI_REGISTER_NAMES \ 1985{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 1986 1987/* These parallel the array above, and can be used to access bits 8:15 1988 of regs 0 through 3. */ 1989 1990#define QI_HIGH_REGISTER_NAMES \ 1991{"ah", "dh", "ch", "bh", } 1992 1993/* How to renumber registers for dbx and gdb. */ 1994 1995#define DBX_REGISTER_NUMBER(N) \ 1996 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 1997 1998extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 1999extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2000extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2001 2002/* Before the prologue, RA is at 0(%esp). */ 2003#define INCOMING_RETURN_ADDR_RTX \ 2004 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2005 2006/* After the prologue, RA is at -4(AP) in the current frame. */ 2007#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2008 ((COUNT) == 0 \ 2009 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2010 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2011 2012/* PC is dbx register 8; let's use that column for RA. */ 2013#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2014 2015/* Before the prologue, the top of the frame is at 4(%esp). */ 2016#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2017 2018/* Describe how we implement __builtin_eh_return. */ 2019#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2020#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2021 2022 2023/* Select a format to encode pointers in exception handling data. CODE 2024 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2025 true if the symbol may be affected by dynamic relocations. 2026 2027 ??? All x86 object file formats are capable of representing this. 2028 After all, the relocation needed is the same as for the call insn. 2029 Whether or not a particular assembler allows us to enter such, I 2030 guess we'll have to see. */ 2031#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2032 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 2033 2034/* This is how to output an insn to push a register on the stack. 2035 It need not be very fast code. */ 2036 2037#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2038do { \ 2039 if (TARGET_64BIT) \ 2040 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2041 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2042 else \ 2043 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2044} while (0) 2045 2046/* This is how to output an insn to pop a register from the stack. 2047 It need not be very fast code. */ 2048 2049#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2050do { \ 2051 if (TARGET_64BIT) \ 2052 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2053 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2054 else \ 2055 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2056} while (0) 2057 2058/* This is how to output an element of a case-vector that is absolute. */ 2059 2060#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2061 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2062 2063/* This is how to output an element of a case-vector that is relative. */ 2064 2065#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2066 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2067 2068/* Under some conditions we need jump tables in the text section, 2069 because the assembler cannot handle label differences between 2070 sections. This is the case for x86_64 on Mach-O for example. */ 2071 2072#define JUMP_TABLES_IN_TEXT_SECTION \ 2073 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2074 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2075 2076/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2077 and switch back. For x86 we do this only to save a few bytes that 2078 would otherwise be unused in the text section. */ 2079#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2080 asm (SECTION_OP "\n\t" \ 2081 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2082 TEXT_SECTION_ASM_OP); 2083 2084/* Print operand X (an rtx) in assembler syntax to file FILE. 2085 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2086 Effect of various CODE letters is described in i386.c near 2087 print_operand function. */ 2088 2089#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2090 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') 2091 2092#define PRINT_OPERAND(FILE, X, CODE) \ 2093 print_operand ((FILE), (X), (CODE)) 2094 2095#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2096 print_operand_address ((FILE), (ADDR)) 2097 2098#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2099do { \ 2100 if (! output_addr_const_extra (FILE, (X))) \ 2101 goto FAIL; \ 2102} while (0); 2103 2104/* a letter which is not needed by the normal asm syntax, which 2105 we can use for operand syntax in the extended asm */ 2106 2107#define ASM_OPERAND_LETTER '#' 2108#define RET return "" 2109#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 2110 2111/* Which processor to schedule for. The cpu attribute defines a list that 2112 mirrors this list, so changes to i386.md must be made at the same time. */ 2113 2114enum processor_type 2115{ 2116 PROCESSOR_I386, /* 80386 */ 2117 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2118 PROCESSOR_PENTIUM, 2119 PROCESSOR_PENTIUMPRO, 2120 PROCESSOR_GEODE, 2121 PROCESSOR_K6, 2122 PROCESSOR_ATHLON, 2123 PROCESSOR_PENTIUM4, 2124 PROCESSOR_K8, 2125 PROCESSOR_NOCONA, 2126 PROCESSOR_CORE2, 2127 PROCESSOR_GENERIC32, 2128 PROCESSOR_GENERIC64, 2129 PROCESSOR_AMDFAM10, 2130 PROCESSOR_max 2131}; 2132 2133extern enum processor_type ix86_tune; 2134extern enum processor_type ix86_arch; 2135 2136enum fpmath_unit 2137{ 2138 FPMATH_387 = 1, 2139 FPMATH_SSE = 2 2140}; 2141 2142extern enum fpmath_unit ix86_fpmath; 2143 2144enum tls_dialect 2145{ 2146 TLS_DIALECT_GNU, 2147 TLS_DIALECT_GNU2, 2148 TLS_DIALECT_SUN 2149}; 2150 2151extern enum tls_dialect ix86_tls_dialect; 2152 2153enum cmodel { 2154 CM_32, /* The traditional 32-bit ABI. */ 2155 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 2156 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 2157 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 2158 CM_LARGE, /* No assumptions. */ 2159 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ 2160 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */ 2161}; 2162 2163extern enum cmodel ix86_cmodel; 2164 2165/* Size of the RED_ZONE area. */ 2166#define RED_ZONE_SIZE 128 2167/* Reserved area of the red zone for temporaries. */ 2168#define RED_ZONE_RESERVE 8 2169 2170enum asm_dialect { 2171 ASM_ATT, 2172 ASM_INTEL 2173}; 2174 2175extern enum asm_dialect ix86_asm_dialect; 2176extern unsigned int ix86_preferred_stack_boundary; 2177extern int ix86_branch_cost, ix86_section_threshold; 2178 2179/* Smallest class containing REGNO. */ 2180extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2181 2182extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 2183extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 2184extern rtx ix86_compare_emitted; 2185 2186/* To properly truncate FP values into integers, we need to set i387 control 2187 word. We can't emit proper mode switching code before reload, as spills 2188 generated by reload may truncate values incorrectly, but we still can avoid 2189 redundant computation of new control word by the mode switching pass. 2190 The fldcw instructions are still emitted redundantly, but this is probably 2191 not going to be noticeable problem, as most CPUs do have fast path for 2192 the sequence. 2193 2194 The machinery is to emit simple truncation instructions and split them 2195 before reload to instructions having USEs of two memory locations that 2196 are filled by this code to old and new control word. 2197 2198 Post-reload pass may be later used to eliminate the redundant fildcw if 2199 needed. */ 2200 2201enum ix86_entity 2202{ 2203 I387_TRUNC = 0, 2204 I387_FLOOR, 2205 I387_CEIL, 2206 I387_MASK_PM, 2207 MAX_386_ENTITIES 2208}; 2209 2210enum ix86_stack_slot 2211{ 2212 SLOT_VIRTUAL = 0, 2213 SLOT_TEMP, 2214 SLOT_CW_STORED, 2215 SLOT_CW_TRUNC, 2216 SLOT_CW_FLOOR, 2217 SLOT_CW_CEIL, 2218 SLOT_CW_MASK_PM, 2219 MAX_386_STACK_LOCALS 2220}; 2221 2222/* Define this macro if the port needs extra instructions inserted 2223 for mode switching in an optimizing compilation. */ 2224 2225#define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2226 ix86_optimize_mode_switching[(ENTITY)] 2227 2228/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2229 initializer for an array of integers. Each initializer element N 2230 refers to an entity that needs mode switching, and specifies the 2231 number of different modes that might need to be set for this 2232 entity. The position of the initializer in the initializer - 2233 starting counting at zero - determines the integer that is used to 2234 refer to the mode-switched entity in question. */ 2235 2236#define NUM_MODES_FOR_MODE_SWITCHING \ 2237 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2238 2239/* ENTITY is an integer specifying a mode-switched entity. If 2240 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2241 return an integer value not larger than the corresponding element 2242 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2243 must be switched into prior to the execution of INSN. */ 2244 2245#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2246 2247/* This macro specifies the order in which modes for ENTITY are 2248 processed. 0 is the highest priority. */ 2249 2250#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2251 2252/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2253 is the set of hard registers live at the point where the insn(s) 2254 are to be inserted. */ 2255 2256#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2257 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ 2258 ? emit_i387_cw_initialization (MODE), 0 \ 2259 : 0) 2260 2261 2262/* Avoid renaming of stack registers, as doing so in combination with 2263 scheduling just increases amount of live registers at time and in 2264 the turn amount of fxch instructions needed. 2265 2266 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2267 2268#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2269 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 2270 2271 2272#define DLL_IMPORT_EXPORT_PREFIX '#' 2273 2274#define FASTCALL_PREFIX '@' 2275 2276struct machine_function GTY(()) 2277{ 2278 struct stack_local_entry *stack_locals; 2279 const char *some_ld_name; 2280 rtx force_align_arg_pointer; 2281 int save_varrargs_registers; 2282 int accesses_prev_frame; 2283 int optimize_mode_switching[MAX_386_ENTITIES]; 2284 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to 2285 determine the style used. */ 2286 int use_fast_prologue_epilogue; 2287 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed 2288 for. */ 2289 int use_fast_prologue_epilogue_nregs; 2290 /* If true, the current function needs the default PIC register, not 2291 an alternate register (on x86) and must not use the red zone (on 2292 x86_64), even if it's a leaf function. We don't want the 2293 function to be regarded as non-leaf because TLS calls need not 2294 affect register allocation. This flag is set when a TLS call 2295 instruction is expanded within a function, and never reset, even 2296 if all such instructions are optimized away. Use the 2297 ix86_current_function_calls_tls_descriptor macro for a better 2298 approximation. */ 2299 int tls_descriptor_call_expanded_p; 2300}; 2301 2302#define ix86_stack_locals (cfun->machine->stack_locals) 2303#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) 2304#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2305#define ix86_tls_descriptor_calls_expanded_in_cfun \ 2306 (cfun->machine->tls_descriptor_call_expanded_p) 2307/* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2308 calls are optimized away, we try to detect cases in which it was 2309 optimized away. Since such instructions (use (reg REG_SP)), we can 2310 verify whether there's any such instruction live by testing that 2311 REG_SP is live. */ 2312#define ix86_current_function_calls_tls_descriptor \ 2313 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG]) 2314 2315/* Control behavior of x86_file_start. */ 2316#define X86_FILE_START_VERSION_DIRECTIVE false 2317#define X86_FILE_START_FLTUSED false 2318 2319/* Flag to mark data that is in the large address area. */ 2320#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2321#define SYMBOL_REF_FAR_ADDR_P(X) \ 2322 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2323/* 2324Local variables: 2325version-control: t 2326End: 2327*/ 2328