i386.h revision 122193
1207618Srdivacky/* Definitions of target machine for GNU compiler for IA-32. 2207618Srdivacky Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3207618Srdivacky 2001, 2002 Free Software Foundation, Inc. 4207618Srdivacky 5207618SrdivackyThis file is part of GNU CC. 6207618Srdivacky 7207618SrdivackyGNU CC is free software; you can redistribute it and/or modify 8207618Srdivackyit under the terms of the GNU General Public License as published by 9207618Srdivackythe Free Software Foundation; either version 2, or (at your option) 10207618Srdivackyany later version. 11207618Srdivacky 12207618SrdivackyGNU CC is distributed in the hope that it will be useful, 13207618Srdivackybut WITHOUT ANY WARRANTY; without even the implied warranty of 14208599SrdivackyMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15223017SdimGNU General Public License for more details. 16249423Sdim 17207618SrdivackyYou should have received a copy of the GNU General Public License 18207618Srdivackyalong with GNU CC; see the file COPYING. If not, write to 19276479Sdimthe Free Software Foundation, 59 Temple Place - Suite 330, 20207618SrdivackyBoston, MA 02111-1307, USA. */ 21288943Sdim 22288943Sdim/* The purpose of this file is to define the characteristics of the i386, 23288943Sdim independent of assembler syntax or operating system. 24288943Sdim 25288943Sdim Three other files build on this one to describe a specific assembler syntax: 26288943Sdim bsd386.h, att386.h, and sun386.h. 27288943Sdim 28288943Sdim The actual tm.h file for a particular system should include 29288943Sdim this file, and then the file for the appropriate assembler syntax. 30288943Sdim 31288943Sdim Many macros that specify assembler syntax are omitted entirely from 32288943Sdim this file because they really belong in the files for particular 33276479Sdim assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34288943Sdim ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35288943Sdim that start with ASM_ or end in ASM_OP. */ 36288943Sdim 37288943Sdim/* Define the specific costs for a given cpu */ 38288943Sdim 39288943Sdimstruct processor_costs { 40288943Sdim const int add; /* cost of an add instruction */ 41288943Sdim const int lea; /* cost of a lea instruction */ 42288943Sdim const int shift_var; /* variable shift costs */ 43288943Sdim const int shift_const; /* constant shift costs */ 44288943Sdim const int mult_init; /* cost of starting a multiply */ 45288943Sdim const int mult_bit; /* cost of multiply per each bit set */ 46288943Sdim const int divide; /* cost of a divide/mod */ 47288943Sdim int movsx; /* The cost of movsx operation. */ 48288943Sdim int movzx; /* The cost of movzx operation. */ 49288943Sdim const int large_insn; /* insns larger than this cost more */ 50288943Sdim const int move_ratio; /* The threshold of number of scalar 51288943Sdim memory-to-memory move insns. */ 52288943Sdim const int movzbl_load; /* cost of loading using movzbl */ 53288943Sdim const int int_load[3]; /* cost of loading integer registers 54288943Sdim in QImode, HImode and SImode relative 55288943Sdim to reg-reg move (2). */ 56288943Sdim const int int_store[3]; /* cost of storing integer register 57288943Sdim in QImode, HImode and SImode */ 58288943Sdim const int fp_move; /* cost of reg,reg fld/fst */ 59288943Sdim const int fp_load[3]; /* cost of loading FP register 60288943Sdim in SFmode, DFmode and XFmode */ 61288943Sdim const int fp_store[3]; /* cost of storing FP register 62288943Sdim in SFmode, DFmode and XFmode */ 63288943Sdim const int mmx_move; /* cost of moving MMX register. */ 64288943Sdim const int mmx_load[2]; /* cost of loading MMX register 65288943Sdim in SImode and DImode */ 66288943Sdim const int mmx_store[2]; /* cost of storing MMX register 67288943Sdim in SImode and DImode */ 68288943Sdim const int sse_move; /* cost of moving SSE register. */ 69288943Sdim const int sse_load[3]; /* cost of loading SSE register 70288943Sdim in SImode, DImode and TImode*/ 71288943Sdim const int sse_store[3]; /* cost of storing SSE register 72288943Sdim in SImode, DImode and TImode*/ 73288943Sdim const int mmxsse_to_integer; /* cost of moving mmxsse register to 74288943Sdim integer and vice versa. */ 75288943Sdim const int prefetch_block; /* bytes moved to cache for prefetch. */ 76288943Sdim const int simultaneous_prefetches; /* number of parallel prefetch 77288943Sdim operations. */ 78288943Sdim const int fadd; /* cost of FADD and FSUB instructions. */ 79288943Sdim const int fmul; /* cost of FMUL instruction. */ 80288943Sdim const int fdiv; /* cost of FDIV instruction. */ 81288943Sdim const int fabs; /* cost of FABS instruction. */ 82288943Sdim const int fchs; /* cost of FCHS instruction. */ 83288943Sdim const int fsqrt; /* cost of FSQRT instruction. */ 84288943Sdim}; 85288943Sdim 86288943Sdimextern const struct processor_costs *ix86_cost; 87288943Sdim 88288943Sdim/* Run-time compilation parameters selecting different hardware subsets. */ 89288943Sdim 90288943Sdimextern int target_flags; 91288943Sdim 92288943Sdim/* Macros used in the machine description to test the flags. */ 93288943Sdim 94288943Sdim/* configure can arrange to make this 2, to force a 486. */ 95288943Sdim 96288943Sdim#ifndef TARGET_CPU_DEFAULT 97288943Sdim#define TARGET_CPU_DEFAULT 0 98288943Sdim#endif 99288943Sdim 100288943Sdim/* Masks for the -m switches */ 101288943Sdim#define MASK_80387 0x00000001 /* Hardware floating point */ 102288943Sdim#define MASK_RTD 0x00000002 /* Use ret that pops args */ 103288943Sdim#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ 104288943Sdim#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ 105288943Sdim#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ 106288943Sdim#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ 107288943Sdim#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ 108288943Sdim#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ 109288943Sdim#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ 110288943Sdim#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ 111288943Sdim#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ 112288943Sdim#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ 113288943Sdim#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ 114288943Sdim#define MASK_MMX 0x00002000 /* Support MMX regs/builtins */ 115288943Sdim#define MASK_SSE 0x00004000 /* Support SSE regs/builtins */ 116288943Sdim#define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */ 117288943Sdim#define MASK_PNI 0x00010000 /* Support PNI builtins */ 118288943Sdim#define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */ 119288943Sdim#define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */ 120288943Sdim#define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */ 121288943Sdim#define MASK_64BIT 0x00100000 /* Produce 64bit code */ 122288943Sdim 123288943Sdim/* Unused: 0x03f0000 */ 124288943Sdim 125288943Sdim/* ... overlap with subtarget options starts by 0x04000000. */ 126288943Sdim#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ 127288943Sdim#define MASK_NO_ALIGN_LONG_STRINGS 0x08000000 /* Do not align long strings specially */ 128288943Sdim 129207618Srdivacky/* Use the floating point instructions */ 130208599Srdivacky#define TARGET_80387 (target_flags & MASK_80387) 131208599Srdivacky 132261991Sdim/* Compile using ret insn that pops args. 133208599Srdivacky This will not work unless you use prototypes at least 134208599Srdivacky for all functions that can take varying numbers of args. */ 135208599Srdivacky#define TARGET_RTD (target_flags & MASK_RTD) 136208599Srdivacky 137218893Sdim/* Align doubles to a two word boundary. This breaks compatibility with 138218893Sdim the published ABI's for structures containing doubles, but produces 139288943Sdim faster code on the pentium. */ 140288943Sdim#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) 141208599Srdivacky 142208599Srdivacky/* Use push instructions to save outgoing args. */ 143208599Srdivacky#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) 144208599Srdivacky 145221345Sdim/* Accumulate stack adjustments to prologue/epilogue. */ 146208599Srdivacky#define TARGET_ACCUMULATE_OUTGOING_ARGS \ 147208599Srdivacky (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) 148208599Srdivacky 149288943Sdim/* Put uninitialized locals into bss, not data. 150288943Sdim Meaningful only on svr3. */ 151208599Srdivacky#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) 152276479Sdim 153288943Sdim/* Use IEEE floating point comparisons. These handle correctly the cases 154288943Sdim where the result of a comparison is unordered. Normally SIGFPE is 155208599Srdivacky generated in such cases, in which case this isn't needed. */ 156208599Srdivacky#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) 157208599Srdivacky 158208599Srdivacky/* Functions that return a floating point value may return that value 159208599Srdivacky in the 387 FPU or in 386 integer registers. If set, this flag causes 160208599Srdivacky the 387 to be used, which is compatible with most calling conventions. */ 161208599Srdivacky#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) 162276479Sdim 163296417Sdim/* Long double is 128bit instead of 96bit, even when only 80bits are used. 164276479Sdim This mode wastes cache, but avoid misaligned data accesses and simplifies 165276479Sdim address calculations. */ 166208599Srdivacky#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) 167208599Srdivacky 168296417Sdim/* Disable generation of FP sin, cos and sqrt operations for 387. 169296417Sdim This is because FreeBSD lacks these in the math-emulator-code */ 170296417Sdim#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) 171296417Sdim 172208599Srdivacky/* Don't create frame pointers for leaf functions */ 173296417Sdim#define TARGET_OMIT_LEAF_FRAME_POINTER \ 174296417Sdim (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) 175296417Sdim 176296417Sdim/* Debug GO_IF_LEGITIMATE_ADDRESS */ 177296417Sdim#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) 178208599Srdivacky 179296417Sdim/* Debug FUNCTION_ARG macros */ 180296417Sdim#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) 181296417Sdim 182296417Sdim/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 183296417Sdim compile-time constant. */ 184296417Sdim#ifdef IN_LIBGCC2 185296417Sdim#ifdef __x86_64__ 186296417Sdim#define TARGET_64BIT 1 187296417Sdim#else 188296417Sdim#define TARGET_64BIT 0 189296417Sdim#endif 190296417Sdim#else 191296417Sdim#ifdef TARGET_BI_ARCH 192296417Sdim#define TARGET_64BIT (target_flags & MASK_64BIT) 193296417Sdim#else 194296417Sdim#if TARGET_64BIT_DEFAULT 195296417Sdim#define TARGET_64BIT 1 196208599Srdivacky#else 197208599Srdivacky#define TARGET_64BIT 0 198208599Srdivacky#endif 199208599Srdivacky#endif 200208599Srdivacky#endif 201208599Srdivacky 202208599Srdivacky#define TARGET_386 (ix86_cpu == PROCESSOR_I386) 203208599Srdivacky#define TARGET_486 (ix86_cpu == PROCESSOR_I486) 204208599Srdivacky#define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) 205208599Srdivacky#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) 206208599Srdivacky#define TARGET_K6 (ix86_cpu == PROCESSOR_K6) 207208599Srdivacky#define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) 208208599Srdivacky#define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4) 209208599Srdivacky 210208599Srdivacky#define CPUMASK (1 << ix86_cpu) 211208599Srdivackyextern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 212208599Srdivackyextern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 213208599Srdivackyextern const int x86_branch_hints, x86_unroll_strlen; 214208599Srdivackyextern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 215288943Sdimextern const int x86_use_loop, x86_use_fiop, x86_use_mov0; 216234353Sdimextern const int x86_use_cltd, x86_read_modify_write; 217234353Sdimextern const int x86_read_modify, x86_split_long_moves; 218208599Srdivackyextern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; 219208599Srdivackyextern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 220208599Srdivackyextern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 221208599Srdivackyextern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 222208599Srdivackyextern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 223276479Sdimextern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 224276479Sdimextern const int x86_epilogue_using_move, x86_decompose_lea; 225208599Srdivackyextern const int x86_arch_always_fancy_math_387, x86_shift1; 226208599Srdivackyextern int x86_prefetch_sse; 227208599Srdivacky 228208599Srdivacky#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) 229208599Srdivacky#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) 230208599Srdivacky#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) 231208599Srdivacky#define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) 232208599Srdivacky#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) 233208599Srdivacky/* For sane SSE instruction set generation we need fcomi instruction. It is 234208599Srdivacky safe to enable all CMOVE instructions. */ 235208599Srdivacky#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 236208599Srdivacky#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) 237208599Srdivacky#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK) 238208599Srdivacky#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) 239288943Sdim#define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT) 240218893Sdim#define TARGET_MOVX (x86_movx & CPUMASK) 241208599Srdivacky#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) 242208599Srdivacky#define TARGET_USE_LOOP (x86_use_loop & CPUMASK) 243208599Srdivacky#define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) 244208599Srdivacky#define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) 245276479Sdim#define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) 246276479Sdim#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) 247208599Srdivacky#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) 248223017Sdim#define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) 249288943Sdim#define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) 250226633Sdim#define TARGET_FAST_PREFIX (x86_fast_prefix & CPUMASK) 251288943Sdim#define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) 252288943Sdim#define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) 253288943Sdim#define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) 254288943Sdim#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) 255288943Sdim#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) 256288943Sdim#define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK) 257288943Sdim#define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK) 258288943Sdim#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK) 259288943Sdim#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK) 260288943Sdim#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK) 261288943Sdim#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK) 262288943Sdim#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK) 263288943Sdim#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK) 264261991Sdim#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK) 265226633Sdim#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK) 266226633Sdim#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 267226633Sdim#define TARGET_SHIFT1 (x86_shift1 & CPUMASK) 268226633Sdim 269288943Sdim#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) 270288943Sdim 271223017Sdim#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) 272#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) 273 274#define ASSEMBLER_DIALECT (ix86_asm_dialect) 275 276#define TARGET_SSE ((target_flags & MASK_SSE) != 0) 277#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) 278#define TARGET_PNI ((target_flags & MASK_PNI) != 0) 279#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 280#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 281 && (ix86_fpmath & FPMATH_387)) 282#define TARGET_MMX ((target_flags & MASK_MMX) != 0) 283#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) 284#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) 285 286#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) 287 288#define TARGET_NO_ALIGN_LONG_STRINGS (target_flags & MASK_NO_ALIGN_LONG_STRINGS) 289 290#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 291#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) 292 293/* WARNING: Do not mark empty strings for translation, as calling 294 gettext on an empty string does NOT return an empty 295 string. */ 296 297 298#define TARGET_SWITCHES \ 299{ { "80387", MASK_80387, N_("Use hardware fp") }, \ 300 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ 301 { "hard-float", MASK_80387, N_("Use hardware fp") }, \ 302 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ 303 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ 304 { "386", 0, "" /*Deprecated.*/}, \ 305 { "486", 0, "" /*Deprecated.*/}, \ 306 { "pentium", 0, "" /*Deprecated.*/}, \ 307 { "pentiumpro", 0, "" /*Deprecated.*/}, \ 308 { "intel-syntax", 0, "" /*Deprecated.*/}, \ 309 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ 310 { "rtd", MASK_RTD, \ 311 N_("Alternate calling convention") }, \ 312 { "no-rtd", -MASK_RTD, \ 313 N_("Use normal calling convention") }, \ 314 { "align-double", MASK_ALIGN_DOUBLE, \ 315 N_("Align some doubles on dword boundary") }, \ 316 { "no-align-double", -MASK_ALIGN_DOUBLE, \ 317 N_("Align doubles on word boundary") }, \ 318 { "svr3-shlib", MASK_SVR3_SHLIB, \ 319 N_("Uninitialized locals in .bss") }, \ 320 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ 321 N_("Uninitialized locals in .data") }, \ 322 { "ieee-fp", MASK_IEEE_FP, \ 323 N_("Use IEEE math for fp comparisons") }, \ 324 { "no-ieee-fp", -MASK_IEEE_FP, \ 325 N_("Do not use IEEE math for fp comparisons") }, \ 326 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ 327 N_("Return values of functions in FPU registers") }, \ 328 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ 329 N_("Do not return values of functions in FPU registers")}, \ 330 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ 331 N_("Do not generate sin, cos, sqrt for FPU") }, \ 332 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ 333 N_("Generate sin, cos, sqrt for FPU")}, \ 334 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ 335 N_("Omit the frame pointer in leaf functions") }, \ 336 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ 337 { "stack-arg-probe", MASK_STACK_PROBE, \ 338 N_("Enable stack probing") }, \ 339 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ 340 { "windows", 0, 0 /* undocumented */ }, \ 341 { "dll", 0, 0 /* undocumented */ }, \ 342 { "align-stringops", -MASK_NO_ALIGN_STROPS, \ 343 N_("Align destination of the string operations") }, \ 344 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ 345 N_("Do not align destination of the string operations") }, \ 346 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ 347 N_("Inline all known string operations") }, \ 348 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ 349 N_("Do not inline all known string operations") }, \ 350 { "push-args", -MASK_NO_PUSH_ARGS, \ 351 N_("Use push instructions to save outgoing arguments") }, \ 352 { "no-push-args", MASK_NO_PUSH_ARGS, \ 353 N_("Do not use push instructions to save outgoing arguments") }, \ 354 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \ 355 N_("Use push instructions to save outgoing arguments") }, \ 356 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \ 357 N_("Do not use push instructions to save outgoing arguments") }, \ 358 { "mmx", MASK_MMX, \ 359 N_("Support MMX built-in functions") }, \ 360 { "no-mmx", -MASK_MMX, \ 361 N_("Do not support MMX built-in functions") }, \ 362 { "3dnow", MASK_3DNOW, \ 363 N_("Support 3DNow! built-in functions") }, \ 364 { "no-3dnow", -MASK_3DNOW, \ 365 N_("Do not support 3DNow! built-in functions") }, \ 366 { "sse", MASK_SSE, \ 367 N_("Support MMX and SSE built-in functions and code generation") }, \ 368 { "no-sse", -MASK_SSE, \ 369 N_("Do not support MMX and SSE built-in functions and code generation") },\ 370 { "sse2", MASK_SSE2, \ 371 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ 372 { "no-sse2", -MASK_SSE2, \ 373 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ 374 { "pni", MASK_PNI, \ 375 N_("Support MMX, SSE, SSE2 and PNI built-in functions and code generation") }, \ 376 { "no-pni", -MASK_PNI, \ 377 N_("Do not support MMX, SSE, SSE2 and PNI built-in functions and code generation") }, \ 378 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ 379 N_("sizeof(long double) is 16") }, \ 380 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ 381 N_("sizeof(long double) is 12") }, \ 382 { "64", MASK_64BIT, \ 383 N_("Generate 64bit x86-64 code") }, \ 384 { "32", -MASK_64BIT, \ 385 N_("Generate 32bit i386 code") }, \ 386 { "red-zone", -MASK_NO_RED_ZONE, \ 387 N_("Use red-zone in the x86-64 code") }, \ 388 { "no-red-zone", MASK_NO_RED_ZONE, \ 389 N_("Do not use red-zone in the x86-64 code") }, \ 390 { "no-align-long-strings", MASK_NO_ALIGN_LONG_STRINGS, \ 391 N_("Do not align long strings specially") }, \ 392 { "align-long-strings", -MASK_NO_ALIGN_LONG_STRINGS, \ 393 N_("Align strings longer than 30 on a 32-byte boundary") }, \ 394 SUBTARGET_SWITCHES \ 395 { "", TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT, 0 }} 396 397#ifndef TARGET_64BIT_DEFAULT 398#define TARGET_64BIT_DEFAULT 0 399#endif 400 401/* Once GDB has been enhanced to deal with functions without frame 402 pointers, we can change this to allow for elimination of 403 the frame pointer in leaf functions. */ 404#define TARGET_DEFAULT 0 405 406/* This is not really a target flag, but is done this way so that 407 it's analogous to similar code for Mach-O on PowerPC. darwin.h 408 redefines this to 1. */ 409#define TARGET_MACHO 0 410 411/* This macro is similar to `TARGET_SWITCHES' but defines names of 412 command options that have values. Its definition is an 413 initializer with a subgrouping for each command option. 414 415 Each subgrouping contains a string constant, that defines the 416 fixed part of the option name, and the address of a variable. The 417 variable, type `char *', is set to the variable part of the given 418 option if the fixed part matches. The actual option name is made 419 by appending `-m' to the specified name. */ 420#define TARGET_OPTIONS \ 421{ { "cpu=", &ix86_cpu_string, \ 422 N_("Schedule code for given CPU")}, \ 423 { "fpmath=", &ix86_fpmath_string, \ 424 N_("Generate floating point mathematics using given instruction set")},\ 425 { "arch=", &ix86_arch_string, \ 426 N_("Generate code for given CPU")}, \ 427 { "regparm=", &ix86_regparm_string, \ 428 N_("Number of registers used to pass integer arguments") }, \ 429 { "align-loops=", &ix86_align_loops_string, \ 430 N_("Loop code aligned to this power of 2") }, \ 431 { "align-jumps=", &ix86_align_jumps_string, \ 432 N_("Jump targets are aligned to this power of 2") }, \ 433 { "align-functions=", &ix86_align_funcs_string, \ 434 N_("Function starts are aligned to this power of 2") }, \ 435 { "preferred-stack-boundary=", \ 436 &ix86_preferred_stack_boundary_string, \ 437 N_("Attempt to keep stack aligned to this power of 2") }, \ 438 { "branch-cost=", &ix86_branch_cost_string, \ 439 N_("Branches are this expensive (1-5, arbitrary units)") }, \ 440 { "cmodel=", &ix86_cmodel_string, \ 441 N_("Use given x86-64 code model") }, \ 442 { "debug-arg", &ix86_debug_arg_string, \ 443 "" /* Undocumented. */ }, \ 444 { "debug-addr", &ix86_debug_addr_string, \ 445 "" /* Undocumented. */ }, \ 446 { "asm=", &ix86_asm_string, \ 447 N_("Use given assembler dialect") }, \ 448 { "tls-dialect=", &ix86_tls_dialect_string, \ 449 N_("Use given thread-local storage dialect") }, \ 450 SUBTARGET_OPTIONS \ 451} 452 453/* Sometimes certain combinations of command options do not make 454 sense on a particular target machine. You can define a macro 455 `OVERRIDE_OPTIONS' to take account of this. This macro, if 456 defined, is executed once just after all the command options have 457 been parsed. 458 459 Don't use this macro to turn on various extra optimizations for 460 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 461 462#define OVERRIDE_OPTIONS override_options () 463 464/* These are meant to be redefined in the host dependent files */ 465#define SUBTARGET_SWITCHES 466#define SUBTARGET_OPTIONS 467 468/* Define this to change the optimizations performed by default. */ 469#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 470 optimization_options ((LEVEL), (SIZE)) 471 472/* Specs for the compiler proper */ 473 474#ifndef CC1_CPU_SPEC 475#define CC1_CPU_SPEC "\ 476%{!mcpu*: \ 477%{m386:-mcpu=i386 \ 478%n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \ 479%{m486:-mcpu=i486 \ 480%n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \ 481%{mpentium:-mcpu=pentium \ 482%n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \ 483%{mpentiumpro:-mcpu=pentiumpro \ 484%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \ 485%{mintel-syntax:-masm=intel \ 486%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 487%{mno-intel-syntax:-masm=att \ 488%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 489#endif 490 491/* Target CPU builtins. */ 492#define TARGET_CPU_CPP_BUILTINS() \ 493 do \ 494 { \ 495 size_t arch_len = strlen (ix86_arch_string); \ 496 size_t cpu_len = strlen (ix86_cpu_string); \ 497 int last_arch_char = ix86_arch_string[arch_len - 1]; \ 498 int last_cpu_char = ix86_cpu_string[cpu_len - 1]; \ 499 \ 500 if (TARGET_64BIT) \ 501 { \ 502 builtin_assert ("cpu=x86_64"); \ 503 builtin_define ("__x86_64"); \ 504 builtin_define ("__x86_64__"); \ 505 builtin_define ("__amd64"); \ 506 builtin_define ("__amd64__"); \ 507 } \ 508 else \ 509 { \ 510 builtin_assert ("cpu=i386"); \ 511 builtin_assert ("machine=i386"); \ 512 builtin_define_std ("i386"); \ 513 } \ 514 \ 515 /* Built-ins based on -mcpu= (or -march= if no \ 516 CPU given). */ \ 517 if (TARGET_386) \ 518 builtin_define ("__tune_i386__"); \ 519 else if (TARGET_486) \ 520 builtin_define ("__tune_i486__"); \ 521 else if (TARGET_PENTIUM) \ 522 { \ 523 builtin_define ("__tune_i586__"); \ 524 builtin_define ("__tune_pentium__"); \ 525 if (last_cpu_char == 'x') \ 526 builtin_define ("__tune_pentium_mmx__"); \ 527 } \ 528 else if (TARGET_PENTIUMPRO) \ 529 { \ 530 builtin_define ("__tune_i686__"); \ 531 builtin_define ("__tune_pentiumpro__"); \ 532 switch (last_cpu_char) \ 533 { \ 534 case '3': \ 535 builtin_define ("__tune_pentium3__"); \ 536 /* FALLTHRU */ \ 537 case '2': \ 538 builtin_define ("__tune_pentium2__"); \ 539 break; \ 540 } \ 541 } \ 542 else if (TARGET_K6) \ 543 { \ 544 builtin_define ("__tune_k6__"); \ 545 if (last_cpu_char == '2') \ 546 builtin_define ("__tune_k6_2__"); \ 547 else if (last_cpu_char == '3') \ 548 builtin_define ("__tune_k6_3__"); \ 549 } \ 550 else if (TARGET_ATHLON) \ 551 { \ 552 builtin_define ("__tune_athlon__"); \ 553 /* Only plain "athlon" lacks SSE. */ \ 554 if (last_cpu_char != 'n') \ 555 builtin_define ("__tune_athlon_sse__"); \ 556 } \ 557 else if (TARGET_PENTIUM4) \ 558 builtin_define ("__tune_pentium4__"); \ 559 \ 560 if (TARGET_MMX) \ 561 builtin_define ("__MMX__"); \ 562 if (TARGET_3DNOW) \ 563 builtin_define ("__3dNOW__"); \ 564 if (TARGET_3DNOW_A) \ 565 builtin_define ("__3dNOW_A__"); \ 566 if (TARGET_SSE) \ 567 builtin_define ("__SSE__"); \ 568 if (TARGET_SSE2) \ 569 builtin_define ("__SSE2__"); \ 570 if (TARGET_PNI) \ 571 builtin_define ("__PNI__"); \ 572 if (TARGET_SSE_MATH && TARGET_SSE) \ 573 builtin_define ("__SSE_MATH__"); \ 574 if (TARGET_SSE_MATH && TARGET_SSE2) \ 575 builtin_define ("__SSE2_MATH__"); \ 576 \ 577 /* Built-ins based on -march=. */ \ 578 if (ix86_arch == PROCESSOR_I486) \ 579 { \ 580 builtin_define ("__i486"); \ 581 builtin_define ("__i486__"); \ 582 } \ 583 else if (ix86_arch == PROCESSOR_PENTIUM) \ 584 { \ 585 builtin_define ("__i586"); \ 586 builtin_define ("__i586__"); \ 587 builtin_define ("__pentium"); \ 588 builtin_define ("__pentium__"); \ 589 if (last_arch_char == 'x') \ 590 builtin_define ("__pentium_mmx__"); \ 591 } \ 592 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ 593 { \ 594 builtin_define ("__i686"); \ 595 builtin_define ("__i686__"); \ 596 builtin_define ("__pentiumpro"); \ 597 builtin_define ("__pentiumpro__"); \ 598 } \ 599 else if (ix86_arch == PROCESSOR_K6) \ 600 { \ 601 \ 602 builtin_define ("__k6"); \ 603 builtin_define ("__k6__"); \ 604 if (last_arch_char == '2') \ 605 builtin_define ("__k6_2__"); \ 606 else if (last_arch_char == '3') \ 607 builtin_define ("__k6_3__"); \ 608 } \ 609 else if (ix86_arch == PROCESSOR_ATHLON) \ 610 { \ 611 builtin_define ("__athlon"); \ 612 builtin_define ("__athlon__"); \ 613 /* Only plain "athlon" lacks SSE. */ \ 614 if (last_arch_char != 'n') \ 615 builtin_define ("__athlon_sse__"); \ 616 } \ 617 else if (ix86_arch == PROCESSOR_PENTIUM4) \ 618 { \ 619 builtin_define ("__pentium4"); \ 620 builtin_define ("__pentium4__"); \ 621 } \ 622 } \ 623 while (0) 624 625#define TARGET_CPU_DEFAULT_i386 0 626#define TARGET_CPU_DEFAULT_i486 1 627#define TARGET_CPU_DEFAULT_pentium 2 628#define TARGET_CPU_DEFAULT_pentium_mmx 3 629#define TARGET_CPU_DEFAULT_pentiumpro 4 630#define TARGET_CPU_DEFAULT_pentium2 5 631#define TARGET_CPU_DEFAULT_pentium3 6 632#define TARGET_CPU_DEFAULT_pentium4 7 633#define TARGET_CPU_DEFAULT_k6 8 634#define TARGET_CPU_DEFAULT_k6_2 9 635#define TARGET_CPU_DEFAULT_k6_3 10 636#define TARGET_CPU_DEFAULT_athlon 11 637#define TARGET_CPU_DEFAULT_athlon_sse 12 638 639#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 640 "pentiumpro", "pentium2", "pentium3", \ 641 "pentium4", "k6", "k6-2", "k6-3",\ 642 "athlon", "athlon-4"} 643 644#ifndef CC1_SPEC 645#define CC1_SPEC "%(cc1_cpu) " 646#endif 647 648/* This macro defines names of additional specifications to put in the 649 specs that can be used in various specifications like CC1_SPEC. Its 650 definition is an initializer with a subgrouping for each command option. 651 652 Each subgrouping contains a string constant, that defines the 653 specification name, and a string constant that used by the GNU CC driver 654 program. 655 656 Do not define this macro if it does not need to do anything. */ 657 658#ifndef SUBTARGET_EXTRA_SPECS 659#define SUBTARGET_EXTRA_SPECS 660#endif 661 662#define EXTRA_SPECS \ 663 { "cc1_cpu", CC1_CPU_SPEC }, \ 664 SUBTARGET_EXTRA_SPECS 665 666/* target machine storage layout */ 667 668/* Define for XFmode or TFmode extended real floating point support. 669 The XFmode is specified by i386 ABI, while TFmode may be faster 670 due to alignment and simplifications in the address calculations. */ 671#define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96) 672#define MAX_LONG_DOUBLE_TYPE_SIZE 128 673#ifdef __x86_64__ 674#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 675#else 676#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 677#endif 678 679/* Set the value of FLT_EVAL_METHOD in float.h. When using only the 680 FPU, assume that the fpcw is set to extended precision; when using 681 only SSE, rounding is correct; when using both SSE and the FPU, 682 the rounding precision is indeterminate, since either may be chosen 683 apparently at random. */ 684#define TARGET_FLT_EVAL_METHOD \ 685 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 1 : 2) 686 687#define SHORT_TYPE_SIZE 16 688#define INT_TYPE_SIZE 32 689#define FLOAT_TYPE_SIZE 32 690#ifndef LONG_TYPE_SIZE 691#define LONG_TYPE_SIZE BITS_PER_WORD 692#endif 693#define MAX_WCHAR_TYPE_SIZE 32 694#define DOUBLE_TYPE_SIZE 64 695#define LONG_LONG_TYPE_SIZE 64 696 697#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 698#define MAX_BITS_PER_WORD 64 699#define MAX_LONG_TYPE_SIZE 64 700#else 701#define MAX_BITS_PER_WORD 32 702#define MAX_LONG_TYPE_SIZE 32 703#endif 704 705/* Define this if most significant byte of a word is the lowest numbered. */ 706/* That is true on the 80386. */ 707 708#define BITS_BIG_ENDIAN 0 709 710/* Define this if most significant byte of a word is the lowest numbered. */ 711/* That is not true on the 80386. */ 712#define BYTES_BIG_ENDIAN 0 713 714/* Define this if most significant word of a multiword number is the lowest 715 numbered. */ 716/* Not true for 80386 */ 717#define WORDS_BIG_ENDIAN 0 718 719/* Width of a word, in units (bytes). */ 720#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 721#ifdef IN_LIBGCC2 722#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 723#else 724#define MIN_UNITS_PER_WORD 4 725#endif 726 727/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 728#define PARM_BOUNDARY BITS_PER_WORD 729 730/* Boundary (in *bits*) on which stack pointer should be aligned. */ 731#define STACK_BOUNDARY BITS_PER_WORD 732 733/* Boundary (in *bits*) on which the stack pointer preferrs to be 734 aligned; the compiler cannot rely on having this alignment. */ 735#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 736 737/* As of July 2001, many runtimes to not align the stack properly when 738 entering main. This causes expand_main_function to forcably align 739 the stack, which results in aligned frames for functions called from 740 main, though it does nothing for the alignment of main itself. */ 741#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 742 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 743 744/* Minimum allocation boundary for the code of a function. */ 745#define FUNCTION_BOUNDARY 8 746 747/* C++ stores the virtual bit in the lowest bit of function pointers. */ 748#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 749 750/* Alignment of field after `int : 0' in a structure. */ 751 752#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 753 754/* Minimum size in bits of the largest boundary to which any 755 and all fundamental data types supported by the hardware 756 might need to be aligned. No data type wants to be aligned 757 rounder than this. 758 759 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary 760 and Pentium Pro XFmode values at 128 bit boundaries. */ 761 762#define BIGGEST_ALIGNMENT 128 763 764/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 765#define ALIGN_MODE_128(MODE) \ 766 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE)) 767 768/* The published ABIs say that doubles should be aligned on word 769 boundaries, so lower the aligment for structure fields unless 770 -malign-double is set. */ 771 772/* ??? Blah -- this macro is used directly by libobjc. Since it 773 supports no vector modes, cut out the complexity and fall back 774 on BIGGEST_FIELD_ALIGNMENT. */ 775#ifdef IN_TARGET_LIBS 776#ifdef __x86_64__ 777#define BIGGEST_FIELD_ALIGNMENT 128 778#else 779#define BIGGEST_FIELD_ALIGNMENT 32 780#endif 781#else 782#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 783 x86_field_alignment (FIELD, COMPUTED) 784#endif 785 786/* If defined, a C expression to compute the alignment given to a 787 constant that is being placed in memory. EXP is the constant 788 and ALIGN is the alignment that the object would ordinarily have. 789 The value of this macro is used instead of that alignment to align 790 the object. 791 792 If this macro is not defined, then ALIGN is used. 793 794 The typical use of this macro is to increase alignment for string 795 constants to be word aligned so that `strcpy' calls that copy 796 constants can be done inline. */ 797 798#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 799 800/* If defined, a C expression to compute the alignment for a static 801 variable. TYPE is the data type, and ALIGN is the alignment that 802 the object would ordinarily have. The value of this macro is used 803 instead of that alignment to align the object. 804 805 If this macro is not defined, then ALIGN is used. 806 807 One use of this macro is to increase alignment of medium-size 808 data to make it all fit in fewer cache lines. Another is to 809 cause character arrays to be word-aligned so that `strcpy' calls 810 that copy constants to character arrays can be done inline. */ 811 812#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 813 814/* If defined, a C expression to compute the alignment for a local 815 variable. TYPE is the data type, and ALIGN is the alignment that 816 the object would ordinarily have. The value of this macro is used 817 instead of that alignment to align the object. 818 819 If this macro is not defined, then ALIGN is used. 820 821 One use of this macro is to increase alignment of medium-size 822 data to make it all fit in fewer cache lines. */ 823 824#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 825 826/* If defined, a C expression that gives the alignment boundary, in 827 bits, of an argument with the specified mode and type. If it is 828 not defined, `PARM_BOUNDARY' is used for all arguments. */ 829 830#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 831 ix86_function_arg_boundary ((MODE), (TYPE)) 832 833/* Set this nonzero if move instructions will actually fail to work 834 when given unaligned data. */ 835#define STRICT_ALIGNMENT 0 836 837/* If bit field type is int, don't let it cross an int, 838 and give entire struct the alignment of an int. */ 839/* Required on the 386 since it doesn't have bit-field insns. */ 840#define PCC_BITFIELD_TYPE_MATTERS 1 841 842/* Standard register usage. */ 843 844/* This processor has special stack-like registers. See reg-stack.c 845 for details. */ 846 847#define STACK_REGS 848#define IS_STACK_MODE(MODE) \ 849 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ 850 || (MODE) == TFmode) 851 852/* Number of actual hardware registers. 853 The hardware registers are assigned numbers for the compiler 854 from 0 to just below FIRST_PSEUDO_REGISTER. 855 All registers that the compiler knows about must be given numbers, 856 even those that are not normally considered general registers. 857 858 In the 80386 we give the 8 general purpose registers the numbers 0-7. 859 We number the floating point registers 8-15. 860 Note that registers 0-7 can be accessed as a short or int, 861 while only 0-3 may be used with byte `mov' instructions. 862 863 Reg 16 does not correspond to any hardware register, but instead 864 appears in the RTL as an argument pointer prior to reload, and is 865 eliminated during reloading in favor of either the stack or frame 866 pointer. */ 867 868#define FIRST_PSEUDO_REGISTER 53 869 870/* Number of hardware registers that go into the DWARF-2 unwind info. 871 If not defined, equals FIRST_PSEUDO_REGISTER. */ 872 873#define DWARF_FRAME_REGISTERS 17 874 875/* 1 for registers that have pervasive standard uses 876 and are not available for the register allocator. 877 On the 80386, the stack pointer is such, as is the arg pointer. 878 879 The value is an mask - bit 1 is set for fixed registers 880 for 32bit target, while 2 is set for fixed registers for 64bit. 881 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 882 */ 883#define FIXED_REGISTERS \ 884/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 885{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ 886/*arg,flags,fpsr,dir,frame*/ \ 887 3, 3, 3, 3, 3, \ 888/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 889 0, 0, 0, 0, 0, 0, 0, 0, \ 890/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 891 0, 0, 0, 0, 0, 0, 0, 0, \ 892/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 893 1, 1, 1, 1, 1, 1, 1, 1, \ 894/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 895 1, 1, 1, 1, 1, 1, 1, 1} 896 897 898/* 1 for registers not available across function calls. 899 These must include the FIXED_REGISTERS and also any 900 registers that can be used without being saved. 901 The latter must include the registers where values are returned 902 and the register where structure-value addresses are passed. 903 Aside from that, you can include as many other registers as you like. 904 905 The value is an mask - bit 1 is set for call used 906 for 32bit target, while 2 is set for call used for 64bit. 907 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 908*/ 909#define CALL_USED_REGISTERS \ 910/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 911{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 912/*arg,flags,fpsr,dir,frame*/ \ 913 3, 3, 3, 3, 3, \ 914/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 915 3, 3, 3, 3, 3, 3, 3, 3, \ 916/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 917 3, 3, 3, 3, 3, 3, 3, 3, \ 918/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 919 3, 3, 3, 3, 1, 1, 1, 1, \ 920/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 921 3, 3, 3, 3, 3, 3, 3, 3} \ 922 923/* Order in which to allocate registers. Each register must be 924 listed once, even those in FIXED_REGISTERS. List frame pointer 925 late and fixed registers last. Note that, in general, we prefer 926 registers listed in CALL_USED_REGISTERS, keeping the others 927 available for storage of persistent values. 928 929 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 930 so this is just empty initializer for array. */ 931 932#define REG_ALLOC_ORDER \ 933{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 934 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 935 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 936 48, 49, 50, 51, 52 } 937 938/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 939 to be rearranged based on a particular function. When using sse math, 940 we want to allocase SSE before x87 registers and vice vera. */ 941 942#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 943 944 945/* Macro to conditionally modify fixed_regs/call_used_regs. */ 946#define CONDITIONAL_REGISTER_USAGE \ 947do { \ 948 int i; \ 949 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 950 { \ 951 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ 952 call_used_regs[i] = (call_used_regs[i] \ 953 & (TARGET_64BIT ? 2 : 1)) != 0; \ 954 } \ 955 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 956 { \ 957 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 958 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 959 } \ 960 if (! TARGET_MMX) \ 961 { \ 962 int i; \ 963 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 964 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 965 fixed_regs[i] = call_used_regs[i] = 1; \ 966 } \ 967 if (! TARGET_SSE) \ 968 { \ 969 int i; \ 970 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 971 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 972 fixed_regs[i] = call_used_regs[i] = 1; \ 973 } \ 974 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 975 { \ 976 int i; \ 977 HARD_REG_SET x; \ 978 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 979 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 980 if (TEST_HARD_REG_BIT (x, i)) \ 981 fixed_regs[i] = call_used_regs[i] = 1; \ 982 } \ 983 } while (0) 984 985/* Return number of consecutive hard regs needed starting at reg REGNO 986 to hold something of mode MODE. 987 This is ordinarily the length in words of a value of mode MODE 988 but can be less for certain modes in special long registers. 989 990 Actually there are no two word move instructions for consecutive 991 registers. And only registers 0-3 may have mov byte instructions 992 applied to them. 993 */ 994 995#define HARD_REGNO_NREGS(REGNO, MODE) \ 996 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 997 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 998 : ((MODE) == TFmode \ 999 ? (TARGET_64BIT ? 2 : 3) \ 1000 : (MODE) == TCmode \ 1001 ? (TARGET_64BIT ? 4 : 6) \ 1002 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1003 1004#define VALID_SSE2_REG_MODE(MODE) \ 1005 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1006 || (MODE) == V2DImode) 1007 1008#define VALID_SSE_REG_MODE(MODE) \ 1009 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1010 || (MODE) == SFmode \ 1011 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \ 1012 || VALID_SSE2_REG_MODE (MODE) \ 1013 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) 1014 1015#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1016 ((MODE) == V2SFmode || (MODE) == SFmode) 1017 1018#define VALID_MMX_REG_MODE(MODE) \ 1019 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 1020 || (MODE) == V2SImode || (MODE) == SImode) 1021 1022#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1023 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ 1024 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ 1025 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) 1026 1027#define VALID_FP_MODE_P(MODE) \ 1028 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 1029 || (!TARGET_64BIT && (MODE) == XFmode) \ 1030 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \ 1031 || (!TARGET_64BIT && (MODE) == XCmode)) 1032 1033#define VALID_INT_MODE_P(MODE) \ 1034 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1035 || (MODE) == DImode \ 1036 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1037 || (MODE) == CDImode \ 1038 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) 1039 1040/* Return true for modes passed in SSE registers. */ 1041#define SSE_REG_MODE_P(MODE) \ 1042 ((MODE) == TImode || (MODE) == V16QImode \ 1043 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ 1044 || (MODE) == V4SFmode || (MODE) == V4SImode) 1045 1046/* Return true for modes passed in MMX registers. */ 1047#define MMX_REG_MODE_P(MODE) \ 1048 ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \ 1049 || (MODE) == V2SFmode) 1050 1051/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1052 1053#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1054 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1055 1056/* Value is 1 if it is a good idea to tie two pseudo registers 1057 when one has mode MODE1 and one has mode MODE2. 1058 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1059 for any hard reg, then this must be 0 for correct output. */ 1060 1061#define MODES_TIEABLE_P(MODE1, MODE2) \ 1062 ((MODE1) == (MODE2) \ 1063 || (((MODE1) == HImode || (MODE1) == SImode \ 1064 || ((MODE1) == QImode \ 1065 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1066 || ((MODE1) == DImode && TARGET_64BIT)) \ 1067 && ((MODE2) == HImode || (MODE2) == SImode \ 1068 || ((MODE2) == QImode \ 1069 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1070 || ((MODE2) == DImode && TARGET_64BIT)))) 1071 1072 1073/* Specify the modes required to caller save a given hard regno. 1074 We do this on i386 to prevent flags from being saved at all. 1075 1076 Kill any attempts to combine saving of modes. */ 1077 1078#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1079 (CC_REGNO_P (REGNO) ? VOIDmode \ 1080 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1081 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \ 1082 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1083 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 1084 : (MODE)) 1085/* Specify the registers used for certain standard purposes. 1086 The values of these macros are register numbers. */ 1087 1088/* on the 386 the pc register is %eip, and is not usable as a general 1089 register. The ordinary mov instructions won't work */ 1090/* #define PC_REGNUM */ 1091 1092/* Register to use for pushing function arguments. */ 1093#define STACK_POINTER_REGNUM 7 1094 1095/* Base register for access to local variables of the function. */ 1096#define HARD_FRAME_POINTER_REGNUM 6 1097 1098/* Base register for access to local variables of the function. */ 1099#define FRAME_POINTER_REGNUM 20 1100 1101/* First floating point reg */ 1102#define FIRST_FLOAT_REG 8 1103 1104/* First & last stack-like regs */ 1105#define FIRST_STACK_REG FIRST_FLOAT_REG 1106#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1107 1108#define FLAGS_REG 17 1109#define FPSR_REG 18 1110#define DIRFLAG_REG 19 1111 1112#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1113#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1114 1115#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1116#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1117 1118#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1119#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1120 1121#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1122#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1123 1124/* Value should be nonzero if functions must have frame pointers. 1125 Zero means the frame pointer need not be set up (and parms 1126 may be accessed via the stack pointer) in functions that seem suitable. 1127 This is computed in `reload', in reload1.c. */ 1128#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1129 1130/* Override this in other tm.h files to cope with various OS losage 1131 requiring a frame pointer. */ 1132#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1133#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1134#endif 1135 1136/* Make sure we can access arbitrary call frames. */ 1137#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1138 1139/* Base register for access to arguments of the function. */ 1140#define ARG_POINTER_REGNUM 16 1141 1142/* Register in which static-chain is passed to a function. 1143 We do use ECX as static chain register for 32 bit ABI. On the 1144 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1145#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1146 1147/* Register to hold the addressing base for position independent 1148 code access to data items. We don't use PIC pointer for 64bit 1149 mode. Define the regnum to dummy value to prevent gcc from 1150 pessimizing code dealing with EBX. 1151 1152 To avoid clobbering a call-saved register unnecessarily, we renumber 1153 the pic register when possible. The change is visible after the 1154 prologue has been emitted. */ 1155 1156#define REAL_PIC_OFFSET_TABLE_REGNUM 3 1157 1158#define PIC_OFFSET_TABLE_REGNUM \ 1159 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \ 1160 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1161 : REAL_PIC_OFFSET_TABLE_REGNUM) 1162 1163#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1164 1165/* Register in which address to store a structure value 1166 arrives in the function. On the 386, the prologue 1167 copies this from the stack to register %eax. */ 1168#define STRUCT_VALUE_INCOMING 0 1169 1170/* Place in which caller passes the structure value address. 1171 0 means push the value on the stack like an argument. */ 1172#define STRUCT_VALUE 0 1173 1174/* A C expression which can inhibit the returning of certain function 1175 values in registers, based on the type of value. A nonzero value 1176 says to return the function value in memory, just as large 1177 structures are always returned. Here TYPE will be a C expression 1178 of type `tree', representing the data type of the value. 1179 1180 Note that values of mode `BLKmode' must be explicitly handled by 1181 this macro. Also, the option `-fpcc-struct-return' takes effect 1182 regardless of this macro. On most systems, it is possible to 1183 leave the macro undefined; this causes a default definition to be 1184 used, whose value is the constant 1 for `BLKmode' values, and 0 1185 otherwise. 1186 1187 Do not use this macro to indicate that structures and unions 1188 should always be returned in memory. You should instead use 1189 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1190 1191#define RETURN_IN_MEMORY(TYPE) \ 1192 ix86_return_in_memory (TYPE) 1193 1194 1195/* Define the classes of registers for register constraints in the 1196 machine description. Also define ranges of constants. 1197 1198 One of the classes must always be named ALL_REGS and include all hard regs. 1199 If there is more than one class, another class must be named NO_REGS 1200 and contain no registers. 1201 1202 The name GENERAL_REGS must be the name of a class (or an alias for 1203 another name such as ALL_REGS). This is the class of registers 1204 that is allowed by "g" or "r" in a register constraint. 1205 Also, registers outside this class are allocated only when 1206 instructions express preferences for them. 1207 1208 The classes must be numbered in nondecreasing order; that is, 1209 a larger-numbered class must never be contained completely 1210 in a smaller-numbered class. 1211 1212 For any two classes, it is very desirable that there be another 1213 class that represents their union. 1214 1215 It might seem that class BREG is unnecessary, since no useful 386 1216 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1217 and the "b" register constraint is useful in asms for syscalls. 1218 1219 The flags and fpsr registers are in no class. */ 1220 1221enum reg_class 1222{ 1223 NO_REGS, 1224 AREG, DREG, CREG, BREG, SIREG, DIREG, 1225 AD_REGS, /* %eax/%edx for DImode */ 1226 Q_REGS, /* %eax %ebx %ecx %edx */ 1227 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1228 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1229 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1230 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1231 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1232 FLOAT_REGS, 1233 SSE_REGS, 1234 MMX_REGS, 1235 FP_TOP_SSE_REGS, 1236 FP_SECOND_SSE_REGS, 1237 FLOAT_SSE_REGS, 1238 FLOAT_INT_REGS, 1239 INT_SSE_REGS, 1240 FLOAT_INT_SSE_REGS, 1241 ALL_REGS, LIM_REG_CLASSES 1242}; 1243 1244#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1245 1246#define INTEGER_CLASS_P(CLASS) \ 1247 reg_class_subset_p ((CLASS), GENERAL_REGS) 1248#define FLOAT_CLASS_P(CLASS) \ 1249 reg_class_subset_p ((CLASS), FLOAT_REGS) 1250#define SSE_CLASS_P(CLASS) \ 1251 reg_class_subset_p ((CLASS), SSE_REGS) 1252#define MMX_CLASS_P(CLASS) \ 1253 reg_class_subset_p ((CLASS), MMX_REGS) 1254#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1255 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1256#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1257 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1258#define MAYBE_SSE_CLASS_P(CLASS) \ 1259 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1260#define MAYBE_MMX_CLASS_P(CLASS) \ 1261 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1262 1263#define Q_CLASS_P(CLASS) \ 1264 reg_class_subset_p ((CLASS), Q_REGS) 1265 1266/* Give names of register classes as strings for dump file. */ 1267 1268#define REG_CLASS_NAMES \ 1269{ "NO_REGS", \ 1270 "AREG", "DREG", "CREG", "BREG", \ 1271 "SIREG", "DIREG", \ 1272 "AD_REGS", \ 1273 "Q_REGS", "NON_Q_REGS", \ 1274 "INDEX_REGS", \ 1275 "LEGACY_REGS", \ 1276 "GENERAL_REGS", \ 1277 "FP_TOP_REG", "FP_SECOND_REG", \ 1278 "FLOAT_REGS", \ 1279 "SSE_REGS", \ 1280 "MMX_REGS", \ 1281 "FP_TOP_SSE_REGS", \ 1282 "FP_SECOND_SSE_REGS", \ 1283 "FLOAT_SSE_REGS", \ 1284 "FLOAT_INT_REGS", \ 1285 "INT_SSE_REGS", \ 1286 "FLOAT_INT_SSE_REGS", \ 1287 "ALL_REGS" } 1288 1289/* Define which registers fit in which classes. 1290 This is an initializer for a vector of HARD_REG_SET 1291 of length N_REG_CLASSES. */ 1292 1293#define REG_CLASS_CONTENTS \ 1294{ { 0x00, 0x0 }, \ 1295 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1296 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1297 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1298 { 0x03, 0x0 }, /* AD_REGS */ \ 1299 { 0x0f, 0x0 }, /* Q_REGS */ \ 1300 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1301 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1302 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1303 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1304 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1305 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1306{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1307{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1308{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1309{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1310{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1311 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1312{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1313{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1314{ 0xffffffff,0x1fffff } \ 1315} 1316 1317/* The same information, inverted: 1318 Return the class number of the smallest class containing 1319 reg number REGNO. This could be a conditional expression 1320 or could index an array. */ 1321 1322#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1323 1324/* When defined, the compiler allows registers explicitly used in the 1325 rtl to be used as spill registers but prevents the compiler from 1326 extending the lifetime of these registers. */ 1327 1328#define SMALL_REGISTER_CLASSES 1 1329 1330#define QI_REG_P(X) \ 1331 (REG_P (X) && REGNO (X) < 4) 1332 1333#define GENERAL_REGNO_P(N) \ 1334 ((N) < 8 || REX_INT_REGNO_P (N)) 1335 1336#define GENERAL_REG_P(X) \ 1337 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1338 1339#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1340 1341#define NON_QI_REG_P(X) \ 1342 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1343 1344#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1345#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1346 1347#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1348#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1349#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1350#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1351 1352#define SSE_REGNO_P(N) \ 1353 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1354 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1355 1356#define SSE_REGNO(N) \ 1357 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1358#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1359 1360#define SSE_FLOAT_MODE_P(MODE) \ 1361 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1362 1363#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1364#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1365 1366#define STACK_REG_P(XOP) \ 1367 (REG_P (XOP) && \ 1368 REGNO (XOP) >= FIRST_STACK_REG && \ 1369 REGNO (XOP) <= LAST_STACK_REG) 1370 1371#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1372 1373#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1374 1375#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1376#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1377 1378/* Indicate whether hard register numbered REG_NO should be converted 1379 to SSA form. */ 1380#define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \ 1381 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM) 1382 1383/* The class value for index registers, and the one for base regs. */ 1384 1385#define INDEX_REG_CLASS INDEX_REGS 1386#define BASE_REG_CLASS GENERAL_REGS 1387 1388/* Get reg_class from a letter such as appears in the machine description. */ 1389 1390#define REG_CLASS_FROM_LETTER(C) \ 1391 ((C) == 'r' ? GENERAL_REGS : \ 1392 (C) == 'R' ? LEGACY_REGS : \ 1393 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1394 (C) == 'Q' ? Q_REGS : \ 1395 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1396 ? FLOAT_REGS \ 1397 : NO_REGS) : \ 1398 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1399 ? FP_TOP_REG \ 1400 : NO_REGS) : \ 1401 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1402 ? FP_SECOND_REG \ 1403 : NO_REGS) : \ 1404 (C) == 'a' ? AREG : \ 1405 (C) == 'b' ? BREG : \ 1406 (C) == 'c' ? CREG : \ 1407 (C) == 'd' ? DREG : \ 1408 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1409 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1410 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1411 (C) == 'A' ? AD_REGS : \ 1412 (C) == 'D' ? DIREG : \ 1413 (C) == 'S' ? SIREG : NO_REGS) 1414 1415/* The letters I, J, K, L and M in a register constraint string 1416 can be used to stand for particular ranges of immediate operands. 1417 This macro defines what the ranges are. 1418 C is the letter, and VALUE is a constant value. 1419 Return 1 if VALUE is in the range specified by C. 1420 1421 I is for non-DImode shifts. 1422 J is for DImode shifts. 1423 K is for signed imm8 operands. 1424 L is for andsi as zero-extending move. 1425 M is for shifts that can be executed by the "lea" opcode. 1426 N is for immedaite operands for out/in instructions (0-255) 1427 */ 1428 1429#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1430 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1431 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1432 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1433 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1434 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1435 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1436 : 0) 1437 1438/* Similar, but for floating constants, and defining letters G and H. 1439 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1440 TARGET_387 isn't set, because the stack register converter may need to 1441 load 0.0 into the function value register. */ 1442 1443#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1444 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1445 : 0) 1446 1447/* A C expression that defines the optional machine-dependent 1448 constraint letters that can be used to segregate specific types of 1449 operands, usually memory references, for the target machine. Any 1450 letter that is not elsewhere defined and not matched by 1451 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1452 be defined. 1453 1454 If it is required for a particular target machine, it should 1455 return 1 if VALUE corresponds to the operand type represented by 1456 the constraint letter C. If C is not defined as an extra 1457 constraint, the value returned should be 0 regardless of VALUE. */ 1458 1459#define EXTRA_CONSTRAINT(VALUE, D) \ 1460 ((D) == 'e' ? x86_64_sign_extended_value (VALUE) \ 1461 : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \ 1462 : (D) == 'C' ? standard_sse_constant_p (VALUE) \ 1463 : 0) 1464 1465/* Place additional restrictions on the register class to use when it 1466 is necessary to be able to hold a value of mode MODE in a reload 1467 register for which class CLASS would ordinarily be used. */ 1468 1469#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1470 ((MODE) == QImode && !TARGET_64BIT \ 1471 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1472 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1473 ? Q_REGS : (CLASS)) 1474 1475/* Given an rtx X being reloaded into a reg required to be 1476 in class CLASS, return the class of reg to actually use. 1477 In general this is just CLASS; but on some machines 1478 in some cases it is preferable to use a more restrictive class. 1479 On the 80386 series, we prevent floating constants from being 1480 reloaded into floating registers (since no move-insn can do that) 1481 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1482 1483/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1484 QImode must go into class Q_REGS. 1485 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1486 movdf to do mem-to-mem moves through integer regs. */ 1487 1488#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1489 ix86_preferred_reload_class ((X), (CLASS)) 1490 1491/* If we are copying between general and FP registers, we need a memory 1492 location. The same is true for SSE and MMX registers. */ 1493#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1494 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1495 1496/* QImode spills from non-QI registers need a scratch. This does not 1497 happen often -- the only example so far requires an uninitialized 1498 pseudo. */ 1499 1500#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1501 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1502 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1503 ? Q_REGS : NO_REGS) 1504 1505/* Return the maximum number of consecutive registers 1506 needed to represent mode MODE in a register of class CLASS. */ 1507/* On the 80386, this is the size of MODE in words, 1508 except in the FP regs, where a single reg is always enough. 1509 The TFmodes are really just 80bit values, so we use only 3 registers 1510 to hold them, instead of 4, as the size would suggest. 1511 */ 1512#define CLASS_MAX_NREGS(CLASS, MODE) \ 1513 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1514 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1515 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ 1516 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1517 1518/* A C expression whose value is nonzero if pseudos that have been 1519 assigned to registers of class CLASS would likely be spilled 1520 because registers of CLASS are needed for spill registers. 1521 1522 The default value of this macro returns 1 if CLASS has exactly one 1523 register and zero otherwise. On most machines, this default 1524 should be used. Only define this macro to some other expression 1525 if pseudo allocated by `local-alloc.c' end up in memory because 1526 their hard registers were needed for spill registers. If this 1527 macro returns nonzero for those classes, those pseudos will only 1528 be allocated by `global.c', which knows how to reallocate the 1529 pseudo to another register. If there would not be another 1530 register available for reallocation, you should not change the 1531 definition of this macro since the only effect of such a 1532 definition would be to slow down register allocation. */ 1533 1534#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1535 (((CLASS) == AREG) \ 1536 || ((CLASS) == DREG) \ 1537 || ((CLASS) == CREG) \ 1538 || ((CLASS) == BREG) \ 1539 || ((CLASS) == AD_REGS) \ 1540 || ((CLASS) == SIREG) \ 1541 || ((CLASS) == DIREG)) 1542 1543/* Return a class of registers that cannot change FROM mode to TO mode. 1544 1545 x87 registers can't do subreg as all values are reformated to extended 1546 precision. XMM registers does not support with nonzero offsets equal 1547 to 4, 8 and 12 otherwise valid for integer registers. Since we can't 1548 determine these, prohibit all nonparadoxical subregs changing size. */ 1549 1550#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1551 (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \ 1552 ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \ 1553 || MAYBE_MMX_CLASS_P (CLASS) \ 1554 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1555 ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0) 1556 1557/* A C statement that adds to CLOBBERS any hard regs the port wishes 1558 to automatically clobber for all asms. 1559 1560 We do this in the new i386 backend to maintain source compatibility 1561 with the old cc0-based compiler. */ 1562 1563#define MD_ASM_CLOBBERS(CLOBBERS) \ 1564 do { \ 1565 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ 1566 (CLOBBERS)); \ 1567 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ 1568 (CLOBBERS)); \ 1569 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ 1570 (CLOBBERS)); \ 1571 } while (0) 1572 1573/* Stack layout; function entry, exit and calling. */ 1574 1575/* Define this if pushing a word on the stack 1576 makes the stack pointer a smaller address. */ 1577#define STACK_GROWS_DOWNWARD 1578 1579/* Define this if the nominal address of the stack frame 1580 is at the high-address end of the local variables; 1581 that is, each additional local variable allocated 1582 goes at a more negative offset in the frame. */ 1583#define FRAME_GROWS_DOWNWARD 1584 1585/* Offset within stack frame to start allocating local variables at. 1586 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1587 first local allocated. Otherwise, it is the offset to the BEGINNING 1588 of the first local allocated. */ 1589#define STARTING_FRAME_OFFSET 0 1590 1591/* If we generate an insn to push BYTES bytes, 1592 this says how many the stack pointer really advances by. 1593 On 386 pushw decrements by exactly 2 no matter what the position was. 1594 On the 386 there is no pushb; we use pushw instead, and this 1595 has the effect of rounding up to 2. 1596 1597 For 64bit ABI we round up to 8 bytes. 1598 */ 1599 1600#define PUSH_ROUNDING(BYTES) \ 1601 (TARGET_64BIT \ 1602 ? (((BYTES) + 7) & (-8)) \ 1603 : (((BYTES) + 1) & (-2))) 1604 1605/* If defined, the maximum amount of space required for outgoing arguments will 1606 be computed and placed into the variable 1607 `current_function_outgoing_args_size'. No space will be pushed onto the 1608 stack for each call; instead, the function prologue should increase the stack 1609 frame size by this amount. */ 1610 1611#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1612 1613/* If defined, a C expression whose value is nonzero when we want to use PUSH 1614 instructions to pass outgoing arguments. */ 1615 1616#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1617 1618/* We want the stack and args grow in opposite directions, even if 1619 PUSH_ARGS is 0. */ 1620#define PUSH_ARGS_REVERSED 1 1621 1622/* Offset of first parameter from the argument pointer register value. */ 1623#define FIRST_PARM_OFFSET(FNDECL) 0 1624 1625/* Define this macro if functions should assume that stack space has been 1626 allocated for arguments even when their values are passed in registers. 1627 1628 The value of this macro is the size, in bytes, of the area reserved for 1629 arguments passed in registers for the function represented by FNDECL. 1630 1631 This space can be allocated by the caller, or be a part of the 1632 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1633 which. */ 1634#define REG_PARM_STACK_SPACE(FNDECL) 0 1635 1636/* Define as a C expression that evaluates to nonzero if we do not know how 1637 to pass TYPE solely in registers. The file expr.h defines a 1638 definition that is usually appropriate, refer to expr.h for additional 1639 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be 1640 computed in the stack and then loaded into a register. */ 1641#define MUST_PASS_IN_STACK(MODE, TYPE) \ 1642 ((TYPE) != 0 \ 1643 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1644 || TREE_ADDRESSABLE (TYPE) \ 1645 || ((MODE) == TImode) \ 1646 || ((MODE) == BLKmode \ 1647 && ! ((TYPE) != 0 \ 1648 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ 1649 && 0 == (int_size_in_bytes (TYPE) \ 1650 % (PARM_BOUNDARY / BITS_PER_UNIT))) \ 1651 && (FUNCTION_ARG_PADDING (MODE, TYPE) \ 1652 == (BYTES_BIG_ENDIAN ? upward : downward))))) 1653 1654/* Value is the number of bytes of arguments automatically 1655 popped when returning from a subroutine call. 1656 FUNDECL is the declaration node of the function (as a tree), 1657 FUNTYPE is the data type of the function (as a tree), 1658 or for a library call it is an identifier node for the subroutine name. 1659 SIZE is the number of bytes of arguments passed on the stack. 1660 1661 On the 80386, the RTD insn may be used to pop them if the number 1662 of args is fixed, but if the number is variable then the caller 1663 must pop them all. RTD can't be used for library calls now 1664 because the library is compiled with the Unix compiler. 1665 Use of RTD is a selectable option, since it is incompatible with 1666 standard Unix calling sequences. If the option is not selected, 1667 the caller must always pop the args. 1668 1669 The attribute stdcall is equivalent to RTD on a per module basis. */ 1670 1671#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1672 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1673 1674/* Define how to find the value returned by a function. 1675 VALTYPE is the data type of the value (as a tree). 1676 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1677 otherwise, FUNC is 0. */ 1678#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1679 ix86_function_value (VALTYPE) 1680 1681#define FUNCTION_VALUE_REGNO_P(N) \ 1682 ix86_function_value_regno_p (N) 1683 1684/* Define how to find the value returned by a library function 1685 assuming the value has mode MODE. */ 1686 1687#define LIBCALL_VALUE(MODE) \ 1688 ix86_libcall_value (MODE) 1689 1690/* Define the size of the result block used for communication between 1691 untyped_call and untyped_return. The block contains a DImode value 1692 followed by the block used by fnsave and frstor. */ 1693 1694#define APPLY_RESULT_SIZE (8+108) 1695 1696/* 1 if N is a possible register number for function argument passing. */ 1697#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1698 1699/* Define a data type for recording info about an argument list 1700 during the scan of that argument list. This data type should 1701 hold all necessary information about the function itself 1702 and about the args processed so far, enough to enable macros 1703 such as FUNCTION_ARG to determine where the next arg should go. */ 1704 1705typedef struct ix86_args { 1706 int words; /* # words passed so far */ 1707 int nregs; /* # registers available for passing */ 1708 int regno; /* next available register number */ 1709 int sse_words; /* # sse words passed so far */ 1710 int sse_nregs; /* # sse registers available for passing */ 1711 int sse_regno; /* next available sse register number */ 1712 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1713} CUMULATIVE_ARGS; 1714 1715/* Initialize a variable CUM of type CUMULATIVE_ARGS 1716 for a call to a function whose data type is FNTYPE. 1717 For a library call, FNTYPE is 0. */ 1718 1719#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1720 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) 1721 1722/* Update the data in CUM to advance over an argument 1723 of mode MODE and data type TYPE. 1724 (TYPE is null for libcalls where that information may not be available.) */ 1725 1726#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1727 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1728 1729/* Define where to put the arguments to a function. 1730 Value is zero to push the argument on the stack, 1731 or a hard register in which to store the argument. 1732 1733 MODE is the argument's machine mode. 1734 TYPE is the data type of the argument (as a tree). 1735 This is null for libcalls where that information may 1736 not be available. 1737 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1738 the preceding args and about the function being called. 1739 NAMED is nonzero if this argument is a named parameter 1740 (otherwise it is an extra parameter matching an ellipsis). */ 1741 1742#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1743 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1744 1745/* For an arg passed partly in registers and partly in memory, 1746 this is the number of registers used. 1747 For args passed entirely in registers or entirely in memory, zero. */ 1748 1749#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1750 1751/* A C expression that indicates when an argument must be passed by 1752 reference. If nonzero for an argument, a copy of that argument is 1753 made in memory and a pointer to the argument is passed instead of 1754 the argument itself. The pointer is passed in whatever way is 1755 appropriate for passing a pointer to that type. */ 1756 1757#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1758 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED) 1759 1760/* If PIC, we cannot make sibling calls to global functions 1761 because the PLT requires %ebx live. 1762 If we are returning floats on the 80387 register stack, we cannot 1763 make a sibcall from a function that doesn't return a float to a 1764 function that does or, conversely, from a function that does return 1765 a float to a function that doesn't; the necessary stack adjustment 1766 would not be executed. */ 1767#define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1768 ((DECL) \ 1769 && (! flag_pic || ! TREE_PUBLIC (DECL)) \ 1770 && (! TARGET_FLOAT_RETURNS_IN_80387 \ 1771 || (FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \ 1772 == FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))) 1773 1774/* Perform any needed actions needed for a function that is receiving a 1775 variable number of arguments. 1776 1777 CUM is as above. 1778 1779 MODE and TYPE are the mode and type of the current parameter. 1780 1781 PRETEND_SIZE is a variable that should be set to the amount of stack 1782 that must be pushed by the prolog to pretend that our caller pushed 1783 it. 1784 1785 Normally, this macro will push all remaining incoming registers on the 1786 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1787 1788#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1789 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ 1790 (NO_RTL)) 1791 1792/* Define the `__builtin_va_list' type for the ABI. */ 1793#define BUILD_VA_LIST_TYPE(VALIST) \ 1794 ((VALIST) = ix86_build_va_list ()) 1795 1796/* Implement `va_start' for varargs and stdarg. */ 1797#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ 1798 ix86_va_start (VALIST, NEXTARG) 1799 1800/* Implement `va_arg'. */ 1801#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ 1802 ix86_va_arg ((VALIST), (TYPE)) 1803 1804/* This macro is invoked at the end of compilation. It is used here to 1805 output code for -fpic that will load the return address into %ebx. */ 1806 1807#undef ASM_FILE_END 1808#define ASM_FILE_END(FILE) ix86_asm_file_end (FILE) 1809 1810/* Output assembler code to FILE to increment profiler label # LABELNO 1811 for profiling a function entry. */ 1812 1813#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1814 1815#define MCOUNT_NAME "_mcount" 1816 1817#define PROFILE_COUNT_REGISTER "edx" 1818 1819/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1820 the stack pointer does not matter. The value is tested only in 1821 functions that have frame pointers. 1822 No definition is equivalent to always zero. */ 1823/* Note on the 386 it might be more efficient not to define this since 1824 we have to restore it ourselves from the frame pointer, in order to 1825 use pop */ 1826 1827#define EXIT_IGNORE_STACK 1 1828 1829/* Output assembler code for a block containing the constant parts 1830 of a trampoline, leaving space for the variable parts. */ 1831 1832/* On the 386, the trampoline contains two instructions: 1833 mov #STATIC,ecx 1834 jmp FUNCTION 1835 The trampoline is generated entirely at runtime. The operand of JMP 1836 is the address of FUNCTION relative to the instruction following the 1837 JMP (which is 5 bytes long). */ 1838 1839/* Length in units of the trampoline for entering a nested function. */ 1840 1841#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1842 1843/* Emit RTL insns to initialize the variable parts of a trampoline. 1844 FNADDR is an RTX for the address of the function's pure code. 1845 CXT is an RTX for the static chain value for the function. */ 1846 1847#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1848 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1849 1850/* Definitions for register eliminations. 1851 1852 This is an array of structures. Each structure initializes one pair 1853 of eliminable registers. The "from" register number is given first, 1854 followed by "to". Eliminations of the same "from" register are listed 1855 in order of preference. 1856 1857 There are two registers that can always be eliminated on the i386. 1858 The frame pointer and the arg pointer can be replaced by either the 1859 hard frame pointer or to the stack pointer, depending upon the 1860 circumstances. The hard frame pointer is not used before reload and 1861 so it is not eligible for elimination. */ 1862 1863#define ELIMINABLE_REGS \ 1864{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1865 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1866 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1867 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1868 1869/* Given FROM and TO register numbers, say whether this elimination is 1870 allowed. Frame pointer elimination is automatically handled. 1871 1872 All other eliminations are valid. */ 1873 1874#define CAN_ELIMINATE(FROM, TO) \ 1875 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1876 1877/* Define the offset between two registers, one to be eliminated, and the other 1878 its replacement, at the start of a routine. */ 1879 1880#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1881 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1882 1883/* Addressing modes, and classification of registers for them. */ 1884 1885/* #define HAVE_POST_INCREMENT 0 */ 1886/* #define HAVE_POST_DECREMENT 0 */ 1887 1888/* #define HAVE_PRE_DECREMENT 0 */ 1889/* #define HAVE_PRE_INCREMENT 0 */ 1890 1891/* Macros to check register numbers against specific register classes. */ 1892 1893/* These assume that REGNO is a hard or pseudo reg number. 1894 They give nonzero only if REGNO is a hard reg of the suitable class 1895 or a pseudo reg currently allocated to a suitable hard reg. 1896 Since they use reg_renumber, they are safe only once reg_renumber 1897 has been allocated, which happens in local-alloc.c. */ 1898 1899#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1900 ((REGNO) < STACK_POINTER_REGNUM \ 1901 || (REGNO >= FIRST_REX_INT_REG \ 1902 && (REGNO) <= LAST_REX_INT_REG) \ 1903 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1904 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1905 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1906 1907#define REGNO_OK_FOR_BASE_P(REGNO) \ 1908 ((REGNO) <= STACK_POINTER_REGNUM \ 1909 || (REGNO) == ARG_POINTER_REGNUM \ 1910 || (REGNO) == FRAME_POINTER_REGNUM \ 1911 || (REGNO >= FIRST_REX_INT_REG \ 1912 && (REGNO) <= LAST_REX_INT_REG) \ 1913 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1914 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1915 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1916 1917#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1918 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1919#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1920 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1921 1922/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1923 and check its validity for a certain class. 1924 We have two alternate definitions for each of them. 1925 The usual definition accepts all pseudo regs; the other rejects 1926 them unless they have been allocated suitable hard regs. 1927 The symbol REG_OK_STRICT causes the latter definition to be used. 1928 1929 Most source files want to accept pseudo regs in the hope that 1930 they will get allocated to the class that the insn wants them to be in. 1931 Source files for reload pass need to be strict. 1932 After reload, it makes no difference, since pseudo regs have 1933 been eliminated by then. */ 1934 1935 1936/* Non strict versions, pseudos are ok */ 1937#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1938 (REGNO (X) < STACK_POINTER_REGNUM \ 1939 || (REGNO (X) >= FIRST_REX_INT_REG \ 1940 && REGNO (X) <= LAST_REX_INT_REG) \ 1941 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1942 1943#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1944 (REGNO (X) <= STACK_POINTER_REGNUM \ 1945 || REGNO (X) == ARG_POINTER_REGNUM \ 1946 || REGNO (X) == FRAME_POINTER_REGNUM \ 1947 || (REGNO (X) >= FIRST_REX_INT_REG \ 1948 && REGNO (X) <= LAST_REX_INT_REG) \ 1949 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1950 1951/* Strict versions, hard registers only */ 1952#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1953#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1954 1955#ifndef REG_OK_STRICT 1956#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1957#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1958 1959#else 1960#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1961#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1962#endif 1963 1964/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1965 that is a valid memory address for an instruction. 1966 The MODE argument is the machine mode for the MEM expression 1967 that wants to use this address. 1968 1969 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1970 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1971 1972 See legitimize_pic_address in i386.c for details as to what 1973 constitutes a legitimate address when -fpic is used. */ 1974 1975#define MAX_REGS_PER_ADDRESS 2 1976 1977#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1978 1979/* Nonzero if the constant value X is a legitimate general operand. 1980 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1981 1982#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1983 1984#ifdef REG_OK_STRICT 1985#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1986do { \ 1987 if (legitimate_address_p ((MODE), (X), 1)) \ 1988 goto ADDR; \ 1989} while (0) 1990 1991#else 1992#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1993do { \ 1994 if (legitimate_address_p ((MODE), (X), 0)) \ 1995 goto ADDR; \ 1996} while (0) 1997 1998#endif 1999 2000/* If defined, a C expression to determine the base term of address X. 2001 This macro is used in only one place: `find_base_term' in alias.c. 2002 2003 It is always safe for this macro to not be defined. It exists so 2004 that alias analysis can understand machine-dependent addresses. 2005 2006 The typical use of this macro is to handle addresses containing 2007 a label_ref or symbol_ref within an UNSPEC. */ 2008 2009#define FIND_BASE_TERM(X) ix86_find_base_term (X) 2010 2011/* Try machine-dependent ways of modifying an illegitimate address 2012 to be legitimate. If we find one, return the new, valid address. 2013 This macro is used in only one place: `memory_address' in explow.c. 2014 2015 OLDX is the address as it was before break_out_memory_refs was called. 2016 In some cases it is useful to look at this to decide what needs to be done. 2017 2018 MODE and WIN are passed so that this macro can use 2019 GO_IF_LEGITIMATE_ADDRESS. 2020 2021 It is always safe for this macro to do nothing. It exists to recognize 2022 opportunities to optimize the output. 2023 2024 For the 80386, we handle X+REG by loading X into a register R and 2025 using R+REG. R will go in a general reg and indexing will be used. 2026 However, if REG is a broken-out memory address or multiplication, 2027 nothing needs to be done because REG can certainly go in a general reg. 2028 2029 When -fpic is used, special handling is needed for symbolic references. 2030 See comments by legitimize_pic_address in i386.c for details. */ 2031 2032#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2033do { \ 2034 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 2035 if (memory_address_p ((MODE), (X))) \ 2036 goto WIN; \ 2037} while (0) 2038 2039#define REWRITE_ADDRESS(X) rewrite_address (X) 2040 2041/* Nonzero if the constant value X is a legitimate general operand 2042 when generating PIC code. It is given that flag_pic is on and 2043 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2044 2045#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 2046 2047#define SYMBOLIC_CONST(X) \ 2048 (GET_CODE (X) == SYMBOL_REF \ 2049 || GET_CODE (X) == LABEL_REF \ 2050 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 2051 2052/* Go to LABEL if ADDR (a legitimate address expression) 2053 has an effect that depends on the machine mode it is used for. 2054 On the 80386, only postdecrement and postincrement address depend thus 2055 (the amount of decrement or increment being the length of the operand). */ 2056#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2057do { \ 2058 if (GET_CODE (ADDR) == POST_INC \ 2059 || GET_CODE (ADDR) == POST_DEC) \ 2060 goto LABEL; \ 2061} while (0) 2062 2063/* Codes for all the SSE/MMX builtins. */ 2064enum ix86_builtins 2065{ 2066 IX86_BUILTIN_ADDPS, 2067 IX86_BUILTIN_ADDSS, 2068 IX86_BUILTIN_DIVPS, 2069 IX86_BUILTIN_DIVSS, 2070 IX86_BUILTIN_MULPS, 2071 IX86_BUILTIN_MULSS, 2072 IX86_BUILTIN_SUBPS, 2073 IX86_BUILTIN_SUBSS, 2074 2075 IX86_BUILTIN_CMPEQPS, 2076 IX86_BUILTIN_CMPLTPS, 2077 IX86_BUILTIN_CMPLEPS, 2078 IX86_BUILTIN_CMPGTPS, 2079 IX86_BUILTIN_CMPGEPS, 2080 IX86_BUILTIN_CMPNEQPS, 2081 IX86_BUILTIN_CMPNLTPS, 2082 IX86_BUILTIN_CMPNLEPS, 2083 IX86_BUILTIN_CMPNGTPS, 2084 IX86_BUILTIN_CMPNGEPS, 2085 IX86_BUILTIN_CMPORDPS, 2086 IX86_BUILTIN_CMPUNORDPS, 2087 IX86_BUILTIN_CMPNEPS, 2088 IX86_BUILTIN_CMPEQSS, 2089 IX86_BUILTIN_CMPLTSS, 2090 IX86_BUILTIN_CMPLESS, 2091 IX86_BUILTIN_CMPNEQSS, 2092 IX86_BUILTIN_CMPNLTSS, 2093 IX86_BUILTIN_CMPNLESS, 2094 IX86_BUILTIN_CMPORDSS, 2095 IX86_BUILTIN_CMPUNORDSS, 2096 IX86_BUILTIN_CMPNESS, 2097 2098 IX86_BUILTIN_COMIEQSS, 2099 IX86_BUILTIN_COMILTSS, 2100 IX86_BUILTIN_COMILESS, 2101 IX86_BUILTIN_COMIGTSS, 2102 IX86_BUILTIN_COMIGESS, 2103 IX86_BUILTIN_COMINEQSS, 2104 IX86_BUILTIN_UCOMIEQSS, 2105 IX86_BUILTIN_UCOMILTSS, 2106 IX86_BUILTIN_UCOMILESS, 2107 IX86_BUILTIN_UCOMIGTSS, 2108 IX86_BUILTIN_UCOMIGESS, 2109 IX86_BUILTIN_UCOMINEQSS, 2110 2111 IX86_BUILTIN_CVTPI2PS, 2112 IX86_BUILTIN_CVTPS2PI, 2113 IX86_BUILTIN_CVTSI2SS, 2114 IX86_BUILTIN_CVTSI642SS, 2115 IX86_BUILTIN_CVTSS2SI, 2116 IX86_BUILTIN_CVTSS2SI64, 2117 IX86_BUILTIN_CVTTPS2PI, 2118 IX86_BUILTIN_CVTTSS2SI, 2119 IX86_BUILTIN_CVTTSS2SI64, 2120 2121 IX86_BUILTIN_MAXPS, 2122 IX86_BUILTIN_MAXSS, 2123 IX86_BUILTIN_MINPS, 2124 IX86_BUILTIN_MINSS, 2125 2126 IX86_BUILTIN_LOADAPS, 2127 IX86_BUILTIN_LOADUPS, 2128 IX86_BUILTIN_STOREAPS, 2129 IX86_BUILTIN_STOREUPS, 2130 IX86_BUILTIN_LOADSS, 2131 IX86_BUILTIN_STORESS, 2132 IX86_BUILTIN_MOVSS, 2133 2134 IX86_BUILTIN_MOVHLPS, 2135 IX86_BUILTIN_MOVLHPS, 2136 IX86_BUILTIN_LOADHPS, 2137 IX86_BUILTIN_LOADLPS, 2138 IX86_BUILTIN_STOREHPS, 2139 IX86_BUILTIN_STORELPS, 2140 2141 IX86_BUILTIN_MASKMOVQ, 2142 IX86_BUILTIN_MOVMSKPS, 2143 IX86_BUILTIN_PMOVMSKB, 2144 2145 IX86_BUILTIN_MOVNTPS, 2146 IX86_BUILTIN_MOVNTQ, 2147 2148 IX86_BUILTIN_LOADDQA, 2149 IX86_BUILTIN_LOADDQU, 2150 IX86_BUILTIN_STOREDQA, 2151 IX86_BUILTIN_STOREDQU, 2152 IX86_BUILTIN_MOVQ, 2153 IX86_BUILTIN_LOADD, 2154 IX86_BUILTIN_STORED, 2155 2156 IX86_BUILTIN_CLRTI, 2157 2158 IX86_BUILTIN_PACKSSWB, 2159 IX86_BUILTIN_PACKSSDW, 2160 IX86_BUILTIN_PACKUSWB, 2161 2162 IX86_BUILTIN_PADDB, 2163 IX86_BUILTIN_PADDW, 2164 IX86_BUILTIN_PADDD, 2165 IX86_BUILTIN_PADDQ, 2166 IX86_BUILTIN_PADDSB, 2167 IX86_BUILTIN_PADDSW, 2168 IX86_BUILTIN_PADDUSB, 2169 IX86_BUILTIN_PADDUSW, 2170 IX86_BUILTIN_PSUBB, 2171 IX86_BUILTIN_PSUBW, 2172 IX86_BUILTIN_PSUBD, 2173 IX86_BUILTIN_PSUBQ, 2174 IX86_BUILTIN_PSUBSB, 2175 IX86_BUILTIN_PSUBSW, 2176 IX86_BUILTIN_PSUBUSB, 2177 IX86_BUILTIN_PSUBUSW, 2178 2179 IX86_BUILTIN_PAND, 2180 IX86_BUILTIN_PANDN, 2181 IX86_BUILTIN_POR, 2182 IX86_BUILTIN_PXOR, 2183 2184 IX86_BUILTIN_PAVGB, 2185 IX86_BUILTIN_PAVGW, 2186 2187 IX86_BUILTIN_PCMPEQB, 2188 IX86_BUILTIN_PCMPEQW, 2189 IX86_BUILTIN_PCMPEQD, 2190 IX86_BUILTIN_PCMPGTB, 2191 IX86_BUILTIN_PCMPGTW, 2192 IX86_BUILTIN_PCMPGTD, 2193 2194 IX86_BUILTIN_PEXTRW, 2195 IX86_BUILTIN_PINSRW, 2196 2197 IX86_BUILTIN_PMADDWD, 2198 2199 IX86_BUILTIN_PMAXSW, 2200 IX86_BUILTIN_PMAXUB, 2201 IX86_BUILTIN_PMINSW, 2202 IX86_BUILTIN_PMINUB, 2203 2204 IX86_BUILTIN_PMULHUW, 2205 IX86_BUILTIN_PMULHW, 2206 IX86_BUILTIN_PMULLW, 2207 2208 IX86_BUILTIN_PSADBW, 2209 IX86_BUILTIN_PSHUFW, 2210 2211 IX86_BUILTIN_PSLLW, 2212 IX86_BUILTIN_PSLLD, 2213 IX86_BUILTIN_PSLLQ, 2214 IX86_BUILTIN_PSRAW, 2215 IX86_BUILTIN_PSRAD, 2216 IX86_BUILTIN_PSRLW, 2217 IX86_BUILTIN_PSRLD, 2218 IX86_BUILTIN_PSRLQ, 2219 IX86_BUILTIN_PSLLWI, 2220 IX86_BUILTIN_PSLLDI, 2221 IX86_BUILTIN_PSLLQI, 2222 IX86_BUILTIN_PSRAWI, 2223 IX86_BUILTIN_PSRADI, 2224 IX86_BUILTIN_PSRLWI, 2225 IX86_BUILTIN_PSRLDI, 2226 IX86_BUILTIN_PSRLQI, 2227 2228 IX86_BUILTIN_PUNPCKHBW, 2229 IX86_BUILTIN_PUNPCKHWD, 2230 IX86_BUILTIN_PUNPCKHDQ, 2231 IX86_BUILTIN_PUNPCKLBW, 2232 IX86_BUILTIN_PUNPCKLWD, 2233 IX86_BUILTIN_PUNPCKLDQ, 2234 2235 IX86_BUILTIN_SHUFPS, 2236 2237 IX86_BUILTIN_RCPPS, 2238 IX86_BUILTIN_RCPSS, 2239 IX86_BUILTIN_RSQRTPS, 2240 IX86_BUILTIN_RSQRTSS, 2241 IX86_BUILTIN_SQRTPS, 2242 IX86_BUILTIN_SQRTSS, 2243 2244 IX86_BUILTIN_UNPCKHPS, 2245 IX86_BUILTIN_UNPCKLPS, 2246 2247 IX86_BUILTIN_ANDPS, 2248 IX86_BUILTIN_ANDNPS, 2249 IX86_BUILTIN_ORPS, 2250 IX86_BUILTIN_XORPS, 2251 2252 IX86_BUILTIN_EMMS, 2253 IX86_BUILTIN_LDMXCSR, 2254 IX86_BUILTIN_STMXCSR, 2255 IX86_BUILTIN_SFENCE, 2256 2257 /* 3DNow! Original */ 2258 IX86_BUILTIN_FEMMS, 2259 IX86_BUILTIN_PAVGUSB, 2260 IX86_BUILTIN_PF2ID, 2261 IX86_BUILTIN_PFACC, 2262 IX86_BUILTIN_PFADD, 2263 IX86_BUILTIN_PFCMPEQ, 2264 IX86_BUILTIN_PFCMPGE, 2265 IX86_BUILTIN_PFCMPGT, 2266 IX86_BUILTIN_PFMAX, 2267 IX86_BUILTIN_PFMIN, 2268 IX86_BUILTIN_PFMUL, 2269 IX86_BUILTIN_PFRCP, 2270 IX86_BUILTIN_PFRCPIT1, 2271 IX86_BUILTIN_PFRCPIT2, 2272 IX86_BUILTIN_PFRSQIT1, 2273 IX86_BUILTIN_PFRSQRT, 2274 IX86_BUILTIN_PFSUB, 2275 IX86_BUILTIN_PFSUBR, 2276 IX86_BUILTIN_PI2FD, 2277 IX86_BUILTIN_PMULHRW, 2278 2279 /* 3DNow! Athlon Extensions */ 2280 IX86_BUILTIN_PF2IW, 2281 IX86_BUILTIN_PFNACC, 2282 IX86_BUILTIN_PFPNACC, 2283 IX86_BUILTIN_PI2FW, 2284 IX86_BUILTIN_PSWAPDSI, 2285 IX86_BUILTIN_PSWAPDSF, 2286 2287 IX86_BUILTIN_SSE_ZERO, 2288 IX86_BUILTIN_MMX_ZERO, 2289 2290 /* SSE2 */ 2291 IX86_BUILTIN_ADDPD, 2292 IX86_BUILTIN_ADDSD, 2293 IX86_BUILTIN_DIVPD, 2294 IX86_BUILTIN_DIVSD, 2295 IX86_BUILTIN_MULPD, 2296 IX86_BUILTIN_MULSD, 2297 IX86_BUILTIN_SUBPD, 2298 IX86_BUILTIN_SUBSD, 2299 2300 IX86_BUILTIN_CMPEQPD, 2301 IX86_BUILTIN_CMPLTPD, 2302 IX86_BUILTIN_CMPLEPD, 2303 IX86_BUILTIN_CMPGTPD, 2304 IX86_BUILTIN_CMPGEPD, 2305 IX86_BUILTIN_CMPNEQPD, 2306 IX86_BUILTIN_CMPNLTPD, 2307 IX86_BUILTIN_CMPNLEPD, 2308 IX86_BUILTIN_CMPNGTPD, 2309 IX86_BUILTIN_CMPNGEPD, 2310 IX86_BUILTIN_CMPORDPD, 2311 IX86_BUILTIN_CMPUNORDPD, 2312 IX86_BUILTIN_CMPNEPD, 2313 IX86_BUILTIN_CMPEQSD, 2314 IX86_BUILTIN_CMPLTSD, 2315 IX86_BUILTIN_CMPLESD, 2316 IX86_BUILTIN_CMPNEQSD, 2317 IX86_BUILTIN_CMPNLTSD, 2318 IX86_BUILTIN_CMPNLESD, 2319 IX86_BUILTIN_CMPORDSD, 2320 IX86_BUILTIN_CMPUNORDSD, 2321 IX86_BUILTIN_CMPNESD, 2322 2323 IX86_BUILTIN_COMIEQSD, 2324 IX86_BUILTIN_COMILTSD, 2325 IX86_BUILTIN_COMILESD, 2326 IX86_BUILTIN_COMIGTSD, 2327 IX86_BUILTIN_COMIGESD, 2328 IX86_BUILTIN_COMINEQSD, 2329 IX86_BUILTIN_UCOMIEQSD, 2330 IX86_BUILTIN_UCOMILTSD, 2331 IX86_BUILTIN_UCOMILESD, 2332 IX86_BUILTIN_UCOMIGTSD, 2333 IX86_BUILTIN_UCOMIGESD, 2334 IX86_BUILTIN_UCOMINEQSD, 2335 2336 IX86_BUILTIN_MAXPD, 2337 IX86_BUILTIN_MAXSD, 2338 IX86_BUILTIN_MINPD, 2339 IX86_BUILTIN_MINSD, 2340 2341 IX86_BUILTIN_ANDPD, 2342 IX86_BUILTIN_ANDNPD, 2343 IX86_BUILTIN_ORPD, 2344 IX86_BUILTIN_XORPD, 2345 2346 IX86_BUILTIN_SQRTPD, 2347 IX86_BUILTIN_SQRTSD, 2348 2349 IX86_BUILTIN_UNPCKHPD, 2350 IX86_BUILTIN_UNPCKLPD, 2351 2352 IX86_BUILTIN_SHUFPD, 2353 2354 IX86_BUILTIN_LOADAPD, 2355 IX86_BUILTIN_LOADUPD, 2356 IX86_BUILTIN_STOREAPD, 2357 IX86_BUILTIN_STOREUPD, 2358 IX86_BUILTIN_LOADSD, 2359 IX86_BUILTIN_STORESD, 2360 IX86_BUILTIN_MOVSD, 2361 2362 IX86_BUILTIN_LOADHPD, 2363 IX86_BUILTIN_LOADLPD, 2364 IX86_BUILTIN_STOREHPD, 2365 IX86_BUILTIN_STORELPD, 2366 2367 IX86_BUILTIN_CVTDQ2PD, 2368 IX86_BUILTIN_CVTDQ2PS, 2369 2370 IX86_BUILTIN_CVTPD2DQ, 2371 IX86_BUILTIN_CVTPD2PI, 2372 IX86_BUILTIN_CVTPD2PS, 2373 IX86_BUILTIN_CVTTPD2DQ, 2374 IX86_BUILTIN_CVTTPD2PI, 2375 2376 IX86_BUILTIN_CVTPI2PD, 2377 IX86_BUILTIN_CVTSI2SD, 2378 IX86_BUILTIN_CVTSI642SD, 2379 2380 IX86_BUILTIN_CVTSD2SI, 2381 IX86_BUILTIN_CVTSD2SI64, 2382 IX86_BUILTIN_CVTSD2SS, 2383 IX86_BUILTIN_CVTSS2SD, 2384 IX86_BUILTIN_CVTTSD2SI, 2385 IX86_BUILTIN_CVTTSD2SI64, 2386 2387 IX86_BUILTIN_CVTPS2DQ, 2388 IX86_BUILTIN_CVTPS2PD, 2389 IX86_BUILTIN_CVTTPS2DQ, 2390 2391 IX86_BUILTIN_MOVNTI, 2392 IX86_BUILTIN_MOVNTPD, 2393 IX86_BUILTIN_MOVNTDQ, 2394 2395 IX86_BUILTIN_SETPD1, 2396 IX86_BUILTIN_SETPD, 2397 IX86_BUILTIN_CLRPD, 2398 IX86_BUILTIN_SETRPD, 2399 IX86_BUILTIN_LOADPD1, 2400 IX86_BUILTIN_LOADRPD, 2401 IX86_BUILTIN_STOREPD1, 2402 IX86_BUILTIN_STORERPD, 2403 2404 /* SSE2 MMX */ 2405 IX86_BUILTIN_MASKMOVDQU, 2406 IX86_BUILTIN_MOVMSKPD, 2407 IX86_BUILTIN_PMOVMSKB128, 2408 IX86_BUILTIN_MOVQ2DQ, 2409 IX86_BUILTIN_MOVDQ2Q, 2410 2411 IX86_BUILTIN_PACKSSWB128, 2412 IX86_BUILTIN_PACKSSDW128, 2413 IX86_BUILTIN_PACKUSWB128, 2414 2415 IX86_BUILTIN_PADDB128, 2416 IX86_BUILTIN_PADDW128, 2417 IX86_BUILTIN_PADDD128, 2418 IX86_BUILTIN_PADDQ128, 2419 IX86_BUILTIN_PADDSB128, 2420 IX86_BUILTIN_PADDSW128, 2421 IX86_BUILTIN_PADDUSB128, 2422 IX86_BUILTIN_PADDUSW128, 2423 IX86_BUILTIN_PSUBB128, 2424 IX86_BUILTIN_PSUBW128, 2425 IX86_BUILTIN_PSUBD128, 2426 IX86_BUILTIN_PSUBQ128, 2427 IX86_BUILTIN_PSUBSB128, 2428 IX86_BUILTIN_PSUBSW128, 2429 IX86_BUILTIN_PSUBUSB128, 2430 IX86_BUILTIN_PSUBUSW128, 2431 2432 IX86_BUILTIN_PAND128, 2433 IX86_BUILTIN_PANDN128, 2434 IX86_BUILTIN_POR128, 2435 IX86_BUILTIN_PXOR128, 2436 2437 IX86_BUILTIN_PAVGB128, 2438 IX86_BUILTIN_PAVGW128, 2439 2440 IX86_BUILTIN_PCMPEQB128, 2441 IX86_BUILTIN_PCMPEQW128, 2442 IX86_BUILTIN_PCMPEQD128, 2443 IX86_BUILTIN_PCMPGTB128, 2444 IX86_BUILTIN_PCMPGTW128, 2445 IX86_BUILTIN_PCMPGTD128, 2446 2447 IX86_BUILTIN_PEXTRW128, 2448 IX86_BUILTIN_PINSRW128, 2449 2450 IX86_BUILTIN_PMADDWD128, 2451 2452 IX86_BUILTIN_PMAXSW128, 2453 IX86_BUILTIN_PMAXUB128, 2454 IX86_BUILTIN_PMINSW128, 2455 IX86_BUILTIN_PMINUB128, 2456 2457 IX86_BUILTIN_PMULUDQ, 2458 IX86_BUILTIN_PMULUDQ128, 2459 IX86_BUILTIN_PMULHUW128, 2460 IX86_BUILTIN_PMULHW128, 2461 IX86_BUILTIN_PMULLW128, 2462 2463 IX86_BUILTIN_PSADBW128, 2464 IX86_BUILTIN_PSHUFHW, 2465 IX86_BUILTIN_PSHUFLW, 2466 IX86_BUILTIN_PSHUFD, 2467 2468 IX86_BUILTIN_PSLLW128, 2469 IX86_BUILTIN_PSLLD128, 2470 IX86_BUILTIN_PSLLQ128, 2471 IX86_BUILTIN_PSRAW128, 2472 IX86_BUILTIN_PSRAD128, 2473 IX86_BUILTIN_PSRLW128, 2474 IX86_BUILTIN_PSRLD128, 2475 IX86_BUILTIN_PSRLQ128, 2476 IX86_BUILTIN_PSLLDQI128, 2477 IX86_BUILTIN_PSLLWI128, 2478 IX86_BUILTIN_PSLLDI128, 2479 IX86_BUILTIN_PSLLQI128, 2480 IX86_BUILTIN_PSRAWI128, 2481 IX86_BUILTIN_PSRADI128, 2482 IX86_BUILTIN_PSRLDQI128, 2483 IX86_BUILTIN_PSRLWI128, 2484 IX86_BUILTIN_PSRLDI128, 2485 IX86_BUILTIN_PSRLQI128, 2486 2487 IX86_BUILTIN_PUNPCKHBW128, 2488 IX86_BUILTIN_PUNPCKHWD128, 2489 IX86_BUILTIN_PUNPCKHDQ128, 2490 IX86_BUILTIN_PUNPCKHQDQ128, 2491 IX86_BUILTIN_PUNPCKLBW128, 2492 IX86_BUILTIN_PUNPCKLWD128, 2493 IX86_BUILTIN_PUNPCKLDQ128, 2494 IX86_BUILTIN_PUNPCKLQDQ128, 2495 2496 IX86_BUILTIN_CLFLUSH, 2497 IX86_BUILTIN_MFENCE, 2498 IX86_BUILTIN_LFENCE, 2499 2500 /* Prescott New Instructions. */ 2501 IX86_BUILTIN_ADDSUBPS, 2502 IX86_BUILTIN_HADDPS, 2503 IX86_BUILTIN_HSUBPS, 2504 IX86_BUILTIN_MOVSHDUP, 2505 IX86_BUILTIN_MOVSLDUP, 2506 IX86_BUILTIN_ADDSUBPD, 2507 IX86_BUILTIN_HADDPD, 2508 IX86_BUILTIN_HSUBPD, 2509 IX86_BUILTIN_LOADDDUP, 2510 IX86_BUILTIN_MOVDDUP, 2511 IX86_BUILTIN_LDDQU, 2512 2513 IX86_BUILTIN_MONITOR, 2514 IX86_BUILTIN_MWAIT, 2515 2516 IX86_BUILTIN_MAX 2517}; 2518 2519#define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info 2520#define TARGET_STRIP_NAME_ENCODING ix86_strip_name_encoding 2521 2522#define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2523 do { \ 2524 const char *xname = (NAME); \ 2525 if (xname[0] == '%') \ 2526 xname += 2; \ 2527 if (xname[0] == '*') \ 2528 xname += 1; \ 2529 else \ 2530 fputs (user_label_prefix, FILE); \ 2531 fputs (xname, FILE); \ 2532 } while (0) 2533 2534/* Max number of args passed in registers. If this is more than 3, we will 2535 have problems with ebx (register #4), since it is a caller save register and 2536 is also used as the pic register in ELF. So for now, don't allow more than 2537 3 registers to be passed in registers. */ 2538 2539#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 2540 2541#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0) 2542 2543 2544/* Specify the machine mode that this machine uses 2545 for the index in the tablejump instruction. */ 2546#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 2547 2548/* Define as C expression which evaluates to nonzero if the tablejump 2549 instruction expects the table to contain offsets from the address of the 2550 table. 2551 Do not define this if the table should contain absolute addresses. */ 2552/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2553 2554/* Define this as 1 if `char' should by default be signed; else as 0. */ 2555#define DEFAULT_SIGNED_CHAR 1 2556 2557/* Number of bytes moved into a data cache for a single prefetch operation. */ 2558#define PREFETCH_BLOCK ix86_cost->prefetch_block 2559 2560/* Number of prefetch operations that can be done in parallel. */ 2561#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 2562 2563/* Max number of bytes we can move from memory to memory 2564 in one reasonably fast instruction. */ 2565#define MOVE_MAX 16 2566 2567/* MOVE_MAX_PIECES is the number of bytes at a time which we can 2568 move efficiently, as opposed to MOVE_MAX which is the maximum 2569 number of bytes we can move with a single instruction. */ 2570#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 2571 2572/* If a memory-to-memory move would take MOVE_RATIO or more simple 2573 move-instruction pairs, we will do a movstr or libcall instead. 2574 Increasing the value will always make code faster, but eventually 2575 incurs high cost in increased code size. 2576 2577 If you don't define this, a reasonable default is used. */ 2578 2579#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 2580 2581/* Define if shifts truncate the shift count 2582 which implies one can omit a sign-extension or zero-extension 2583 of a shift count. */ 2584/* On i386, shifts do truncate the count. But bit opcodes don't. */ 2585 2586/* #define SHIFT_COUNT_TRUNCATED */ 2587 2588/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2589 is done just by pretending it is already truncated. */ 2590#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2591 2592/* We assume that the store-condition-codes instructions store 0 for false 2593 and some other value for true. This is the value stored for true. */ 2594 2595#define STORE_FLAG_VALUE 1 2596 2597/* When a prototype says `char' or `short', really pass an `int'. 2598 (The 386 can't easily push less than an int.) */ 2599 2600#define PROMOTE_PROTOTYPES 1 2601 2602/* A macro to update M and UNSIGNEDP when an object whose type is 2603 TYPE and which has the specified mode and signedness is to be 2604 stored in a register. This macro is only called when TYPE is a 2605 scalar type. 2606 2607 On i386 it is sometimes useful to promote HImode and QImode 2608 quantities to SImode. The choice depends on target type. */ 2609 2610#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2611do { \ 2612 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 2613 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 2614 (MODE) = SImode; \ 2615} while (0) 2616 2617/* Specify the machine mode that pointers have. 2618 After generation of rtl, the compiler makes no further distinction 2619 between pointers and any other objects of this machine mode. */ 2620#define Pmode (TARGET_64BIT ? DImode : SImode) 2621 2622/* A function address in a call instruction 2623 is a byte address (for indexing purposes) 2624 so give the MEM rtx a byte's mode. */ 2625#define FUNCTION_MODE QImode 2626 2627/* A part of a C `switch' statement that describes the relative costs 2628 of constant RTL expressions. It must contain `case' labels for 2629 expression codes `const_int', `const', `symbol_ref', `label_ref' 2630 and `const_double'. Each case must ultimately reach a `return' 2631 statement to return the relative cost of the use of that kind of 2632 constant value in an expression. The cost may depend on the 2633 precise value of the constant, which is available for examination 2634 in X, and the rtx code of the expression in which it is contained, 2635 found in OUTER_CODE. 2636 2637 CODE is the expression code--redundant, since it can be obtained 2638 with `GET_CODE (X)'. */ 2639 2640#define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 2641 case CONST_INT: \ 2642 case CONST: \ 2643 case LABEL_REF: \ 2644 case SYMBOL_REF: \ 2645 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \ 2646 return 3; \ 2647 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \ 2648 return 2; \ 2649 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \ 2650 \ 2651 case CONST_DOUBLE: \ 2652 if (GET_MODE (RTX) == VOIDmode) \ 2653 return 0; \ 2654 switch (standard_80387_constant_p (RTX)) \ 2655 { \ 2656 case 1: /* 0.0 */ \ 2657 return 1; \ 2658 case 2: /* 1.0 */ \ 2659 return 2; \ 2660 default: \ 2661 /* Start with (MEM (SYMBOL_REF)), since that's where \ 2662 it'll probably end up. Add a penalty for size. */ \ 2663 return (COSTS_N_INSNS (1) + (flag_pic != 0) \ 2664 + (GET_MODE (RTX) == SFmode ? 0 \ 2665 : GET_MODE (RTX) == DFmode ? 1 : 2)); \ 2666 } 2667 2668/* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ 2669#define TOPLEVEL_COSTS_N_INSNS(N) \ 2670 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) 2671 2672/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. 2673 This can be used, for example, to indicate how costly a multiply 2674 instruction is. In writing this macro, you can use the construct 2675 `COSTS_N_INSNS (N)' to specify a cost equal to N fast 2676 instructions. OUTER_CODE is the code of the expression in which X 2677 is contained. 2678 2679 This macro is optional; do not define it if the default cost 2680 assumptions are adequate for the target machine. */ 2681 2682#define RTX_COSTS(X, CODE, OUTER_CODE) \ 2683 case ZERO_EXTEND: \ 2684 /* The zero extensions is often completely free on x86_64, so make \ 2685 it as cheap as possible. */ \ 2686 if (TARGET_64BIT && GET_MODE (X) == DImode \ 2687 && GET_MODE (XEXP (X, 0)) == SImode) \ 2688 { \ 2689 total = 1; goto egress_rtx_costs; \ 2690 } \ 2691 else \ 2692 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \ 2693 ix86_cost->add : ix86_cost->movzx); \ 2694 break; \ 2695 case SIGN_EXTEND: \ 2696 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \ 2697 break; \ 2698 case ASHIFT: \ 2699 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 2700 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \ 2701 { \ 2702 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2703 if (value == 1) \ 2704 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2705 if ((value == 2 || value == 3) \ 2706 && !TARGET_DECOMPOSE_LEA \ 2707 && ix86_cost->lea <= ix86_cost->shift_const) \ 2708 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ 2709 } \ 2710 /* fall through */ \ 2711 \ 2712 case ROTATE: \ 2713 case ASHIFTRT: \ 2714 case LSHIFTRT: \ 2715 case ROTATERT: \ 2716 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \ 2717 { \ 2718 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2719 { \ 2720 if (INTVAL (XEXP (X, 1)) > 32) \ 2721 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ 2722 else \ 2723 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ 2724 } \ 2725 else \ 2726 { \ 2727 if (GET_CODE (XEXP (X, 1)) == AND) \ 2728 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ 2729 else \ 2730 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ 2731 } \ 2732 } \ 2733 else \ 2734 { \ 2735 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2736 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ 2737 else \ 2738 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ 2739 } \ 2740 break; \ 2741 \ 2742 case MULT: \ 2743 if (FLOAT_MODE_P (GET_MODE (X))) \ 2744 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fmul); \ 2745 else if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2746 { \ 2747 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2748 int nbits = 0; \ 2749 \ 2750 while (value != 0) \ 2751 { \ 2752 nbits++; \ 2753 value >>= 1; \ 2754 } \ 2755 \ 2756 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2757 + nbits * ix86_cost->mult_bit); \ 2758 } \ 2759 else /* This is arbitrary */ \ 2760 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2761 + 7 * ix86_cost->mult_bit); \ 2762 \ 2763 case DIV: \ 2764 case UDIV: \ 2765 case MOD: \ 2766 case UMOD: \ 2767 if (FLOAT_MODE_P (GET_MODE (X))) \ 2768 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fdiv); \ 2769 else \ 2770 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ 2771 break; \ 2772 \ 2773 case PLUS: \ 2774 if (FLOAT_MODE_P (GET_MODE (X))) \ 2775 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \ 2776 else if (!TARGET_DECOMPOSE_LEA \ 2777 && INTEGRAL_MODE_P (GET_MODE (X)) \ 2778 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \ 2779 { \ 2780 if (GET_CODE (XEXP (X, 0)) == PLUS \ 2781 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ 2782 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ 2783 && CONSTANT_P (XEXP (X, 1))) \ 2784 { \ 2785 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\ 2786 if (val == 2 || val == 4 || val == 8) \ 2787 { \ 2788 return (COSTS_N_INSNS (ix86_cost->lea) \ 2789 + rtx_cost (XEXP (XEXP (X, 0), 1), \ 2790 (OUTER_CODE)) \ 2791 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \ 2792 (OUTER_CODE)) \ 2793 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2794 } \ 2795 } \ 2796 else if (GET_CODE (XEXP (X, 0)) == MULT \ 2797 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ 2798 { \ 2799 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ 2800 if (val == 2 || val == 4 || val == 8) \ 2801 { \ 2802 return (COSTS_N_INSNS (ix86_cost->lea) \ 2803 + rtx_cost (XEXP (XEXP (X, 0), 0), \ 2804 (OUTER_CODE)) \ 2805 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2806 } \ 2807 } \ 2808 else if (GET_CODE (XEXP (X, 0)) == PLUS) \ 2809 { \ 2810 return (COSTS_N_INSNS (ix86_cost->lea) \ 2811 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \ 2812 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \ 2813 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2814 } \ 2815 } \ 2816 /* fall through */ \ 2817 \ 2818 case MINUS: \ 2819 if (FLOAT_MODE_P (GET_MODE (X))) \ 2820 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \ 2821 /* fall through */ \ 2822 \ 2823 case AND: \ 2824 case IOR: \ 2825 case XOR: \ 2826 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2827 return (COSTS_N_INSNS (ix86_cost->add) * 2 \ 2828 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \ 2829 << (GET_MODE (XEXP (X, 0)) != DImode)) \ 2830 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \ 2831 << (GET_MODE (XEXP (X, 1)) != DImode))); \ 2832 /* fall through */ \ 2833 \ 2834 case NEG: \ 2835 if (FLOAT_MODE_P (GET_MODE (X))) \ 2836 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fchs); \ 2837 /* fall through */ \ 2838 \ 2839 case NOT: \ 2840 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2841 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ 2842 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2843 \ 2844 case FLOAT_EXTEND: \ 2845 if (!TARGET_SSE_MATH \ 2846 || !VALID_SSE_REG_MODE (GET_MODE (X))) \ 2847 TOPLEVEL_COSTS_N_INSNS (0); \ 2848 break; \ 2849 \ 2850 case ABS: \ 2851 if (FLOAT_MODE_P (GET_MODE (X))) \ 2852 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fabs); \ 2853 break; \ 2854 \ 2855 case SQRT: \ 2856 if (FLOAT_MODE_P (GET_MODE (X))) \ 2857 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fsqrt); \ 2858 break; \ 2859 \ 2860 egress_rtx_costs: \ 2861 break; 2862 2863 2864/* An expression giving the cost of an addressing mode that contains 2865 ADDRESS. If not defined, the cost is computed from the ADDRESS 2866 expression and the `CONST_COSTS' values. 2867 2868 For most CISC machines, the default cost is a good approximation 2869 of the true cost of the addressing mode. However, on RISC 2870 machines, all instructions normally have the same length and 2871 execution time. Hence all addresses will have equal costs. 2872 2873 In cases where more than one form of an address is known, the form 2874 with the lowest cost will be used. If multiple forms have the 2875 same, lowest, cost, the one that is the most complex will be used. 2876 2877 For example, suppose an address that is equal to the sum of a 2878 register and a constant is used twice in the same basic block. 2879 When this macro is not defined, the address will be computed in a 2880 register and memory references will be indirect through that 2881 register. On machines where the cost of the addressing mode 2882 containing the sum is no higher than that of a simple indirect 2883 reference, this will produce an additional instruction and 2884 possibly require an additional register. Proper specification of 2885 this macro eliminates this overhead for such machines. 2886 2887 Similar use of this macro is made in strength reduction of loops. 2888 2889 ADDRESS need not be valid as an address. In such a case, the cost 2890 is not relevant and can be any value; invalid addresses need not be 2891 assigned a different cost. 2892 2893 On machines where an address involving more than one register is as 2894 cheap as an address computation involving only one register, 2895 defining `ADDRESS_COST' to reflect this can cause two registers to 2896 be live over a region of code where only one would have been if 2897 `ADDRESS_COST' were not defined in that manner. This effect should 2898 be considered in the definition of this macro. Equivalent costs 2899 should probably only be given to addresses with different numbers 2900 of registers on machines with lots of registers. 2901 2902 This macro will normally either not be defined or be defined as a 2903 constant. 2904 2905 For i386, it is better to use a complex address than let gcc copy 2906 the address into a reg and make a new pseudo. But not if the address 2907 requires to two regs - that would mean more pseudos with longer 2908 lifetimes. */ 2909 2910#define ADDRESS_COST(RTX) \ 2911 ix86_address_cost (RTX) 2912 2913/* A C expression for the cost of moving data from a register in class FROM to 2914 one in class TO. The classes are expressed using the enumeration values 2915 such as `GENERAL_REGS'. A value of 2 is the default; other values are 2916 interpreted relative to that. 2917 2918 It is not required that the cost always equal 2 when FROM is the same as TO; 2919 on some machines it is expensive to move between registers if they are not 2920 general registers. */ 2921 2922#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2923 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 2924 2925/* A C expression for the cost of moving data of mode M between a 2926 register and memory. A value of 2 is the default; this cost is 2927 relative to those in `REGISTER_MOVE_COST'. 2928 2929 If moving between registers and memory is more expensive than 2930 between two registers, you should define this macro to express the 2931 relative cost. */ 2932 2933#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 2934 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 2935 2936/* A C expression for the cost of a branch instruction. A value of 1 2937 is the default; other values are interpreted relative to that. */ 2938 2939#define BRANCH_COST ix86_branch_cost 2940 2941/* Define this macro as a C expression which is nonzero if accessing 2942 less than a word of memory (i.e. a `char' or a `short') is no 2943 faster than accessing a word of memory, i.e., if such access 2944 require more than one instruction or if there is no difference in 2945 cost between byte and (aligned) word loads. 2946 2947 When this macro is not defined, the compiler will access a field by 2948 finding the smallest containing object; when it is defined, a 2949 fullword load will be used if alignment permits. Unless bytes 2950 accesses are faster than word accesses, using word accesses is 2951 preferable since it may eliminate subsequent memory access if 2952 subsequent accesses occur to other fields in the same word of the 2953 structure, but to different bytes. */ 2954 2955#define SLOW_BYTE_ACCESS 0 2956 2957/* Nonzero if access to memory by shorts is slow and undesirable. */ 2958#define SLOW_SHORT_ACCESS 0 2959 2960/* Define this macro to be the value 1 if unaligned accesses have a 2961 cost many times greater than aligned accesses, for example if they 2962 are emulated in a trap handler. 2963 2964 When this macro is nonzero, the compiler will act as if 2965 `STRICT_ALIGNMENT' were nonzero when generating code for block 2966 moves. This can cause significantly more instructions to be 2967 produced. Therefore, do not set this macro nonzero if unaligned 2968 accesses only add a cycle or two to the time for a memory access. 2969 2970 If the value of this macro is always zero, it need not be defined. */ 2971 2972/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2973 2974/* Define this macro to inhibit strength reduction of memory 2975 addresses. (On some machines, such strength reduction seems to do 2976 harm rather than good.) */ 2977 2978/* #define DONT_REDUCE_ADDR */ 2979 2980/* Define this macro if it is as good or better to call a constant 2981 function address than to call an address kept in a register. 2982 2983 Desirable on the 386 because a CALL with a constant address is 2984 faster than one with a register address. */ 2985 2986#define NO_FUNCTION_CSE 2987 2988/* Define this macro if it is as good or better for a function to call 2989 itself with an explicit address than to call an address kept in a 2990 register. */ 2991 2992#define NO_RECURSIVE_FUNCTION_CSE 2993 2994/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2995 return the mode to be used for the comparison. 2996 2997 For floating-point equality comparisons, CCFPEQmode should be used. 2998 VOIDmode should be used in all other cases. 2999 3000 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 3001 possible, to allow for more combinations. */ 3002 3003#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 3004 3005/* Return nonzero if MODE implies a floating point inequality can be 3006 reversed. */ 3007 3008#define REVERSIBLE_CC_MODE(MODE) 1 3009 3010/* A C expression whose value is reversed condition code of the CODE for 3011 comparison done in CC_MODE mode. */ 3012#define REVERSE_CONDITION(CODE, MODE) \ 3013 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ 3014 : reverse_condition_maybe_unordered (CODE)) 3015 3016 3017/* Control the assembler format that we output, to the extent 3018 this does not vary between assemblers. */ 3019 3020/* How to refer to registers in assembler output. 3021 This sequence is indexed by compiler's hard-register-number (see above). */ 3022 3023/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" 3024 For non floating point regs, the following are the HImode names. 3025 3026 For float regs, the stack top is sometimes referred to as "%st(0)" 3027 instead of just "%st". PRINT_REG handles this with the "y" code. */ 3028 3029#undef HI_REGISTER_NAMES 3030#define HI_REGISTER_NAMES \ 3031{"ax","dx","cx","bx","si","di","bp","sp", \ 3032 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ 3033 "flags","fpsr", "dirflag", "frame", \ 3034 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 3035 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 3036 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 3037 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 3038 3039#define REGISTER_NAMES HI_REGISTER_NAMES 3040 3041/* Table of additional register names to use in user input. */ 3042 3043#define ADDITIONAL_REGISTER_NAMES \ 3044{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 3045 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 3046 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 3047 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 3048 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 3049 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 3050 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ 3051 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } 3052 3053/* Note we are omitting these since currently I don't know how 3054to get gcc to use these, since they want the same but different 3055number as al, and ax. 3056*/ 3057 3058#define QI_REGISTER_NAMES \ 3059{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 3060 3061/* These parallel the array above, and can be used to access bits 8:15 3062 of regs 0 through 3. */ 3063 3064#define QI_HIGH_REGISTER_NAMES \ 3065{"ah", "dh", "ch", "bh", } 3066 3067/* How to renumber registers for dbx and gdb. */ 3068 3069#define DBX_REGISTER_NUMBER(N) \ 3070 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 3071 3072extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 3073extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 3074extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 3075 3076/* Before the prologue, RA is at 0(%esp). */ 3077#define INCOMING_RETURN_ADDR_RTX \ 3078 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 3079 3080/* After the prologue, RA is at -4(AP) in the current frame. */ 3081#define RETURN_ADDR_RTX(COUNT, FRAME) \ 3082 ((COUNT) == 0 \ 3083 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 3084 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 3085 3086/* PC is dbx register 8; let's use that column for RA. */ 3087#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 3088 3089/* Before the prologue, the top of the frame is at 4(%esp). */ 3090#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 3091 3092/* Describe how we implement __builtin_eh_return. */ 3093#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 3094#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 3095 3096 3097/* Select a format to encode pointers in exception handling data. CODE 3098 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 3099 true if the symbol may be affected by dynamic relocations. 3100 3101 ??? All x86 object file formats are capable of representing this. 3102 After all, the relocation needed is the same as for the call insn. 3103 Whether or not a particular assembler allows us to enter such, I 3104 guess we'll have to see. */ 3105#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 3106 (flag_pic \ 3107 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 3108 : DW_EH_PE_absptr) 3109 3110/* Store in OUTPUT a string (made with alloca) containing 3111 an assembler-name for a local static variable named NAME. 3112 LABELNO is an integer which is different for each call. */ 3113 3114#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 3115( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 3116 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 3117 3118/* This is how to output an insn to push a register on the stack. 3119 It need not be very fast code. */ 3120 3121#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 3122do { \ 3123 if (TARGET_64BIT) \ 3124 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 3125 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 3126 else \ 3127 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 3128} while (0) 3129 3130/* This is how to output an insn to pop a register from the stack. 3131 It need not be very fast code. */ 3132 3133#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 3134do { \ 3135 if (TARGET_64BIT) \ 3136 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 3137 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 3138 else \ 3139 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 3140} while (0) 3141 3142/* This is how to output an element of a case-vector that is absolute. */ 3143 3144#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 3145 ix86_output_addr_vec_elt ((FILE), (VALUE)) 3146 3147/* This is how to output an element of a case-vector that is relative. */ 3148 3149#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 3150 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 3151 3152/* Under some conditions we need jump tables in the text section, because 3153 the assembler cannot handle label differences between sections. */ 3154 3155#define JUMP_TABLES_IN_TEXT_SECTION \ 3156 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 3157 3158/* A C statement that outputs an address constant appropriate to 3159 for DWARF debugging. */ 3160 3161#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ 3162 i386_dwarf_output_addr_const ((FILE), (X)) 3163 3164/* Either simplify a location expression, or return the original. */ 3165 3166#define ASM_SIMPLIFY_DWARF_ADDR(X) \ 3167 i386_simplify_dwarf_addr (X) 3168 3169/* Emit a dtp-relative reference to a TLS variable. */ 3170 3171#ifdef HAVE_AS_TLS 3172#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ 3173 i386_output_dwarf_dtprel (FILE, SIZE, X) 3174#endif 3175 3176/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 3177 and switch back. For x86 we do this only to save a few bytes that 3178 would otherwise be unused in the text section. */ 3179#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 3180 asm (SECTION_OP "\n\t" \ 3181 "call " USER_LABEL_PREFIX #FUNC "\n" \ 3182 TEXT_SECTION_ASM_OP); 3183 3184/* Print operand X (an rtx) in assembler syntax to file FILE. 3185 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 3186 Effect of various CODE letters is described in i386.c near 3187 print_operand function. */ 3188 3189#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 3190 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') 3191 3192/* Print the name of a register based on its machine mode and number. 3193 If CODE is 'w', pretend the mode is HImode. 3194 If CODE is 'b', pretend the mode is QImode. 3195 If CODE is 'k', pretend the mode is SImode. 3196 If CODE is 'q', pretend the mode is DImode. 3197 If CODE is 'h', pretend the reg is the `high' byte register. 3198 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ 3199 3200#define PRINT_REG(X, CODE, FILE) \ 3201 print_reg ((X), (CODE), (FILE)) 3202 3203#define PRINT_OPERAND(FILE, X, CODE) \ 3204 print_operand ((FILE), (X), (CODE)) 3205 3206#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 3207 print_operand_address ((FILE), (ADDR)) 3208 3209#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 3210do { \ 3211 if (! output_addr_const_extra (FILE, (X))) \ 3212 goto FAIL; \ 3213} while (0); 3214 3215/* Print the name of a register for based on its machine mode and number. 3216 This macro is used to print debugging output. 3217 This macro is different from PRINT_REG in that it may be used in 3218 programs that are not linked with aux-output.o. */ 3219 3220#define DEBUG_PRINT_REG(X, CODE, FILE) \ 3221 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ 3222 static const char * const qi_name[] = QI_REGISTER_NAMES; \ 3223 fprintf ((FILE), "%d ", REGNO (X)); \ 3224 if (REGNO (X) == FLAGS_REG) \ 3225 { fputs ("flags", (FILE)); break; } \ 3226 if (REGNO (X) == DIRFLAG_REG) \ 3227 { fputs ("dirflag", (FILE)); break; } \ 3228 if (REGNO (X) == FPSR_REG) \ 3229 { fputs ("fpsr", (FILE)); break; } \ 3230 if (REGNO (X) == ARG_POINTER_REGNUM) \ 3231 { fputs ("argp", (FILE)); break; } \ 3232 if (REGNO (X) == FRAME_POINTER_REGNUM) \ 3233 { fputs ("frame", (FILE)); break; } \ 3234 if (STACK_TOP_P (X)) \ 3235 { fputs ("st(0)", (FILE)); break; } \ 3236 if (FP_REG_P (X)) \ 3237 { fputs (hi_name[REGNO(X)], (FILE)); break; } \ 3238 if (REX_INT_REG_P (X)) \ 3239 { \ 3240 switch (GET_MODE_SIZE (GET_MODE (X))) \ 3241 { \ 3242 default: \ 3243 case 8: \ 3244 fprintf ((FILE), "r%i", REGNO (X) \ 3245 - FIRST_REX_INT_REG + 8); \ 3246 break; \ 3247 case 4: \ 3248 fprintf ((FILE), "r%id", REGNO (X) \ 3249 - FIRST_REX_INT_REG + 8); \ 3250 break; \ 3251 case 2: \ 3252 fprintf ((FILE), "r%iw", REGNO (X) \ 3253 - FIRST_REX_INT_REG + 8); \ 3254 break; \ 3255 case 1: \ 3256 fprintf ((FILE), "r%ib", REGNO (X) \ 3257 - FIRST_REX_INT_REG + 8); \ 3258 break; \ 3259 } \ 3260 break; \ 3261 } \ 3262 switch (GET_MODE_SIZE (GET_MODE (X))) \ 3263 { \ 3264 case 8: \ 3265 fputs ("r", (FILE)); \ 3266 fputs (hi_name[REGNO (X)], (FILE)); \ 3267 break; \ 3268 default: \ 3269 fputs ("e", (FILE)); \ 3270 case 2: \ 3271 fputs (hi_name[REGNO (X)], (FILE)); \ 3272 break; \ 3273 case 1: \ 3274 fputs (qi_name[REGNO (X)], (FILE)); \ 3275 break; \ 3276 } \ 3277 } while (0) 3278 3279/* a letter which is not needed by the normal asm syntax, which 3280 we can use for operand syntax in the extended asm */ 3281 3282#define ASM_OPERAND_LETTER '#' 3283#define RET return "" 3284#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 3285 3286/* Define the codes that are matched by predicates in i386.c. */ 3287 3288#define PREDICATE_CODES \ 3289 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ 3290 SYMBOL_REF, LABEL_REF, CONST}}, \ 3291 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3292 SYMBOL_REF, LABEL_REF, CONST}}, \ 3293 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ 3294 SYMBOL_REF, LABEL_REF, CONST}}, \ 3295 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3296 SYMBOL_REF, LABEL_REF, CONST}}, \ 3297 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3298 SYMBOL_REF, LABEL_REF, CONST}}, \ 3299 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3300 SYMBOL_REF, LABEL_REF, CONST}}, \ 3301 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3302 SYMBOL_REF, LABEL_REF}}, \ 3303 {"shiftdi_operand", {SUBREG, REG, MEM}}, \ 3304 {"const_int_1_operand", {CONST_INT}}, \ 3305 {"const_int_1_31_operand", {CONST_INT}}, \ 3306 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 3307 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3308 LABEL_REF, SUBREG, REG, MEM}}, \ 3309 {"pic_symbolic_operand", {CONST}}, \ 3310 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ 3311 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ 3312 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ 3313 {"const1_operand", {CONST_INT}}, \ 3314 {"const248_operand", {CONST_INT}}, \ 3315 {"incdec_operand", {CONST_INT}}, \ 3316 {"mmx_reg_operand", {REG}}, \ 3317 {"reg_no_sp_operand", {SUBREG, REG}}, \ 3318 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3319 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ 3320 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ 3321 {"index_register_operand", {SUBREG, REG}}, \ 3322 {"q_regs_operand", {SUBREG, REG}}, \ 3323 {"non_q_regs_operand", {SUBREG, REG}}, \ 3324 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ 3325 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ 3326 GE, UNGE, LTGT, UNEQ}}, \ 3327 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ 3328 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ 3329 }}, \ 3330 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ 3331 GTU, UNORDERED, ORDERED, UNLE, UNLT, \ 3332 UNGE, UNGT, LTGT, UNEQ }}, \ 3333 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ 3334 {"ext_register_operand", {SUBREG, REG}}, \ 3335 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ 3336 {"mult_operator", {MULT}}, \ 3337 {"div_operator", {DIV}}, \ 3338 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ 3339 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ 3340 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ 3341 LSHIFTRT, ROTATERT}}, \ 3342 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ 3343 {"memory_displacement_operand", {MEM}}, \ 3344 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3345 LABEL_REF, SUBREG, REG, MEM, AND}}, \ 3346 {"long_memory_operand", {MEM}}, \ 3347 {"tls_symbolic_operand", {SYMBOL_REF}}, \ 3348 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \ 3349 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \ 3350 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \ 3351 {"local_exec_symbolic_operand", {SYMBOL_REF}}, \ 3352 {"any_fp_register_operand", {REG}}, \ 3353 {"register_and_not_any_fp_reg_operand", {REG}}, \ 3354 {"fp_register_operand", {REG}}, \ 3355 {"register_and_not_fp_reg_operand", {REG}}, \ 3356 {"vector_move_operand", {CONST_VECTOR, SUBREG, REG, MEM}}, \ 3357 3358/* A list of predicates that do special things with modes, and so 3359 should not elicit warnings for VOIDmode match_operand. */ 3360 3361#define SPECIAL_MODE_PREDICATES \ 3362 "ext_register_operand", 3363 3364/* Which processor to schedule for. The cpu attribute defines a list that 3365 mirrors this list, so changes to i386.md must be made at the same time. */ 3366 3367enum processor_type 3368{ 3369 PROCESSOR_I386, /* 80386 */ 3370 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 3371 PROCESSOR_PENTIUM, 3372 PROCESSOR_PENTIUMPRO, 3373 PROCESSOR_K6, 3374 PROCESSOR_ATHLON, 3375 PROCESSOR_PENTIUM4, 3376 PROCESSOR_max 3377}; 3378 3379extern enum processor_type ix86_cpu; 3380extern const char *ix86_cpu_string; 3381 3382extern enum processor_type ix86_arch; 3383extern const char *ix86_arch_string; 3384 3385enum fpmath_unit 3386{ 3387 FPMATH_387 = 1, 3388 FPMATH_SSE = 2 3389}; 3390 3391extern enum fpmath_unit ix86_fpmath; 3392extern const char *ix86_fpmath_string; 3393 3394enum tls_dialect 3395{ 3396 TLS_DIALECT_GNU, 3397 TLS_DIALECT_SUN 3398}; 3399 3400extern enum tls_dialect ix86_tls_dialect; 3401extern const char *ix86_tls_dialect_string; 3402 3403enum cmodel { 3404 CM_32, /* The traditional 32-bit ABI. */ 3405 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 3406 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 3407 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 3408 CM_LARGE, /* No assumptions. */ 3409 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */ 3410}; 3411 3412extern enum cmodel ix86_cmodel; 3413extern const char *ix86_cmodel_string; 3414 3415/* Size of the RED_ZONE area. */ 3416#define RED_ZONE_SIZE 128 3417/* Reserved area of the red zone for temporaries. */ 3418#define RED_ZONE_RESERVE 8 3419 3420enum asm_dialect { 3421 ASM_ATT, 3422 ASM_INTEL 3423}; 3424 3425extern const char *ix86_asm_string; 3426extern enum asm_dialect ix86_asm_dialect; 3427 3428extern int ix86_regparm; 3429extern const char *ix86_regparm_string; 3430 3431extern int ix86_preferred_stack_boundary; 3432extern const char *ix86_preferred_stack_boundary_string; 3433 3434extern int ix86_branch_cost; 3435extern const char *ix86_branch_cost_string; 3436 3437extern const char *ix86_debug_arg_string; 3438extern const char *ix86_debug_addr_string; 3439 3440/* Obsoleted by -f options. Remove before 3.2 ships. */ 3441extern const char *ix86_align_loops_string; 3442extern const char *ix86_align_jumps_string; 3443extern const char *ix86_align_funcs_string; 3444 3445/* Smallest class containing REGNO. */ 3446extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 3447 3448extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 3449extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 3450 3451/* To properly truncate FP values into integers, we need to set i387 control 3452 word. We can't emit proper mode switching code before reload, as spills 3453 generated by reload may truncate values incorrectly, but we still can avoid 3454 redundant computation of new control word by the mode switching pass. 3455 The fldcw instructions are still emitted redundantly, but this is probably 3456 not going to be noticeable problem, as most CPUs do have fast path for 3457 the sequence. 3458 3459 The machinery is to emit simple truncation instructions and split them 3460 before reload to instructions having USEs of two memory locations that 3461 are filled by this code to old and new control word. 3462 3463 Post-reload pass may be later used to eliminate the redundant fildcw if 3464 needed. */ 3465 3466enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; 3467 3468/* Define this macro if the port needs extra instructions inserted 3469 for mode switching in an optimizing compilation. */ 3470 3471#define OPTIMIZE_MODE_SWITCHING(ENTITY) 1 3472 3473/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 3474 initializer for an array of integers. Each initializer element N 3475 refers to an entity that needs mode switching, and specifies the 3476 number of different modes that might need to be set for this 3477 entity. The position of the initializer in the initializer - 3478 starting counting at zero - determines the integer that is used to 3479 refer to the mode-switched entity in question. */ 3480 3481#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } 3482 3483/* ENTITY is an integer specifying a mode-switched entity. If 3484 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 3485 return an integer value not larger than the corresponding element 3486 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 3487 must be switched into prior to the execution of INSN. */ 3488 3489#define MODE_NEEDED(ENTITY, I) \ 3490 (GET_CODE (I) == CALL_INSN \ 3491 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ 3492 || GET_CODE (PATTERN (I)) == ASM_INPUT))\ 3493 ? FP_CW_UNINITIALIZED \ 3494 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ 3495 ? FP_CW_ANY \ 3496 : FP_CW_STORED) 3497 3498/* This macro specifies the order in which modes for ENTITY are 3499 processed. 0 is the highest priority. */ 3500 3501#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 3502 3503/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 3504 is the set of hard registers live at the point where the insn(s) 3505 are to be inserted. */ 3506 3507#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3508 ((MODE) == FP_CW_STORED \ 3509 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ 3510 assign_386_stack_local (HImode, 2)), 0\ 3511 : 0) 3512 3513/* Avoid renaming of stack registers, as doing so in combination with 3514 scheduling just increases amount of live registers at time and in 3515 the turn amount of fxch instructions needed. 3516 3517 ??? Maybe Pentium chips benefits from renaming, someone can try... */ 3518 3519#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 3520 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 3521 3522 3523#define MACHINE_DEPENDENT_REORG(X) x86_machine_dependent_reorg(X) 3524 3525#define DLL_IMPORT_EXPORT_PREFIX '@' 3526 3527/* 3528Local variables: 3529version-control: t 3530End: 3531*/ 3532