i386.h revision 117407
1/* Definitions of target machine for GNU compiler for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002 Free Software Foundation, Inc. 4 5This file is part of GNU CC. 6 7GNU CC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GNU CC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GNU CC; see the file COPYING. If not, write to 19the Free Software Foundation, 59 Temple Place - Suite 330, 20Boston, MA 02111-1307, USA. */ 21 22/* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37/* Define the specific costs for a given cpu */ 38 39struct processor_costs { 40 const int add; /* cost of an add instruction */ 41 const int lea; /* cost of a lea instruction */ 42 const int shift_var; /* variable shift costs */ 43 const int shift_const; /* constant shift costs */ 44 const int mult_init; /* cost of starting a multiply */ 45 const int mult_bit; /* cost of multiply per each bit set */ 46 const int divide; /* cost of a divide/mod */ 47 int movsx; /* The cost of movsx operation. */ 48 int movzx; /* The cost of movzx operation. */ 49 const int large_insn; /* insns larger than this cost more */ 50 const int move_ratio; /* The threshold of number of scalar 51 memory-to-memory move insns. */ 52 const int movzbl_load; /* cost of loading using movzbl */ 53 const int int_load[3]; /* cost of loading integer registers 54 in QImode, HImode and SImode relative 55 to reg-reg move (2). */ 56 const int int_store[3]; /* cost of storing integer register 57 in QImode, HImode and SImode */ 58 const int fp_move; /* cost of reg,reg fld/fst */ 59 const int fp_load[3]; /* cost of loading FP register 60 in SFmode, DFmode and XFmode */ 61 const int fp_store[3]; /* cost of storing FP register 62 in SFmode, DFmode and XFmode */ 63 const int mmx_move; /* cost of moving MMX register. */ 64 const int mmx_load[2]; /* cost of loading MMX register 65 in SImode and DImode */ 66 const int mmx_store[2]; /* cost of storing MMX register 67 in SImode and DImode */ 68 const int sse_move; /* cost of moving SSE register. */ 69 const int sse_load[3]; /* cost of loading SSE register 70 in SImode, DImode and TImode*/ 71 const int sse_store[3]; /* cost of storing SSE register 72 in SImode, DImode and TImode*/ 73 const int mmxsse_to_integer; /* cost of moving mmxsse register to 74 integer and vice versa. */ 75 const int prefetch_block; /* bytes moved to cache for prefetch. */ 76 const int simultaneous_prefetches; /* number of parallel prefetch 77 operations. */ 78 const int fadd; /* cost of FADD and FSUB instructions. */ 79 const int fmul; /* cost of FMUL instruction. */ 80 const int fdiv; /* cost of FDIV instruction. */ 81 const int fabs; /* cost of FABS instruction. */ 82 const int fchs; /* cost of FCHS instruction. */ 83 const int fsqrt; /* cost of FSQRT instruction. */ 84}; 85 86extern const struct processor_costs *ix86_cost; 87 88/* Run-time compilation parameters selecting different hardware subsets. */ 89 90extern int target_flags; 91 92/* Macros used in the machine description to test the flags. */ 93 94/* configure can arrange to make this 2, to force a 486. */ 95 96#ifndef TARGET_CPU_DEFAULT 97#define TARGET_CPU_DEFAULT 0 98#endif 99 100/* Masks for the -m switches */ 101#define MASK_80387 0x00000001 /* Hardware floating point */ 102#define MASK_RTD 0x00000002 /* Use ret that pops args */ 103#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ 104#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ 105#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ 106#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ 107#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ 108#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ 109#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ 110#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ 111#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ 112#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ 113#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ 114#define MASK_MMX 0x00002000 /* Support MMX regs/builtins */ 115#define MASK_SSE 0x00004000 /* Support SSE regs/builtins */ 116#define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */ 117#define MASK_3DNOW 0x00010000 /* Support 3Dnow builtins */ 118#define MASK_3DNOW_A 0x00020000 /* Support Athlon 3Dnow builtins */ 119#define MASK_128BIT_LONG_DOUBLE 0x00040000 /* long double size is 128bit */ 120#define MASK_64BIT 0x00080000 /* Produce 64bit code */ 121 122/* Unused: 0x03f0000 */ 123 124/* ... overlap with subtarget options starts by 0x04000000. */ 125#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ 126#define MASK_NO_ALIGN_LONG_STRINGS 0x08000000 /* Do not align long strings specially */ 127 128/* Use the floating point instructions */ 129#define TARGET_80387 (target_flags & MASK_80387) 130 131/* Compile using ret insn that pops args. 132 This will not work unless you use prototypes at least 133 for all functions that can take varying numbers of args. */ 134#define TARGET_RTD (target_flags & MASK_RTD) 135 136/* Align doubles to a two word boundary. This breaks compatibility with 137 the published ABI's for structures containing doubles, but produces 138 faster code on the pentium. */ 139#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) 140 141/* Use push instructions to save outgoing args. */ 142#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) 143 144/* Accumulate stack adjustments to prologue/epilogue. */ 145#define TARGET_ACCUMULATE_OUTGOING_ARGS \ 146 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) 147 148/* Put uninitialized locals into bss, not data. 149 Meaningful only on svr3. */ 150#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) 151 152/* Use IEEE floating point comparisons. These handle correctly the cases 153 where the result of a comparison is unordered. Normally SIGFPE is 154 generated in such cases, in which case this isn't needed. */ 155#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) 156 157/* Functions that return a floating point value may return that value 158 in the 387 FPU or in 386 integer registers. If set, this flag causes 159 the 387 to be used, which is compatible with most calling conventions. */ 160#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) 161 162/* Long double is 128bit instead of 96bit, even when only 80bits are used. 163 This mode wastes cache, but avoid misaligned data accesses and simplifies 164 address calculations. */ 165#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) 166 167/* Disable generation of FP sin, cos and sqrt operations for 387. 168 This is because FreeBSD lacks these in the math-emulator-code */ 169#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) 170 171/* Don't create frame pointers for leaf functions */ 172#define TARGET_OMIT_LEAF_FRAME_POINTER \ 173 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) 174 175/* Debug GO_IF_LEGITIMATE_ADDRESS */ 176#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) 177 178/* Debug FUNCTION_ARG macros */ 179#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) 180 181/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 182 compile-time constant. */ 183#ifdef IN_LIBGCC2 184#ifdef __x86_64__ 185#define TARGET_64BIT 1 186#else 187#define TARGET_64BIT 0 188#endif 189#else 190#ifdef TARGET_BI_ARCH 191#define TARGET_64BIT (target_flags & MASK_64BIT) 192#else 193#if TARGET_64BIT_DEFAULT 194#define TARGET_64BIT 1 195#else 196#define TARGET_64BIT 0 197#endif 198#endif 199#endif 200 201#define TARGET_386 (ix86_cpu == PROCESSOR_I386) 202#define TARGET_486 (ix86_cpu == PROCESSOR_I486) 203#define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) 204#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) 205#define TARGET_K6 (ix86_cpu == PROCESSOR_K6) 206#define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) 207#define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4) 208 209#define CPUMASK (1 << ix86_cpu) 210extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 211extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 212extern const int x86_branch_hints, x86_unroll_strlen; 213extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 214extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; 215extern const int x86_use_cltd, x86_read_modify_write; 216extern const int x86_read_modify, x86_split_long_moves; 217extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; 218extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 219extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 220extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 221extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 222extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 223extern const int x86_epilogue_using_move, x86_decompose_lea; 224extern const int x86_arch_always_fancy_math_387, x86_shift1; 225extern int x86_prefetch_sse; 226 227#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) 228#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) 229#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) 230#define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) 231#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) 232/* For sane SSE instruction set generation we need fcomi instruction. It is 233 safe to enable all CMOVE instructions. */ 234#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 235#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) 236#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK) 237#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) 238#define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT) 239#define TARGET_MOVX (x86_movx & CPUMASK) 240#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) 241#define TARGET_USE_LOOP (x86_use_loop & CPUMASK) 242#define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) 243#define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) 244#define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) 245#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) 246#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) 247#define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) 248#define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) 249#define TARGET_FAST_PREFIX (x86_fast_prefix & CPUMASK) 250#define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) 251#define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) 252#define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) 253#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) 254#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) 255#define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK) 256#define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK) 257#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK) 258#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK) 259#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK) 260#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK) 261#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK) 262#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK) 263#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK) 264#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK) 265#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 266#define TARGET_SHIFT1 (x86_shift1 & CPUMASK) 267 268#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) 269 270#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) 271#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) 272 273#define ASSEMBLER_DIALECT (ix86_asm_dialect) 274 275#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0) 276#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) 277#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 278#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 279 && (ix86_fpmath & FPMATH_387)) 280#define TARGET_MMX ((target_flags & MASK_MMX) != 0) 281#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) 282#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) 283 284#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) 285 286#define TARGET_NO_ALIGN_LONG_STRINGS (target_flags & MASK_NO_ALIGN_LONG_STRINGS) 287 288#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 289#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) 290 291/* WARNING: Do not mark empty strings for translation, as calling 292 gettext on an empty string does NOT return an empty 293 string. */ 294 295 296#define TARGET_SWITCHES \ 297{ { "80387", MASK_80387, N_("Use hardware fp") }, \ 298 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ 299 { "hard-float", MASK_80387, N_("Use hardware fp") }, \ 300 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ 301 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ 302 { "386", 0, "" /*Deprecated.*/}, \ 303 { "486", 0, "" /*Deprecated.*/}, \ 304 { "pentium", 0, "" /*Deprecated.*/}, \ 305 { "pentiumpro", 0, "" /*Deprecated.*/}, \ 306 { "intel-syntax", 0, "" /*Deprecated.*/}, \ 307 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ 308 { "rtd", MASK_RTD, \ 309 N_("Alternate calling convention") }, \ 310 { "no-rtd", -MASK_RTD, \ 311 N_("Use normal calling convention") }, \ 312 { "align-double", MASK_ALIGN_DOUBLE, \ 313 N_("Align some doubles on dword boundary") }, \ 314 { "no-align-double", -MASK_ALIGN_DOUBLE, \ 315 N_("Align doubles on word boundary") }, \ 316 { "svr3-shlib", MASK_SVR3_SHLIB, \ 317 N_("Uninitialized locals in .bss") }, \ 318 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ 319 N_("Uninitialized locals in .data") }, \ 320 { "ieee-fp", MASK_IEEE_FP, \ 321 N_("Use IEEE math for fp comparisons") }, \ 322 { "no-ieee-fp", -MASK_IEEE_FP, \ 323 N_("Do not use IEEE math for fp comparisons") }, \ 324 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ 325 N_("Return values of functions in FPU registers") }, \ 326 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ 327 N_("Do not return values of functions in FPU registers")}, \ 328 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ 329 N_("Do not generate sin, cos, sqrt for FPU") }, \ 330 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ 331 N_("Generate sin, cos, sqrt for FPU")}, \ 332 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ 333 N_("Omit the frame pointer in leaf functions") }, \ 334 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ 335 { "stack-arg-probe", MASK_STACK_PROBE, \ 336 N_("Enable stack probing") }, \ 337 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ 338 { "windows", 0, 0 /* undocumented */ }, \ 339 { "dll", 0, 0 /* undocumented */ }, \ 340 { "align-stringops", -MASK_NO_ALIGN_STROPS, \ 341 N_("Align destination of the string operations") }, \ 342 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ 343 N_("Do not align destination of the string operations") }, \ 344 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ 345 N_("Inline all known string operations") }, \ 346 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ 347 N_("Do not inline all known string operations") }, \ 348 { "push-args", -MASK_NO_PUSH_ARGS, \ 349 N_("Use push instructions to save outgoing arguments") }, \ 350 { "no-push-args", MASK_NO_PUSH_ARGS, \ 351 N_("Do not use push instructions to save outgoing arguments") }, \ 352 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \ 353 N_("Use push instructions to save outgoing arguments") }, \ 354 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \ 355 N_("Do not use push instructions to save outgoing arguments") }, \ 356 { "mmx", MASK_MMX, \ 357 N_("Support MMX built-in functions") }, \ 358 { "no-mmx", -MASK_MMX, \ 359 N_("Do not support MMX built-in functions") }, \ 360 { "3dnow", MASK_3DNOW, \ 361 N_("Support 3DNow! built-in functions") }, \ 362 { "no-3dnow", -MASK_3DNOW, \ 363 N_("Do not support 3DNow! built-in functions") }, \ 364 { "sse", MASK_SSE, \ 365 N_("Support MMX and SSE built-in functions and code generation") }, \ 366 { "no-sse", -MASK_SSE, \ 367 N_("Do not support MMX and SSE built-in functions and code generation") },\ 368 { "sse2", MASK_SSE2, \ 369 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ 370 { "no-sse2", -MASK_SSE2, \ 371 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ 372 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ 373 N_("sizeof(long double) is 16") }, \ 374 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ 375 N_("sizeof(long double) is 12") }, \ 376 { "64", MASK_64BIT, \ 377 N_("Generate 64bit x86-64 code") }, \ 378 { "32", -MASK_64BIT, \ 379 N_("Generate 32bit i386 code") }, \ 380 { "red-zone", -MASK_NO_RED_ZONE, \ 381 N_("Use red-zone in the x86-64 code") }, \ 382 { "no-red-zone", MASK_NO_RED_ZONE, \ 383 N_("Do not use red-zone in the x86-64 code") }, \ 384 { "no-align-long-strings", MASK_NO_ALIGN_LONG_STRINGS, \ 385 N_("Do not align long strings specially") }, \ 386 { "align-long-strings", -MASK_NO_ALIGN_LONG_STRINGS, \ 387 N_("Align strings longer than 30 on a 32-byte boundary") }, \ 388 SUBTARGET_SWITCHES \ 389 { "", TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT, 0 }} 390 391#ifndef TARGET_64BIT_DEFAULT 392#define TARGET_64BIT_DEFAULT 0 393#endif 394 395/* Once GDB has been enhanced to deal with functions without frame 396 pointers, we can change this to allow for elimination of 397 the frame pointer in leaf functions. */ 398#define TARGET_DEFAULT 0 399 400/* This is not really a target flag, but is done this way so that 401 it's analogous to similar code for Mach-O on PowerPC. darwin.h 402 redefines this to 1. */ 403#define TARGET_MACHO 0 404 405/* This macro is similar to `TARGET_SWITCHES' but defines names of 406 command options that have values. Its definition is an 407 initializer with a subgrouping for each command option. 408 409 Each subgrouping contains a string constant, that defines the 410 fixed part of the option name, and the address of a variable. The 411 variable, type `char *', is set to the variable part of the given 412 option if the fixed part matches. The actual option name is made 413 by appending `-m' to the specified name. */ 414#define TARGET_OPTIONS \ 415{ { "cpu=", &ix86_cpu_string, \ 416 N_("Schedule code for given CPU")}, \ 417 { "fpmath=", &ix86_fpmath_string, \ 418 N_("Generate floating point mathematics using given instruction set")},\ 419 { "arch=", &ix86_arch_string, \ 420 N_("Generate code for given CPU")}, \ 421 { "regparm=", &ix86_regparm_string, \ 422 N_("Number of registers used to pass integer arguments") }, \ 423 { "align-loops=", &ix86_align_loops_string, \ 424 N_("Loop code aligned to this power of 2") }, \ 425 { "align-jumps=", &ix86_align_jumps_string, \ 426 N_("Jump targets are aligned to this power of 2") }, \ 427 { "align-functions=", &ix86_align_funcs_string, \ 428 N_("Function starts are aligned to this power of 2") }, \ 429 { "preferred-stack-boundary=", \ 430 &ix86_preferred_stack_boundary_string, \ 431 N_("Attempt to keep stack aligned to this power of 2") }, \ 432 { "branch-cost=", &ix86_branch_cost_string, \ 433 N_("Branches are this expensive (1-5, arbitrary units)") }, \ 434 { "cmodel=", &ix86_cmodel_string, \ 435 N_("Use given x86-64 code model") }, \ 436 { "debug-arg", &ix86_debug_arg_string, \ 437 "" /* Undocumented. */ }, \ 438 { "debug-addr", &ix86_debug_addr_string, \ 439 "" /* Undocumented. */ }, \ 440 { "asm=", &ix86_asm_string, \ 441 N_("Use given assembler dialect") }, \ 442 { "tls-dialect=", &ix86_tls_dialect_string, \ 443 N_("Use given thread-local storage dialect") }, \ 444 SUBTARGET_OPTIONS \ 445} 446 447/* Sometimes certain combinations of command options do not make 448 sense on a particular target machine. You can define a macro 449 `OVERRIDE_OPTIONS' to take account of this. This macro, if 450 defined, is executed once just after all the command options have 451 been parsed. 452 453 Don't use this macro to turn on various extra optimizations for 454 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 455 456#define OVERRIDE_OPTIONS override_options () 457 458/* These are meant to be redefined in the host dependent files */ 459#define SUBTARGET_SWITCHES 460#define SUBTARGET_OPTIONS 461 462/* Define this to change the optimizations performed by default. */ 463#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 464 optimization_options ((LEVEL), (SIZE)) 465 466/* Specs for the compiler proper */ 467 468#ifndef CC1_CPU_SPEC 469#define CC1_CPU_SPEC "\ 470%{!mcpu*: \ 471%{m386:-mcpu=i386 \ 472%n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \ 473%{m486:-mcpu=i486 \ 474%n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \ 475%{mpentium:-mcpu=pentium \ 476%n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \ 477%{mpentiumpro:-mcpu=pentiumpro \ 478%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \ 479%{mintel-syntax:-masm=intel \ 480%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 481%{mno-intel-syntax:-masm=att \ 482%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 483#endif 484 485/* Target CPU builtins. */ 486#define TARGET_CPU_CPP_BUILTINS() \ 487 do \ 488 { \ 489 size_t arch_len = strlen (ix86_arch_string); \ 490 size_t cpu_len = strlen (ix86_cpu_string); \ 491 int last_arch_char = ix86_arch_string[arch_len - 1]; \ 492 int last_cpu_char = ix86_cpu_string[cpu_len - 1]; \ 493 \ 494 if (TARGET_64BIT) \ 495 { \ 496 builtin_assert ("cpu=x86_64"); \ 497 builtin_define ("__x86_64"); \ 498 builtin_define ("__x86_64__"); \ 499 builtin_define ("__amd64"); \ 500 builtin_define ("__amd64__"); \ 501 } \ 502 else \ 503 { \ 504 builtin_assert ("cpu=i386"); \ 505 builtin_assert ("machine=i386"); \ 506 builtin_define_std ("i386"); \ 507 } \ 508 \ 509 /* Built-ins based on -mcpu= (or -march= if no \ 510 CPU given). */ \ 511 if (TARGET_386) \ 512 builtin_define ("__tune_i386__"); \ 513 else if (TARGET_486) \ 514 builtin_define ("__tune_i486__"); \ 515 else if (TARGET_PENTIUM) \ 516 { \ 517 builtin_define ("__tune_i586__"); \ 518 builtin_define ("__tune_pentium__"); \ 519 if (last_cpu_char == 'x') \ 520 builtin_define ("__tune_pentium_mmx__"); \ 521 } \ 522 else if (TARGET_PENTIUMPRO) \ 523 { \ 524 builtin_define ("__tune_i686__"); \ 525 builtin_define ("__tune_pentiumpro__"); \ 526 switch (last_cpu_char) \ 527 { \ 528 case '3': \ 529 builtin_define ("__tune_pentium3__"); \ 530 /* FALLTHRU */ \ 531 case '2': \ 532 builtin_define ("__tune_pentium2__"); \ 533 break; \ 534 } \ 535 } \ 536 else if (TARGET_K6) \ 537 { \ 538 builtin_define ("__tune_k6__"); \ 539 if (last_cpu_char == '2') \ 540 builtin_define ("__tune_k6_2__"); \ 541 else if (last_cpu_char == '3') \ 542 builtin_define ("__tune_k6_3__"); \ 543 } \ 544 else if (TARGET_ATHLON) \ 545 { \ 546 builtin_define ("__tune_athlon__"); \ 547 /* Only plain "athlon" lacks SSE. */ \ 548 if (last_cpu_char != 'n') \ 549 builtin_define ("__tune_athlon_sse__"); \ 550 } \ 551 else if (TARGET_PENTIUM4) \ 552 builtin_define ("__tune_pentium4__"); \ 553 \ 554 if (TARGET_MMX) \ 555 builtin_define ("__MMX__"); \ 556 if (TARGET_3DNOW) \ 557 builtin_define ("__3dNOW__"); \ 558 if (TARGET_3DNOW_A) \ 559 builtin_define ("__3dNOW_A__"); \ 560 if (TARGET_SSE) \ 561 builtin_define ("__SSE__"); \ 562 if (TARGET_SSE2) \ 563 builtin_define ("__SSE2__"); \ 564 if (TARGET_SSE_MATH && TARGET_SSE) \ 565 builtin_define ("__SSE_MATH__"); \ 566 if (TARGET_SSE_MATH && TARGET_SSE2) \ 567 builtin_define ("__SSE2_MATH__"); \ 568 \ 569 /* Built-ins based on -march=. */ \ 570 if (ix86_arch == PROCESSOR_I486) \ 571 { \ 572 builtin_define ("__i486"); \ 573 builtin_define ("__i486__"); \ 574 } \ 575 else if (ix86_arch == PROCESSOR_PENTIUM) \ 576 { \ 577 builtin_define ("__i586"); \ 578 builtin_define ("__i586__"); \ 579 builtin_define ("__pentium"); \ 580 builtin_define ("__pentium__"); \ 581 if (last_arch_char == 'x') \ 582 builtin_define ("__pentium_mmx__"); \ 583 } \ 584 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ 585 { \ 586 builtin_define ("__i686"); \ 587 builtin_define ("__i686__"); \ 588 builtin_define ("__pentiumpro"); \ 589 builtin_define ("__pentiumpro__"); \ 590 } \ 591 else if (ix86_arch == PROCESSOR_K6) \ 592 { \ 593 \ 594 builtin_define ("__k6"); \ 595 builtin_define ("__k6__"); \ 596 if (last_arch_char == '2') \ 597 builtin_define ("__k6_2__"); \ 598 else if (last_arch_char == '3') \ 599 builtin_define ("__k6_3__"); \ 600 } \ 601 else if (ix86_arch == PROCESSOR_ATHLON) \ 602 { \ 603 builtin_define ("__athlon"); \ 604 builtin_define ("__athlon__"); \ 605 /* Only plain "athlon" lacks SSE. */ \ 606 if (last_arch_char != 'n') \ 607 builtin_define ("__athlon_sse__"); \ 608 } \ 609 else if (ix86_arch == PROCESSOR_PENTIUM4) \ 610 { \ 611 builtin_define ("__pentium4"); \ 612 builtin_define ("__pentium4__"); \ 613 } \ 614 } \ 615 while (0) 616 617#define TARGET_CPU_DEFAULT_i386 0 618#define TARGET_CPU_DEFAULT_i486 1 619#define TARGET_CPU_DEFAULT_pentium 2 620#define TARGET_CPU_DEFAULT_pentium_mmx 3 621#define TARGET_CPU_DEFAULT_pentiumpro 4 622#define TARGET_CPU_DEFAULT_pentium2 5 623#define TARGET_CPU_DEFAULT_pentium3 6 624#define TARGET_CPU_DEFAULT_pentium4 7 625#define TARGET_CPU_DEFAULT_k6 8 626#define TARGET_CPU_DEFAULT_k6_2 9 627#define TARGET_CPU_DEFAULT_k6_3 10 628#define TARGET_CPU_DEFAULT_athlon 11 629#define TARGET_CPU_DEFAULT_athlon_sse 12 630 631#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 632 "pentiumpro", "pentium2", "pentium3", \ 633 "pentium4", "k6", "k6-2", "k6-3",\ 634 "athlon", "athlon-4"} 635 636#ifndef CC1_SPEC 637#define CC1_SPEC "%(cc1_cpu) " 638#endif 639 640/* This macro defines names of additional specifications to put in the 641 specs that can be used in various specifications like CC1_SPEC. Its 642 definition is an initializer with a subgrouping for each command option. 643 644 Each subgrouping contains a string constant, that defines the 645 specification name, and a string constant that used by the GNU CC driver 646 program. 647 648 Do not define this macro if it does not need to do anything. */ 649 650#ifndef SUBTARGET_EXTRA_SPECS 651#define SUBTARGET_EXTRA_SPECS 652#endif 653 654#define EXTRA_SPECS \ 655 { "cc1_cpu", CC1_CPU_SPEC }, \ 656 SUBTARGET_EXTRA_SPECS 657 658/* target machine storage layout */ 659 660/* Define for XFmode or TFmode extended real floating point support. 661 The XFmode is specified by i386 ABI, while TFmode may be faster 662 due to alignment and simplifications in the address calculations. */ 663#define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96) 664#define MAX_LONG_DOUBLE_TYPE_SIZE 128 665#ifdef __x86_64__ 666#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 667#else 668#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 669#endif 670 671/* Set the value of FLT_EVAL_METHOD in float.h. When using only the 672 FPU, assume that the fpcw is set to extended precision; when using 673 only SSE, rounding is correct; when using both SSE and the FPU, 674 the rounding precision is indeterminate, since either may be chosen 675 apparently at random. */ 676#define TARGET_FLT_EVAL_METHOD \ 677 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 1 : 2) 678 679#define SHORT_TYPE_SIZE 16 680#define INT_TYPE_SIZE 32 681#define FLOAT_TYPE_SIZE 32 682#ifndef LONG_TYPE_SIZE 683#define LONG_TYPE_SIZE BITS_PER_WORD 684#endif 685#define MAX_WCHAR_TYPE_SIZE 32 686#define DOUBLE_TYPE_SIZE 64 687#define LONG_LONG_TYPE_SIZE 64 688 689#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 690#define MAX_BITS_PER_WORD 64 691#define MAX_LONG_TYPE_SIZE 64 692#else 693#define MAX_BITS_PER_WORD 32 694#define MAX_LONG_TYPE_SIZE 32 695#endif 696 697/* Define this if most significant byte of a word is the lowest numbered. */ 698/* That is true on the 80386. */ 699 700#define BITS_BIG_ENDIAN 0 701 702/* Define this if most significant byte of a word is the lowest numbered. */ 703/* That is not true on the 80386. */ 704#define BYTES_BIG_ENDIAN 0 705 706/* Define this if most significant word of a multiword number is the lowest 707 numbered. */ 708/* Not true for 80386 */ 709#define WORDS_BIG_ENDIAN 0 710 711/* Width of a word, in units (bytes). */ 712#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 713#ifdef IN_LIBGCC2 714#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 715#else 716#define MIN_UNITS_PER_WORD 4 717#endif 718 719/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 720#define PARM_BOUNDARY BITS_PER_WORD 721 722/* Boundary (in *bits*) on which stack pointer should be aligned. */ 723#define STACK_BOUNDARY BITS_PER_WORD 724 725/* Boundary (in *bits*) on which the stack pointer preferrs to be 726 aligned; the compiler cannot rely on having this alignment. */ 727#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 728 729/* As of July 2001, many runtimes to not align the stack properly when 730 entering main. This causes expand_main_function to forcably align 731 the stack, which results in aligned frames for functions called from 732 main, though it does nothing for the alignment of main itself. */ 733#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 734 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 735 736/* Minimum allocation boundary for the code of a function. */ 737#define FUNCTION_BOUNDARY 8 738 739/* C++ stores the virtual bit in the lowest bit of function pointers. */ 740#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 741 742/* Alignment of field after `int : 0' in a structure. */ 743 744#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 745 746/* Minimum size in bits of the largest boundary to which any 747 and all fundamental data types supported by the hardware 748 might need to be aligned. No data type wants to be aligned 749 rounder than this. 750 751 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary 752 and Pentium Pro XFmode values at 128 bit boundaries. */ 753 754#define BIGGEST_ALIGNMENT 128 755 756/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 757#define ALIGN_MODE_128(MODE) \ 758 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE)) 759 760/* The published ABIs say that doubles should be aligned on word 761 boundaries, so lower the aligment for structure fields unless 762 -malign-double is set. */ 763 764/* ??? Blah -- this macro is used directly by libobjc. Since it 765 supports no vector modes, cut out the complexity and fall back 766 on BIGGEST_FIELD_ALIGNMENT. */ 767#ifdef IN_TARGET_LIBS 768#ifdef __x86_64__ 769#define BIGGEST_FIELD_ALIGNMENT 128 770#else 771#define BIGGEST_FIELD_ALIGNMENT 32 772#endif 773#else 774#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 775 x86_field_alignment (FIELD, COMPUTED) 776#endif 777 778/* If defined, a C expression to compute the alignment given to a 779 constant that is being placed in memory. EXP is the constant 780 and ALIGN is the alignment that the object would ordinarily have. 781 The value of this macro is used instead of that alignment to align 782 the object. 783 784 If this macro is not defined, then ALIGN is used. 785 786 The typical use of this macro is to increase alignment for string 787 constants to be word aligned so that `strcpy' calls that copy 788 constants can be done inline. */ 789 790#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 791 792/* If defined, a C expression to compute the alignment for a static 793 variable. TYPE is the data type, and ALIGN is the alignment that 794 the object would ordinarily have. The value of this macro is used 795 instead of that alignment to align the object. 796 797 If this macro is not defined, then ALIGN is used. 798 799 One use of this macro is to increase alignment of medium-size 800 data to make it all fit in fewer cache lines. Another is to 801 cause character arrays to be word-aligned so that `strcpy' calls 802 that copy constants to character arrays can be done inline. */ 803 804#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 805 806/* If defined, a C expression to compute the alignment for a local 807 variable. TYPE is the data type, and ALIGN is the alignment that 808 the object would ordinarily have. The value of this macro is used 809 instead of that alignment to align the object. 810 811 If this macro is not defined, then ALIGN is used. 812 813 One use of this macro is to increase alignment of medium-size 814 data to make it all fit in fewer cache lines. */ 815 816#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 817 818/* If defined, a C expression that gives the alignment boundary, in 819 bits, of an argument with the specified mode and type. If it is 820 not defined, `PARM_BOUNDARY' is used for all arguments. */ 821 822#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 823 ix86_function_arg_boundary ((MODE), (TYPE)) 824 825/* Set this nonzero if move instructions will actually fail to work 826 when given unaligned data. */ 827#define STRICT_ALIGNMENT 0 828 829/* If bit field type is int, don't let it cross an int, 830 and give entire struct the alignment of an int. */ 831/* Required on the 386 since it doesn't have bit-field insns. */ 832#define PCC_BITFIELD_TYPE_MATTERS 1 833 834/* Standard register usage. */ 835 836/* This processor has special stack-like registers. See reg-stack.c 837 for details. */ 838 839#define STACK_REGS 840#define IS_STACK_MODE(MODE) \ 841 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ 842 || (MODE) == TFmode) 843 844/* Number of actual hardware registers. 845 The hardware registers are assigned numbers for the compiler 846 from 0 to just below FIRST_PSEUDO_REGISTER. 847 All registers that the compiler knows about must be given numbers, 848 even those that are not normally considered general registers. 849 850 In the 80386 we give the 8 general purpose registers the numbers 0-7. 851 We number the floating point registers 8-15. 852 Note that registers 0-7 can be accessed as a short or int, 853 while only 0-3 may be used with byte `mov' instructions. 854 855 Reg 16 does not correspond to any hardware register, but instead 856 appears in the RTL as an argument pointer prior to reload, and is 857 eliminated during reloading in favor of either the stack or frame 858 pointer. */ 859 860#define FIRST_PSEUDO_REGISTER 53 861 862/* Number of hardware registers that go into the DWARF-2 unwind info. 863 If not defined, equals FIRST_PSEUDO_REGISTER. */ 864 865#define DWARF_FRAME_REGISTERS 17 866 867/* 1 for registers that have pervasive standard uses 868 and are not available for the register allocator. 869 On the 80386, the stack pointer is such, as is the arg pointer. 870 871 The value is an mask - bit 1 is set for fixed registers 872 for 32bit target, while 2 is set for fixed registers for 64bit. 873 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 874 */ 875#define FIXED_REGISTERS \ 876/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 877{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ 878/*arg,flags,fpsr,dir,frame*/ \ 879 3, 3, 3, 3, 3, \ 880/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 881 0, 0, 0, 0, 0, 0, 0, 0, \ 882/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 883 0, 0, 0, 0, 0, 0, 0, 0, \ 884/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 885 1, 1, 1, 1, 1, 1, 1, 1, \ 886/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 887 1, 1, 1, 1, 1, 1, 1, 1} 888 889 890/* 1 for registers not available across function calls. 891 These must include the FIXED_REGISTERS and also any 892 registers that can be used without being saved. 893 The latter must include the registers where values are returned 894 and the register where structure-value addresses are passed. 895 Aside from that, you can include as many other registers as you like. 896 897 The value is an mask - bit 1 is set for call used 898 for 32bit target, while 2 is set for call used for 64bit. 899 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 900*/ 901#define CALL_USED_REGISTERS \ 902/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 903{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 904/*arg,flags,fpsr,dir,frame*/ \ 905 3, 3, 3, 3, 3, \ 906/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 907 3, 3, 3, 3, 3, 3, 3, 3, \ 908/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 909 3, 3, 3, 3, 3, 3, 3, 3, \ 910/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 911 3, 3, 3, 3, 1, 1, 1, 1, \ 912/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 913 3, 3, 3, 3, 3, 3, 3, 3} \ 914 915/* Order in which to allocate registers. Each register must be 916 listed once, even those in FIXED_REGISTERS. List frame pointer 917 late and fixed registers last. Note that, in general, we prefer 918 registers listed in CALL_USED_REGISTERS, keeping the others 919 available for storage of persistent values. 920 921 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 922 so this is just empty initializer for array. */ 923 924#define REG_ALLOC_ORDER \ 925{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 926 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 927 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 928 48, 49, 50, 51, 52 } 929 930/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 931 to be rearranged based on a particular function. When using sse math, 932 we want to allocase SSE before x87 registers and vice vera. */ 933 934#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 935 936 937/* Macro to conditionally modify fixed_regs/call_used_regs. */ 938#define CONDITIONAL_REGISTER_USAGE \ 939do { \ 940 int i; \ 941 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 942 { \ 943 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ 944 call_used_regs[i] = (call_used_regs[i] \ 945 & (TARGET_64BIT ? 2 : 1)) != 0; \ 946 } \ 947 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 948 { \ 949 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 950 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 951 } \ 952 if (! TARGET_MMX) \ 953 { \ 954 int i; \ 955 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 956 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 957 fixed_regs[i] = call_used_regs[i] = 1; \ 958 } \ 959 if (! TARGET_SSE) \ 960 { \ 961 int i; \ 962 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 963 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 964 fixed_regs[i] = call_used_regs[i] = 1; \ 965 } \ 966 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 967 { \ 968 int i; \ 969 HARD_REG_SET x; \ 970 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 971 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 972 if (TEST_HARD_REG_BIT (x, i)) \ 973 fixed_regs[i] = call_used_regs[i] = 1; \ 974 } \ 975 } while (0) 976 977/* Return number of consecutive hard regs needed starting at reg REGNO 978 to hold something of mode MODE. 979 This is ordinarily the length in words of a value of mode MODE 980 but can be less for certain modes in special long registers. 981 982 Actually there are no two word move instructions for consecutive 983 registers. And only registers 0-3 may have mov byte instructions 984 applied to them. 985 */ 986 987#define HARD_REGNO_NREGS(REGNO, MODE) \ 988 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 989 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 990 : ((MODE) == TFmode \ 991 ? (TARGET_64BIT ? 2 : 3) \ 992 : (MODE) == TCmode \ 993 ? (TARGET_64BIT ? 4 : 6) \ 994 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 995 996#define VALID_SSE2_REG_MODE(MODE) \ 997 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 998 || (MODE) == V2DImode) 999 1000#define VALID_SSE_REG_MODE(MODE) \ 1001 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1002 || (MODE) == SFmode \ 1003 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \ 1004 || VALID_SSE2_REG_MODE (MODE) \ 1005 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) 1006 1007#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1008 ((MODE) == V2SFmode || (MODE) == SFmode) 1009 1010#define VALID_MMX_REG_MODE(MODE) \ 1011 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 1012 || (MODE) == V2SImode || (MODE) == SImode) 1013 1014#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1015 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ 1016 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ 1017 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) 1018 1019#define VALID_FP_MODE_P(MODE) \ 1020 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 1021 || (!TARGET_64BIT && (MODE) == XFmode) \ 1022 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \ 1023 || (!TARGET_64BIT && (MODE) == XCmode)) 1024 1025#define VALID_INT_MODE_P(MODE) \ 1026 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1027 || (MODE) == DImode \ 1028 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1029 || (MODE) == CDImode \ 1030 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) 1031 1032/* Return true for modes passed in SSE registers. */ 1033#define SSE_REG_MODE_P(MODE) \ 1034 ((MODE) == TImode || (MODE) == V16QImode \ 1035 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ 1036 || (MODE) == V4SFmode || (MODE) == V4SImode) 1037 1038/* Return true for modes passed in MMX registers. */ 1039#define MMX_REG_MODE_P(MODE) \ 1040 ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \ 1041 || (MODE) == V2SFmode) 1042 1043/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1044 1045#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1046 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1047 1048/* Value is 1 if it is a good idea to tie two pseudo registers 1049 when one has mode MODE1 and one has mode MODE2. 1050 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1051 for any hard reg, then this must be 0 for correct output. */ 1052 1053#define MODES_TIEABLE_P(MODE1, MODE2) \ 1054 ((MODE1) == (MODE2) \ 1055 || (((MODE1) == HImode || (MODE1) == SImode \ 1056 || ((MODE1) == QImode \ 1057 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1058 || ((MODE1) == DImode && TARGET_64BIT)) \ 1059 && ((MODE2) == HImode || (MODE2) == SImode \ 1060 || ((MODE2) == QImode \ 1061 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1062 || ((MODE2) == DImode && TARGET_64BIT)))) 1063 1064 1065/* Specify the modes required to caller save a given hard regno. 1066 We do this on i386 to prevent flags from being saved at all. 1067 1068 Kill any attempts to combine saving of modes. */ 1069 1070#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1071 (CC_REGNO_P (REGNO) ? VOIDmode \ 1072 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1073 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \ 1074 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1075 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 1076 : (MODE)) 1077/* Specify the registers used for certain standard purposes. 1078 The values of these macros are register numbers. */ 1079 1080/* on the 386 the pc register is %eip, and is not usable as a general 1081 register. The ordinary mov instructions won't work */ 1082/* #define PC_REGNUM */ 1083 1084/* Register to use for pushing function arguments. */ 1085#define STACK_POINTER_REGNUM 7 1086 1087/* Base register for access to local variables of the function. */ 1088#define HARD_FRAME_POINTER_REGNUM 6 1089 1090/* Base register for access to local variables of the function. */ 1091#define FRAME_POINTER_REGNUM 20 1092 1093/* First floating point reg */ 1094#define FIRST_FLOAT_REG 8 1095 1096/* First & last stack-like regs */ 1097#define FIRST_STACK_REG FIRST_FLOAT_REG 1098#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1099 1100#define FLAGS_REG 17 1101#define FPSR_REG 18 1102#define DIRFLAG_REG 19 1103 1104#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1105#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1106 1107#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1108#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1109 1110#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1111#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1112 1113#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1114#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1115 1116/* Value should be nonzero if functions must have frame pointers. 1117 Zero means the frame pointer need not be set up (and parms 1118 may be accessed via the stack pointer) in functions that seem suitable. 1119 This is computed in `reload', in reload1.c. */ 1120#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1121 1122/* Override this in other tm.h files to cope with various OS losage 1123 requiring a frame pointer. */ 1124#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1125#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1126#endif 1127 1128/* Make sure we can access arbitrary call frames. */ 1129#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1130 1131/* Base register for access to arguments of the function. */ 1132#define ARG_POINTER_REGNUM 16 1133 1134/* Register in which static-chain is passed to a function. 1135 We do use ECX as static chain register for 32 bit ABI. On the 1136 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1137#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1138 1139/* Register to hold the addressing base for position independent 1140 code access to data items. We don't use PIC pointer for 64bit 1141 mode. Define the regnum to dummy value to prevent gcc from 1142 pessimizing code dealing with EBX. 1143 1144 To avoid clobbering a call-saved register unnecessarily, we renumber 1145 the pic register when possible. The change is visible after the 1146 prologue has been emitted. */ 1147 1148#define REAL_PIC_OFFSET_TABLE_REGNUM 3 1149 1150#define PIC_OFFSET_TABLE_REGNUM \ 1151 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \ 1152 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1153 : REAL_PIC_OFFSET_TABLE_REGNUM) 1154 1155#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1156 1157/* Register in which address to store a structure value 1158 arrives in the function. On the 386, the prologue 1159 copies this from the stack to register %eax. */ 1160#define STRUCT_VALUE_INCOMING 0 1161 1162/* Place in which caller passes the structure value address. 1163 0 means push the value on the stack like an argument. */ 1164#define STRUCT_VALUE 0 1165 1166/* A C expression which can inhibit the returning of certain function 1167 values in registers, based on the type of value. A nonzero value 1168 says to return the function value in memory, just as large 1169 structures are always returned. Here TYPE will be a C expression 1170 of type `tree', representing the data type of the value. 1171 1172 Note that values of mode `BLKmode' must be explicitly handled by 1173 this macro. Also, the option `-fpcc-struct-return' takes effect 1174 regardless of this macro. On most systems, it is possible to 1175 leave the macro undefined; this causes a default definition to be 1176 used, whose value is the constant 1 for `BLKmode' values, and 0 1177 otherwise. 1178 1179 Do not use this macro to indicate that structures and unions 1180 should always be returned in memory. You should instead use 1181 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1182 1183#define RETURN_IN_MEMORY(TYPE) \ 1184 ix86_return_in_memory (TYPE) 1185 1186 1187/* Define the classes of registers for register constraints in the 1188 machine description. Also define ranges of constants. 1189 1190 One of the classes must always be named ALL_REGS and include all hard regs. 1191 If there is more than one class, another class must be named NO_REGS 1192 and contain no registers. 1193 1194 The name GENERAL_REGS must be the name of a class (or an alias for 1195 another name such as ALL_REGS). This is the class of registers 1196 that is allowed by "g" or "r" in a register constraint. 1197 Also, registers outside this class are allocated only when 1198 instructions express preferences for them. 1199 1200 The classes must be numbered in nondecreasing order; that is, 1201 a larger-numbered class must never be contained completely 1202 in a smaller-numbered class. 1203 1204 For any two classes, it is very desirable that there be another 1205 class that represents their union. 1206 1207 It might seem that class BREG is unnecessary, since no useful 386 1208 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1209 and the "b" register constraint is useful in asms for syscalls. 1210 1211 The flags and fpsr registers are in no class. */ 1212 1213enum reg_class 1214{ 1215 NO_REGS, 1216 AREG, DREG, CREG, BREG, SIREG, DIREG, 1217 AD_REGS, /* %eax/%edx for DImode */ 1218 Q_REGS, /* %eax %ebx %ecx %edx */ 1219 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1220 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1221 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1222 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1223 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1224 FLOAT_REGS, 1225 SSE_REGS, 1226 MMX_REGS, 1227 FP_TOP_SSE_REGS, 1228 FP_SECOND_SSE_REGS, 1229 FLOAT_SSE_REGS, 1230 FLOAT_INT_REGS, 1231 INT_SSE_REGS, 1232 FLOAT_INT_SSE_REGS, 1233 ALL_REGS, LIM_REG_CLASSES 1234}; 1235 1236#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1237 1238#define INTEGER_CLASS_P(CLASS) \ 1239 reg_class_subset_p ((CLASS), GENERAL_REGS) 1240#define FLOAT_CLASS_P(CLASS) \ 1241 reg_class_subset_p ((CLASS), FLOAT_REGS) 1242#define SSE_CLASS_P(CLASS) \ 1243 reg_class_subset_p ((CLASS), SSE_REGS) 1244#define MMX_CLASS_P(CLASS) \ 1245 reg_class_subset_p ((CLASS), MMX_REGS) 1246#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1247 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1248#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1249 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1250#define MAYBE_SSE_CLASS_P(CLASS) \ 1251 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1252#define MAYBE_MMX_CLASS_P(CLASS) \ 1253 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1254 1255#define Q_CLASS_P(CLASS) \ 1256 reg_class_subset_p ((CLASS), Q_REGS) 1257 1258/* Give names of register classes as strings for dump file. */ 1259 1260#define REG_CLASS_NAMES \ 1261{ "NO_REGS", \ 1262 "AREG", "DREG", "CREG", "BREG", \ 1263 "SIREG", "DIREG", \ 1264 "AD_REGS", \ 1265 "Q_REGS", "NON_Q_REGS", \ 1266 "INDEX_REGS", \ 1267 "LEGACY_REGS", \ 1268 "GENERAL_REGS", \ 1269 "FP_TOP_REG", "FP_SECOND_REG", \ 1270 "FLOAT_REGS", \ 1271 "SSE_REGS", \ 1272 "MMX_REGS", \ 1273 "FP_TOP_SSE_REGS", \ 1274 "FP_SECOND_SSE_REGS", \ 1275 "FLOAT_SSE_REGS", \ 1276 "FLOAT_INT_REGS", \ 1277 "INT_SSE_REGS", \ 1278 "FLOAT_INT_SSE_REGS", \ 1279 "ALL_REGS" } 1280 1281/* Define which registers fit in which classes. 1282 This is an initializer for a vector of HARD_REG_SET 1283 of length N_REG_CLASSES. */ 1284 1285#define REG_CLASS_CONTENTS \ 1286{ { 0x00, 0x0 }, \ 1287 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1288 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1289 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1290 { 0x03, 0x0 }, /* AD_REGS */ \ 1291 { 0x0f, 0x0 }, /* Q_REGS */ \ 1292 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1293 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1294 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1295 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1296 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1297 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1298{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1299{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1300{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1301{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1302{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1303 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1304{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1305{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1306{ 0xffffffff,0x1fffff } \ 1307} 1308 1309/* The same information, inverted: 1310 Return the class number of the smallest class containing 1311 reg number REGNO. This could be a conditional expression 1312 or could index an array. */ 1313 1314#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1315 1316/* When defined, the compiler allows registers explicitly used in the 1317 rtl to be used as spill registers but prevents the compiler from 1318 extending the lifetime of these registers. */ 1319 1320#define SMALL_REGISTER_CLASSES 1 1321 1322#define QI_REG_P(X) \ 1323 (REG_P (X) && REGNO (X) < 4) 1324 1325#define GENERAL_REGNO_P(N) \ 1326 ((N) < 8 || REX_INT_REGNO_P (N)) 1327 1328#define GENERAL_REG_P(X) \ 1329 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1330 1331#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1332 1333#define NON_QI_REG_P(X) \ 1334 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1335 1336#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1337#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1338 1339#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1340#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1341#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1342#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1343 1344#define SSE_REGNO_P(N) \ 1345 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1346 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1347 1348#define SSE_REGNO(N) \ 1349 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1350#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1351 1352#define SSE_FLOAT_MODE_P(MODE) \ 1353 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1354 1355#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1356#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1357 1358#define STACK_REG_P(XOP) \ 1359 (REG_P (XOP) && \ 1360 REGNO (XOP) >= FIRST_STACK_REG && \ 1361 REGNO (XOP) <= LAST_STACK_REG) 1362 1363#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1364 1365#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1366 1367#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1368#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1369 1370/* Indicate whether hard register numbered REG_NO should be converted 1371 to SSA form. */ 1372#define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \ 1373 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM) 1374 1375/* The class value for index registers, and the one for base regs. */ 1376 1377#define INDEX_REG_CLASS INDEX_REGS 1378#define BASE_REG_CLASS GENERAL_REGS 1379 1380/* Get reg_class from a letter such as appears in the machine description. */ 1381 1382#define REG_CLASS_FROM_LETTER(C) \ 1383 ((C) == 'r' ? GENERAL_REGS : \ 1384 (C) == 'R' ? LEGACY_REGS : \ 1385 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1386 (C) == 'Q' ? Q_REGS : \ 1387 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1388 ? FLOAT_REGS \ 1389 : NO_REGS) : \ 1390 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1391 ? FP_TOP_REG \ 1392 : NO_REGS) : \ 1393 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1394 ? FP_SECOND_REG \ 1395 : NO_REGS) : \ 1396 (C) == 'a' ? AREG : \ 1397 (C) == 'b' ? BREG : \ 1398 (C) == 'c' ? CREG : \ 1399 (C) == 'd' ? DREG : \ 1400 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1401 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1402 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1403 (C) == 'A' ? AD_REGS : \ 1404 (C) == 'D' ? DIREG : \ 1405 (C) == 'S' ? SIREG : NO_REGS) 1406 1407/* The letters I, J, K, L and M in a register constraint string 1408 can be used to stand for particular ranges of immediate operands. 1409 This macro defines what the ranges are. 1410 C is the letter, and VALUE is a constant value. 1411 Return 1 if VALUE is in the range specified by C. 1412 1413 I is for non-DImode shifts. 1414 J is for DImode shifts. 1415 K is for signed imm8 operands. 1416 L is for andsi as zero-extending move. 1417 M is for shifts that can be executed by the "lea" opcode. 1418 N is for immedaite operands for out/in instructions (0-255) 1419 */ 1420 1421#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1422 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1423 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1424 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1425 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1426 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1427 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1428 : 0) 1429 1430/* Similar, but for floating constants, and defining letters G and H. 1431 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1432 TARGET_387 isn't set, because the stack register converter may need to 1433 load 0.0 into the function value register. */ 1434 1435#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1436 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1437 : 0) 1438 1439/* A C expression that defines the optional machine-dependent 1440 constraint letters that can be used to segregate specific types of 1441 operands, usually memory references, for the target machine. Any 1442 letter that is not elsewhere defined and not matched by 1443 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1444 be defined. 1445 1446 If it is required for a particular target machine, it should 1447 return 1 if VALUE corresponds to the operand type represented by 1448 the constraint letter C. If C is not defined as an extra 1449 constraint, the value returned should be 0 regardless of VALUE. */ 1450 1451#define EXTRA_CONSTRAINT(VALUE, D) \ 1452 ((D) == 'e' ? x86_64_sign_extended_value (VALUE) \ 1453 : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \ 1454 : (D) == 'C' ? standard_sse_constant_p (VALUE) \ 1455 : 0) 1456 1457/* Place additional restrictions on the register class to use when it 1458 is necessary to be able to hold a value of mode MODE in a reload 1459 register for which class CLASS would ordinarily be used. */ 1460 1461#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1462 ((MODE) == QImode && !TARGET_64BIT \ 1463 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1464 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1465 ? Q_REGS : (CLASS)) 1466 1467/* Given an rtx X being reloaded into a reg required to be 1468 in class CLASS, return the class of reg to actually use. 1469 In general this is just CLASS; but on some machines 1470 in some cases it is preferable to use a more restrictive class. 1471 On the 80386 series, we prevent floating constants from being 1472 reloaded into floating registers (since no move-insn can do that) 1473 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1474 1475/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1476 QImode must go into class Q_REGS. 1477 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1478 movdf to do mem-to-mem moves through integer regs. */ 1479 1480#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1481 ix86_preferred_reload_class ((X), (CLASS)) 1482 1483/* If we are copying between general and FP registers, we need a memory 1484 location. The same is true for SSE and MMX registers. */ 1485#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1486 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1487 1488/* QImode spills from non-QI registers need a scratch. This does not 1489 happen often -- the only example so far requires an uninitialized 1490 pseudo. */ 1491 1492#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1493 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1494 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1495 ? Q_REGS : NO_REGS) 1496 1497/* Return the maximum number of consecutive registers 1498 needed to represent mode MODE in a register of class CLASS. */ 1499/* On the 80386, this is the size of MODE in words, 1500 except in the FP regs, where a single reg is always enough. 1501 The TFmodes are really just 80bit values, so we use only 3 registers 1502 to hold them, instead of 4, as the size would suggest. 1503 */ 1504#define CLASS_MAX_NREGS(CLASS, MODE) \ 1505 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1506 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1507 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ 1508 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1509 1510/* A C expression whose value is nonzero if pseudos that have been 1511 assigned to registers of class CLASS would likely be spilled 1512 because registers of CLASS are needed for spill registers. 1513 1514 The default value of this macro returns 1 if CLASS has exactly one 1515 register and zero otherwise. On most machines, this default 1516 should be used. Only define this macro to some other expression 1517 if pseudo allocated by `local-alloc.c' end up in memory because 1518 their hard registers were needed for spill registers. If this 1519 macro returns nonzero for those classes, those pseudos will only 1520 be allocated by `global.c', which knows how to reallocate the 1521 pseudo to another register. If there would not be another 1522 register available for reallocation, you should not change the 1523 definition of this macro since the only effect of such a 1524 definition would be to slow down register allocation. */ 1525 1526#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1527 (((CLASS) == AREG) \ 1528 || ((CLASS) == DREG) \ 1529 || ((CLASS) == CREG) \ 1530 || ((CLASS) == BREG) \ 1531 || ((CLASS) == AD_REGS) \ 1532 || ((CLASS) == SIREG) \ 1533 || ((CLASS) == DIREG)) 1534 1535/* Return a class of registers that cannot change FROM mode to TO mode. 1536 1537 x87 registers can't do subreg as all values are reformated to extended 1538 precision. XMM registers does not support with nonzero offsets equal 1539 to 4, 8 and 12 otherwise valid for integer registers. Since we can't 1540 determine these, prohibit all nonparadoxical subregs changing size. */ 1541 1542#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1543 (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \ 1544 ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \ 1545 || MAYBE_MMX_CLASS_P (CLASS) \ 1546 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1547 ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0) 1548 1549/* A C statement that adds to CLOBBERS any hard regs the port wishes 1550 to automatically clobber for all asms. 1551 1552 We do this in the new i386 backend to maintain source compatibility 1553 with the old cc0-based compiler. */ 1554 1555#define MD_ASM_CLOBBERS(CLOBBERS) \ 1556 do { \ 1557 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ 1558 (CLOBBERS)); \ 1559 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ 1560 (CLOBBERS)); \ 1561 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ 1562 (CLOBBERS)); \ 1563 } while (0) 1564 1565/* Stack layout; function entry, exit and calling. */ 1566 1567/* Define this if pushing a word on the stack 1568 makes the stack pointer a smaller address. */ 1569#define STACK_GROWS_DOWNWARD 1570 1571/* Define this if the nominal address of the stack frame 1572 is at the high-address end of the local variables; 1573 that is, each additional local variable allocated 1574 goes at a more negative offset in the frame. */ 1575#define FRAME_GROWS_DOWNWARD 1576 1577/* Offset within stack frame to start allocating local variables at. 1578 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1579 first local allocated. Otherwise, it is the offset to the BEGINNING 1580 of the first local allocated. */ 1581#define STARTING_FRAME_OFFSET 0 1582 1583/* If we generate an insn to push BYTES bytes, 1584 this says how many the stack pointer really advances by. 1585 On 386 pushw decrements by exactly 2 no matter what the position was. 1586 On the 386 there is no pushb; we use pushw instead, and this 1587 has the effect of rounding up to 2. 1588 1589 For 64bit ABI we round up to 8 bytes. 1590 */ 1591 1592#define PUSH_ROUNDING(BYTES) \ 1593 (TARGET_64BIT \ 1594 ? (((BYTES) + 7) & (-8)) \ 1595 : (((BYTES) + 1) & (-2))) 1596 1597/* If defined, the maximum amount of space required for outgoing arguments will 1598 be computed and placed into the variable 1599 `current_function_outgoing_args_size'. No space will be pushed onto the 1600 stack for each call; instead, the function prologue should increase the stack 1601 frame size by this amount. */ 1602 1603#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1604 1605/* If defined, a C expression whose value is nonzero when we want to use PUSH 1606 instructions to pass outgoing arguments. */ 1607 1608#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1609 1610/* We want the stack and args grow in opposite directions, even if 1611 PUSH_ARGS is 0. */ 1612#define PUSH_ARGS_REVERSED 1 1613 1614/* Offset of first parameter from the argument pointer register value. */ 1615#define FIRST_PARM_OFFSET(FNDECL) 0 1616 1617/* Define this macro if functions should assume that stack space has been 1618 allocated for arguments even when their values are passed in registers. 1619 1620 The value of this macro is the size, in bytes, of the area reserved for 1621 arguments passed in registers for the function represented by FNDECL. 1622 1623 This space can be allocated by the caller, or be a part of the 1624 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1625 which. */ 1626#define REG_PARM_STACK_SPACE(FNDECL) 0 1627 1628/* Define as a C expression that evaluates to nonzero if we do not know how 1629 to pass TYPE solely in registers. The file expr.h defines a 1630 definition that is usually appropriate, refer to expr.h for additional 1631 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be 1632 computed in the stack and then loaded into a register. */ 1633#define MUST_PASS_IN_STACK(MODE, TYPE) \ 1634 ((TYPE) != 0 \ 1635 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1636 || TREE_ADDRESSABLE (TYPE) \ 1637 || ((MODE) == TImode) \ 1638 || ((MODE) == BLKmode \ 1639 && ! ((TYPE) != 0 \ 1640 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ 1641 && 0 == (int_size_in_bytes (TYPE) \ 1642 % (PARM_BOUNDARY / BITS_PER_UNIT))) \ 1643 && (FUNCTION_ARG_PADDING (MODE, TYPE) \ 1644 == (BYTES_BIG_ENDIAN ? upward : downward))))) 1645 1646/* Value is the number of bytes of arguments automatically 1647 popped when returning from a subroutine call. 1648 FUNDECL is the declaration node of the function (as a tree), 1649 FUNTYPE is the data type of the function (as a tree), 1650 or for a library call it is an identifier node for the subroutine name. 1651 SIZE is the number of bytes of arguments passed on the stack. 1652 1653 On the 80386, the RTD insn may be used to pop them if the number 1654 of args is fixed, but if the number is variable then the caller 1655 must pop them all. RTD can't be used for library calls now 1656 because the library is compiled with the Unix compiler. 1657 Use of RTD is a selectable option, since it is incompatible with 1658 standard Unix calling sequences. If the option is not selected, 1659 the caller must always pop the args. 1660 1661 The attribute stdcall is equivalent to RTD on a per module basis. */ 1662 1663#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1664 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1665 1666/* Define how to find the value returned by a function. 1667 VALTYPE is the data type of the value (as a tree). 1668 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1669 otherwise, FUNC is 0. */ 1670#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1671 ix86_function_value (VALTYPE) 1672 1673#define FUNCTION_VALUE_REGNO_P(N) \ 1674 ix86_function_value_regno_p (N) 1675 1676/* Define how to find the value returned by a library function 1677 assuming the value has mode MODE. */ 1678 1679#define LIBCALL_VALUE(MODE) \ 1680 ix86_libcall_value (MODE) 1681 1682/* Define the size of the result block used for communication between 1683 untyped_call and untyped_return. The block contains a DImode value 1684 followed by the block used by fnsave and frstor. */ 1685 1686#define APPLY_RESULT_SIZE (8+108) 1687 1688/* 1 if N is a possible register number for function argument passing. */ 1689#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1690 1691/* Define a data type for recording info about an argument list 1692 during the scan of that argument list. This data type should 1693 hold all necessary information about the function itself 1694 and about the args processed so far, enough to enable macros 1695 such as FUNCTION_ARG to determine where the next arg should go. */ 1696 1697typedef struct ix86_args { 1698 int words; /* # words passed so far */ 1699 int nregs; /* # registers available for passing */ 1700 int regno; /* next available register number */ 1701 int sse_words; /* # sse words passed so far */ 1702 int sse_nregs; /* # sse registers available for passing */ 1703 int sse_regno; /* next available sse register number */ 1704 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1705} CUMULATIVE_ARGS; 1706 1707/* Initialize a variable CUM of type CUMULATIVE_ARGS 1708 for a call to a function whose data type is FNTYPE. 1709 For a library call, FNTYPE is 0. */ 1710 1711#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1712 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) 1713 1714/* Update the data in CUM to advance over an argument 1715 of mode MODE and data type TYPE. 1716 (TYPE is null for libcalls where that information may not be available.) */ 1717 1718#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1719 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1720 1721/* Define where to put the arguments to a function. 1722 Value is zero to push the argument on the stack, 1723 or a hard register in which to store the argument. 1724 1725 MODE is the argument's machine mode. 1726 TYPE is the data type of the argument (as a tree). 1727 This is null for libcalls where that information may 1728 not be available. 1729 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1730 the preceding args and about the function being called. 1731 NAMED is nonzero if this argument is a named parameter 1732 (otherwise it is an extra parameter matching an ellipsis). */ 1733 1734#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1735 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1736 1737/* For an arg passed partly in registers and partly in memory, 1738 this is the number of registers used. 1739 For args passed entirely in registers or entirely in memory, zero. */ 1740 1741#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1742 1743/* A C expression that indicates when an argument must be passed by 1744 reference. If nonzero for an argument, a copy of that argument is 1745 made in memory and a pointer to the argument is passed instead of 1746 the argument itself. The pointer is passed in whatever way is 1747 appropriate for passing a pointer to that type. */ 1748 1749#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1750 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED) 1751 1752/* If PIC, we cannot make sibling calls to global functions 1753 because the PLT requires %ebx live. 1754 If we are returning floats on the 80387 register stack, we cannot 1755 make a sibcall from a function that doesn't return a float to a 1756 function that does or, conversely, from a function that does return 1757 a float to a function that doesn't; the necessary stack adjustment 1758 would not be executed. */ 1759#define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1760 ((DECL) \ 1761 && (! flag_pic || ! TREE_PUBLIC (DECL)) \ 1762 && (! TARGET_FLOAT_RETURNS_IN_80387 \ 1763 || (FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \ 1764 == FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))) 1765 1766/* Perform any needed actions needed for a function that is receiving a 1767 variable number of arguments. 1768 1769 CUM is as above. 1770 1771 MODE and TYPE are the mode and type of the current parameter. 1772 1773 PRETEND_SIZE is a variable that should be set to the amount of stack 1774 that must be pushed by the prolog to pretend that our caller pushed 1775 it. 1776 1777 Normally, this macro will push all remaining incoming registers on the 1778 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1779 1780#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1781 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ 1782 (NO_RTL)) 1783 1784/* Define the `__builtin_va_list' type for the ABI. */ 1785#define BUILD_VA_LIST_TYPE(VALIST) \ 1786 ((VALIST) = ix86_build_va_list ()) 1787 1788/* Implement `va_start' for varargs and stdarg. */ 1789#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ 1790 ix86_va_start (VALIST, NEXTARG) 1791 1792/* Implement `va_arg'. */ 1793#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ 1794 ix86_va_arg ((VALIST), (TYPE)) 1795 1796/* This macro is invoked at the end of compilation. It is used here to 1797 output code for -fpic that will load the return address into %ebx. */ 1798 1799#undef ASM_FILE_END 1800#define ASM_FILE_END(FILE) ix86_asm_file_end (FILE) 1801 1802/* Output assembler code to FILE to increment profiler label # LABELNO 1803 for profiling a function entry. */ 1804 1805#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1806 1807#define MCOUNT_NAME "_mcount" 1808 1809#define PROFILE_COUNT_REGISTER "edx" 1810 1811/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1812 the stack pointer does not matter. The value is tested only in 1813 functions that have frame pointers. 1814 No definition is equivalent to always zero. */ 1815/* Note on the 386 it might be more efficient not to define this since 1816 we have to restore it ourselves from the frame pointer, in order to 1817 use pop */ 1818 1819#define EXIT_IGNORE_STACK 1 1820 1821/* Output assembler code for a block containing the constant parts 1822 of a trampoline, leaving space for the variable parts. */ 1823 1824/* On the 386, the trampoline contains two instructions: 1825 mov #STATIC,ecx 1826 jmp FUNCTION 1827 The trampoline is generated entirely at runtime. The operand of JMP 1828 is the address of FUNCTION relative to the instruction following the 1829 JMP (which is 5 bytes long). */ 1830 1831/* Length in units of the trampoline for entering a nested function. */ 1832 1833#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1834 1835/* Emit RTL insns to initialize the variable parts of a trampoline. 1836 FNADDR is an RTX for the address of the function's pure code. 1837 CXT is an RTX for the static chain value for the function. */ 1838 1839#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1840 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1841 1842/* Definitions for register eliminations. 1843 1844 This is an array of structures. Each structure initializes one pair 1845 of eliminable registers. The "from" register number is given first, 1846 followed by "to". Eliminations of the same "from" register are listed 1847 in order of preference. 1848 1849 There are two registers that can always be eliminated on the i386. 1850 The frame pointer and the arg pointer can be replaced by either the 1851 hard frame pointer or to the stack pointer, depending upon the 1852 circumstances. The hard frame pointer is not used before reload and 1853 so it is not eligible for elimination. */ 1854 1855#define ELIMINABLE_REGS \ 1856{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1857 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1858 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1859 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1860 1861/* Given FROM and TO register numbers, say whether this elimination is 1862 allowed. Frame pointer elimination is automatically handled. 1863 1864 All other eliminations are valid. */ 1865 1866#define CAN_ELIMINATE(FROM, TO) \ 1867 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1868 1869/* Define the offset between two registers, one to be eliminated, and the other 1870 its replacement, at the start of a routine. */ 1871 1872#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1873 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1874 1875/* Addressing modes, and classification of registers for them. */ 1876 1877/* #define HAVE_POST_INCREMENT 0 */ 1878/* #define HAVE_POST_DECREMENT 0 */ 1879 1880/* #define HAVE_PRE_DECREMENT 0 */ 1881/* #define HAVE_PRE_INCREMENT 0 */ 1882 1883/* Macros to check register numbers against specific register classes. */ 1884 1885/* These assume that REGNO is a hard or pseudo reg number. 1886 They give nonzero only if REGNO is a hard reg of the suitable class 1887 or a pseudo reg currently allocated to a suitable hard reg. 1888 Since they use reg_renumber, they are safe only once reg_renumber 1889 has been allocated, which happens in local-alloc.c. */ 1890 1891#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1892 ((REGNO) < STACK_POINTER_REGNUM \ 1893 || (REGNO >= FIRST_REX_INT_REG \ 1894 && (REGNO) <= LAST_REX_INT_REG) \ 1895 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1896 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1897 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1898 1899#define REGNO_OK_FOR_BASE_P(REGNO) \ 1900 ((REGNO) <= STACK_POINTER_REGNUM \ 1901 || (REGNO) == ARG_POINTER_REGNUM \ 1902 || (REGNO) == FRAME_POINTER_REGNUM \ 1903 || (REGNO >= FIRST_REX_INT_REG \ 1904 && (REGNO) <= LAST_REX_INT_REG) \ 1905 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1906 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1907 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1908 1909#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1910 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1911#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1912 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1913 1914/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1915 and check its validity for a certain class. 1916 We have two alternate definitions for each of them. 1917 The usual definition accepts all pseudo regs; the other rejects 1918 them unless they have been allocated suitable hard regs. 1919 The symbol REG_OK_STRICT causes the latter definition to be used. 1920 1921 Most source files want to accept pseudo regs in the hope that 1922 they will get allocated to the class that the insn wants them to be in. 1923 Source files for reload pass need to be strict. 1924 After reload, it makes no difference, since pseudo regs have 1925 been eliminated by then. */ 1926 1927 1928/* Non strict versions, pseudos are ok */ 1929#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1930 (REGNO (X) < STACK_POINTER_REGNUM \ 1931 || (REGNO (X) >= FIRST_REX_INT_REG \ 1932 && REGNO (X) <= LAST_REX_INT_REG) \ 1933 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1934 1935#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1936 (REGNO (X) <= STACK_POINTER_REGNUM \ 1937 || REGNO (X) == ARG_POINTER_REGNUM \ 1938 || REGNO (X) == FRAME_POINTER_REGNUM \ 1939 || (REGNO (X) >= FIRST_REX_INT_REG \ 1940 && REGNO (X) <= LAST_REX_INT_REG) \ 1941 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1942 1943/* Strict versions, hard registers only */ 1944#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1945#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1946 1947#ifndef REG_OK_STRICT 1948#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1949#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1950 1951#else 1952#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1953#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1954#endif 1955 1956/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1957 that is a valid memory address for an instruction. 1958 The MODE argument is the machine mode for the MEM expression 1959 that wants to use this address. 1960 1961 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1962 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1963 1964 See legitimize_pic_address in i386.c for details as to what 1965 constitutes a legitimate address when -fpic is used. */ 1966 1967#define MAX_REGS_PER_ADDRESS 2 1968 1969#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1970 1971/* Nonzero if the constant value X is a legitimate general operand. 1972 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1973 1974#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1975 1976#ifdef REG_OK_STRICT 1977#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1978do { \ 1979 if (legitimate_address_p ((MODE), (X), 1)) \ 1980 goto ADDR; \ 1981} while (0) 1982 1983#else 1984#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1985do { \ 1986 if (legitimate_address_p ((MODE), (X), 0)) \ 1987 goto ADDR; \ 1988} while (0) 1989 1990#endif 1991 1992/* If defined, a C expression to determine the base term of address X. 1993 This macro is used in only one place: `find_base_term' in alias.c. 1994 1995 It is always safe for this macro to not be defined. It exists so 1996 that alias analysis can understand machine-dependent addresses. 1997 1998 The typical use of this macro is to handle addresses containing 1999 a label_ref or symbol_ref within an UNSPEC. */ 2000 2001#define FIND_BASE_TERM(X) ix86_find_base_term (X) 2002 2003/* Try machine-dependent ways of modifying an illegitimate address 2004 to be legitimate. If we find one, return the new, valid address. 2005 This macro is used in only one place: `memory_address' in explow.c. 2006 2007 OLDX is the address as it was before break_out_memory_refs was called. 2008 In some cases it is useful to look at this to decide what needs to be done. 2009 2010 MODE and WIN are passed so that this macro can use 2011 GO_IF_LEGITIMATE_ADDRESS. 2012 2013 It is always safe for this macro to do nothing. It exists to recognize 2014 opportunities to optimize the output. 2015 2016 For the 80386, we handle X+REG by loading X into a register R and 2017 using R+REG. R will go in a general reg and indexing will be used. 2018 However, if REG is a broken-out memory address or multiplication, 2019 nothing needs to be done because REG can certainly go in a general reg. 2020 2021 When -fpic is used, special handling is needed for symbolic references. 2022 See comments by legitimize_pic_address in i386.c for details. */ 2023 2024#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2025do { \ 2026 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 2027 if (memory_address_p ((MODE), (X))) \ 2028 goto WIN; \ 2029} while (0) 2030 2031#define REWRITE_ADDRESS(X) rewrite_address (X) 2032 2033/* Nonzero if the constant value X is a legitimate general operand 2034 when generating PIC code. It is given that flag_pic is on and 2035 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2036 2037#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 2038 2039#define SYMBOLIC_CONST(X) \ 2040 (GET_CODE (X) == SYMBOL_REF \ 2041 || GET_CODE (X) == LABEL_REF \ 2042 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 2043 2044/* Go to LABEL if ADDR (a legitimate address expression) 2045 has an effect that depends on the machine mode it is used for. 2046 On the 80386, only postdecrement and postincrement address depend thus 2047 (the amount of decrement or increment being the length of the operand). */ 2048#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2049do { \ 2050 if (GET_CODE (ADDR) == POST_INC \ 2051 || GET_CODE (ADDR) == POST_DEC) \ 2052 goto LABEL; \ 2053} while (0) 2054 2055/* Codes for all the SSE/MMX builtins. */ 2056enum ix86_builtins 2057{ 2058 IX86_BUILTIN_ADDPS, 2059 IX86_BUILTIN_ADDSS, 2060 IX86_BUILTIN_DIVPS, 2061 IX86_BUILTIN_DIVSS, 2062 IX86_BUILTIN_MULPS, 2063 IX86_BUILTIN_MULSS, 2064 IX86_BUILTIN_SUBPS, 2065 IX86_BUILTIN_SUBSS, 2066 2067 IX86_BUILTIN_CMPEQPS, 2068 IX86_BUILTIN_CMPLTPS, 2069 IX86_BUILTIN_CMPLEPS, 2070 IX86_BUILTIN_CMPGTPS, 2071 IX86_BUILTIN_CMPGEPS, 2072 IX86_BUILTIN_CMPNEQPS, 2073 IX86_BUILTIN_CMPNLTPS, 2074 IX86_BUILTIN_CMPNLEPS, 2075 IX86_BUILTIN_CMPNGTPS, 2076 IX86_BUILTIN_CMPNGEPS, 2077 IX86_BUILTIN_CMPORDPS, 2078 IX86_BUILTIN_CMPUNORDPS, 2079 IX86_BUILTIN_CMPNEPS, 2080 IX86_BUILTIN_CMPEQSS, 2081 IX86_BUILTIN_CMPLTSS, 2082 IX86_BUILTIN_CMPLESS, 2083 IX86_BUILTIN_CMPNEQSS, 2084 IX86_BUILTIN_CMPNLTSS, 2085 IX86_BUILTIN_CMPNLESS, 2086 IX86_BUILTIN_CMPORDSS, 2087 IX86_BUILTIN_CMPUNORDSS, 2088 IX86_BUILTIN_CMPNESS, 2089 2090 IX86_BUILTIN_COMIEQSS, 2091 IX86_BUILTIN_COMILTSS, 2092 IX86_BUILTIN_COMILESS, 2093 IX86_BUILTIN_COMIGTSS, 2094 IX86_BUILTIN_COMIGESS, 2095 IX86_BUILTIN_COMINEQSS, 2096 IX86_BUILTIN_UCOMIEQSS, 2097 IX86_BUILTIN_UCOMILTSS, 2098 IX86_BUILTIN_UCOMILESS, 2099 IX86_BUILTIN_UCOMIGTSS, 2100 IX86_BUILTIN_UCOMIGESS, 2101 IX86_BUILTIN_UCOMINEQSS, 2102 2103 IX86_BUILTIN_CVTPI2PS, 2104 IX86_BUILTIN_CVTPS2PI, 2105 IX86_BUILTIN_CVTSI2SS, 2106 IX86_BUILTIN_CVTSI642SS, 2107 IX86_BUILTIN_CVTSS2SI, 2108 IX86_BUILTIN_CVTSS2SI64, 2109 IX86_BUILTIN_CVTTPS2PI, 2110 IX86_BUILTIN_CVTTSS2SI, 2111 IX86_BUILTIN_CVTTSS2SI64, 2112 2113 IX86_BUILTIN_MAXPS, 2114 IX86_BUILTIN_MAXSS, 2115 IX86_BUILTIN_MINPS, 2116 IX86_BUILTIN_MINSS, 2117 2118 IX86_BUILTIN_LOADAPS, 2119 IX86_BUILTIN_LOADUPS, 2120 IX86_BUILTIN_STOREAPS, 2121 IX86_BUILTIN_STOREUPS, 2122 IX86_BUILTIN_LOADSS, 2123 IX86_BUILTIN_STORESS, 2124 IX86_BUILTIN_MOVSS, 2125 2126 IX86_BUILTIN_MOVHLPS, 2127 IX86_BUILTIN_MOVLHPS, 2128 IX86_BUILTIN_LOADHPS, 2129 IX86_BUILTIN_LOADLPS, 2130 IX86_BUILTIN_STOREHPS, 2131 IX86_BUILTIN_STORELPS, 2132 2133 IX86_BUILTIN_MASKMOVQ, 2134 IX86_BUILTIN_MOVMSKPS, 2135 IX86_BUILTIN_PMOVMSKB, 2136 2137 IX86_BUILTIN_MOVNTPS, 2138 IX86_BUILTIN_MOVNTQ, 2139 2140 IX86_BUILTIN_LOADDQA, 2141 IX86_BUILTIN_LOADDQU, 2142 IX86_BUILTIN_STOREDQA, 2143 IX86_BUILTIN_STOREDQU, 2144 IX86_BUILTIN_MOVQ, 2145 IX86_BUILTIN_LOADD, 2146 IX86_BUILTIN_STORED, 2147 2148 IX86_BUILTIN_CLRTI, 2149 2150 IX86_BUILTIN_PACKSSWB, 2151 IX86_BUILTIN_PACKSSDW, 2152 IX86_BUILTIN_PACKUSWB, 2153 2154 IX86_BUILTIN_PADDB, 2155 IX86_BUILTIN_PADDW, 2156 IX86_BUILTIN_PADDD, 2157 IX86_BUILTIN_PADDQ, 2158 IX86_BUILTIN_PADDSB, 2159 IX86_BUILTIN_PADDSW, 2160 IX86_BUILTIN_PADDUSB, 2161 IX86_BUILTIN_PADDUSW, 2162 IX86_BUILTIN_PSUBB, 2163 IX86_BUILTIN_PSUBW, 2164 IX86_BUILTIN_PSUBD, 2165 IX86_BUILTIN_PSUBQ, 2166 IX86_BUILTIN_PSUBSB, 2167 IX86_BUILTIN_PSUBSW, 2168 IX86_BUILTIN_PSUBUSB, 2169 IX86_BUILTIN_PSUBUSW, 2170 2171 IX86_BUILTIN_PAND, 2172 IX86_BUILTIN_PANDN, 2173 IX86_BUILTIN_POR, 2174 IX86_BUILTIN_PXOR, 2175 2176 IX86_BUILTIN_PAVGB, 2177 IX86_BUILTIN_PAVGW, 2178 2179 IX86_BUILTIN_PCMPEQB, 2180 IX86_BUILTIN_PCMPEQW, 2181 IX86_BUILTIN_PCMPEQD, 2182 IX86_BUILTIN_PCMPGTB, 2183 IX86_BUILTIN_PCMPGTW, 2184 IX86_BUILTIN_PCMPGTD, 2185 2186 IX86_BUILTIN_PEXTRW, 2187 IX86_BUILTIN_PINSRW, 2188 2189 IX86_BUILTIN_PMADDWD, 2190 2191 IX86_BUILTIN_PMAXSW, 2192 IX86_BUILTIN_PMAXUB, 2193 IX86_BUILTIN_PMINSW, 2194 IX86_BUILTIN_PMINUB, 2195 2196 IX86_BUILTIN_PMULHUW, 2197 IX86_BUILTIN_PMULHW, 2198 IX86_BUILTIN_PMULLW, 2199 2200 IX86_BUILTIN_PSADBW, 2201 IX86_BUILTIN_PSHUFW, 2202 2203 IX86_BUILTIN_PSLLW, 2204 IX86_BUILTIN_PSLLD, 2205 IX86_BUILTIN_PSLLQ, 2206 IX86_BUILTIN_PSRAW, 2207 IX86_BUILTIN_PSRAD, 2208 IX86_BUILTIN_PSRLW, 2209 IX86_BUILTIN_PSRLD, 2210 IX86_BUILTIN_PSRLQ, 2211 IX86_BUILTIN_PSLLWI, 2212 IX86_BUILTIN_PSLLDI, 2213 IX86_BUILTIN_PSLLQI, 2214 IX86_BUILTIN_PSRAWI, 2215 IX86_BUILTIN_PSRADI, 2216 IX86_BUILTIN_PSRLWI, 2217 IX86_BUILTIN_PSRLDI, 2218 IX86_BUILTIN_PSRLQI, 2219 2220 IX86_BUILTIN_PUNPCKHBW, 2221 IX86_BUILTIN_PUNPCKHWD, 2222 IX86_BUILTIN_PUNPCKHDQ, 2223 IX86_BUILTIN_PUNPCKLBW, 2224 IX86_BUILTIN_PUNPCKLWD, 2225 IX86_BUILTIN_PUNPCKLDQ, 2226 2227 IX86_BUILTIN_SHUFPS, 2228 2229 IX86_BUILTIN_RCPPS, 2230 IX86_BUILTIN_RCPSS, 2231 IX86_BUILTIN_RSQRTPS, 2232 IX86_BUILTIN_RSQRTSS, 2233 IX86_BUILTIN_SQRTPS, 2234 IX86_BUILTIN_SQRTSS, 2235 2236 IX86_BUILTIN_UNPCKHPS, 2237 IX86_BUILTIN_UNPCKLPS, 2238 2239 IX86_BUILTIN_ANDPS, 2240 IX86_BUILTIN_ANDNPS, 2241 IX86_BUILTIN_ORPS, 2242 IX86_BUILTIN_XORPS, 2243 2244 IX86_BUILTIN_EMMS, 2245 IX86_BUILTIN_LDMXCSR, 2246 IX86_BUILTIN_STMXCSR, 2247 IX86_BUILTIN_SFENCE, 2248 2249 /* 3DNow! Original */ 2250 IX86_BUILTIN_FEMMS, 2251 IX86_BUILTIN_PAVGUSB, 2252 IX86_BUILTIN_PF2ID, 2253 IX86_BUILTIN_PFACC, 2254 IX86_BUILTIN_PFADD, 2255 IX86_BUILTIN_PFCMPEQ, 2256 IX86_BUILTIN_PFCMPGE, 2257 IX86_BUILTIN_PFCMPGT, 2258 IX86_BUILTIN_PFMAX, 2259 IX86_BUILTIN_PFMIN, 2260 IX86_BUILTIN_PFMUL, 2261 IX86_BUILTIN_PFRCP, 2262 IX86_BUILTIN_PFRCPIT1, 2263 IX86_BUILTIN_PFRCPIT2, 2264 IX86_BUILTIN_PFRSQIT1, 2265 IX86_BUILTIN_PFRSQRT, 2266 IX86_BUILTIN_PFSUB, 2267 IX86_BUILTIN_PFSUBR, 2268 IX86_BUILTIN_PI2FD, 2269 IX86_BUILTIN_PMULHRW, 2270 2271 /* 3DNow! Athlon Extensions */ 2272 IX86_BUILTIN_PF2IW, 2273 IX86_BUILTIN_PFNACC, 2274 IX86_BUILTIN_PFPNACC, 2275 IX86_BUILTIN_PI2FW, 2276 IX86_BUILTIN_PSWAPDSI, 2277 IX86_BUILTIN_PSWAPDSF, 2278 2279 IX86_BUILTIN_SSE_ZERO, 2280 IX86_BUILTIN_MMX_ZERO, 2281 2282 /* SSE2 */ 2283 IX86_BUILTIN_ADDPD, 2284 IX86_BUILTIN_ADDSD, 2285 IX86_BUILTIN_DIVPD, 2286 IX86_BUILTIN_DIVSD, 2287 IX86_BUILTIN_MULPD, 2288 IX86_BUILTIN_MULSD, 2289 IX86_BUILTIN_SUBPD, 2290 IX86_BUILTIN_SUBSD, 2291 2292 IX86_BUILTIN_CMPEQPD, 2293 IX86_BUILTIN_CMPLTPD, 2294 IX86_BUILTIN_CMPLEPD, 2295 IX86_BUILTIN_CMPGTPD, 2296 IX86_BUILTIN_CMPGEPD, 2297 IX86_BUILTIN_CMPNEQPD, 2298 IX86_BUILTIN_CMPNLTPD, 2299 IX86_BUILTIN_CMPNLEPD, 2300 IX86_BUILTIN_CMPNGTPD, 2301 IX86_BUILTIN_CMPNGEPD, 2302 IX86_BUILTIN_CMPORDPD, 2303 IX86_BUILTIN_CMPUNORDPD, 2304 IX86_BUILTIN_CMPNEPD, 2305 IX86_BUILTIN_CMPEQSD, 2306 IX86_BUILTIN_CMPLTSD, 2307 IX86_BUILTIN_CMPLESD, 2308 IX86_BUILTIN_CMPNEQSD, 2309 IX86_BUILTIN_CMPNLTSD, 2310 IX86_BUILTIN_CMPNLESD, 2311 IX86_BUILTIN_CMPORDSD, 2312 IX86_BUILTIN_CMPUNORDSD, 2313 IX86_BUILTIN_CMPNESD, 2314 2315 IX86_BUILTIN_COMIEQSD, 2316 IX86_BUILTIN_COMILTSD, 2317 IX86_BUILTIN_COMILESD, 2318 IX86_BUILTIN_COMIGTSD, 2319 IX86_BUILTIN_COMIGESD, 2320 IX86_BUILTIN_COMINEQSD, 2321 IX86_BUILTIN_UCOMIEQSD, 2322 IX86_BUILTIN_UCOMILTSD, 2323 IX86_BUILTIN_UCOMILESD, 2324 IX86_BUILTIN_UCOMIGTSD, 2325 IX86_BUILTIN_UCOMIGESD, 2326 IX86_BUILTIN_UCOMINEQSD, 2327 2328 IX86_BUILTIN_MAXPD, 2329 IX86_BUILTIN_MAXSD, 2330 IX86_BUILTIN_MINPD, 2331 IX86_BUILTIN_MINSD, 2332 2333 IX86_BUILTIN_ANDPD, 2334 IX86_BUILTIN_ANDNPD, 2335 IX86_BUILTIN_ORPD, 2336 IX86_BUILTIN_XORPD, 2337 2338 IX86_BUILTIN_SQRTPD, 2339 IX86_BUILTIN_SQRTSD, 2340 2341 IX86_BUILTIN_UNPCKHPD, 2342 IX86_BUILTIN_UNPCKLPD, 2343 2344 IX86_BUILTIN_SHUFPD, 2345 2346 IX86_BUILTIN_LOADAPD, 2347 IX86_BUILTIN_LOADUPD, 2348 IX86_BUILTIN_STOREAPD, 2349 IX86_BUILTIN_STOREUPD, 2350 IX86_BUILTIN_LOADSD, 2351 IX86_BUILTIN_STORESD, 2352 IX86_BUILTIN_MOVSD, 2353 2354 IX86_BUILTIN_LOADHPD, 2355 IX86_BUILTIN_LOADLPD, 2356 IX86_BUILTIN_STOREHPD, 2357 IX86_BUILTIN_STORELPD, 2358 2359 IX86_BUILTIN_CVTDQ2PD, 2360 IX86_BUILTIN_CVTDQ2PS, 2361 2362 IX86_BUILTIN_CVTPD2DQ, 2363 IX86_BUILTIN_CVTPD2PI, 2364 IX86_BUILTIN_CVTPD2PS, 2365 IX86_BUILTIN_CVTTPD2DQ, 2366 IX86_BUILTIN_CVTTPD2PI, 2367 2368 IX86_BUILTIN_CVTPI2PD, 2369 IX86_BUILTIN_CVTSI2SD, 2370 IX86_BUILTIN_CVTSI642SD, 2371 2372 IX86_BUILTIN_CVTSD2SI, 2373 IX86_BUILTIN_CVTSD2SI64, 2374 IX86_BUILTIN_CVTSD2SS, 2375 IX86_BUILTIN_CVTSS2SD, 2376 IX86_BUILTIN_CVTTSD2SI, 2377 IX86_BUILTIN_CVTTSD2SI64, 2378 2379 IX86_BUILTIN_CVTPS2DQ, 2380 IX86_BUILTIN_CVTPS2PD, 2381 IX86_BUILTIN_CVTTPS2DQ, 2382 2383 IX86_BUILTIN_MOVNTI, 2384 IX86_BUILTIN_MOVNTPD, 2385 IX86_BUILTIN_MOVNTDQ, 2386 2387 IX86_BUILTIN_SETPD1, 2388 IX86_BUILTIN_SETPD, 2389 IX86_BUILTIN_CLRPD, 2390 IX86_BUILTIN_SETRPD, 2391 IX86_BUILTIN_LOADPD1, 2392 IX86_BUILTIN_LOADRPD, 2393 IX86_BUILTIN_STOREPD1, 2394 IX86_BUILTIN_STORERPD, 2395 2396 /* SSE2 MMX */ 2397 IX86_BUILTIN_MASKMOVDQU, 2398 IX86_BUILTIN_MOVMSKPD, 2399 IX86_BUILTIN_PMOVMSKB128, 2400 IX86_BUILTIN_MOVQ2DQ, 2401 IX86_BUILTIN_MOVDQ2Q, 2402 2403 IX86_BUILTIN_PACKSSWB128, 2404 IX86_BUILTIN_PACKSSDW128, 2405 IX86_BUILTIN_PACKUSWB128, 2406 2407 IX86_BUILTIN_PADDB128, 2408 IX86_BUILTIN_PADDW128, 2409 IX86_BUILTIN_PADDD128, 2410 IX86_BUILTIN_PADDQ128, 2411 IX86_BUILTIN_PADDSB128, 2412 IX86_BUILTIN_PADDSW128, 2413 IX86_BUILTIN_PADDUSB128, 2414 IX86_BUILTIN_PADDUSW128, 2415 IX86_BUILTIN_PSUBB128, 2416 IX86_BUILTIN_PSUBW128, 2417 IX86_BUILTIN_PSUBD128, 2418 IX86_BUILTIN_PSUBQ128, 2419 IX86_BUILTIN_PSUBSB128, 2420 IX86_BUILTIN_PSUBSW128, 2421 IX86_BUILTIN_PSUBUSB128, 2422 IX86_BUILTIN_PSUBUSW128, 2423 2424 IX86_BUILTIN_PAND128, 2425 IX86_BUILTIN_PANDN128, 2426 IX86_BUILTIN_POR128, 2427 IX86_BUILTIN_PXOR128, 2428 2429 IX86_BUILTIN_PAVGB128, 2430 IX86_BUILTIN_PAVGW128, 2431 2432 IX86_BUILTIN_PCMPEQB128, 2433 IX86_BUILTIN_PCMPEQW128, 2434 IX86_BUILTIN_PCMPEQD128, 2435 IX86_BUILTIN_PCMPGTB128, 2436 IX86_BUILTIN_PCMPGTW128, 2437 IX86_BUILTIN_PCMPGTD128, 2438 2439 IX86_BUILTIN_PEXTRW128, 2440 IX86_BUILTIN_PINSRW128, 2441 2442 IX86_BUILTIN_PMADDWD128, 2443 2444 IX86_BUILTIN_PMAXSW128, 2445 IX86_BUILTIN_PMAXUB128, 2446 IX86_BUILTIN_PMINSW128, 2447 IX86_BUILTIN_PMINUB128, 2448 2449 IX86_BUILTIN_PMULUDQ, 2450 IX86_BUILTIN_PMULUDQ128, 2451 IX86_BUILTIN_PMULHUW128, 2452 IX86_BUILTIN_PMULHW128, 2453 IX86_BUILTIN_PMULLW128, 2454 2455 IX86_BUILTIN_PSADBW128, 2456 IX86_BUILTIN_PSHUFHW, 2457 IX86_BUILTIN_PSHUFLW, 2458 IX86_BUILTIN_PSHUFD, 2459 2460 IX86_BUILTIN_PSLLW128, 2461 IX86_BUILTIN_PSLLD128, 2462 IX86_BUILTIN_PSLLQ128, 2463 IX86_BUILTIN_PSRAW128, 2464 IX86_BUILTIN_PSRAD128, 2465 IX86_BUILTIN_PSRLW128, 2466 IX86_BUILTIN_PSRLD128, 2467 IX86_BUILTIN_PSRLQ128, 2468 IX86_BUILTIN_PSLLDQI128, 2469 IX86_BUILTIN_PSLLWI128, 2470 IX86_BUILTIN_PSLLDI128, 2471 IX86_BUILTIN_PSLLQI128, 2472 IX86_BUILTIN_PSRAWI128, 2473 IX86_BUILTIN_PSRADI128, 2474 IX86_BUILTIN_PSRLDQI128, 2475 IX86_BUILTIN_PSRLWI128, 2476 IX86_BUILTIN_PSRLDI128, 2477 IX86_BUILTIN_PSRLQI128, 2478 2479 IX86_BUILTIN_PUNPCKHBW128, 2480 IX86_BUILTIN_PUNPCKHWD128, 2481 IX86_BUILTIN_PUNPCKHDQ128, 2482 IX86_BUILTIN_PUNPCKHQDQ128, 2483 IX86_BUILTIN_PUNPCKLBW128, 2484 IX86_BUILTIN_PUNPCKLWD128, 2485 IX86_BUILTIN_PUNPCKLDQ128, 2486 IX86_BUILTIN_PUNPCKLQDQ128, 2487 2488 IX86_BUILTIN_CLFLUSH, 2489 IX86_BUILTIN_MFENCE, 2490 IX86_BUILTIN_LFENCE, 2491 2492 IX86_BUILTIN_MAX 2493}; 2494 2495#define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info 2496#define TARGET_STRIP_NAME_ENCODING ix86_strip_name_encoding 2497 2498#define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2499 do { \ 2500 const char *xname = (NAME); \ 2501 if (xname[0] == '%') \ 2502 xname += 2; \ 2503 if (xname[0] == '*') \ 2504 xname += 1; \ 2505 else \ 2506 fputs (user_label_prefix, FILE); \ 2507 fputs (xname, FILE); \ 2508 } while (0) 2509 2510/* Max number of args passed in registers. If this is more than 3, we will 2511 have problems with ebx (register #4), since it is a caller save register and 2512 is also used as the pic register in ELF. So for now, don't allow more than 2513 3 registers to be passed in registers. */ 2514 2515#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 2516 2517#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0) 2518 2519 2520/* Specify the machine mode that this machine uses 2521 for the index in the tablejump instruction. */ 2522#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 2523 2524/* Define as C expression which evaluates to nonzero if the tablejump 2525 instruction expects the table to contain offsets from the address of the 2526 table. 2527 Do not define this if the table should contain absolute addresses. */ 2528/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2529 2530/* Define this as 1 if `char' should by default be signed; else as 0. */ 2531#define DEFAULT_SIGNED_CHAR 1 2532 2533/* Number of bytes moved into a data cache for a single prefetch operation. */ 2534#define PREFETCH_BLOCK ix86_cost->prefetch_block 2535 2536/* Number of prefetch operations that can be done in parallel. */ 2537#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 2538 2539/* Max number of bytes we can move from memory to memory 2540 in one reasonably fast instruction. */ 2541#define MOVE_MAX 16 2542 2543/* MOVE_MAX_PIECES is the number of bytes at a time which we can 2544 move efficiently, as opposed to MOVE_MAX which is the maximum 2545 number of bytes we can move with a single instruction. */ 2546#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 2547 2548/* If a memory-to-memory move would take MOVE_RATIO or more simple 2549 move-instruction pairs, we will do a movstr or libcall instead. 2550 Increasing the value will always make code faster, but eventually 2551 incurs high cost in increased code size. 2552 2553 If you don't define this, a reasonable default is used. */ 2554 2555#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 2556 2557/* Define if shifts truncate the shift count 2558 which implies one can omit a sign-extension or zero-extension 2559 of a shift count. */ 2560/* On i386, shifts do truncate the count. But bit opcodes don't. */ 2561 2562/* #define SHIFT_COUNT_TRUNCATED */ 2563 2564/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2565 is done just by pretending it is already truncated. */ 2566#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2567 2568/* We assume that the store-condition-codes instructions store 0 for false 2569 and some other value for true. This is the value stored for true. */ 2570 2571#define STORE_FLAG_VALUE 1 2572 2573/* When a prototype says `char' or `short', really pass an `int'. 2574 (The 386 can't easily push less than an int.) */ 2575 2576#define PROMOTE_PROTOTYPES 1 2577 2578/* A macro to update M and UNSIGNEDP when an object whose type is 2579 TYPE and which has the specified mode and signedness is to be 2580 stored in a register. This macro is only called when TYPE is a 2581 scalar type. 2582 2583 On i386 it is sometimes useful to promote HImode and QImode 2584 quantities to SImode. The choice depends on target type. */ 2585 2586#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2587do { \ 2588 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 2589 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 2590 (MODE) = SImode; \ 2591} while (0) 2592 2593/* Specify the machine mode that pointers have. 2594 After generation of rtl, the compiler makes no further distinction 2595 between pointers and any other objects of this machine mode. */ 2596#define Pmode (TARGET_64BIT ? DImode : SImode) 2597 2598/* A function address in a call instruction 2599 is a byte address (for indexing purposes) 2600 so give the MEM rtx a byte's mode. */ 2601#define FUNCTION_MODE QImode 2602 2603/* A part of a C `switch' statement that describes the relative costs 2604 of constant RTL expressions. It must contain `case' labels for 2605 expression codes `const_int', `const', `symbol_ref', `label_ref' 2606 and `const_double'. Each case must ultimately reach a `return' 2607 statement to return the relative cost of the use of that kind of 2608 constant value in an expression. The cost may depend on the 2609 precise value of the constant, which is available for examination 2610 in X, and the rtx code of the expression in which it is contained, 2611 found in OUTER_CODE. 2612 2613 CODE is the expression code--redundant, since it can be obtained 2614 with `GET_CODE (X)'. */ 2615 2616#define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 2617 case CONST_INT: \ 2618 case CONST: \ 2619 case LABEL_REF: \ 2620 case SYMBOL_REF: \ 2621 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \ 2622 return 3; \ 2623 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \ 2624 return 2; \ 2625 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \ 2626 \ 2627 case CONST_DOUBLE: \ 2628 if (GET_MODE (RTX) == VOIDmode) \ 2629 return 0; \ 2630 switch (standard_80387_constant_p (RTX)) \ 2631 { \ 2632 case 1: /* 0.0 */ \ 2633 return 1; \ 2634 case 2: /* 1.0 */ \ 2635 return 2; \ 2636 default: \ 2637 /* Start with (MEM (SYMBOL_REF)), since that's where \ 2638 it'll probably end up. Add a penalty for size. */ \ 2639 return (COSTS_N_INSNS (1) + (flag_pic != 0) \ 2640 + (GET_MODE (RTX) == SFmode ? 0 \ 2641 : GET_MODE (RTX) == DFmode ? 1 : 2)); \ 2642 } 2643 2644/* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ 2645#define TOPLEVEL_COSTS_N_INSNS(N) \ 2646 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) 2647 2648/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. 2649 This can be used, for example, to indicate how costly a multiply 2650 instruction is. In writing this macro, you can use the construct 2651 `COSTS_N_INSNS (N)' to specify a cost equal to N fast 2652 instructions. OUTER_CODE is the code of the expression in which X 2653 is contained. 2654 2655 This macro is optional; do not define it if the default cost 2656 assumptions are adequate for the target machine. */ 2657 2658#define RTX_COSTS(X, CODE, OUTER_CODE) \ 2659 case ZERO_EXTEND: \ 2660 /* The zero extensions is often completely free on x86_64, so make \ 2661 it as cheap as possible. */ \ 2662 if (TARGET_64BIT && GET_MODE (X) == DImode \ 2663 && GET_MODE (XEXP (X, 0)) == SImode) \ 2664 { \ 2665 total = 1; goto egress_rtx_costs; \ 2666 } \ 2667 else \ 2668 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \ 2669 ix86_cost->add : ix86_cost->movzx); \ 2670 break; \ 2671 case SIGN_EXTEND: \ 2672 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \ 2673 break; \ 2674 case ASHIFT: \ 2675 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 2676 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \ 2677 { \ 2678 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2679 if (value == 1) \ 2680 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2681 if ((value == 2 || value == 3) \ 2682 && !TARGET_DECOMPOSE_LEA \ 2683 && ix86_cost->lea <= ix86_cost->shift_const) \ 2684 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ 2685 } \ 2686 /* fall through */ \ 2687 \ 2688 case ROTATE: \ 2689 case ASHIFTRT: \ 2690 case LSHIFTRT: \ 2691 case ROTATERT: \ 2692 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \ 2693 { \ 2694 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2695 { \ 2696 if (INTVAL (XEXP (X, 1)) > 32) \ 2697 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ 2698 else \ 2699 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ 2700 } \ 2701 else \ 2702 { \ 2703 if (GET_CODE (XEXP (X, 1)) == AND) \ 2704 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ 2705 else \ 2706 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ 2707 } \ 2708 } \ 2709 else \ 2710 { \ 2711 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2712 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ 2713 else \ 2714 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ 2715 } \ 2716 break; \ 2717 \ 2718 case MULT: \ 2719 if (FLOAT_MODE_P (GET_MODE (X))) \ 2720 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fmul); \ 2721 else if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2722 { \ 2723 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2724 int nbits = 0; \ 2725 \ 2726 while (value != 0) \ 2727 { \ 2728 nbits++; \ 2729 value >>= 1; \ 2730 } \ 2731 \ 2732 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2733 + nbits * ix86_cost->mult_bit); \ 2734 } \ 2735 else /* This is arbitrary */ \ 2736 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2737 + 7 * ix86_cost->mult_bit); \ 2738 \ 2739 case DIV: \ 2740 case UDIV: \ 2741 case MOD: \ 2742 case UMOD: \ 2743 if (FLOAT_MODE_P (GET_MODE (X))) \ 2744 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fdiv); \ 2745 else \ 2746 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ 2747 break; \ 2748 \ 2749 case PLUS: \ 2750 if (FLOAT_MODE_P (GET_MODE (X))) \ 2751 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \ 2752 else if (!TARGET_DECOMPOSE_LEA \ 2753 && INTEGRAL_MODE_P (GET_MODE (X)) \ 2754 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \ 2755 { \ 2756 if (GET_CODE (XEXP (X, 0)) == PLUS \ 2757 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ 2758 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ 2759 && CONSTANT_P (XEXP (X, 1))) \ 2760 { \ 2761 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\ 2762 if (val == 2 || val == 4 || val == 8) \ 2763 { \ 2764 return (COSTS_N_INSNS (ix86_cost->lea) \ 2765 + rtx_cost (XEXP (XEXP (X, 0), 1), \ 2766 (OUTER_CODE)) \ 2767 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \ 2768 (OUTER_CODE)) \ 2769 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2770 } \ 2771 } \ 2772 else if (GET_CODE (XEXP (X, 0)) == MULT \ 2773 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ 2774 { \ 2775 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ 2776 if (val == 2 || val == 4 || val == 8) \ 2777 { \ 2778 return (COSTS_N_INSNS (ix86_cost->lea) \ 2779 + rtx_cost (XEXP (XEXP (X, 0), 0), \ 2780 (OUTER_CODE)) \ 2781 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2782 } \ 2783 } \ 2784 else if (GET_CODE (XEXP (X, 0)) == PLUS) \ 2785 { \ 2786 return (COSTS_N_INSNS (ix86_cost->lea) \ 2787 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \ 2788 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \ 2789 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2790 } \ 2791 } \ 2792 /* fall through */ \ 2793 \ 2794 case MINUS: \ 2795 if (FLOAT_MODE_P (GET_MODE (X))) \ 2796 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \ 2797 /* fall through */ \ 2798 \ 2799 case AND: \ 2800 case IOR: \ 2801 case XOR: \ 2802 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2803 return (COSTS_N_INSNS (ix86_cost->add) * 2 \ 2804 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \ 2805 << (GET_MODE (XEXP (X, 0)) != DImode)) \ 2806 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \ 2807 << (GET_MODE (XEXP (X, 1)) != DImode))); \ 2808 /* fall through */ \ 2809 \ 2810 case NEG: \ 2811 if (FLOAT_MODE_P (GET_MODE (X))) \ 2812 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fchs); \ 2813 /* fall through */ \ 2814 \ 2815 case NOT: \ 2816 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2817 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ 2818 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2819 \ 2820 case FLOAT_EXTEND: \ 2821 if (!TARGET_SSE_MATH \ 2822 || !VALID_SSE_REG_MODE (GET_MODE (X))) \ 2823 TOPLEVEL_COSTS_N_INSNS (0); \ 2824 break; \ 2825 \ 2826 case ABS: \ 2827 if (FLOAT_MODE_P (GET_MODE (X))) \ 2828 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fabs); \ 2829 break; \ 2830 \ 2831 case SQRT: \ 2832 if (FLOAT_MODE_P (GET_MODE (X))) \ 2833 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fsqrt); \ 2834 break; \ 2835 \ 2836 egress_rtx_costs: \ 2837 break; 2838 2839 2840/* An expression giving the cost of an addressing mode that contains 2841 ADDRESS. If not defined, the cost is computed from the ADDRESS 2842 expression and the `CONST_COSTS' values. 2843 2844 For most CISC machines, the default cost is a good approximation 2845 of the true cost of the addressing mode. However, on RISC 2846 machines, all instructions normally have the same length and 2847 execution time. Hence all addresses will have equal costs. 2848 2849 In cases where more than one form of an address is known, the form 2850 with the lowest cost will be used. If multiple forms have the 2851 same, lowest, cost, the one that is the most complex will be used. 2852 2853 For example, suppose an address that is equal to the sum of a 2854 register and a constant is used twice in the same basic block. 2855 When this macro is not defined, the address will be computed in a 2856 register and memory references will be indirect through that 2857 register. On machines where the cost of the addressing mode 2858 containing the sum is no higher than that of a simple indirect 2859 reference, this will produce an additional instruction and 2860 possibly require an additional register. Proper specification of 2861 this macro eliminates this overhead for such machines. 2862 2863 Similar use of this macro is made in strength reduction of loops. 2864 2865 ADDRESS need not be valid as an address. In such a case, the cost 2866 is not relevant and can be any value; invalid addresses need not be 2867 assigned a different cost. 2868 2869 On machines where an address involving more than one register is as 2870 cheap as an address computation involving only one register, 2871 defining `ADDRESS_COST' to reflect this can cause two registers to 2872 be live over a region of code where only one would have been if 2873 `ADDRESS_COST' were not defined in that manner. This effect should 2874 be considered in the definition of this macro. Equivalent costs 2875 should probably only be given to addresses with different numbers 2876 of registers on machines with lots of registers. 2877 2878 This macro will normally either not be defined or be defined as a 2879 constant. 2880 2881 For i386, it is better to use a complex address than let gcc copy 2882 the address into a reg and make a new pseudo. But not if the address 2883 requires to two regs - that would mean more pseudos with longer 2884 lifetimes. */ 2885 2886#define ADDRESS_COST(RTX) \ 2887 ix86_address_cost (RTX) 2888 2889/* A C expression for the cost of moving data from a register in class FROM to 2890 one in class TO. The classes are expressed using the enumeration values 2891 such as `GENERAL_REGS'. A value of 2 is the default; other values are 2892 interpreted relative to that. 2893 2894 It is not required that the cost always equal 2 when FROM is the same as TO; 2895 on some machines it is expensive to move between registers if they are not 2896 general registers. */ 2897 2898#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2899 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 2900 2901/* A C expression for the cost of moving data of mode M between a 2902 register and memory. A value of 2 is the default; this cost is 2903 relative to those in `REGISTER_MOVE_COST'. 2904 2905 If moving between registers and memory is more expensive than 2906 between two registers, you should define this macro to express the 2907 relative cost. */ 2908 2909#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 2910 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 2911 2912/* A C expression for the cost of a branch instruction. A value of 1 2913 is the default; other values are interpreted relative to that. */ 2914 2915#define BRANCH_COST ix86_branch_cost 2916 2917/* Define this macro as a C expression which is nonzero if accessing 2918 less than a word of memory (i.e. a `char' or a `short') is no 2919 faster than accessing a word of memory, i.e., if such access 2920 require more than one instruction or if there is no difference in 2921 cost between byte and (aligned) word loads. 2922 2923 When this macro is not defined, the compiler will access a field by 2924 finding the smallest containing object; when it is defined, a 2925 fullword load will be used if alignment permits. Unless bytes 2926 accesses are faster than word accesses, using word accesses is 2927 preferable since it may eliminate subsequent memory access if 2928 subsequent accesses occur to other fields in the same word of the 2929 structure, but to different bytes. */ 2930 2931#define SLOW_BYTE_ACCESS 0 2932 2933/* Nonzero if access to memory by shorts is slow and undesirable. */ 2934#define SLOW_SHORT_ACCESS 0 2935 2936/* Define this macro to be the value 1 if unaligned accesses have a 2937 cost many times greater than aligned accesses, for example if they 2938 are emulated in a trap handler. 2939 2940 When this macro is nonzero, the compiler will act as if 2941 `STRICT_ALIGNMENT' were nonzero when generating code for block 2942 moves. This can cause significantly more instructions to be 2943 produced. Therefore, do not set this macro nonzero if unaligned 2944 accesses only add a cycle or two to the time for a memory access. 2945 2946 If the value of this macro is always zero, it need not be defined. */ 2947 2948/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2949 2950/* Define this macro to inhibit strength reduction of memory 2951 addresses. (On some machines, such strength reduction seems to do 2952 harm rather than good.) */ 2953 2954/* #define DONT_REDUCE_ADDR */ 2955 2956/* Define this macro if it is as good or better to call a constant 2957 function address than to call an address kept in a register. 2958 2959 Desirable on the 386 because a CALL with a constant address is 2960 faster than one with a register address. */ 2961 2962#define NO_FUNCTION_CSE 2963 2964/* Define this macro if it is as good or better for a function to call 2965 itself with an explicit address than to call an address kept in a 2966 register. */ 2967 2968#define NO_RECURSIVE_FUNCTION_CSE 2969 2970/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2971 return the mode to be used for the comparison. 2972 2973 For floating-point equality comparisons, CCFPEQmode should be used. 2974 VOIDmode should be used in all other cases. 2975 2976 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2977 possible, to allow for more combinations. */ 2978 2979#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2980 2981/* Return nonzero if MODE implies a floating point inequality can be 2982 reversed. */ 2983 2984#define REVERSIBLE_CC_MODE(MODE) 1 2985 2986/* A C expression whose value is reversed condition code of the CODE for 2987 comparison done in CC_MODE mode. */ 2988#define REVERSE_CONDITION(CODE, MODE) \ 2989 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ 2990 : reverse_condition_maybe_unordered (CODE)) 2991 2992 2993/* Control the assembler format that we output, to the extent 2994 this does not vary between assemblers. */ 2995 2996/* How to refer to registers in assembler output. 2997 This sequence is indexed by compiler's hard-register-number (see above). */ 2998 2999/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" 3000 For non floating point regs, the following are the HImode names. 3001 3002 For float regs, the stack top is sometimes referred to as "%st(0)" 3003 instead of just "%st". PRINT_REG handles this with the "y" code. */ 3004 3005#undef HI_REGISTER_NAMES 3006#define HI_REGISTER_NAMES \ 3007{"ax","dx","cx","bx","si","di","bp","sp", \ 3008 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ 3009 "flags","fpsr", "dirflag", "frame", \ 3010 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 3011 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 3012 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 3013 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 3014 3015#define REGISTER_NAMES HI_REGISTER_NAMES 3016 3017/* Table of additional register names to use in user input. */ 3018 3019#define ADDITIONAL_REGISTER_NAMES \ 3020{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 3021 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 3022 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 3023 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 3024 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 3025 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 3026 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ 3027 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } 3028 3029/* Note we are omitting these since currently I don't know how 3030to get gcc to use these, since they want the same but different 3031number as al, and ax. 3032*/ 3033 3034#define QI_REGISTER_NAMES \ 3035{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 3036 3037/* These parallel the array above, and can be used to access bits 8:15 3038 of regs 0 through 3. */ 3039 3040#define QI_HIGH_REGISTER_NAMES \ 3041{"ah", "dh", "ch", "bh", } 3042 3043/* How to renumber registers for dbx and gdb. */ 3044 3045#define DBX_REGISTER_NUMBER(N) \ 3046 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 3047 3048extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 3049extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 3050extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 3051 3052/* Before the prologue, RA is at 0(%esp). */ 3053#define INCOMING_RETURN_ADDR_RTX \ 3054 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 3055 3056/* After the prologue, RA is at -4(AP) in the current frame. */ 3057#define RETURN_ADDR_RTX(COUNT, FRAME) \ 3058 ((COUNT) == 0 \ 3059 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 3060 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 3061 3062/* PC is dbx register 8; let's use that column for RA. */ 3063#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 3064 3065/* Before the prologue, the top of the frame is at 4(%esp). */ 3066#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 3067 3068/* Describe how we implement __builtin_eh_return. */ 3069#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 3070#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 3071 3072 3073/* Select a format to encode pointers in exception handling data. CODE 3074 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 3075 true if the symbol may be affected by dynamic relocations. 3076 3077 ??? All x86 object file formats are capable of representing this. 3078 After all, the relocation needed is the same as for the call insn. 3079 Whether or not a particular assembler allows us to enter such, I 3080 guess we'll have to see. */ 3081#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 3082 (flag_pic \ 3083 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 3084 : DW_EH_PE_absptr) 3085 3086/* Store in OUTPUT a string (made with alloca) containing 3087 an assembler-name for a local static variable named NAME. 3088 LABELNO is an integer which is different for each call. */ 3089 3090#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 3091( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 3092 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 3093 3094/* This is how to output an insn to push a register on the stack. 3095 It need not be very fast code. */ 3096 3097#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 3098do { \ 3099 if (TARGET_64BIT) \ 3100 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 3101 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 3102 else \ 3103 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 3104} while (0) 3105 3106/* This is how to output an insn to pop a register from the stack. 3107 It need not be very fast code. */ 3108 3109#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 3110do { \ 3111 if (TARGET_64BIT) \ 3112 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 3113 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 3114 else \ 3115 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 3116} while (0) 3117 3118/* This is how to output an element of a case-vector that is absolute. */ 3119 3120#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 3121 ix86_output_addr_vec_elt ((FILE), (VALUE)) 3122 3123/* This is how to output an element of a case-vector that is relative. */ 3124 3125#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 3126 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 3127 3128/* Under some conditions we need jump tables in the text section, because 3129 the assembler cannot handle label differences between sections. */ 3130 3131#define JUMP_TABLES_IN_TEXT_SECTION \ 3132 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 3133 3134/* A C statement that outputs an address constant appropriate to 3135 for DWARF debugging. */ 3136 3137#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ 3138 i386_dwarf_output_addr_const ((FILE), (X)) 3139 3140/* Either simplify a location expression, or return the original. */ 3141 3142#define ASM_SIMPLIFY_DWARF_ADDR(X) \ 3143 i386_simplify_dwarf_addr (X) 3144 3145/* Emit a dtp-relative reference to a TLS variable. */ 3146 3147#ifdef HAVE_AS_TLS 3148#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ 3149 i386_output_dwarf_dtprel (FILE, SIZE, X) 3150#endif 3151 3152/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 3153 and switch back. For x86 we do this only to save a few bytes that 3154 would otherwise be unused in the text section. */ 3155#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 3156 asm (SECTION_OP "\n\t" \ 3157 "call " USER_LABEL_PREFIX #FUNC "\n" \ 3158 TEXT_SECTION_ASM_OP); 3159 3160/* Print operand X (an rtx) in assembler syntax to file FILE. 3161 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 3162 Effect of various CODE letters is described in i386.c near 3163 print_operand function. */ 3164 3165#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 3166 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') 3167 3168/* Print the name of a register based on its machine mode and number. 3169 If CODE is 'w', pretend the mode is HImode. 3170 If CODE is 'b', pretend the mode is QImode. 3171 If CODE is 'k', pretend the mode is SImode. 3172 If CODE is 'q', pretend the mode is DImode. 3173 If CODE is 'h', pretend the reg is the `high' byte register. 3174 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ 3175 3176#define PRINT_REG(X, CODE, FILE) \ 3177 print_reg ((X), (CODE), (FILE)) 3178 3179#define PRINT_OPERAND(FILE, X, CODE) \ 3180 print_operand ((FILE), (X), (CODE)) 3181 3182#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 3183 print_operand_address ((FILE), (ADDR)) 3184 3185#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 3186do { \ 3187 if (! output_addr_const_extra (FILE, (X))) \ 3188 goto FAIL; \ 3189} while (0); 3190 3191/* Print the name of a register for based on its machine mode and number. 3192 This macro is used to print debugging output. 3193 This macro is different from PRINT_REG in that it may be used in 3194 programs that are not linked with aux-output.o. */ 3195 3196#define DEBUG_PRINT_REG(X, CODE, FILE) \ 3197 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ 3198 static const char * const qi_name[] = QI_REGISTER_NAMES; \ 3199 fprintf ((FILE), "%d ", REGNO (X)); \ 3200 if (REGNO (X) == FLAGS_REG) \ 3201 { fputs ("flags", (FILE)); break; } \ 3202 if (REGNO (X) == DIRFLAG_REG) \ 3203 { fputs ("dirflag", (FILE)); break; } \ 3204 if (REGNO (X) == FPSR_REG) \ 3205 { fputs ("fpsr", (FILE)); break; } \ 3206 if (REGNO (X) == ARG_POINTER_REGNUM) \ 3207 { fputs ("argp", (FILE)); break; } \ 3208 if (REGNO (X) == FRAME_POINTER_REGNUM) \ 3209 { fputs ("frame", (FILE)); break; } \ 3210 if (STACK_TOP_P (X)) \ 3211 { fputs ("st(0)", (FILE)); break; } \ 3212 if (FP_REG_P (X)) \ 3213 { fputs (hi_name[REGNO(X)], (FILE)); break; } \ 3214 if (REX_INT_REG_P (X)) \ 3215 { \ 3216 switch (GET_MODE_SIZE (GET_MODE (X))) \ 3217 { \ 3218 default: \ 3219 case 8: \ 3220 fprintf ((FILE), "r%i", REGNO (X) \ 3221 - FIRST_REX_INT_REG + 8); \ 3222 break; \ 3223 case 4: \ 3224 fprintf ((FILE), "r%id", REGNO (X) \ 3225 - FIRST_REX_INT_REG + 8); \ 3226 break; \ 3227 case 2: \ 3228 fprintf ((FILE), "r%iw", REGNO (X) \ 3229 - FIRST_REX_INT_REG + 8); \ 3230 break; \ 3231 case 1: \ 3232 fprintf ((FILE), "r%ib", REGNO (X) \ 3233 - FIRST_REX_INT_REG + 8); \ 3234 break; \ 3235 } \ 3236 break; \ 3237 } \ 3238 switch (GET_MODE_SIZE (GET_MODE (X))) \ 3239 { \ 3240 case 8: \ 3241 fputs ("r", (FILE)); \ 3242 fputs (hi_name[REGNO (X)], (FILE)); \ 3243 break; \ 3244 default: \ 3245 fputs ("e", (FILE)); \ 3246 case 2: \ 3247 fputs (hi_name[REGNO (X)], (FILE)); \ 3248 break; \ 3249 case 1: \ 3250 fputs (qi_name[REGNO (X)], (FILE)); \ 3251 break; \ 3252 } \ 3253 } while (0) 3254 3255/* a letter which is not needed by the normal asm syntax, which 3256 we can use for operand syntax in the extended asm */ 3257 3258#define ASM_OPERAND_LETTER '#' 3259#define RET return "" 3260#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 3261 3262/* Define the codes that are matched by predicates in i386.c. */ 3263 3264#define PREDICATE_CODES \ 3265 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ 3266 SYMBOL_REF, LABEL_REF, CONST}}, \ 3267 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3268 SYMBOL_REF, LABEL_REF, CONST}}, \ 3269 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ 3270 SYMBOL_REF, LABEL_REF, CONST}}, \ 3271 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3272 SYMBOL_REF, LABEL_REF, CONST}}, \ 3273 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3274 SYMBOL_REF, LABEL_REF, CONST}}, \ 3275 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3276 SYMBOL_REF, LABEL_REF, CONST}}, \ 3277 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3278 SYMBOL_REF, LABEL_REF}}, \ 3279 {"shiftdi_operand", {SUBREG, REG, MEM}}, \ 3280 {"const_int_1_operand", {CONST_INT}}, \ 3281 {"const_int_1_31_operand", {CONST_INT}}, \ 3282 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 3283 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3284 LABEL_REF, SUBREG, REG, MEM}}, \ 3285 {"pic_symbolic_operand", {CONST}}, \ 3286 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ 3287 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ 3288 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ 3289 {"const1_operand", {CONST_INT}}, \ 3290 {"const248_operand", {CONST_INT}}, \ 3291 {"incdec_operand", {CONST_INT}}, \ 3292 {"mmx_reg_operand", {REG}}, \ 3293 {"reg_no_sp_operand", {SUBREG, REG}}, \ 3294 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3295 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ 3296 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ 3297 {"index_register_operand", {SUBREG, REG}}, \ 3298 {"q_regs_operand", {SUBREG, REG}}, \ 3299 {"non_q_regs_operand", {SUBREG, REG}}, \ 3300 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ 3301 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ 3302 GE, UNGE, LTGT, UNEQ}}, \ 3303 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ 3304 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ 3305 }}, \ 3306 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ 3307 GTU, UNORDERED, ORDERED, UNLE, UNLT, \ 3308 UNGE, UNGT, LTGT, UNEQ }}, \ 3309 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ 3310 {"ext_register_operand", {SUBREG, REG}}, \ 3311 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ 3312 {"mult_operator", {MULT}}, \ 3313 {"div_operator", {DIV}}, \ 3314 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ 3315 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ 3316 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ 3317 LSHIFTRT, ROTATERT}}, \ 3318 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ 3319 {"memory_displacement_operand", {MEM}}, \ 3320 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3321 LABEL_REF, SUBREG, REG, MEM, AND}}, \ 3322 {"long_memory_operand", {MEM}}, \ 3323 {"tls_symbolic_operand", {SYMBOL_REF}}, \ 3324 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \ 3325 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \ 3326 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \ 3327 {"local_exec_symbolic_operand", {SYMBOL_REF}}, \ 3328 {"any_fp_register_operand", {REG}}, \ 3329 {"register_and_not_any_fp_reg_operand", {REG}}, \ 3330 {"fp_register_operand", {REG}}, \ 3331 {"register_and_not_fp_reg_operand", {REG}}, \ 3332 {"vector_move_operand", {CONST_VECTOR, SUBREG, REG, MEM}}, \ 3333 3334/* A list of predicates that do special things with modes, and so 3335 should not elicit warnings for VOIDmode match_operand. */ 3336 3337#define SPECIAL_MODE_PREDICATES \ 3338 "ext_register_operand", 3339 3340/* Which processor to schedule for. The cpu attribute defines a list that 3341 mirrors this list, so changes to i386.md must be made at the same time. */ 3342 3343enum processor_type 3344{ 3345 PROCESSOR_I386, /* 80386 */ 3346 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 3347 PROCESSOR_PENTIUM, 3348 PROCESSOR_PENTIUMPRO, 3349 PROCESSOR_K6, 3350 PROCESSOR_ATHLON, 3351 PROCESSOR_PENTIUM4, 3352 PROCESSOR_max 3353}; 3354 3355extern enum processor_type ix86_cpu; 3356extern const char *ix86_cpu_string; 3357 3358extern enum processor_type ix86_arch; 3359extern const char *ix86_arch_string; 3360 3361enum fpmath_unit 3362{ 3363 FPMATH_387 = 1, 3364 FPMATH_SSE = 2 3365}; 3366 3367extern enum fpmath_unit ix86_fpmath; 3368extern const char *ix86_fpmath_string; 3369 3370enum tls_dialect 3371{ 3372 TLS_DIALECT_GNU, 3373 TLS_DIALECT_SUN 3374}; 3375 3376extern enum tls_dialect ix86_tls_dialect; 3377extern const char *ix86_tls_dialect_string; 3378 3379enum cmodel { 3380 CM_32, /* The traditional 32-bit ABI. */ 3381 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 3382 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 3383 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 3384 CM_LARGE, /* No assumptions. */ 3385 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */ 3386}; 3387 3388extern enum cmodel ix86_cmodel; 3389extern const char *ix86_cmodel_string; 3390 3391/* Size of the RED_ZONE area. */ 3392#define RED_ZONE_SIZE 128 3393/* Reserved area of the red zone for temporaries. */ 3394#define RED_ZONE_RESERVE 8 3395 3396enum asm_dialect { 3397 ASM_ATT, 3398 ASM_INTEL 3399}; 3400 3401extern const char *ix86_asm_string; 3402extern enum asm_dialect ix86_asm_dialect; 3403 3404extern int ix86_regparm; 3405extern const char *ix86_regparm_string; 3406 3407extern int ix86_preferred_stack_boundary; 3408extern const char *ix86_preferred_stack_boundary_string; 3409 3410extern int ix86_branch_cost; 3411extern const char *ix86_branch_cost_string; 3412 3413extern const char *ix86_debug_arg_string; 3414extern const char *ix86_debug_addr_string; 3415 3416/* Obsoleted by -f options. Remove before 3.2 ships. */ 3417extern const char *ix86_align_loops_string; 3418extern const char *ix86_align_jumps_string; 3419extern const char *ix86_align_funcs_string; 3420 3421/* Smallest class containing REGNO. */ 3422extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 3423 3424extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 3425extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 3426 3427/* To properly truncate FP values into integers, we need to set i387 control 3428 word. We can't emit proper mode switching code before reload, as spills 3429 generated by reload may truncate values incorrectly, but we still can avoid 3430 redundant computation of new control word by the mode switching pass. 3431 The fldcw instructions are still emitted redundantly, but this is probably 3432 not going to be noticeable problem, as most CPUs do have fast path for 3433 the sequence. 3434 3435 The machinery is to emit simple truncation instructions and split them 3436 before reload to instructions having USEs of two memory locations that 3437 are filled by this code to old and new control word. 3438 3439 Post-reload pass may be later used to eliminate the redundant fildcw if 3440 needed. */ 3441 3442enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; 3443 3444/* Define this macro if the port needs extra instructions inserted 3445 for mode switching in an optimizing compilation. */ 3446 3447#define OPTIMIZE_MODE_SWITCHING(ENTITY) 1 3448 3449/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 3450 initializer for an array of integers. Each initializer element N 3451 refers to an entity that needs mode switching, and specifies the 3452 number of different modes that might need to be set for this 3453 entity. The position of the initializer in the initializer - 3454 starting counting at zero - determines the integer that is used to 3455 refer to the mode-switched entity in question. */ 3456 3457#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } 3458 3459/* ENTITY is an integer specifying a mode-switched entity. If 3460 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 3461 return an integer value not larger than the corresponding element 3462 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 3463 must be switched into prior to the execution of INSN. */ 3464 3465#define MODE_NEEDED(ENTITY, I) \ 3466 (GET_CODE (I) == CALL_INSN \ 3467 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ 3468 || GET_CODE (PATTERN (I)) == ASM_INPUT))\ 3469 ? FP_CW_UNINITIALIZED \ 3470 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ 3471 ? FP_CW_ANY \ 3472 : FP_CW_STORED) 3473 3474/* This macro specifies the order in which modes for ENTITY are 3475 processed. 0 is the highest priority. */ 3476 3477#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 3478 3479/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 3480 is the set of hard registers live at the point where the insn(s) 3481 are to be inserted. */ 3482 3483#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3484 ((MODE) == FP_CW_STORED \ 3485 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ 3486 assign_386_stack_local (HImode, 2)), 0\ 3487 : 0) 3488 3489/* Avoid renaming of stack registers, as doing so in combination with 3490 scheduling just increases amount of live registers at time and in 3491 the turn amount of fxch instructions needed. 3492 3493 ??? Maybe Pentium chips benefits from renaming, someone can try... */ 3494 3495#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 3496 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 3497 3498 3499#define MACHINE_DEPENDENT_REORG(X) x86_machine_dependent_reorg(X) 3500 3501#define DLL_IMPORT_EXPORT_PREFIX '@' 3502 3503/* 3504Local variables: 3505version-control: t 3506End: 3507*/ 3508