i386.h revision 107598
1/* Definitions of target machine for GNU compiler for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002 Free Software Foundation, Inc. 4 5This file is part of GNU CC. 6 7GNU CC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GNU CC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GNU CC; see the file COPYING. If not, write to 19the Free Software Foundation, 59 Temple Place - Suite 330, 20Boston, MA 02111-1307, USA. */ 21 22/* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37 38/* $FreeBSD: head/contrib/gcc/config/i386/i386.h 107598 2002-12-04 16:07:58Z obrien $ */ 39 40 41/* Stubs for half-pic support if not OSF/1 reference platform. */ 42 43#ifndef HALF_PIC_P 44#define HALF_PIC_P() 0 45#define HALF_PIC_NUMBER_PTRS 0 46#define HALF_PIC_NUMBER_REFS 0 47#define HALF_PIC_ENCODE(DECL) 48#define HALF_PIC_DECLARE(NAME) 49#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it") 50#define HALF_PIC_ADDRESS_P(X) 0 51#define HALF_PIC_PTR(X) (X) 52#define HALF_PIC_FINISH(STREAM) 53#endif 54 55/* Define the specific costs for a given cpu */ 56 57struct processor_costs { 58 const int add; /* cost of an add instruction */ 59 const int lea; /* cost of a lea instruction */ 60 const int shift_var; /* variable shift costs */ 61 const int shift_const; /* constant shift costs */ 62 const int mult_init; /* cost of starting a multiply */ 63 const int mult_bit; /* cost of multiply per each bit set */ 64 const int divide; /* cost of a divide/mod */ 65 int movsx; /* The cost of movsx operation. */ 66 int movzx; /* The cost of movzx operation. */ 67 const int large_insn; /* insns larger than this cost more */ 68 const int move_ratio; /* The threshold of number of scalar 69 memory-to-memory move insns. */ 70 const int movzbl_load; /* cost of loading using movzbl */ 71 const int int_load[3]; /* cost of loading integer registers 72 in QImode, HImode and SImode relative 73 to reg-reg move (2). */ 74 const int int_store[3]; /* cost of storing integer register 75 in QImode, HImode and SImode */ 76 const int fp_move; /* cost of reg,reg fld/fst */ 77 const int fp_load[3]; /* cost of loading FP register 78 in SFmode, DFmode and XFmode */ 79 const int fp_store[3]; /* cost of storing FP register 80 in SFmode, DFmode and XFmode */ 81 const int mmx_move; /* cost of moving MMX register. */ 82 const int mmx_load[2]; /* cost of loading MMX register 83 in SImode and DImode */ 84 const int mmx_store[2]; /* cost of storing MMX register 85 in SImode and DImode */ 86 const int sse_move; /* cost of moving SSE register. */ 87 const int sse_load[3]; /* cost of loading SSE register 88 in SImode, DImode and TImode*/ 89 const int sse_store[3]; /* cost of storing SSE register 90 in SImode, DImode and TImode*/ 91 const int mmxsse_to_integer; /* cost of moving mmxsse register to 92 integer and vice versa. */ 93 const int prefetch_block; /* bytes moved to cache for prefetch. */ 94 const int simultaneous_prefetches; /* number of parallel prefetch 95 operations. */ 96}; 97 98extern const struct processor_costs *ix86_cost; 99 100/* Run-time compilation parameters selecting different hardware subsets. */ 101 102extern int target_flags; 103 104/* Macros used in the machine description to test the flags. */ 105 106/* configure can arrange to make this 2, to force a 486. */ 107 108#ifndef TARGET_CPU_DEFAULT 109#define TARGET_CPU_DEFAULT 0 110#endif 111 112/* Masks for the -m switches */ 113#define MASK_80387 0x00000001 /* Hardware floating point */ 114#define MASK_RTD 0x00000002 /* Use ret that pops args */ 115#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ 116#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ 117#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ 118#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ 119#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ 120#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ 121#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ 122#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ 123#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ 124#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ 125#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ 126#define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000 127#define MASK_MMX 0x00004000 /* Support MMX regs/builtins */ 128#define MASK_MMX_SET 0x00008000 129#define MASK_SSE 0x00010000 /* Support SSE regs/builtins */ 130#define MASK_SSE_SET 0x00020000 131#define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */ 132#define MASK_SSE2_SET 0x00080000 133#define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */ 134#define MASK_3DNOW_SET 0x00200000 135#define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */ 136#define MASK_3DNOW_A_SET 0x00800000 137#define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */ 138#define MASK_64BIT 0x02000000 /* Produce 64bit code */ 139/* ... overlap with subtarget options starts by 0x04000000. */ 140#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ 141#define MASK_NO_ALIGN_LONG_STRINGS 0x08000000 /* Do not align long strings specially */ 142 143/* Use the floating point instructions */ 144#define TARGET_80387 (target_flags & MASK_80387) 145 146/* Compile using ret insn that pops args. 147 This will not work unless you use prototypes at least 148 for all functions that can take varying numbers of args. */ 149#define TARGET_RTD (target_flags & MASK_RTD) 150 151/* Align doubles to a two word boundary. This breaks compatibility with 152 the published ABI's for structures containing doubles, but produces 153 faster code on the pentium. */ 154#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) 155 156/* Use push instructions to save outgoing args. */ 157#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) 158 159/* Accumulate stack adjustments to prologue/epilogue. */ 160#define TARGET_ACCUMULATE_OUTGOING_ARGS \ 161 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) 162 163/* Put uninitialized locals into bss, not data. 164 Meaningful only on svr3. */ 165#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) 166 167/* Use IEEE floating point comparisons. These handle correctly the cases 168 where the result of a comparison is unordered. Normally SIGFPE is 169 generated in such cases, in which case this isn't needed. */ 170#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) 171 172/* Functions that return a floating point value may return that value 173 in the 387 FPU or in 386 integer registers. If set, this flag causes 174 the 387 to be used, which is compatible with most calling conventions. */ 175#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) 176 177/* Long double is 128bit instead of 96bit, even when only 80bits are used. 178 This mode wastes cache, but avoid misaligned data accesses and simplifies 179 address calculations. */ 180#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) 181 182/* Disable generation of FP sin, cos and sqrt operations for 387. 183 This is because FreeBSD lacks these in the math-emulator-code */ 184#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) 185 186/* Don't create frame pointers for leaf functions */ 187#define TARGET_OMIT_LEAF_FRAME_POINTER \ 188 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) 189 190/* Debug GO_IF_LEGITIMATE_ADDRESS */ 191#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) 192 193/* Debug FUNCTION_ARG macros */ 194#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) 195 196/* 64bit Sledgehammer mode */ 197#ifdef TARGET_BI_ARCH 198#define TARGET_64BIT (target_flags & MASK_64BIT) 199#else 200#ifdef TARGET_64BIT_DEFAULT 201#define TARGET_64BIT 1 202#else 203#define TARGET_64BIT 0 204#endif 205#endif 206 207#define TARGET_386 (ix86_cpu == PROCESSOR_I386) 208#define TARGET_486 (ix86_cpu == PROCESSOR_I486) 209#define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) 210#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) 211#define TARGET_K6 (ix86_cpu == PROCESSOR_K6) 212#define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) 213#define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4) 214 215#define CPUMASK (1 << ix86_cpu) 216extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 217extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 218extern const int x86_branch_hints, x86_unroll_strlen; 219extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 220extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; 221extern const int x86_use_cltd, x86_read_modify_write; 222extern const int x86_read_modify, x86_split_long_moves; 223extern const int x86_promote_QImode, x86_single_stringop; 224extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 225extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 226extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 227extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 228extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 229extern const int x86_epilogue_using_move, x86_decompose_lea; 230extern const int x86_arch_always_fancy_math_387; 231extern int x86_prefetch_sse; 232 233#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) 234#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) 235#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) 236#define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) 237#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) 238/* For sane SSE instruction set generation we need fcomi instruction. It is 239 safe to enable all CMOVE instructions. */ 240#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 241#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) 242#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK) 243#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) 244#define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT) 245#define TARGET_MOVX (x86_movx & CPUMASK) 246#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) 247#define TARGET_USE_LOOP (x86_use_loop & CPUMASK) 248#define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) 249#define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) 250#define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) 251#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) 252#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) 253#define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) 254#define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) 255#define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) 256#define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) 257#define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) 258#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) 259#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) 260#define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK) 261#define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK) 262#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK) 263#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK) 264#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK) 265#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK) 266#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK) 267#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK) 268#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK) 269#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK) 270#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 271 272#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) 273 274#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) 275#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) 276 277#define ASSEMBLER_DIALECT (ix86_asm_dialect) 278 279#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0) 280#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) 281#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 282#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 283 && (ix86_fpmath & FPMATH_387)) 284#define TARGET_MMX ((target_flags & MASK_MMX) != 0) 285#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) 286#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) 287 288#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) 289 290#define TARGET_NO_ALIGN_LONG_STRINGS (target_flags & MASK_NO_ALIGN_LONG_STRINGS) 291 292/* WARNING: Do not mark empty strings for translation, as calling 293 gettext on an empty string does NOT return an empty 294 string. */ 295 296 297#define TARGET_SWITCHES \ 298{ { "80387", MASK_80387, N_("Use hardware fp") }, \ 299 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ 300 { "hard-float", MASK_80387, N_("Use hardware fp") }, \ 301 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ 302 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ 303 { "386", 0, "" /*Deprecated.*/}, \ 304 { "486", 0, "" /*Deprecated.*/}, \ 305 { "pentium", 0, "" /*Deprecated.*/}, \ 306 { "pentiumpro", 0, "" /*Deprecated.*/}, \ 307 { "intel-syntax", 0, "" /*Deprecated.*/}, \ 308 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ 309 { "rtd", MASK_RTD, \ 310 N_("Alternate calling convention") }, \ 311 { "no-rtd", -MASK_RTD, \ 312 N_("Use normal calling convention") }, \ 313 { "align-double", MASK_ALIGN_DOUBLE, \ 314 N_("Align some doubles on dword boundary") }, \ 315 { "no-align-double", -MASK_ALIGN_DOUBLE, \ 316 N_("Align doubles on word boundary") }, \ 317 { "svr3-shlib", MASK_SVR3_SHLIB, \ 318 N_("Uninitialized locals in .bss") }, \ 319 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ 320 N_("Uninitialized locals in .data") }, \ 321 { "ieee-fp", MASK_IEEE_FP, \ 322 N_("Use IEEE math for fp comparisons") }, \ 323 { "no-ieee-fp", -MASK_IEEE_FP, \ 324 N_("Do not use IEEE math for fp comparisons") }, \ 325 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ 326 N_("Return values of functions in FPU registers") }, \ 327 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ 328 N_("Do not return values of functions in FPU registers")}, \ 329 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ 330 N_("Do not generate sin, cos, sqrt for FPU") }, \ 331 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ 332 N_("Generate sin, cos, sqrt for FPU")}, \ 333 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ 334 N_("Omit the frame pointer in leaf functions") }, \ 335 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ 336 { "stack-arg-probe", MASK_STACK_PROBE, \ 337 N_("Enable stack probing") }, \ 338 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ 339 { "windows", 0, 0 /* undocumented */ }, \ 340 { "dll", 0, 0 /* undocumented */ }, \ 341 { "align-stringops", -MASK_NO_ALIGN_STROPS, \ 342 N_("Align destination of the string operations") }, \ 343 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ 344 N_("Do not align destination of the string operations") }, \ 345 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ 346 N_("Inline all known string operations") }, \ 347 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ 348 N_("Do not inline all known string operations") }, \ 349 { "push-args", -MASK_NO_PUSH_ARGS, \ 350 N_("Use push instructions to save outgoing arguments") }, \ 351 { "no-push-args", MASK_NO_PUSH_ARGS, \ 352 N_("Do not use push instructions to save outgoing arguments") }, \ 353 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \ 354 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \ 355 N_("Use push instructions to save outgoing arguments") }, \ 356 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \ 357 N_("Do not use push instructions to save outgoing arguments") }, \ 358 { "mmx", MASK_MMX | MASK_MMX_SET, \ 359 N_("Support MMX built-in functions") }, \ 360 { "no-mmx", -MASK_MMX, \ 361 N_("Do not support MMX built-in functions") }, \ 362 { "no-mmx", MASK_MMX_SET, "" }, \ 363 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \ 364 N_("Support 3DNow! built-in functions") }, \ 365 { "no-3dnow", -MASK_3DNOW, "" }, \ 366 { "no-3dnow", MASK_3DNOW_SET, \ 367 N_("Do not support 3DNow! built-in functions") }, \ 368 { "sse", MASK_SSE | MASK_SSE_SET, \ 369 N_("Support MMX and SSE built-in functions and code generation") }, \ 370 { "no-sse", -MASK_SSE, "" }, \ 371 { "no-sse", MASK_SSE_SET, \ 372 N_("Do not support MMX and SSE built-in functions and code generation") },\ 373 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \ 374 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ 375 { "no-sse2", -MASK_SSE2, "" }, \ 376 { "no-sse2", MASK_SSE2_SET, \ 377 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ 378 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ 379 N_("sizeof(long double) is 16") }, \ 380 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ 381 N_("sizeof(long double) is 12") }, \ 382 { "64", MASK_64BIT, \ 383 N_("Generate 64bit x86-64 code") }, \ 384 { "32", -MASK_64BIT, \ 385 N_("Generate 32bit i386 code") }, \ 386 { "red-zone", -MASK_NO_RED_ZONE, \ 387 N_("Use red-zone in the x86-64 code") }, \ 388 { "no-red-zone", MASK_NO_RED_ZONE, \ 389 N_("Do not use red-zone in the x86-64 code") }, \ 390 { "no-align-long-strings", MASK_NO_ALIGN_LONG_STRINGS, \ 391 N_("Do not align long strings specially") }, \ 392 { "align-long-strings", -MASK_NO_ALIGN_LONG_STRINGS, \ 393 N_("Align strings longer than 30 on a 32-byte boundary") }, \ 394 SUBTARGET_SWITCHES \ 395 { "", TARGET_DEFAULT, 0 }} 396 397#ifdef TARGET_64BIT_DEFAULT 398#define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT) 399#else 400#define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT 401#endif 402 403/* Which processor to schedule for. The cpu attribute defines a list that 404 mirrors this list, so changes to i386.md must be made at the same time. */ 405 406enum processor_type 407{ 408 PROCESSOR_I386, /* 80386 */ 409 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 410 PROCESSOR_PENTIUM, 411 PROCESSOR_PENTIUMPRO, 412 PROCESSOR_K6, 413 PROCESSOR_ATHLON, 414 PROCESSOR_PENTIUM4, 415 PROCESSOR_max 416}; 417enum fpmath_unit 418{ 419 FPMATH_387 = 1, 420 FPMATH_SSE = 2 421}; 422 423extern enum processor_type ix86_cpu; 424extern enum fpmath_unit ix86_fpmath; 425 426extern int ix86_arch; 427 428/* This macro is similar to `TARGET_SWITCHES' but defines names of 429 command options that have values. Its definition is an 430 initializer with a subgrouping for each command option. 431 432 Each subgrouping contains a string constant, that defines the 433 fixed part of the option name, and the address of a variable. The 434 variable, type `char *', is set to the variable part of the given 435 option if the fixed part matches. The actual option name is made 436 by appending `-m' to the specified name. */ 437#define TARGET_OPTIONS \ 438{ { "cpu=", &ix86_cpu_string, \ 439 N_("Schedule code for given CPU")}, \ 440 { "fpmath=", &ix86_fpmath_string, \ 441 N_("Generate floating point mathematics using given instruction set")},\ 442 { "arch=", &ix86_arch_string, \ 443 N_("Generate code for given CPU")}, \ 444 { "regparm=", &ix86_regparm_string, \ 445 N_("Number of registers used to pass integer arguments") }, \ 446 { "align-loops=", &ix86_align_loops_string, \ 447 N_("Loop code aligned to this power of 2") }, \ 448 { "align-jumps=", &ix86_align_jumps_string, \ 449 N_("Jump targets are aligned to this power of 2") }, \ 450 { "align-functions=", &ix86_align_funcs_string, \ 451 N_("Function starts are aligned to this power of 2") }, \ 452 { "preferred-stack-boundary=", \ 453 &ix86_preferred_stack_boundary_string, \ 454 N_("Attempt to keep stack aligned to this power of 2") }, \ 455 { "branch-cost=", &ix86_branch_cost_string, \ 456 N_("Branches are this expensive (1-5, arbitrary units)") }, \ 457 { "cmodel=", &ix86_cmodel_string, \ 458 N_("Use given x86-64 code model") }, \ 459 { "debug-arg", &ix86_debug_arg_string, \ 460 "" /* Undocumented. */ }, \ 461 { "debug-addr", &ix86_debug_addr_string, \ 462 "" /* Undocumented. */ }, \ 463 { "asm=", &ix86_asm_string, \ 464 N_("Use given assembler dialect") }, \ 465 SUBTARGET_OPTIONS \ 466} 467 468/* Sometimes certain combinations of command options do not make 469 sense on a particular target machine. You can define a macro 470 `OVERRIDE_OPTIONS' to take account of this. This macro, if 471 defined, is executed once just after all the command options have 472 been parsed. 473 474 Don't use this macro to turn on various extra optimizations for 475 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 476 477#define OVERRIDE_OPTIONS override_options () 478 479/* These are meant to be redefined in the host dependent files */ 480#define SUBTARGET_SWITCHES 481#define SUBTARGET_OPTIONS 482 483/* Define this to change the optimizations performed by default. */ 484#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 485 optimization_options ((LEVEL), (SIZE)) 486 487/* Specs for the compiler proper */ 488 489#ifndef CC1_CPU_SPEC 490#define CC1_CPU_SPEC "\ 491%{!mcpu*: \ 492%{m386:-mcpu=i386 \ 493%n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \ 494%{m486:-mcpu=i486 \ 495%n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \ 496%{mpentium:-mcpu=pentium \ 497%n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \ 498%{mpentiumpro:-mcpu=pentiumpro \ 499%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \ 500%{mintel-syntax:-masm=intel \ 501%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 502%{mno-intel-syntax:-masm=att \ 503%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 504#endif 505 506#define TARGET_CPU_DEFAULT_i386 0 507#define TARGET_CPU_DEFAULT_i486 1 508#define TARGET_CPU_DEFAULT_pentium 2 509#define TARGET_CPU_DEFAULT_pentium_mmx 3 510#define TARGET_CPU_DEFAULT_pentiumpro 4 511#define TARGET_CPU_DEFAULT_pentium2 5 512#define TARGET_CPU_DEFAULT_pentium3 6 513#define TARGET_CPU_DEFAULT_pentium4 7 514#define TARGET_CPU_DEFAULT_k6 8 515#define TARGET_CPU_DEFAULT_k6_2 9 516#define TARGET_CPU_DEFAULT_k6_3 10 517#define TARGET_CPU_DEFAULT_athlon 11 518#define TARGET_CPU_DEFAULT_athlon_sse 12 519 520#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 521 "pentiumpro", "pentium2", "pentium3", \ 522 "pentium4", "k6", "k6-2", "k6-3",\ 523 "athlon", "athlon-4"} 524#ifndef CPP_CPU_DEFAULT_SPEC 525#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486 526#define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__" 527#endif 528#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium 529#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__" 530#endif 531#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx 532#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__" 533#endif 534#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro 535#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__" 536#endif 537#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2 538#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 539-D__tune_pentium2__" 540#endif 541#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3 542#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 543-D__tune_pentium2__ -D__tune_pentium3__" 544#endif 545#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4 546#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__" 547#endif 548#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6 549#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__" 550#endif 551#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2 552#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__" 553#endif 554#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3 555#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__" 556#endif 557#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon 558#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__" 559#endif 560#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse 561#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__" 562#endif 563#ifndef CPP_CPU_DEFAULT_SPEC 564#define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__" 565#endif 566#endif /* CPP_CPU_DEFAULT_SPEC */ 567 568#ifdef TARGET_BI_ARCH 569#define NO_BUILTIN_SIZE_TYPE 570#define NO_BUILTIN_PTRDIFF_TYPE 571#endif 572 573#ifdef NO_BUILTIN_SIZE_TYPE 574#define CPP_CPU32_SIZE_TYPE_SPEC \ 575 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int" 576#define CPP_CPU64_SIZE_TYPE_SPEC \ 577 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int" 578#else 579#define CPP_CPU32_SIZE_TYPE_SPEC "" 580#define CPP_CPU64_SIZE_TYPE_SPEC "" 581#endif 582 583#define CPP_CPU32_SPEC \ 584 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \ 585-D__i386__ %(cpp_cpu32sizet)" 586 587#define CPP_CPU64_SPEC \ 588 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)" 589 590#define CPP_CPUCOMMON_SPEC "\ 591%{march=i386:%{!mcpu*:-D__tune_i386__ }}\ 592%{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\ 593%{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 594 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\ 595%{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 596 -D__pentium__mmx__ \ 597 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\ 598%{march=pentiumpro|march=i686|march=pentium2|march=pentium3:-D__i686 -D__i686__ \ 599 -D__pentiumpro -D__pentiumpro__ \ 600 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\ 601%{march=march=pentium2|march=pentium3: -D__pentium2 -D__pentium2__\ 602 %{!mcpu*:-D__tune_pentium2__ }}\ 603%{march=pentium3: -D__pentium3 -D__pentium3__\ 604 %{!mcpu*:-D__tune_pentium3__ }}\ 605%{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\ 606%{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \ 607 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\ 608%{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \ 609 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\ 610%{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \ 611 %{!mcpu*:-D__tune_athlon__ }}\ 612%{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \ 613 -D__athlon_sse__ \ 614 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\ 615%{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\ 616%{m386|mcpu=i386:-D__tune_i386__ }\ 617%{m486|mcpu=i486:-D__tune_i486__ }\ 618%{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\ 619%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|mcpu=pentium2|mcpu=pentium3:-D__tune_i686__ \ 620-D__tune_pentiumpro__ }\ 621%{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\ 622%{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 623-D__tune_athlon__ }\ 624%{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 625-D__tune_athlon_sse__ }\ 626%{mcpu=pentium4:-D__tune_pentium4__ }\ 627%{march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4|msse|msse2:\ 628-D__SSE__ }\ 629%{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\ 630|march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 631|march=athlon-mp|march=pentium2|march=pentium3|march=pentium4|mmx|msse|m3dnow: -D__MMX__ }\ 632%{march=k6-2|march=k6-3\ 633|march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 634|march=athlon-mp|m3dnow: -D__3dNOW__ }\ 635%{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 636|march=athlon-mp: -D__3dNOW_A__ }\ 637%{march=pentium4|msse2: -D__SSE2__ }\ 638%{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}" 639 640#ifndef CPP_CPU_SPEC 641#ifdef TARGET_BI_ARCH 642#ifdef TARGET_64BIT_DEFAULT 643#define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)" 644#else 645#define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)" 646#endif 647#else 648#ifdef TARGET_64BIT_DEFAULT 649#define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)" 650#else 651#define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)" 652#endif 653#endif 654#endif 655 656#ifndef CC1_SPEC 657#define CC1_SPEC "%(cc1_cpu) " 658#endif 659 660/* This macro defines names of additional specifications to put in the 661 specs that can be used in various specifications like CC1_SPEC. Its 662 definition is an initializer with a subgrouping for each command option. 663 664 Each subgrouping contains a string constant, that defines the 665 specification name, and a string constant that used by the GNU CC driver 666 program. 667 668 Do not define this macro if it does not need to do anything. */ 669 670#ifndef SUBTARGET_EXTRA_SPECS 671#define SUBTARGET_EXTRA_SPECS 672#endif 673 674#define EXTRA_SPECS \ 675 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 676 { "cpp_cpu", CPP_CPU_SPEC }, \ 677 { "cpp_cpu32", CPP_CPU32_SPEC }, \ 678 { "cpp_cpu64", CPP_CPU64_SPEC }, \ 679 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \ 680 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \ 681 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \ 682 { "cc1_cpu", CC1_CPU_SPEC }, \ 683 SUBTARGET_EXTRA_SPECS 684 685/* target machine storage layout */ 686 687/* Define for XFmode or TFmode extended real floating point support. 688 This will automatically cause REAL_ARITHMETIC to be defined. 689 690 The XFmode is specified by i386 ABI, while TFmode may be faster 691 due to alignment and simplifications in the address calculations. 692 */ 693#define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96) 694#define MAX_LONG_DOUBLE_TYPE_SIZE 128 695#ifdef __x86_64__ 696#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 697#else 698#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 699#endif 700/* Tell real.c that this is the 80-bit Intel extended float format 701 packaged in a 128-bit or 96bit entity. */ 702#define INTEL_EXTENDED_IEEE_FORMAT 1 703 704 705#define SHORT_TYPE_SIZE 16 706#define INT_TYPE_SIZE 32 707#define FLOAT_TYPE_SIZE 32 708#ifndef LONG_TYPE_SIZE 709#define LONG_TYPE_SIZE BITS_PER_WORD 710#endif 711#define MAX_WCHAR_TYPE_SIZE 32 712#define DOUBLE_TYPE_SIZE 64 713#define LONG_LONG_TYPE_SIZE 64 714 715#if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT) 716#define MAX_BITS_PER_WORD 64 717#define MAX_LONG_TYPE_SIZE 64 718#else 719#define MAX_BITS_PER_WORD 32 720#define MAX_LONG_TYPE_SIZE 32 721#endif 722 723/* Define if you don't want extended real, but do want to use the 724 software floating point emulator for REAL_ARITHMETIC and 725 decimal <-> binary conversion. */ 726/* #define REAL_ARITHMETIC */ 727 728/* Define this if most significant byte of a word is the lowest numbered. */ 729/* That is true on the 80386. */ 730 731#define BITS_BIG_ENDIAN 0 732 733/* Define this if most significant byte of a word is the lowest numbered. */ 734/* That is not true on the 80386. */ 735#define BYTES_BIG_ENDIAN 0 736 737/* Define this if most significant word of a multiword number is the lowest 738 numbered. */ 739/* Not true for 80386 */ 740#define WORDS_BIG_ENDIAN 0 741 742/* number of bits in an addressable storage unit */ 743#define BITS_PER_UNIT 8 744 745/* Width in bits of a "word", which is the contents of a machine register. 746 Note that this is not necessarily the width of data type `int'; 747 if using 16-bit ints on a 80386, this would still be 32. 748 But on a machine with 16-bit registers, this would be 16. */ 749#define BITS_PER_WORD (TARGET_64BIT ? 64 : 32) 750 751/* Width of a word, in units (bytes). */ 752#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 753#define MIN_UNITS_PER_WORD 4 754 755/* Width in bits of a pointer. 756 See also the macro `Pmode' defined below. */ 757#define POINTER_SIZE BITS_PER_WORD 758 759/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 760#define PARM_BOUNDARY BITS_PER_WORD 761 762/* Boundary (in *bits*) on which stack pointer should be aligned. */ 763#define STACK_BOUNDARY BITS_PER_WORD 764 765/* Boundary (in *bits*) on which the stack pointer preferrs to be 766 aligned; the compiler cannot rely on having this alignment. */ 767#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 768 769/* As of July 2001, many runtimes to not align the stack properly when 770 entering main. This causes expand_main_function to forcably align 771 the stack, which results in aligned frames for functions called from 772 main, though it does nothing for the alignment of main itself. */ 773#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 774 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 775 776/* Minimum allocation boundary for the code of a function. */ 777#define FUNCTION_BOUNDARY 8 778 779/* C++ stores the virtual bit in the lowest bit of function pointers. */ 780#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 781 782/* Alignment of field after `int : 0' in a structure. */ 783 784#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 785 786/* Minimum size in bits of the largest boundary to which any 787 and all fundamental data types supported by the hardware 788 might need to be aligned. No data type wants to be aligned 789 rounder than this. 790 791 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary 792 and Pentium Pro XFmode values at 128 bit boundaries. */ 793 794#define BIGGEST_ALIGNMENT 128 795 796/* Decide whether a variable of mode MODE must be 128 bit aligned. */ 797#define ALIGN_MODE_128(MODE) \ 798 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \ 799 || (MODE) == V4SFmode || (MODE) == V4SImode) 800 801/* The published ABIs say that doubles should be aligned on word 802 boundaries, so lower the aligment for structure fields unless 803 -malign-double is set. */ 804 805/* ??? Blah -- this macro is used directly by libobjc. Since it 806 supports no vector modes, cut out the complexity and fall back 807 on BIGGEST_FIELD_ALIGNMENT. */ 808#ifdef IN_TARGET_LIBS 809#define BIGGEST_FIELD_ALIGNMENT 32 810#else 811#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 812 x86_field_alignment (FIELD, COMPUTED) 813#endif 814 815/* If defined, a C expression to compute the alignment given to a 816 constant that is being placed in memory. EXP is the constant 817 and ALIGN is the alignment that the object would ordinarily have. 818 The value of this macro is used instead of that alignment to align 819 the object. 820 821 If this macro is not defined, then ALIGN is used. 822 823 The typical use of this macro is to increase alignment for string 824 constants to be word aligned so that `strcpy' calls that copy 825 constants can be done inline. */ 826 827#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 828 829/* If defined, a C expression to compute the alignment for a static 830 variable. TYPE is the data type, and ALIGN is the alignment that 831 the object would ordinarily have. The value of this macro is used 832 instead of that alignment to align the object. 833 834 If this macro is not defined, then ALIGN is used. 835 836 One use of this macro is to increase alignment of medium-size 837 data to make it all fit in fewer cache lines. Another is to 838 cause character arrays to be word-aligned so that `strcpy' calls 839 that copy constants to character arrays can be done inline. */ 840 841#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 842 843/* If defined, a C expression to compute the alignment for a local 844 variable. TYPE is the data type, and ALIGN is the alignment that 845 the object would ordinarily have. The value of this macro is used 846 instead of that alignment to align the object. 847 848 If this macro is not defined, then ALIGN is used. 849 850 One use of this macro is to increase alignment of medium-size 851 data to make it all fit in fewer cache lines. */ 852 853#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 854 855/* If defined, a C expression that gives the alignment boundary, in 856 bits, of an argument with the specified mode and type. If it is 857 not defined, `PARM_BOUNDARY' is used for all arguments. */ 858 859#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 860 ix86_function_arg_boundary ((MODE), (TYPE)) 861 862/* Set this non-zero if move instructions will actually fail to work 863 when given unaligned data. */ 864#define STRICT_ALIGNMENT 0 865 866/* If bit field type is int, don't let it cross an int, 867 and give entire struct the alignment of an int. */ 868/* Required on the 386 since it doesn't have bitfield insns. */ 869#define PCC_BITFIELD_TYPE_MATTERS 1 870 871/* Standard register usage. */ 872 873/* This processor has special stack-like registers. See reg-stack.c 874 for details. */ 875 876#define STACK_REGS 877#define IS_STACK_MODE(MODE) \ 878 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ 879 || (MODE) == TFmode) 880 881/* Number of actual hardware registers. 882 The hardware registers are assigned numbers for the compiler 883 from 0 to just below FIRST_PSEUDO_REGISTER. 884 All registers that the compiler knows about must be given numbers, 885 even those that are not normally considered general registers. 886 887 In the 80386 we give the 8 general purpose registers the numbers 0-7. 888 We number the floating point registers 8-15. 889 Note that registers 0-7 can be accessed as a short or int, 890 while only 0-3 may be used with byte `mov' instructions. 891 892 Reg 16 does not correspond to any hardware register, but instead 893 appears in the RTL as an argument pointer prior to reload, and is 894 eliminated during reloading in favor of either the stack or frame 895 pointer. */ 896 897#define FIRST_PSEUDO_REGISTER 53 898 899/* Number of hardware registers that go into the DWARF-2 unwind info. 900 If not defined, equals FIRST_PSEUDO_REGISTER. */ 901 902#define DWARF_FRAME_REGISTERS 17 903 904/* 1 for registers that have pervasive standard uses 905 and are not available for the register allocator. 906 On the 80386, the stack pointer is such, as is the arg pointer. 907 908 The value is an mask - bit 1 is set for fixed registers 909 for 32bit target, while 2 is set for fixed registers for 64bit. 910 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 911 */ 912#define FIXED_REGISTERS \ 913/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 914{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ 915/*arg,flags,fpsr,dir,frame*/ \ 916 3, 3, 3, 3, 3, \ 917/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 918 0, 0, 0, 0, 0, 0, 0, 0, \ 919/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 920 0, 0, 0, 0, 0, 0, 0, 0, \ 921/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 922 1, 1, 1, 1, 1, 1, 1, 1, \ 923/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 924 1, 1, 1, 1, 1, 1, 1, 1} 925 926 927/* 1 for registers not available across function calls. 928 These must include the FIXED_REGISTERS and also any 929 registers that can be used without being saved. 930 The latter must include the registers where values are returned 931 and the register where structure-value addresses are passed. 932 Aside from that, you can include as many other registers as you like. 933 934 The value is an mask - bit 1 is set for call used 935 for 32bit target, while 2 is set for call used for 64bit. 936 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 937*/ 938#define CALL_USED_REGISTERS \ 939/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 940{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 941/*arg,flags,fpsr,dir,frame*/ \ 942 3, 3, 3, 3, 3, \ 943/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 944 3, 3, 3, 3, 3, 3, 3, 3, \ 945/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 946 3, 3, 3, 3, 3, 3, 3, 3, \ 947/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 948 3, 3, 3, 3, 1, 1, 1, 1, \ 949/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 950 3, 3, 3, 3, 3, 3, 3, 3} \ 951 952/* Order in which to allocate registers. Each register must be 953 listed once, even those in FIXED_REGISTERS. List frame pointer 954 late and fixed registers last. Note that, in general, we prefer 955 registers listed in CALL_USED_REGISTERS, keeping the others 956 available for storage of persistent values. 957 958 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 959 so this is just empty initializer for array. */ 960 961#define REG_ALLOC_ORDER \ 962{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 963 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 964 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 965 48, 49, 50, 51, 52 } 966 967/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 968 to be rearranged based on a particular function. When using sse math, 969 we want to allocase SSE before x87 registers and vice vera. */ 970 971#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 972 973 974/* Macro to conditionally modify fixed_regs/call_used_regs. */ 975#define CONDITIONAL_REGISTER_USAGE \ 976do { \ 977 int i; \ 978 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 979 { \ 980 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ 981 call_used_regs[i] = (call_used_regs[i] \ 982 & (TARGET_64BIT ? 2 : 1)) != 0; \ 983 } \ 984 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 985 { \ 986 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 987 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 988 } \ 989 if (! TARGET_MMX) \ 990 { \ 991 int i; \ 992 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 993 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 994 fixed_regs[i] = call_used_regs[i] = 1; \ 995 } \ 996 if (! TARGET_SSE) \ 997 { \ 998 int i; \ 999 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1000 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 1001 fixed_regs[i] = call_used_regs[i] = 1; \ 1002 } \ 1003 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 1004 { \ 1005 int i; \ 1006 HARD_REG_SET x; \ 1007 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 1008 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1009 if (TEST_HARD_REG_BIT (x, i)) \ 1010 fixed_regs[i] = call_used_regs[i] = 1; \ 1011 } \ 1012 } while (0) 1013 1014/* Return number of consecutive hard regs needed starting at reg REGNO 1015 to hold something of mode MODE. 1016 This is ordinarily the length in words of a value of mode MODE 1017 but can be less for certain modes in special long registers. 1018 1019 Actually there are no two word move instructions for consecutive 1020 registers. And only registers 0-3 may have mov byte instructions 1021 applied to them. 1022 */ 1023 1024#define HARD_REGNO_NREGS(REGNO, MODE) \ 1025 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1026 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1027 : ((MODE) == TFmode \ 1028 ? (TARGET_64BIT ? 2 : 3) \ 1029 : (MODE) == TCmode \ 1030 ? (TARGET_64BIT ? 4 : 6) \ 1031 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1032 1033#define VALID_SSE_REG_MODE(MODE) \ 1034 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1035 || (MODE) == SFmode \ 1036 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) 1037 1038#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1039 ((MODE) == V2SFmode || (MODE) == SFmode) 1040 1041#define VALID_MMX_REG_MODE(MODE) \ 1042 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 1043 || (MODE) == V2SImode || (MODE) == SImode) 1044 1045#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1046 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ 1047 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ 1048 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) 1049 1050#define VALID_FP_MODE_P(MODE) \ 1051 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 1052 || (!TARGET_64BIT && (MODE) == XFmode) \ 1053 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \ 1054 || (!TARGET_64BIT && (MODE) == XCmode)) 1055 1056#define VALID_INT_MODE_P(MODE) \ 1057 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1058 || (MODE) == DImode \ 1059 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1060 || (MODE) == CDImode \ 1061 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) 1062 1063/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1064 1065#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1066 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1067 1068/* Value is 1 if it is a good idea to tie two pseudo registers 1069 when one has mode MODE1 and one has mode MODE2. 1070 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1071 for any hard reg, then this must be 0 for correct output. */ 1072 1073#define MODES_TIEABLE_P(MODE1, MODE2) \ 1074 ((MODE1) == (MODE2) \ 1075 || (((MODE1) == HImode || (MODE1) == SImode \ 1076 || ((MODE1) == QImode \ 1077 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1078 || ((MODE1) == DImode && TARGET_64BIT)) \ 1079 && ((MODE2) == HImode || (MODE2) == SImode \ 1080 || ((MODE1) == QImode \ 1081 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1082 || ((MODE2) == DImode && TARGET_64BIT)))) 1083 1084 1085/* Specify the modes required to caller save a given hard regno. 1086 We do this on i386 to prevent flags from being saved at all. 1087 1088 Kill any attempts to combine saving of modes. */ 1089 1090#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1091 (CC_REGNO_P (REGNO) ? VOIDmode \ 1092 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1093 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \ 1094 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1095 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 1096 : (MODE)) 1097/* Specify the registers used for certain standard purposes. 1098 The values of these macros are register numbers. */ 1099 1100/* on the 386 the pc register is %eip, and is not usable as a general 1101 register. The ordinary mov instructions won't work */ 1102/* #define PC_REGNUM */ 1103 1104/* Register to use for pushing function arguments. */ 1105#define STACK_POINTER_REGNUM 7 1106 1107/* Base register for access to local variables of the function. */ 1108#define HARD_FRAME_POINTER_REGNUM 6 1109 1110/* Base register for access to local variables of the function. */ 1111#define FRAME_POINTER_REGNUM 20 1112 1113/* First floating point reg */ 1114#define FIRST_FLOAT_REG 8 1115 1116/* First & last stack-like regs */ 1117#define FIRST_STACK_REG FIRST_FLOAT_REG 1118#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1119 1120#define FLAGS_REG 17 1121#define FPSR_REG 18 1122#define DIRFLAG_REG 19 1123 1124#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1125#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1126 1127#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1128#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1129 1130#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1131#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1132 1133#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1134#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1135 1136/* Value should be nonzero if functions must have frame pointers. 1137 Zero means the frame pointer need not be set up (and parms 1138 may be accessed via the stack pointer) in functions that seem suitable. 1139 This is computed in `reload', in reload1.c. */ 1140#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1141 1142/* Override this in other tm.h files to cope with various OS losage 1143 requiring a frame pointer. */ 1144#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1145#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1146#endif 1147 1148/* Make sure we can access arbitrary call frames. */ 1149#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1150 1151/* Base register for access to arguments of the function. */ 1152#define ARG_POINTER_REGNUM 16 1153 1154/* Register in which static-chain is passed to a function. 1155 We do use ECX as static chain register for 32 bit ABI. On the 1156 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1157#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1158 1159/* Register to hold the addressing base for position independent 1160 code access to data items. We don't use PIC pointer for 64bit 1161 mode. Define the regnum to dummy value to prevent gcc from 1162 pessimizing code dealing with EBX. */ 1163#define PIC_OFFSET_TABLE_REGNUM \ 1164 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM : 3) 1165 1166/* Register in which address to store a structure value 1167 arrives in the function. On the 386, the prologue 1168 copies this from the stack to register %eax. */ 1169#define STRUCT_VALUE_INCOMING 0 1170 1171/* Place in which caller passes the structure value address. 1172 0 means push the value on the stack like an argument. */ 1173#define STRUCT_VALUE 0 1174 1175/* A C expression which can inhibit the returning of certain function 1176 values in registers, based on the type of value. A nonzero value 1177 says to return the function value in memory, just as large 1178 structures are always returned. Here TYPE will be a C expression 1179 of type `tree', representing the data type of the value. 1180 1181 Note that values of mode `BLKmode' must be explicitly handled by 1182 this macro. Also, the option `-fpcc-struct-return' takes effect 1183 regardless of this macro. On most systems, it is possible to 1184 leave the macro undefined; this causes a default definition to be 1185 used, whose value is the constant 1 for `BLKmode' values, and 0 1186 otherwise. 1187 1188 Do not use this macro to indicate that structures and unions 1189 should always be returned in memory. You should instead use 1190 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1191 1192#define RETURN_IN_MEMORY(TYPE) \ 1193 ix86_return_in_memory (TYPE) 1194 1195 1196/* Define the classes of registers for register constraints in the 1197 machine description. Also define ranges of constants. 1198 1199 One of the classes must always be named ALL_REGS and include all hard regs. 1200 If there is more than one class, another class must be named NO_REGS 1201 and contain no registers. 1202 1203 The name GENERAL_REGS must be the name of a class (or an alias for 1204 another name such as ALL_REGS). This is the class of registers 1205 that is allowed by "g" or "r" in a register constraint. 1206 Also, registers outside this class are allocated only when 1207 instructions express preferences for them. 1208 1209 The classes must be numbered in nondecreasing order; that is, 1210 a larger-numbered class must never be contained completely 1211 in a smaller-numbered class. 1212 1213 For any two classes, it is very desirable that there be another 1214 class that represents their union. 1215 1216 It might seem that class BREG is unnecessary, since no useful 386 1217 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1218 and the "b" register constraint is useful in asms for syscalls. 1219 1220 The flags and fpsr registers are in no class. */ 1221 1222enum reg_class 1223{ 1224 NO_REGS, 1225 AREG, DREG, CREG, BREG, SIREG, DIREG, 1226 AD_REGS, /* %eax/%edx for DImode */ 1227 Q_REGS, /* %eax %ebx %ecx %edx */ 1228 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1229 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1230 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1231 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1232 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1233 FLOAT_REGS, 1234 SSE_REGS, 1235 MMX_REGS, 1236 FP_TOP_SSE_REGS, 1237 FP_SECOND_SSE_REGS, 1238 FLOAT_SSE_REGS, 1239 FLOAT_INT_REGS, 1240 INT_SSE_REGS, 1241 FLOAT_INT_SSE_REGS, 1242 ALL_REGS, LIM_REG_CLASSES 1243}; 1244 1245#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1246 1247#define INTEGER_CLASS_P(CLASS) \ 1248 reg_class_subset_p ((CLASS), GENERAL_REGS) 1249#define FLOAT_CLASS_P(CLASS) \ 1250 reg_class_subset_p ((CLASS), FLOAT_REGS) 1251#define SSE_CLASS_P(CLASS) \ 1252 reg_class_subset_p ((CLASS), SSE_REGS) 1253#define MMX_CLASS_P(CLASS) \ 1254 reg_class_subset_p ((CLASS), MMX_REGS) 1255#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1256 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1257#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1258 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1259#define MAYBE_SSE_CLASS_P(CLASS) \ 1260 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1261#define MAYBE_MMX_CLASS_P(CLASS) \ 1262 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1263 1264#define Q_CLASS_P(CLASS) \ 1265 reg_class_subset_p ((CLASS), Q_REGS) 1266 1267/* Give names of register classes as strings for dump file. */ 1268 1269#define REG_CLASS_NAMES \ 1270{ "NO_REGS", \ 1271 "AREG", "DREG", "CREG", "BREG", \ 1272 "SIREG", "DIREG", \ 1273 "AD_REGS", \ 1274 "Q_REGS", "NON_Q_REGS", \ 1275 "INDEX_REGS", \ 1276 "LEGACY_REGS", \ 1277 "GENERAL_REGS", \ 1278 "FP_TOP_REG", "FP_SECOND_REG", \ 1279 "FLOAT_REGS", \ 1280 "SSE_REGS", \ 1281 "MMX_REGS", \ 1282 "FP_TOP_SSE_REGS", \ 1283 "FP_SECOND_SSE_REGS", \ 1284 "FLOAT_SSE_REGS", \ 1285 "FLOAT_INT_REGS", \ 1286 "INT_SSE_REGS", \ 1287 "FLOAT_INT_SSE_REGS", \ 1288 "ALL_REGS" } 1289 1290/* Define which registers fit in which classes. 1291 This is an initializer for a vector of HARD_REG_SET 1292 of length N_REG_CLASSES. */ 1293 1294#define REG_CLASS_CONTENTS \ 1295{ { 0x00, 0x0 }, \ 1296 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1297 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1298 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1299 { 0x03, 0x0 }, /* AD_REGS */ \ 1300 { 0x0f, 0x0 }, /* Q_REGS */ \ 1301 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1302 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1303 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1304 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1305 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1306 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1307{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1308{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1309{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1310{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1311{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1312 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1313{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1314{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1315{ 0xffffffff,0x1fffff } \ 1316} 1317 1318/* The same information, inverted: 1319 Return the class number of the smallest class containing 1320 reg number REGNO. This could be a conditional expression 1321 or could index an array. */ 1322 1323#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1324 1325/* When defined, the compiler allows registers explicitly used in the 1326 rtl to be used as spill registers but prevents the compiler from 1327 extending the lifetime of these registers. */ 1328 1329#define SMALL_REGISTER_CLASSES 1 1330 1331#define QI_REG_P(X) \ 1332 (REG_P (X) && REGNO (X) < 4) 1333 1334#define GENERAL_REGNO_P(N) \ 1335 ((N) < 8 || REX_INT_REGNO_P (N)) 1336 1337#define GENERAL_REG_P(X) \ 1338 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1339 1340#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1341 1342#define NON_QI_REG_P(X) \ 1343 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1344 1345#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1346#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1347 1348#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1349#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1350#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1351#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1352 1353#define SSE_REGNO_P(N) \ 1354 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1355 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1356 1357#define SSE_REGNO(N) \ 1358 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1359#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1360 1361#define SSE_FLOAT_MODE_P(MODE) \ 1362 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1363 1364#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1365#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1366 1367#define STACK_REG_P(XOP) \ 1368 (REG_P (XOP) && \ 1369 REGNO (XOP) >= FIRST_STACK_REG && \ 1370 REGNO (XOP) <= LAST_STACK_REG) 1371 1372#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1373 1374#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1375 1376#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1377#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1378 1379/* Indicate whether hard register numbered REG_NO should be converted 1380 to SSA form. */ 1381#define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \ 1382 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM) 1383 1384/* The class value for index registers, and the one for base regs. */ 1385 1386#define INDEX_REG_CLASS INDEX_REGS 1387#define BASE_REG_CLASS GENERAL_REGS 1388 1389/* Get reg_class from a letter such as appears in the machine description. */ 1390 1391#define REG_CLASS_FROM_LETTER(C) \ 1392 ((C) == 'r' ? GENERAL_REGS : \ 1393 (C) == 'R' ? LEGACY_REGS : \ 1394 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1395 (C) == 'Q' ? Q_REGS : \ 1396 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1397 ? FLOAT_REGS \ 1398 : NO_REGS) : \ 1399 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1400 ? FP_TOP_REG \ 1401 : NO_REGS) : \ 1402 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1403 ? FP_SECOND_REG \ 1404 : NO_REGS) : \ 1405 (C) == 'a' ? AREG : \ 1406 (C) == 'b' ? BREG : \ 1407 (C) == 'c' ? CREG : \ 1408 (C) == 'd' ? DREG : \ 1409 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1410 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1411 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1412 (C) == 'A' ? AD_REGS : \ 1413 (C) == 'D' ? DIREG : \ 1414 (C) == 'S' ? SIREG : NO_REGS) 1415 1416/* The letters I, J, K, L and M in a register constraint string 1417 can be used to stand for particular ranges of immediate operands. 1418 This macro defines what the ranges are. 1419 C is the letter, and VALUE is a constant value. 1420 Return 1 if VALUE is in the range specified by C. 1421 1422 I is for non-DImode shifts. 1423 J is for DImode shifts. 1424 K is for signed imm8 operands. 1425 L is for andsi as zero-extending move. 1426 M is for shifts that can be executed by the "lea" opcode. 1427 N is for immedaite operands for out/in instructions (0-255) 1428 */ 1429 1430#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1431 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1432 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1433 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1434 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1435 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1436 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1437 : 0) 1438 1439/* Similar, but for floating constants, and defining letters G and H. 1440 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1441 TARGET_387 isn't set, because the stack register converter may need to 1442 load 0.0 into the function value register. */ 1443 1444#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1445 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1446 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0)) 1447 1448/* A C expression that defines the optional machine-dependent 1449 constraint letters that can be used to segregate specific types of 1450 operands, usually memory references, for the target machine. Any 1451 letter that is not elsewhere defined and not matched by 1452 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1453 be defined. 1454 1455 If it is required for a particular target machine, it should 1456 return 1 if VALUE corresponds to the operand type represented by 1457 the constraint letter C. If C is not defined as an extra 1458 constraint, the value returned should be 0 regardless of VALUE. */ 1459 1460#define EXTRA_CONSTRAINT(VALUE, C) \ 1461 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \ 1462 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \ 1463 : 0) 1464 1465/* Place additional restrictions on the register class to use when it 1466 is necessary to be able to hold a value of mode MODE in a reload 1467 register for which class CLASS would ordinarily be used. */ 1468 1469#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1470 ((MODE) == QImode && !TARGET_64BIT \ 1471 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1472 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1473 ? Q_REGS : (CLASS)) 1474 1475/* Given an rtx X being reloaded into a reg required to be 1476 in class CLASS, return the class of reg to actually use. 1477 In general this is just CLASS; but on some machines 1478 in some cases it is preferable to use a more restrictive class. 1479 On the 80386 series, we prevent floating constants from being 1480 reloaded into floating registers (since no move-insn can do that) 1481 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1482 1483/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1484 QImode must go into class Q_REGS. 1485 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1486 movdf to do mem-to-mem moves through integer regs. */ 1487 1488#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1489 ix86_preferred_reload_class ((X), (CLASS)) 1490 1491/* If we are copying between general and FP registers, we need a memory 1492 location. The same is true for SSE and MMX registers. */ 1493#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1494 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1495 1496/* QImode spills from non-QI registers need a scratch. This does not 1497 happen often -- the only example so far requires an uninitialized 1498 pseudo. */ 1499 1500#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1501 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1502 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1503 ? Q_REGS : NO_REGS) 1504 1505/* Return the maximum number of consecutive registers 1506 needed to represent mode MODE in a register of class CLASS. */ 1507/* On the 80386, this is the size of MODE in words, 1508 except in the FP regs, where a single reg is always enough. 1509 The TFmodes are really just 80bit values, so we use only 3 registers 1510 to hold them, instead of 4, as the size would suggest. 1511 */ 1512#define CLASS_MAX_NREGS(CLASS, MODE) \ 1513 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1514 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1515 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ 1516 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1517 1518/* A C expression whose value is nonzero if pseudos that have been 1519 assigned to registers of class CLASS would likely be spilled 1520 because registers of CLASS are needed for spill registers. 1521 1522 The default value of this macro returns 1 if CLASS has exactly one 1523 register and zero otherwise. On most machines, this default 1524 should be used. Only define this macro to some other expression 1525 if pseudo allocated by `local-alloc.c' end up in memory because 1526 their hard registers were needed for spill registers. If this 1527 macro returns nonzero for those classes, those pseudos will only 1528 be allocated by `global.c', which knows how to reallocate the 1529 pseudo to another register. If there would not be another 1530 register available for reallocation, you should not change the 1531 definition of this macro since the only effect of such a 1532 definition would be to slow down register allocation. */ 1533 1534#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1535 (((CLASS) == AREG) \ 1536 || ((CLASS) == DREG) \ 1537 || ((CLASS) == CREG) \ 1538 || ((CLASS) == BREG) \ 1539 || ((CLASS) == AD_REGS) \ 1540 || ((CLASS) == SIREG) \ 1541 || ((CLASS) == DIREG)) 1542 1543/* A C statement that adds to CLOBBERS any hard regs the port wishes 1544 to automatically clobber for all asms. 1545 1546 We do this in the new i386 backend to maintain source compatibility 1547 with the old cc0-based compiler. */ 1548 1549#define MD_ASM_CLOBBERS(CLOBBERS) \ 1550 do { \ 1551 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ 1552 (CLOBBERS)); \ 1553 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ 1554 (CLOBBERS)); \ 1555 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ 1556 (CLOBBERS)); \ 1557 } while (0) 1558 1559/* Stack layout; function entry, exit and calling. */ 1560 1561/* Define this if pushing a word on the stack 1562 makes the stack pointer a smaller address. */ 1563#define STACK_GROWS_DOWNWARD 1564 1565/* Define this if the nominal address of the stack frame 1566 is at the high-address end of the local variables; 1567 that is, each additional local variable allocated 1568 goes at a more negative offset in the frame. */ 1569#define FRAME_GROWS_DOWNWARD 1570 1571/* Offset within stack frame to start allocating local variables at. 1572 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1573 first local allocated. Otherwise, it is the offset to the BEGINNING 1574 of the first local allocated. */ 1575#define STARTING_FRAME_OFFSET 0 1576 1577/* If we generate an insn to push BYTES bytes, 1578 this says how many the stack pointer really advances by. 1579 On 386 pushw decrements by exactly 2 no matter what the position was. 1580 On the 386 there is no pushb; we use pushw instead, and this 1581 has the effect of rounding up to 2. 1582 1583 For 64bit ABI we round up to 8 bytes. 1584 */ 1585 1586#define PUSH_ROUNDING(BYTES) \ 1587 (TARGET_64BIT \ 1588 ? (((BYTES) + 7) & (-8)) \ 1589 : (((BYTES) + 1) & (-2))) 1590 1591/* If defined, the maximum amount of space required for outgoing arguments will 1592 be computed and placed into the variable 1593 `current_function_outgoing_args_size'. No space will be pushed onto the 1594 stack for each call; instead, the function prologue should increase the stack 1595 frame size by this amount. */ 1596 1597#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1598 1599/* If defined, a C expression whose value is nonzero when we want to use PUSH 1600 instructions to pass outgoing arguments. */ 1601 1602#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1603 1604/* We want the stack and args grow in opposite directions, even if 1605 PUSH_ARGS is 0. */ 1606#define PUSH_ARGS_REVERSED 1 1607 1608/* Offset of first parameter from the argument pointer register value. */ 1609#define FIRST_PARM_OFFSET(FNDECL) 0 1610 1611/* Define this macro if functions should assume that stack space has been 1612 allocated for arguments even when their values are passed in registers. 1613 1614 The value of this macro is the size, in bytes, of the area reserved for 1615 arguments passed in registers for the function represented by FNDECL. 1616 1617 This space can be allocated by the caller, or be a part of the 1618 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1619 which. */ 1620#define REG_PARM_STACK_SPACE(FNDECL) 0 1621 1622/* Define as a C expression that evaluates to nonzero if we do not know how 1623 to pass TYPE solely in registers. The file expr.h defines a 1624 definition that is usually appropriate, refer to expr.h for additional 1625 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be 1626 computed in the stack and then loaded into a register. */ 1627#define MUST_PASS_IN_STACK(MODE, TYPE) \ 1628 ((TYPE) != 0 \ 1629 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1630 || TREE_ADDRESSABLE (TYPE) \ 1631 || ((MODE) == TImode) \ 1632 || ((MODE) == BLKmode \ 1633 && ! ((TYPE) != 0 \ 1634 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ 1635 && 0 == (int_size_in_bytes (TYPE) \ 1636 % (PARM_BOUNDARY / BITS_PER_UNIT))) \ 1637 && (FUNCTION_ARG_PADDING (MODE, TYPE) \ 1638 == (BYTES_BIG_ENDIAN ? upward : downward))))) 1639 1640/* Value is the number of bytes of arguments automatically 1641 popped when returning from a subroutine call. 1642 FUNDECL is the declaration node of the function (as a tree), 1643 FUNTYPE is the data type of the function (as a tree), 1644 or for a library call it is an identifier node for the subroutine name. 1645 SIZE is the number of bytes of arguments passed on the stack. 1646 1647 On the 80386, the RTD insn may be used to pop them if the number 1648 of args is fixed, but if the number is variable then the caller 1649 must pop them all. RTD can't be used for library calls now 1650 because the library is compiled with the Unix compiler. 1651 Use of RTD is a selectable option, since it is incompatible with 1652 standard Unix calling sequences. If the option is not selected, 1653 the caller must always pop the args. 1654 1655 The attribute stdcall is equivalent to RTD on a per module basis. */ 1656 1657#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1658 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1659 1660/* Define how to find the value returned by a function. 1661 VALTYPE is the data type of the value (as a tree). 1662 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1663 otherwise, FUNC is 0. */ 1664#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1665 ix86_function_value (VALTYPE) 1666 1667#define FUNCTION_VALUE_REGNO_P(N) \ 1668 ix86_function_value_regno_p (N) 1669 1670/* Define how to find the value returned by a library function 1671 assuming the value has mode MODE. */ 1672 1673#define LIBCALL_VALUE(MODE) \ 1674 ix86_libcall_value (MODE) 1675 1676/* Define the size of the result block used for communication between 1677 untyped_call and untyped_return. The block contains a DImode value 1678 followed by the block used by fnsave and frstor. */ 1679 1680#define APPLY_RESULT_SIZE (8+108) 1681 1682/* 1 if N is a possible register number for function argument passing. */ 1683#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1684 1685/* Define a data type for recording info about an argument list 1686 during the scan of that argument list. This data type should 1687 hold all necessary information about the function itself 1688 and about the args processed so far, enough to enable macros 1689 such as FUNCTION_ARG to determine where the next arg should go. */ 1690 1691typedef struct ix86_args { 1692 int words; /* # words passed so far */ 1693 int nregs; /* # registers available for passing */ 1694 int regno; /* next available register number */ 1695 int sse_words; /* # sse words passed so far */ 1696 int sse_nregs; /* # sse registers available for passing */ 1697 int sse_regno; /* next available sse register number */ 1698 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1699} CUMULATIVE_ARGS; 1700 1701/* Initialize a variable CUM of type CUMULATIVE_ARGS 1702 for a call to a function whose data type is FNTYPE. 1703 For a library call, FNTYPE is 0. */ 1704 1705#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1706 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) 1707 1708/* Update the data in CUM to advance over an argument 1709 of mode MODE and data type TYPE. 1710 (TYPE is null for libcalls where that information may not be available.) */ 1711 1712#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1713 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1714 1715/* Define where to put the arguments to a function. 1716 Value is zero to push the argument on the stack, 1717 or a hard register in which to store the argument. 1718 1719 MODE is the argument's machine mode. 1720 TYPE is the data type of the argument (as a tree). 1721 This is null for libcalls where that information may 1722 not be available. 1723 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1724 the preceding args and about the function being called. 1725 NAMED is nonzero if this argument is a named parameter 1726 (otherwise it is an extra parameter matching an ellipsis). */ 1727 1728#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1729 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1730 1731/* For an arg passed partly in registers and partly in memory, 1732 this is the number of registers used. 1733 For args passed entirely in registers or entirely in memory, zero. */ 1734 1735#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1736 1737/* If PIC, we cannot make sibling calls to global functions 1738 because the PLT requires %ebx live. 1739 If we are returning floats on the register stack, we cannot make 1740 sibling calls to functions that return floats. (The stack adjust 1741 instruction will wind up after the sibcall jump, and not be executed.) */ 1742#define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1743 ((DECL) \ 1744 && (! flag_pic || ! TREE_PUBLIC (DECL)) \ 1745 && (! TARGET_FLOAT_RETURNS_IN_80387 \ 1746 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \ 1747 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl)))))) 1748 1749/* Perform any needed actions needed for a function that is receiving a 1750 variable number of arguments. 1751 1752 CUM is as above. 1753 1754 MODE and TYPE are the mode and type of the current parameter. 1755 1756 PRETEND_SIZE is a variable that should be set to the amount of stack 1757 that must be pushed by the prolog to pretend that our caller pushed 1758 it. 1759 1760 Normally, this macro will push all remaining incoming registers on the 1761 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1762 1763#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1764 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ 1765 (NO_RTL)) 1766 1767/* Define the `__builtin_va_list' type for the ABI. */ 1768#define BUILD_VA_LIST_TYPE(VALIST) \ 1769 ((VALIST) = ix86_build_va_list ()) 1770 1771/* Implement `va_start' for varargs and stdarg. */ 1772#define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \ 1773 ix86_va_start ((STDARG), (VALIST), (NEXTARG)) 1774 1775/* Implement `va_arg'. */ 1776#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ 1777 ix86_va_arg ((VALIST), (TYPE)) 1778 1779/* This macro is invoked at the end of compilation. It is used here to 1780 output code for -fpic that will load the return address into %ebx. */ 1781 1782#undef ASM_FILE_END 1783#define ASM_FILE_END(FILE) ix86_asm_file_end (FILE) 1784 1785/* Output assembler code to FILE to increment profiler label # LABELNO 1786 for profiling a function entry. */ 1787 1788#define FUNCTION_PROFILER(FILE, LABELNO) \ 1789do { \ 1790 if (flag_pic) \ 1791 { \ 1792 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \ 1793 LPREFIX, (LABELNO)); \ 1794 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \ 1795 } \ 1796 else \ 1797 { \ 1798 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ 1799 fprintf ((FILE), "\tcall\t_mcount\n"); \ 1800 } \ 1801} while (0) 1802 1803/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1804 the stack pointer does not matter. The value is tested only in 1805 functions that have frame pointers. 1806 No definition is equivalent to always zero. */ 1807/* Note on the 386 it might be more efficient not to define this since 1808 we have to restore it ourselves from the frame pointer, in order to 1809 use pop */ 1810 1811#define EXIT_IGNORE_STACK 1 1812 1813/* Output assembler code for a block containing the constant parts 1814 of a trampoline, leaving space for the variable parts. */ 1815 1816/* On the 386, the trampoline contains two instructions: 1817 mov #STATIC,ecx 1818 jmp FUNCTION 1819 The trampoline is generated entirely at runtime. The operand of JMP 1820 is the address of FUNCTION relative to the instruction following the 1821 JMP (which is 5 bytes long). */ 1822 1823/* Length in units of the trampoline for entering a nested function. */ 1824 1825#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1826 1827/* Emit RTL insns to initialize the variable parts of a trampoline. 1828 FNADDR is an RTX for the address of the function's pure code. 1829 CXT is an RTX for the static chain value for the function. */ 1830 1831#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1832 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1833 1834/* Definitions for register eliminations. 1835 1836 This is an array of structures. Each structure initializes one pair 1837 of eliminable registers. The "from" register number is given first, 1838 followed by "to". Eliminations of the same "from" register are listed 1839 in order of preference. 1840 1841 There are two registers that can always be eliminated on the i386. 1842 The frame pointer and the arg pointer can be replaced by either the 1843 hard frame pointer or to the stack pointer, depending upon the 1844 circumstances. The hard frame pointer is not used before reload and 1845 so it is not eligible for elimination. */ 1846 1847#define ELIMINABLE_REGS \ 1848{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1849 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1850 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1851 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1852 1853/* Given FROM and TO register numbers, say whether this elimination is 1854 allowed. Frame pointer elimination is automatically handled. 1855 1856 All other eliminations are valid. */ 1857 1858#define CAN_ELIMINATE(FROM, TO) \ 1859 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1860 1861/* Define the offset between two registers, one to be eliminated, and the other 1862 its replacement, at the start of a routine. */ 1863 1864#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1865 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1866 1867/* Addressing modes, and classification of registers for them. */ 1868 1869/* #define HAVE_POST_INCREMENT 0 */ 1870/* #define HAVE_POST_DECREMENT 0 */ 1871 1872/* #define HAVE_PRE_DECREMENT 0 */ 1873/* #define HAVE_PRE_INCREMENT 0 */ 1874 1875/* Macros to check register numbers against specific register classes. */ 1876 1877/* These assume that REGNO is a hard or pseudo reg number. 1878 They give nonzero only if REGNO is a hard reg of the suitable class 1879 or a pseudo reg currently allocated to a suitable hard reg. 1880 Since they use reg_renumber, they are safe only once reg_renumber 1881 has been allocated, which happens in local-alloc.c. */ 1882 1883#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1884 ((REGNO) < STACK_POINTER_REGNUM \ 1885 || (REGNO >= FIRST_REX_INT_REG \ 1886 && (REGNO) <= LAST_REX_INT_REG) \ 1887 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1888 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1889 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1890 1891#define REGNO_OK_FOR_BASE_P(REGNO) \ 1892 ((REGNO) <= STACK_POINTER_REGNUM \ 1893 || (REGNO) == ARG_POINTER_REGNUM \ 1894 || (REGNO) == FRAME_POINTER_REGNUM \ 1895 || (REGNO >= FIRST_REX_INT_REG \ 1896 && (REGNO) <= LAST_REX_INT_REG) \ 1897 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1898 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1899 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1900 1901#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1902 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1903#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1904 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1905 1906/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1907 and check its validity for a certain class. 1908 We have two alternate definitions for each of them. 1909 The usual definition accepts all pseudo regs; the other rejects 1910 them unless they have been allocated suitable hard regs. 1911 The symbol REG_OK_STRICT causes the latter definition to be used. 1912 1913 Most source files want to accept pseudo regs in the hope that 1914 they will get allocated to the class that the insn wants them to be in. 1915 Source files for reload pass need to be strict. 1916 After reload, it makes no difference, since pseudo regs have 1917 been eliminated by then. */ 1918 1919 1920/* Non strict versions, pseudos are ok */ 1921#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1922 (REGNO (X) < STACK_POINTER_REGNUM \ 1923 || (REGNO (X) >= FIRST_REX_INT_REG \ 1924 && REGNO (X) <= LAST_REX_INT_REG) \ 1925 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1926 1927#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1928 (REGNO (X) <= STACK_POINTER_REGNUM \ 1929 || REGNO (X) == ARG_POINTER_REGNUM \ 1930 || REGNO (X) == FRAME_POINTER_REGNUM \ 1931 || (REGNO (X) >= FIRST_REX_INT_REG \ 1932 && REGNO (X) <= LAST_REX_INT_REG) \ 1933 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1934 1935/* Strict versions, hard registers only */ 1936#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1937#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1938 1939#ifndef REG_OK_STRICT 1940#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1941#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1942 1943#else 1944#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1945#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1946#endif 1947 1948/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1949 that is a valid memory address for an instruction. 1950 The MODE argument is the machine mode for the MEM expression 1951 that wants to use this address. 1952 1953 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1954 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1955 1956 See legitimize_pic_address in i386.c for details as to what 1957 constitutes a legitimate address when -fpic is used. */ 1958 1959#define MAX_REGS_PER_ADDRESS 2 1960 1961#define CONSTANT_ADDRESS_P(X) \ 1962 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1963 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1964 || GET_CODE (X) == CONST_DOUBLE) 1965 1966/* Nonzero if the constant value X is a legitimate general operand. 1967 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1968 1969#define LEGITIMATE_CONSTANT_P(X) 1 1970 1971#ifdef REG_OK_STRICT 1972#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1973do { \ 1974 if (legitimate_address_p ((MODE), (X), 1)) \ 1975 goto ADDR; \ 1976} while (0) 1977 1978#else 1979#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1980do { \ 1981 if (legitimate_address_p ((MODE), (X), 0)) \ 1982 goto ADDR; \ 1983} while (0) 1984 1985#endif 1986 1987/* If defined, a C expression to determine the base term of address X. 1988 This macro is used in only one place: `find_base_term' in alias.c. 1989 1990 It is always safe for this macro to not be defined. It exists so 1991 that alias analysis can understand machine-dependent addresses. 1992 1993 The typical use of this macro is to handle addresses containing 1994 a label_ref or symbol_ref within an UNSPEC. */ 1995 1996#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1997 1998/* Try machine-dependent ways of modifying an illegitimate address 1999 to be legitimate. If we find one, return the new, valid address. 2000 This macro is used in only one place: `memory_address' in explow.c. 2001 2002 OLDX is the address as it was before break_out_memory_refs was called. 2003 In some cases it is useful to look at this to decide what needs to be done. 2004 2005 MODE and WIN are passed so that this macro can use 2006 GO_IF_LEGITIMATE_ADDRESS. 2007 2008 It is always safe for this macro to do nothing. It exists to recognize 2009 opportunities to optimize the output. 2010 2011 For the 80386, we handle X+REG by loading X into a register R and 2012 using R+REG. R will go in a general reg and indexing will be used. 2013 However, if REG is a broken-out memory address or multiplication, 2014 nothing needs to be done because REG can certainly go in a general reg. 2015 2016 When -fpic is used, special handling is needed for symbolic references. 2017 See comments by legitimize_pic_address in i386.c for details. */ 2018 2019#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2020do { \ 2021 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 2022 if (memory_address_p ((MODE), (X))) \ 2023 goto WIN; \ 2024} while (0) 2025 2026#define REWRITE_ADDRESS(X) rewrite_address (X) 2027 2028/* Nonzero if the constant value X is a legitimate general operand 2029 when generating PIC code. It is given that flag_pic is on and 2030 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2031 2032#define LEGITIMATE_PIC_OPERAND_P(X) \ 2033 (! SYMBOLIC_CONST (X) \ 2034 || legitimate_pic_address_disp_p (X)) 2035 2036#define SYMBOLIC_CONST(X) \ 2037 (GET_CODE (X) == SYMBOL_REF \ 2038 || GET_CODE (X) == LABEL_REF \ 2039 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 2040 2041/* Go to LABEL if ADDR (a legitimate address expression) 2042 has an effect that depends on the machine mode it is used for. 2043 On the 80386, only postdecrement and postincrement address depend thus 2044 (the amount of decrement or increment being the length of the operand). */ 2045#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2046do { \ 2047 if (GET_CODE (ADDR) == POST_INC \ 2048 || GET_CODE (ADDR) == POST_DEC) \ 2049 goto LABEL; \ 2050} while (0) 2051 2052/* Codes for all the SSE/MMX builtins. */ 2053enum ix86_builtins 2054{ 2055 IX86_BUILTIN_ADDPS, 2056 IX86_BUILTIN_ADDSS, 2057 IX86_BUILTIN_DIVPS, 2058 IX86_BUILTIN_DIVSS, 2059 IX86_BUILTIN_MULPS, 2060 IX86_BUILTIN_MULSS, 2061 IX86_BUILTIN_SUBPS, 2062 IX86_BUILTIN_SUBSS, 2063 2064 IX86_BUILTIN_CMPEQPS, 2065 IX86_BUILTIN_CMPLTPS, 2066 IX86_BUILTIN_CMPLEPS, 2067 IX86_BUILTIN_CMPGTPS, 2068 IX86_BUILTIN_CMPGEPS, 2069 IX86_BUILTIN_CMPNEQPS, 2070 IX86_BUILTIN_CMPNLTPS, 2071 IX86_BUILTIN_CMPNLEPS, 2072 IX86_BUILTIN_CMPNGTPS, 2073 IX86_BUILTIN_CMPNGEPS, 2074 IX86_BUILTIN_CMPORDPS, 2075 IX86_BUILTIN_CMPUNORDPS, 2076 IX86_BUILTIN_CMPNEPS, 2077 IX86_BUILTIN_CMPEQSS, 2078 IX86_BUILTIN_CMPLTSS, 2079 IX86_BUILTIN_CMPLESS, 2080 IX86_BUILTIN_CMPNEQSS, 2081 IX86_BUILTIN_CMPNLTSS, 2082 IX86_BUILTIN_CMPNLESS, 2083 IX86_BUILTIN_CMPORDSS, 2084 IX86_BUILTIN_CMPUNORDSS, 2085 IX86_BUILTIN_CMPNESS, 2086 2087 IX86_BUILTIN_COMIEQSS, 2088 IX86_BUILTIN_COMILTSS, 2089 IX86_BUILTIN_COMILESS, 2090 IX86_BUILTIN_COMIGTSS, 2091 IX86_BUILTIN_COMIGESS, 2092 IX86_BUILTIN_COMINEQSS, 2093 IX86_BUILTIN_UCOMIEQSS, 2094 IX86_BUILTIN_UCOMILTSS, 2095 IX86_BUILTIN_UCOMILESS, 2096 IX86_BUILTIN_UCOMIGTSS, 2097 IX86_BUILTIN_UCOMIGESS, 2098 IX86_BUILTIN_UCOMINEQSS, 2099 2100 IX86_BUILTIN_CVTPI2PS, 2101 IX86_BUILTIN_CVTPS2PI, 2102 IX86_BUILTIN_CVTSI2SS, 2103 IX86_BUILTIN_CVTSS2SI, 2104 IX86_BUILTIN_CVTTPS2PI, 2105 IX86_BUILTIN_CVTTSS2SI, 2106 2107 IX86_BUILTIN_MAXPS, 2108 IX86_BUILTIN_MAXSS, 2109 IX86_BUILTIN_MINPS, 2110 IX86_BUILTIN_MINSS, 2111 2112 IX86_BUILTIN_LOADAPS, 2113 IX86_BUILTIN_LOADUPS, 2114 IX86_BUILTIN_STOREAPS, 2115 IX86_BUILTIN_STOREUPS, 2116 IX86_BUILTIN_LOADSS, 2117 IX86_BUILTIN_STORESS, 2118 IX86_BUILTIN_MOVSS, 2119 2120 IX86_BUILTIN_MOVHLPS, 2121 IX86_BUILTIN_MOVLHPS, 2122 IX86_BUILTIN_LOADHPS, 2123 IX86_BUILTIN_LOADLPS, 2124 IX86_BUILTIN_STOREHPS, 2125 IX86_BUILTIN_STORELPS, 2126 2127 IX86_BUILTIN_MASKMOVQ, 2128 IX86_BUILTIN_MOVMSKPS, 2129 IX86_BUILTIN_PMOVMSKB, 2130 2131 IX86_BUILTIN_MOVNTPS, 2132 IX86_BUILTIN_MOVNTQ, 2133 2134 IX86_BUILTIN_PACKSSWB, 2135 IX86_BUILTIN_PACKSSDW, 2136 IX86_BUILTIN_PACKUSWB, 2137 2138 IX86_BUILTIN_PADDB, 2139 IX86_BUILTIN_PADDW, 2140 IX86_BUILTIN_PADDD, 2141 IX86_BUILTIN_PADDSB, 2142 IX86_BUILTIN_PADDSW, 2143 IX86_BUILTIN_PADDUSB, 2144 IX86_BUILTIN_PADDUSW, 2145 IX86_BUILTIN_PSUBB, 2146 IX86_BUILTIN_PSUBW, 2147 IX86_BUILTIN_PSUBD, 2148 IX86_BUILTIN_PSUBSB, 2149 IX86_BUILTIN_PSUBSW, 2150 IX86_BUILTIN_PSUBUSB, 2151 IX86_BUILTIN_PSUBUSW, 2152 2153 IX86_BUILTIN_PAND, 2154 IX86_BUILTIN_PANDN, 2155 IX86_BUILTIN_POR, 2156 IX86_BUILTIN_PXOR, 2157 2158 IX86_BUILTIN_PAVGB, 2159 IX86_BUILTIN_PAVGW, 2160 2161 IX86_BUILTIN_PCMPEQB, 2162 IX86_BUILTIN_PCMPEQW, 2163 IX86_BUILTIN_PCMPEQD, 2164 IX86_BUILTIN_PCMPGTB, 2165 IX86_BUILTIN_PCMPGTW, 2166 IX86_BUILTIN_PCMPGTD, 2167 2168 IX86_BUILTIN_PEXTRW, 2169 IX86_BUILTIN_PINSRW, 2170 2171 IX86_BUILTIN_PMADDWD, 2172 2173 IX86_BUILTIN_PMAXSW, 2174 IX86_BUILTIN_PMAXUB, 2175 IX86_BUILTIN_PMINSW, 2176 IX86_BUILTIN_PMINUB, 2177 2178 IX86_BUILTIN_PMULHUW, 2179 IX86_BUILTIN_PMULHW, 2180 IX86_BUILTIN_PMULLW, 2181 2182 IX86_BUILTIN_PSADBW, 2183 IX86_BUILTIN_PSHUFW, 2184 2185 IX86_BUILTIN_PSLLW, 2186 IX86_BUILTIN_PSLLD, 2187 IX86_BUILTIN_PSLLQ, 2188 IX86_BUILTIN_PSRAW, 2189 IX86_BUILTIN_PSRAD, 2190 IX86_BUILTIN_PSRLW, 2191 IX86_BUILTIN_PSRLD, 2192 IX86_BUILTIN_PSRLQ, 2193 IX86_BUILTIN_PSLLWI, 2194 IX86_BUILTIN_PSLLDI, 2195 IX86_BUILTIN_PSLLQI, 2196 IX86_BUILTIN_PSRAWI, 2197 IX86_BUILTIN_PSRADI, 2198 IX86_BUILTIN_PSRLWI, 2199 IX86_BUILTIN_PSRLDI, 2200 IX86_BUILTIN_PSRLQI, 2201 2202 IX86_BUILTIN_PUNPCKHBW, 2203 IX86_BUILTIN_PUNPCKHWD, 2204 IX86_BUILTIN_PUNPCKHDQ, 2205 IX86_BUILTIN_PUNPCKLBW, 2206 IX86_BUILTIN_PUNPCKLWD, 2207 IX86_BUILTIN_PUNPCKLDQ, 2208 2209 IX86_BUILTIN_SHUFPS, 2210 2211 IX86_BUILTIN_RCPPS, 2212 IX86_BUILTIN_RCPSS, 2213 IX86_BUILTIN_RSQRTPS, 2214 IX86_BUILTIN_RSQRTSS, 2215 IX86_BUILTIN_SQRTPS, 2216 IX86_BUILTIN_SQRTSS, 2217 2218 IX86_BUILTIN_UNPCKHPS, 2219 IX86_BUILTIN_UNPCKLPS, 2220 2221 IX86_BUILTIN_ANDPS, 2222 IX86_BUILTIN_ANDNPS, 2223 IX86_BUILTIN_ORPS, 2224 IX86_BUILTIN_XORPS, 2225 2226 IX86_BUILTIN_EMMS, 2227 IX86_BUILTIN_LDMXCSR, 2228 IX86_BUILTIN_STMXCSR, 2229 IX86_BUILTIN_SFENCE, 2230 2231 /* 3DNow! Original */ 2232 IX86_BUILTIN_FEMMS, 2233 IX86_BUILTIN_PAVGUSB, 2234 IX86_BUILTIN_PF2ID, 2235 IX86_BUILTIN_PFACC, 2236 IX86_BUILTIN_PFADD, 2237 IX86_BUILTIN_PFCMPEQ, 2238 IX86_BUILTIN_PFCMPGE, 2239 IX86_BUILTIN_PFCMPGT, 2240 IX86_BUILTIN_PFMAX, 2241 IX86_BUILTIN_PFMIN, 2242 IX86_BUILTIN_PFMUL, 2243 IX86_BUILTIN_PFRCP, 2244 IX86_BUILTIN_PFRCPIT1, 2245 IX86_BUILTIN_PFRCPIT2, 2246 IX86_BUILTIN_PFRSQIT1, 2247 IX86_BUILTIN_PFRSQRT, 2248 IX86_BUILTIN_PFSUB, 2249 IX86_BUILTIN_PFSUBR, 2250 IX86_BUILTIN_PI2FD, 2251 IX86_BUILTIN_PMULHRW, 2252 2253 /* 3DNow! Athlon Extensions */ 2254 IX86_BUILTIN_PF2IW, 2255 IX86_BUILTIN_PFNACC, 2256 IX86_BUILTIN_PFPNACC, 2257 IX86_BUILTIN_PI2FW, 2258 IX86_BUILTIN_PSWAPDSI, 2259 IX86_BUILTIN_PSWAPDSF, 2260 2261 IX86_BUILTIN_SSE_ZERO, 2262 IX86_BUILTIN_MMX_ZERO, 2263 2264 IX86_BUILTIN_MAX 2265}; 2266 2267/* Define this macro if references to a symbol must be treated 2268 differently depending on something about the variable or 2269 function named by the symbol (such as what section it is in). 2270 2271 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol 2272 so that we may access it directly in the GOT. */ 2273 2274#define ENCODE_SECTION_INFO(DECL) \ 2275do { \ 2276 if (flag_pic) \ 2277 { \ 2278 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2279 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ 2280 \ 2281 if (GET_CODE (rtl) == MEM) \ 2282 { \ 2283 if (TARGET_DEBUG_ADDR \ 2284 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \ 2285 { \ 2286 fprintf (stderr, "Encode %s, public = %d\n", \ 2287 IDENTIFIER_POINTER (DECL_NAME (DECL)), \ 2288 TREE_PUBLIC (DECL)); \ 2289 } \ 2290 \ 2291 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ 2292 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2293 || ! TREE_PUBLIC (DECL)); \ 2294 } \ 2295 } \ 2296} while (0) 2297 2298/* The `FINALIZE_PIC' macro serves as a hook to emit these special 2299 codes once the function is being compiled into assembly code, but 2300 not before. (It is not done before, because in the case of 2301 compiling an inline function, it would lead to multiple PIC 2302 prologues being included in functions which used inline functions 2303 and were compiled to assembly language.) */ 2304 2305#define FINALIZE_PIC \ 2306 (current_function_uses_pic_offset_table |= current_function_profile) 2307 2308 2309/* Max number of args passed in registers. If this is more than 3, we will 2310 have problems with ebx (register #4), since it is a caller save register and 2311 is also used as the pic register in ELF. So for now, don't allow more than 2312 3 registers to be passed in registers. */ 2313 2314#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 2315 2316#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0) 2317 2318 2319/* Specify the machine mode that this machine uses 2320 for the index in the tablejump instruction. */ 2321#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 2322 2323/* Define as C expression which evaluates to nonzero if the tablejump 2324 instruction expects the table to contain offsets from the address of the 2325 table. 2326 Do not define this if the table should contain absolute addresses. */ 2327/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2328 2329/* Define this as 1 if `char' should by default be signed; else as 0. */ 2330#define DEFAULT_SIGNED_CHAR 1 2331 2332/* Number of bytes moved into a data cache for a single prefetch operation. */ 2333#define PREFETCH_BLOCK ix86_cost->prefetch_block 2334 2335/* Number of prefetch operations that can be done in parallel. */ 2336#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 2337 2338/* Max number of bytes we can move from memory to memory 2339 in one reasonably fast instruction. */ 2340#define MOVE_MAX 16 2341 2342/* MOVE_MAX_PIECES is the number of bytes at a time which we can 2343 move efficiently, as opposed to MOVE_MAX which is the maximum 2344 number of bytes we can move with a single instruction. */ 2345#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 2346 2347/* If a memory-to-memory move would take MOVE_RATIO or more simple 2348 move-instruction pairs, we will do a movstr or libcall instead. 2349 Increasing the value will always make code faster, but eventually 2350 incurs high cost in increased code size. 2351 2352 If you don't define this, a reasonable default is used. */ 2353 2354#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 2355 2356/* Define if shifts truncate the shift count 2357 which implies one can omit a sign-extension or zero-extension 2358 of a shift count. */ 2359/* On i386, shifts do truncate the count. But bit opcodes don't. */ 2360 2361/* #define SHIFT_COUNT_TRUNCATED */ 2362 2363/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2364 is done just by pretending it is already truncated. */ 2365#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2366 2367/* We assume that the store-condition-codes instructions store 0 for false 2368 and some other value for true. This is the value stored for true. */ 2369 2370#define STORE_FLAG_VALUE 1 2371 2372/* When a prototype says `char' or `short', really pass an `int'. 2373 (The 386 can't easily push less than an int.) */ 2374 2375#define PROMOTE_PROTOTYPES (!TARGET_64BIT) 2376 2377/* A macro to update M and UNSIGNEDP when an object whose type is 2378 TYPE and which has the specified mode and signedness is to be 2379 stored in a register. This macro is only called when TYPE is a 2380 scalar type. 2381 2382 On i386 it is sometimes useful to promote HImode and QImode 2383 quantities to SImode. The choice depends on target type. */ 2384 2385#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2386do { \ 2387 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 2388 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 2389 (MODE) = SImode; \ 2390} while (0) 2391 2392/* Specify the machine mode that pointers have. 2393 After generation of rtl, the compiler makes no further distinction 2394 between pointers and any other objects of this machine mode. */ 2395#define Pmode (TARGET_64BIT ? DImode : SImode) 2396 2397/* A function address in a call instruction 2398 is a byte address (for indexing purposes) 2399 so give the MEM rtx a byte's mode. */ 2400#define FUNCTION_MODE QImode 2401 2402/* A part of a C `switch' statement that describes the relative costs 2403 of constant RTL expressions. It must contain `case' labels for 2404 expression codes `const_int', `const', `symbol_ref', `label_ref' 2405 and `const_double'. Each case must ultimately reach a `return' 2406 statement to return the relative cost of the use of that kind of 2407 constant value in an expression. The cost may depend on the 2408 precise value of the constant, which is available for examination 2409 in X, and the rtx code of the expression in which it is contained, 2410 found in OUTER_CODE. 2411 2412 CODE is the expression code--redundant, since it can be obtained 2413 with `GET_CODE (X)'. */ 2414 2415#define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 2416 case CONST_INT: \ 2417 case CONST: \ 2418 case LABEL_REF: \ 2419 case SYMBOL_REF: \ 2420 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \ 2421 return 3; \ 2422 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \ 2423 return 2; \ 2424 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \ 2425 \ 2426 case CONST_DOUBLE: \ 2427 { \ 2428 int code; \ 2429 if (GET_MODE (RTX) == VOIDmode) \ 2430 return 0; \ 2431 \ 2432 code = standard_80387_constant_p (RTX); \ 2433 return code == 1 ? 1 : \ 2434 code == 2 ? 2 : \ 2435 3; \ 2436 } 2437 2438/* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ 2439#define TOPLEVEL_COSTS_N_INSNS(N) \ 2440 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) 2441 2442/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. 2443 This can be used, for example, to indicate how costly a multiply 2444 instruction is. In writing this macro, you can use the construct 2445 `COSTS_N_INSNS (N)' to specify a cost equal to N fast 2446 instructions. OUTER_CODE is the code of the expression in which X 2447 is contained. 2448 2449 This macro is optional; do not define it if the default cost 2450 assumptions are adequate for the target machine. */ 2451 2452#define RTX_COSTS(X, CODE, OUTER_CODE) \ 2453 case ZERO_EXTEND: \ 2454 /* The zero extensions is often completely free on x86_64, so make \ 2455 it as cheap as possible. */ \ 2456 if (TARGET_64BIT && GET_MODE (X) == DImode \ 2457 && GET_MODE (XEXP (X, 0)) == SImode) \ 2458 { \ 2459 total = 1; goto egress_rtx_costs; \ 2460 } \ 2461 else \ 2462 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \ 2463 ix86_cost->add : ix86_cost->movzx); \ 2464 break; \ 2465 case SIGN_EXTEND: \ 2466 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \ 2467 break; \ 2468 case ASHIFT: \ 2469 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 2470 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \ 2471 { \ 2472 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2473 if (value == 1) \ 2474 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2475 if ((value == 2 || value == 3) \ 2476 && !TARGET_DECOMPOSE_LEA \ 2477 && ix86_cost->lea <= ix86_cost->shift_const) \ 2478 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ 2479 } \ 2480 /* fall through */ \ 2481 \ 2482 case ROTATE: \ 2483 case ASHIFTRT: \ 2484 case LSHIFTRT: \ 2485 case ROTATERT: \ 2486 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \ 2487 { \ 2488 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2489 { \ 2490 if (INTVAL (XEXP (X, 1)) > 32) \ 2491 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ 2492 else \ 2493 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ 2494 } \ 2495 else \ 2496 { \ 2497 if (GET_CODE (XEXP (X, 1)) == AND) \ 2498 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ 2499 else \ 2500 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ 2501 } \ 2502 } \ 2503 else \ 2504 { \ 2505 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2506 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ 2507 else \ 2508 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ 2509 } \ 2510 break; \ 2511 \ 2512 case MULT: \ 2513 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2514 { \ 2515 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2516 int nbits = 0; \ 2517 \ 2518 while (value != 0) \ 2519 { \ 2520 nbits++; \ 2521 value >>= 1; \ 2522 } \ 2523 \ 2524 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2525 + nbits * ix86_cost->mult_bit); \ 2526 } \ 2527 else /* This is arbitrary */ \ 2528 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2529 + 7 * ix86_cost->mult_bit); \ 2530 \ 2531 case DIV: \ 2532 case UDIV: \ 2533 case MOD: \ 2534 case UMOD: \ 2535 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ 2536 \ 2537 case PLUS: \ 2538 if (!TARGET_DECOMPOSE_LEA \ 2539 && INTEGRAL_MODE_P (GET_MODE (X)) \ 2540 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \ 2541 { \ 2542 if (GET_CODE (XEXP (X, 0)) == PLUS \ 2543 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ 2544 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ 2545 && CONSTANT_P (XEXP (X, 1))) \ 2546 { \ 2547 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\ 2548 if (val == 2 || val == 4 || val == 8) \ 2549 { \ 2550 return (COSTS_N_INSNS (ix86_cost->lea) \ 2551 + rtx_cost (XEXP (XEXP (X, 0), 1), \ 2552 (OUTER_CODE)) \ 2553 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \ 2554 (OUTER_CODE)) \ 2555 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2556 } \ 2557 } \ 2558 else if (GET_CODE (XEXP (X, 0)) == MULT \ 2559 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ 2560 { \ 2561 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ 2562 if (val == 2 || val == 4 || val == 8) \ 2563 { \ 2564 return (COSTS_N_INSNS (ix86_cost->lea) \ 2565 + rtx_cost (XEXP (XEXP (X, 0), 0), \ 2566 (OUTER_CODE)) \ 2567 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2568 } \ 2569 } \ 2570 else if (GET_CODE (XEXP (X, 0)) == PLUS) \ 2571 { \ 2572 return (COSTS_N_INSNS (ix86_cost->lea) \ 2573 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \ 2574 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \ 2575 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2576 } \ 2577 } \ 2578 \ 2579 /* fall through */ \ 2580 case AND: \ 2581 case IOR: \ 2582 case XOR: \ 2583 case MINUS: \ 2584 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2585 return (COSTS_N_INSNS (ix86_cost->add) * 2 \ 2586 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \ 2587 << (GET_MODE (XEXP (X, 0)) != DImode)) \ 2588 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \ 2589 << (GET_MODE (XEXP (X, 1)) != DImode))); \ 2590 \ 2591 /* fall through */ \ 2592 case NEG: \ 2593 case NOT: \ 2594 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2595 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ 2596 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2597 \ 2598 egress_rtx_costs: \ 2599 break; 2600 2601 2602/* An expression giving the cost of an addressing mode that contains 2603 ADDRESS. If not defined, the cost is computed from the ADDRESS 2604 expression and the `CONST_COSTS' values. 2605 2606 For most CISC machines, the default cost is a good approximation 2607 of the true cost of the addressing mode. However, on RISC 2608 machines, all instructions normally have the same length and 2609 execution time. Hence all addresses will have equal costs. 2610 2611 In cases where more than one form of an address is known, the form 2612 with the lowest cost will be used. If multiple forms have the 2613 same, lowest, cost, the one that is the most complex will be used. 2614 2615 For example, suppose an address that is equal to the sum of a 2616 register and a constant is used twice in the same basic block. 2617 When this macro is not defined, the address will be computed in a 2618 register and memory references will be indirect through that 2619 register. On machines where the cost of the addressing mode 2620 containing the sum is no higher than that of a simple indirect 2621 reference, this will produce an additional instruction and 2622 possibly require an additional register. Proper specification of 2623 this macro eliminates this overhead for such machines. 2624 2625 Similar use of this macro is made in strength reduction of loops. 2626 2627 ADDRESS need not be valid as an address. In such a case, the cost 2628 is not relevant and can be any value; invalid addresses need not be 2629 assigned a different cost. 2630 2631 On machines where an address involving more than one register is as 2632 cheap as an address computation involving only one register, 2633 defining `ADDRESS_COST' to reflect this can cause two registers to 2634 be live over a region of code where only one would have been if 2635 `ADDRESS_COST' were not defined in that manner. This effect should 2636 be considered in the definition of this macro. Equivalent costs 2637 should probably only be given to addresses with different numbers 2638 of registers on machines with lots of registers. 2639 2640 This macro will normally either not be defined or be defined as a 2641 constant. 2642 2643 For i386, it is better to use a complex address than let gcc copy 2644 the address into a reg and make a new pseudo. But not if the address 2645 requires to two regs - that would mean more pseudos with longer 2646 lifetimes. */ 2647 2648#define ADDRESS_COST(RTX) \ 2649 ix86_address_cost (RTX) 2650 2651/* A C expression for the cost of moving data from a register in class FROM to 2652 one in class TO. The classes are expressed using the enumeration values 2653 such as `GENERAL_REGS'. A value of 2 is the default; other values are 2654 interpreted relative to that. 2655 2656 It is not required that the cost always equal 2 when FROM is the same as TO; 2657 on some machines it is expensive to move between registers if they are not 2658 general registers. */ 2659 2660#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2661 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 2662 2663/* A C expression for the cost of moving data of mode M between a 2664 register and memory. A value of 2 is the default; this cost is 2665 relative to those in `REGISTER_MOVE_COST'. 2666 2667 If moving between registers and memory is more expensive than 2668 between two registers, you should define this macro to express the 2669 relative cost. */ 2670 2671#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 2672 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 2673 2674/* A C expression for the cost of a branch instruction. A value of 1 2675 is the default; other values are interpreted relative to that. */ 2676 2677#define BRANCH_COST ix86_branch_cost 2678 2679/* Define this macro as a C expression which is nonzero if accessing 2680 less than a word of memory (i.e. a `char' or a `short') is no 2681 faster than accessing a word of memory, i.e., if such access 2682 require more than one instruction or if there is no difference in 2683 cost between byte and (aligned) word loads. 2684 2685 When this macro is not defined, the compiler will access a field by 2686 finding the smallest containing object; when it is defined, a 2687 fullword load will be used if alignment permits. Unless bytes 2688 accesses are faster than word accesses, using word accesses is 2689 preferable since it may eliminate subsequent memory access if 2690 subsequent accesses occur to other fields in the same word of the 2691 structure, but to different bytes. */ 2692 2693#define SLOW_BYTE_ACCESS 0 2694 2695/* Nonzero if access to memory by shorts is slow and undesirable. */ 2696#define SLOW_SHORT_ACCESS 0 2697 2698/* Define this macro to be the value 1 if unaligned accesses have a 2699 cost many times greater than aligned accesses, for example if they 2700 are emulated in a trap handler. 2701 2702 When this macro is non-zero, the compiler will act as if 2703 `STRICT_ALIGNMENT' were non-zero when generating code for block 2704 moves. This can cause significantly more instructions to be 2705 produced. Therefore, do not set this macro non-zero if unaligned 2706 accesses only add a cycle or two to the time for a memory access. 2707 2708 If the value of this macro is always zero, it need not be defined. */ 2709 2710/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2711 2712/* Define this macro to inhibit strength reduction of memory 2713 addresses. (On some machines, such strength reduction seems to do 2714 harm rather than good.) */ 2715 2716/* #define DONT_REDUCE_ADDR */ 2717 2718/* Define this macro if it is as good or better to call a constant 2719 function address than to call an address kept in a register. 2720 2721 Desirable on the 386 because a CALL with a constant address is 2722 faster than one with a register address. */ 2723 2724#define NO_FUNCTION_CSE 2725 2726/* Define this macro if it is as good or better for a function to call 2727 itself with an explicit address than to call an address kept in a 2728 register. */ 2729 2730#define NO_RECURSIVE_FUNCTION_CSE 2731 2732/* Add any extra modes needed to represent the condition code. 2733 2734 For the i386, we need separate modes when floating-point 2735 equality comparisons are being done. 2736 2737 Add CCNO to indicate comparisons against zero that requires 2738 Overflow flag to be unset. Sign bit test is used instead and 2739 thus can be used to form "a&b>0" type of tests. 2740 2741 Add CCGC to indicate comparisons agains zero that allows 2742 unspecified garbage in the Carry flag. This mode is used 2743 by inc/dec instructions. 2744 2745 Add CCGOC to indicate comparisons agains zero that allows 2746 unspecified garbage in the Carry and Overflow flag. This 2747 mode is used to simulate comparisons of (a-b) and (a+b) 2748 against zero using sub/cmp/add operations. 2749 2750 Add CCZ to indicate that only the Zero flag is valid. */ 2751 2752#define EXTRA_CC_MODES \ 2753 CC (CCGCmode, "CCGC") \ 2754 CC (CCGOCmode, "CCGOC") \ 2755 CC (CCNOmode, "CCNO") \ 2756 CC (CCZmode, "CCZ") \ 2757 CC (CCFPmode, "CCFP") \ 2758 CC (CCFPUmode, "CCFPU") 2759 2760/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2761 return the mode to be used for the comparison. 2762 2763 For floating-point equality comparisons, CCFPEQmode should be used. 2764 VOIDmode should be used in all other cases. 2765 2766 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2767 possible, to allow for more combinations. */ 2768 2769#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2770 2771/* Return non-zero if MODE implies a floating point inequality can be 2772 reversed. */ 2773 2774#define REVERSIBLE_CC_MODE(MODE) 1 2775 2776/* A C expression whose value is reversed condition code of the CODE for 2777 comparison done in CC_MODE mode. */ 2778#define REVERSE_CONDITION(CODE, MODE) \ 2779 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ 2780 : reverse_condition_maybe_unordered (CODE)) 2781 2782 2783/* Control the assembler format that we output, to the extent 2784 this does not vary between assemblers. */ 2785 2786/* How to refer to registers in assembler output. 2787 This sequence is indexed by compiler's hard-register-number (see above). */ 2788 2789/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" 2790 For non floating point regs, the following are the HImode names. 2791 2792 For float regs, the stack top is sometimes referred to as "%st(0)" 2793 instead of just "%st". PRINT_REG handles this with the "y" code. */ 2794 2795#undef HI_REGISTER_NAMES 2796#define HI_REGISTER_NAMES \ 2797{"ax","dx","cx","bx","si","di","bp","sp", \ 2798 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ 2799 "flags","fpsr", "dirflag", "frame", \ 2800 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2801 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 2802 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2803 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 2804 2805#define REGISTER_NAMES HI_REGISTER_NAMES 2806 2807/* Table of additional register names to use in user input. */ 2808 2809#define ADDITIONAL_REGISTER_NAMES \ 2810{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2811 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2812 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2813 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2814 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2815 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2816 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ 2817 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } 2818 2819/* Note we are omitting these since currently I don't know how 2820to get gcc to use these, since they want the same but different 2821number as al, and ax. 2822*/ 2823 2824#define QI_REGISTER_NAMES \ 2825{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2826 2827/* These parallel the array above, and can be used to access bits 8:15 2828 of regs 0 through 3. */ 2829 2830#define QI_HIGH_REGISTER_NAMES \ 2831{"ah", "dh", "ch", "bh", } 2832 2833/* How to renumber registers for dbx and gdb. */ 2834 2835#define DBX_REGISTER_NUMBER(N) \ 2836 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2837 2838extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2839extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2840extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2841 2842/* Before the prologue, RA is at 0(%esp). */ 2843#define INCOMING_RETURN_ADDR_RTX \ 2844 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2845 2846/* After the prologue, RA is at -4(AP) in the current frame. */ 2847#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2848 ((COUNT) == 0 \ 2849 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2850 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2851 2852/* PC is dbx register 8; let's use that column for RA. */ 2853#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2854 2855/* Before the prologue, the top of the frame is at 4(%esp). */ 2856#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2857 2858/* Describe how we implement __builtin_eh_return. */ 2859#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2860#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2861 2862 2863/* Select a format to encode pointers in exception handling data. CODE 2864 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2865 true if the symbol may be affected by dynamic relocations. 2866 2867 ??? All x86 object file formats are capable of representing this. 2868 After all, the relocation needed is the same as for the call insn. 2869 Whether or not a particular assembler allows us to enter such, I 2870 guess we'll have to see. */ 2871#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2872 (flag_pic \ 2873 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 2874 : DW_EH_PE_absptr) 2875 2876/* This is how to output the definition of a user-level label named NAME, 2877 such as the label on a static function or variable NAME. */ 2878 2879#define ASM_OUTPUT_LABEL(FILE, NAME) \ 2880 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE))) 2881 2882/* Store in OUTPUT a string (made with alloca) containing 2883 an assembler-name for a local static variable named NAME. 2884 LABELNO is an integer which is different for each call. */ 2885 2886#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2887( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2888 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2889 2890/* This is how to output an insn to push a register on the stack. 2891 It need not be very fast code. */ 2892 2893#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2894do { \ 2895 if (TARGET_64BIT) \ 2896 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2897 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2898 else \ 2899 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2900} while (0) 2901 2902/* This is how to output an insn to pop a register from the stack. 2903 It need not be very fast code. */ 2904 2905#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2906do { \ 2907 if (TARGET_64BIT) \ 2908 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2909 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2910 else \ 2911 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2912} while (0) 2913 2914/* This is how to output an element of a case-vector that is absolute. */ 2915 2916#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2917 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2918 2919/* This is how to output an element of a case-vector that is relative. */ 2920 2921#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2922 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2923 2924/* Under some conditions we need jump tables in the text section, because 2925 the assembler cannot handle label differences between sections. */ 2926 2927#define JUMP_TABLES_IN_TEXT_SECTION \ 2928 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 2929 2930/* A C statement that outputs an address constant appropriate to 2931 for DWARF debugging. */ 2932 2933#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ 2934 i386_dwarf_output_addr_const ((FILE), (X)) 2935 2936/* Either simplify a location expression, or return the original. */ 2937 2938#define ASM_SIMPLIFY_DWARF_ADDR(X) \ 2939 i386_simplify_dwarf_addr (X) 2940 2941/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2942 and switch back. For x86 we do this only to save a few bytes that 2943 would otherwise be unused in the text section. */ 2944#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2945 asm (SECTION_OP "\n\t" \ 2946 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2947 TEXT_SECTION_ASM_OP); 2948 2949/* Print operand X (an rtx) in assembler syntax to file FILE. 2950 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2951 Effect of various CODE letters is described in i386.c near 2952 print_operand function. */ 2953 2954#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2955 ((CODE) == '*' || (CODE) == '+') 2956 2957/* Print the name of a register based on its machine mode and number. 2958 If CODE is 'w', pretend the mode is HImode. 2959 If CODE is 'b', pretend the mode is QImode. 2960 If CODE is 'k', pretend the mode is SImode. 2961 If CODE is 'q', pretend the mode is DImode. 2962 If CODE is 'h', pretend the reg is the `high' byte register. 2963 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ 2964 2965#define PRINT_REG(X, CODE, FILE) \ 2966 print_reg ((X), (CODE), (FILE)) 2967 2968#define PRINT_OPERAND(FILE, X, CODE) \ 2969 print_operand ((FILE), (X), (CODE)) 2970 2971#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2972 print_operand_address ((FILE), (ADDR)) 2973 2974/* Print the name of a register for based on its machine mode and number. 2975 This macro is used to print debugging output. 2976 This macro is different from PRINT_REG in that it may be used in 2977 programs that are not linked with aux-output.o. */ 2978 2979#define DEBUG_PRINT_REG(X, CODE, FILE) \ 2980 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ 2981 static const char * const qi_name[] = QI_REGISTER_NAMES; \ 2982 fprintf ((FILE), "%d ", REGNO (X)); \ 2983 if (REGNO (X) == FLAGS_REG) \ 2984 { fputs ("flags", (FILE)); break; } \ 2985 if (REGNO (X) == DIRFLAG_REG) \ 2986 { fputs ("dirflag", (FILE)); break; } \ 2987 if (REGNO (X) == FPSR_REG) \ 2988 { fputs ("fpsr", (FILE)); break; } \ 2989 if (REGNO (X) == ARG_POINTER_REGNUM) \ 2990 { fputs ("argp", (FILE)); break; } \ 2991 if (REGNO (X) == FRAME_POINTER_REGNUM) \ 2992 { fputs ("frame", (FILE)); break; } \ 2993 if (STACK_TOP_P (X)) \ 2994 { fputs ("st(0)", (FILE)); break; } \ 2995 if (FP_REG_P (X)) \ 2996 { fputs (hi_name[REGNO(X)], (FILE)); break; } \ 2997 if (REX_INT_REG_P (X)) \ 2998 { \ 2999 switch (GET_MODE_SIZE (GET_MODE (X))) \ 3000 { \ 3001 default: \ 3002 case 8: \ 3003 fprintf ((FILE), "r%i", REGNO (X) \ 3004 - FIRST_REX_INT_REG + 8); \ 3005 break; \ 3006 case 4: \ 3007 fprintf ((FILE), "r%id", REGNO (X) \ 3008 - FIRST_REX_INT_REG + 8); \ 3009 break; \ 3010 case 2: \ 3011 fprintf ((FILE), "r%iw", REGNO (X) \ 3012 - FIRST_REX_INT_REG + 8); \ 3013 break; \ 3014 case 1: \ 3015 fprintf ((FILE), "r%ib", REGNO (X) \ 3016 - FIRST_REX_INT_REG + 8); \ 3017 break; \ 3018 } \ 3019 break; \ 3020 } \ 3021 switch (GET_MODE_SIZE (GET_MODE (X))) \ 3022 { \ 3023 case 8: \ 3024 fputs ("r", (FILE)); \ 3025 fputs (hi_name[REGNO (X)], (FILE)); \ 3026 break; \ 3027 default: \ 3028 fputs ("e", (FILE)); \ 3029 case 2: \ 3030 fputs (hi_name[REGNO (X)], (FILE)); \ 3031 break; \ 3032 case 1: \ 3033 fputs (qi_name[REGNO (X)], (FILE)); \ 3034 break; \ 3035 } \ 3036 } while (0) 3037 3038/* a letter which is not needed by the normal asm syntax, which 3039 we can use for operand syntax in the extended asm */ 3040 3041#define ASM_OPERAND_LETTER '#' 3042#define RET return "" 3043#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 3044 3045/* Define the codes that are matched by predicates in i386.c. */ 3046 3047#define PREDICATE_CODES \ 3048 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ 3049 SYMBOL_REF, LABEL_REF, CONST}}, \ 3050 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3051 SYMBOL_REF, LABEL_REF, CONST}}, \ 3052 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ 3053 SYMBOL_REF, LABEL_REF, CONST}}, \ 3054 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3055 SYMBOL_REF, LABEL_REF, CONST}}, \ 3056 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3057 SYMBOL_REF, LABEL_REF, CONST}}, \ 3058 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3059 SYMBOL_REF, LABEL_REF, CONST}}, \ 3060 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3061 SYMBOL_REF, LABEL_REF}}, \ 3062 {"shiftdi_operand", {SUBREG, REG, MEM}}, \ 3063 {"const_int_1_operand", {CONST_INT}}, \ 3064 {"const_int_1_31_operand", {CONST_INT}}, \ 3065 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 3066 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3067 LABEL_REF, SUBREG, REG, MEM}}, \ 3068 {"pic_symbolic_operand", {CONST}}, \ 3069 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ 3070 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ 3071 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ 3072 {"const1_operand", {CONST_INT}}, \ 3073 {"const248_operand", {CONST_INT}}, \ 3074 {"incdec_operand", {CONST_INT}}, \ 3075 {"mmx_reg_operand", {REG}}, \ 3076 {"reg_no_sp_operand", {SUBREG, REG}}, \ 3077 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3078 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ 3079 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ 3080 {"q_regs_operand", {SUBREG, REG}}, \ 3081 {"non_q_regs_operand", {SUBREG, REG}}, \ 3082 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ 3083 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ 3084 GE, UNGE, LTGT, UNEQ}}, \ 3085 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ 3086 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ 3087 }}, \ 3088 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ 3089 GTU, UNORDERED, ORDERED, UNLE, UNLT, \ 3090 UNGE, UNGT, LTGT, UNEQ }}, \ 3091 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ 3092 {"ext_register_operand", {SUBREG, REG}}, \ 3093 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ 3094 {"mult_operator", {MULT}}, \ 3095 {"div_operator", {DIV}}, \ 3096 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ 3097 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ 3098 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ 3099 LSHIFTRT, ROTATERT}}, \ 3100 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ 3101 {"memory_displacement_operand", {MEM}}, \ 3102 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3103 LABEL_REF, SUBREG, REG, MEM, AND}}, \ 3104 {"long_memory_operand", {MEM}}, 3105 3106/* A list of predicates that do special things with modes, and so 3107 should not elicit warnings for VOIDmode match_operand. */ 3108 3109#define SPECIAL_MODE_PREDICATES \ 3110 "ext_register_operand", 3111 3112/* CM_32 is used by 32bit ABI 3113 CM_SMALL is small model assuming that all code and data fits in the first 3114 31bits of address space. 3115 CM_KERNEL is model assuming that all code and data fits in the negative 3116 31bits of address space. 3117 CM_MEDIUM is model assuming that code fits in the first 31bits of address 3118 space. Size of data is unlimited. 3119 CM_LARGE is model making no assumptions about size of particular sections. 3120 3121 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt 3122 tables first in 31bits of address space. 3123 */ 3124enum cmodel { 3125 CM_32, 3126 CM_SMALL, 3127 CM_KERNEL, 3128 CM_MEDIUM, 3129 CM_LARGE, 3130 CM_SMALL_PIC 3131}; 3132 3133/* Size of the RED_ZONE area. */ 3134#define RED_ZONE_SIZE 128 3135/* Reserved area of the red zone for temporaries. */ 3136#define RED_ZONE_RESERVE 8 3137extern const char *ix86_debug_arg_string, *ix86_debug_addr_string; 3138 3139enum asm_dialect { 3140 ASM_ATT, 3141 ASM_INTEL 3142}; 3143extern const char *ix86_asm_string; 3144extern enum asm_dialect ix86_asm_dialect; 3145/* Value of -mcmodel specified by user. */ 3146extern const char *ix86_cmodel_string; 3147extern enum cmodel ix86_cmodel; 3148 3149/* Variables in i386.c */ 3150extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */ 3151extern const char *ix86_arch_string; /* for -march=<xxx> */ 3152extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */ 3153extern const char *ix86_regparm_string; /* # registers to use to pass args */ 3154extern const char *ix86_align_loops_string; /* power of two alignment for loops */ 3155extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */ 3156extern const char *ix86_align_funcs_string; /* power of two alignment for functions */ 3157extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */ 3158extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */ 3159extern int ix86_regparm; /* ix86_regparm_string as a number */ 3160extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */ 3161extern int ix86_branch_cost; /* values 1-5: see jump.c */ 3162extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */ 3163extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 3164extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 3165 3166/* To properly truncate FP values into integers, we need to set i387 control 3167 word. We can't emit proper mode switching code before reload, as spills 3168 generated by reload may truncate values incorrectly, but we still can avoid 3169 redundant computation of new control word by the mode switching pass. 3170 The fldcw instructions are still emitted redundantly, but this is probably 3171 not going to be noticeable problem, as most CPUs do have fast path for 3172 the sequence. 3173 3174 The machinery is to emit simple truncation instructions and split them 3175 before reload to instructions having USEs of two memory locations that 3176 are filled by this code to old and new control word. 3177 3178 Post-reload pass may be later used to eliminate the redundant fildcw if 3179 needed. */ 3180 3181enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; 3182 3183/* Define this macro if the port needs extra instructions inserted 3184 for mode switching in an optimizing compilation. */ 3185 3186#define OPTIMIZE_MODE_SWITCHING(ENTITY) 1 3187 3188/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 3189 initializer for an array of integers. Each initializer element N 3190 refers to an entity that needs mode switching, and specifies the 3191 number of different modes that might need to be set for this 3192 entity. The position of the initializer in the initializer - 3193 starting counting at zero - determines the integer that is used to 3194 refer to the mode-switched entity in question. */ 3195 3196#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } 3197 3198/* ENTITY is an integer specifying a mode-switched entity. If 3199 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 3200 return an integer value not larger than the corresponding element 3201 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 3202 must be switched into prior to the execution of INSN. */ 3203 3204#define MODE_NEEDED(ENTITY, I) \ 3205 (GET_CODE (I) == CALL_INSN \ 3206 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ 3207 || GET_CODE (PATTERN (I)) == ASM_INPUT))\ 3208 ? FP_CW_UNINITIALIZED \ 3209 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ 3210 ? FP_CW_ANY \ 3211 : FP_CW_STORED) 3212 3213/* This macro specifies the order in which modes for ENTITY are 3214 processed. 0 is the highest priority. */ 3215 3216#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 3217 3218/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 3219 is the set of hard registers live at the point where the insn(s) 3220 are to be inserted. */ 3221 3222#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3223 ((MODE) == FP_CW_STORED \ 3224 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ 3225 assign_386_stack_local (HImode, 2)), 0\ 3226 : 0) 3227 3228/* Avoid renaming of stack registers, as doing so in combination with 3229 scheduling just increases amount of live registers at time and in 3230 the turn amount of fxch instructions needed. 3231 3232 ??? Maybe Pentium chips benefits from renaming, someone can try... */ 3233 3234#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 3235 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 3236 3237 3238/* 3239Local variables: 3240version-control: t 3241End: 3242*/ 3243