1;; Patterns for the Intel Wireless MMX technology architecture. 2;; Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc. 3;; Contributed by Red Hat. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it under 8;; the terms of the GNU General Public License as published by the Free 9;; Software Foundation; either version 2, or (at your option) any later 10;; version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20;; Boston, MA 02110-1301, USA. 21 22(define_insn "iwmmxt_iordi3" 23 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") 24 (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r") 25 (match_operand:DI 2 "register_operand" "y,r,r")))] 26 "TARGET_REALLY_IWMMXT" 27 "@ 28 wor%?\\t%0, %1, %2 29 # 30 #" 31 [(set_attr "predicable" "yes") 32 (set_attr "length" "4,8,8")]) 33 34(define_insn "iwmmxt_xordi3" 35 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") 36 (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r") 37 (match_operand:DI 2 "register_operand" "y,r,r")))] 38 "TARGET_REALLY_IWMMXT" 39 "@ 40 wxor%?\\t%0, %1, %2 41 # 42 #" 43 [(set_attr "predicable" "yes") 44 (set_attr "length" "4,8,8")]) 45 46(define_insn "iwmmxt_anddi3" 47 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") 48 (and:DI (match_operand:DI 1 "register_operand" "%y,0,r") 49 (match_operand:DI 2 "register_operand" "y,r,r")))] 50 "TARGET_REALLY_IWMMXT" 51 "@ 52 wand%?\\t%0, %1, %2 53 # 54 #" 55 [(set_attr "predicable" "yes") 56 (set_attr "length" "4,8,8")]) 57 58(define_insn "iwmmxt_nanddi3" 59 [(set (match_operand:DI 0 "register_operand" "=y") 60 (and:DI (match_operand:DI 1 "register_operand" "y") 61 (not:DI (match_operand:DI 2 "register_operand" "y"))))] 62 "TARGET_REALLY_IWMMXT" 63 "wandn%?\\t%0, %1, %2" 64 [(set_attr "predicable" "yes")]) 65 66(define_insn "*iwmmxt_arm_movdi" 67 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy") 68 (match_operand:DI 1 "di_operand" "rIK,mi,r,y,yr,y,yrUy,y"))] 69 "TARGET_REALLY_IWMMXT 70 && ( register_operand (operands[0], DImode) 71 || register_operand (operands[1], DImode))" 72 "* 73{ 74 switch (which_alternative) 75 { 76 default: 77 return output_move_double (operands); 78 case 0: 79 return \"#\"; 80 case 3: 81 return \"wmov%?\\t%0,%1\"; 82 case 4: 83 return \"tmcrr%?\\t%0,%Q1,%R1\"; 84 case 5: 85 return \"tmrrc%?\\t%Q0,%R0,%1\"; 86 case 6: 87 return \"wldrd%?\\t%0,%1\"; 88 case 7: 89 return \"wstrd%?\\t%1,%0\"; 90 } 91}" 92 [(set_attr "length" "8,8,8,4,4,4,4,4") 93 (set_attr "type" "*,load1,store2,*,*,*,*,*") 94 (set_attr "pool_range" "*,1020,*,*,*,*,*,*") 95 (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")] 96) 97 98(define_insn "*iwmmxt_movsi_insn" 99 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,Uy,z") 100 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z,Uy,z,z"))] 101 "TARGET_REALLY_IWMMXT 102 && ( register_operand (operands[0], SImode) 103 || register_operand (operands[1], SImode))" 104 "* 105 switch (which_alternative) 106 { 107 case 0: return \"mov\\t%0, %1\"; 108 case 1: return \"mvn\\t%0, #%B1\"; 109 case 2: return \"ldr\\t%0, %1\"; 110 case 3: return \"str\\t%1, %0\"; 111 case 4: return \"tmcr\\t%0, %1\"; 112 case 5: return \"tmrc\\t%0, %1\"; 113 case 6: return arm_output_load_gr (operands); 114 case 7: return \"wstrw\\t%1, %0\"; 115 default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\"; 116 }" 117 [(set_attr "type" "*,*,load1,store1,*,*,load1,store1,*") 118 (set_attr "length" "*,*,*, *,*,*, 16, *,8") 119 (set_attr "pool_range" "*,*,4096, *,*,*,1024, *,*") 120 (set_attr "neg_pool_range" "*,*,4084, *,*,*, *, 1012,*") 121 ;; Note - the "predicable" attribute is not allowed to have alternatives. 122 ;; Since the wSTRw wCx instruction is not predicable, we cannot support 123 ;; predicating any of the alternatives in this template. Instead, 124 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn. 125 (set_attr "predicable" "no") 126 ;; Also - we have to pretend that these insns clobber the condition code 127 ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize 128 ;; them. 129 (set_attr "conds" "clob")] 130) 131 132;; Because iwmmxt_movsi_insn is not predicable, we provide the 133;; cond_exec version explicitly, with appropriate constraints. 134 135(define_insn "*cond_iwmmxt_movsi_insn" 136 [(cond_exec 137 (match_operator 2 "arm_comparison_operator" 138 [(match_operand 3 "cc_register" "") 139 (const_int 0)]) 140 (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r") 141 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))] 142 "TARGET_REALLY_IWMMXT 143 && ( register_operand (operands[0], SImode) 144 || register_operand (operands[1], SImode))" 145 "* 146 switch (which_alternative) 147 { 148 case 0: return \"mov%?\\t%0, %1\"; 149 case 1: return \"mvn%?\\t%0, #%B1\"; 150 case 2: return \"ldr%?\\t%0, %1\"; 151 case 3: return \"str%?\\t%1, %0\"; 152 case 4: return \"tmcr%?\\t%0, %1\"; 153 default: return \"tmrc%?\\t%0, %1\"; 154 }" 155 [(set_attr "type" "*,*,load1,store1,*,*") 156 (set_attr "pool_range" "*,*,4096, *,*,*") 157 (set_attr "neg_pool_range" "*,*,4084, *,*,*")] 158) 159 160(define_insn "movv8qi_internal" 161 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r") 162 (match_operand:V8QI 1 "general_operand" "y,y,mi,y,r,mi"))] 163 "TARGET_REALLY_IWMMXT" 164 "* 165 switch (which_alternative) 166 { 167 case 0: return \"wmov%?\\t%0, %1\"; 168 case 1: return \"wstrd%?\\t%1, %0\"; 169 case 2: return \"wldrd%?\\t%0, %1\"; 170 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; 171 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; 172 default: return output_move_double (operands); 173 }" 174 [(set_attr "predicable" "yes") 175 (set_attr "length" "4, 4, 4,4,4, 8") 176 (set_attr "type" "*,store1,load1,*,*,load1") 177 (set_attr "pool_range" "*, *, 256,*,*, 256") 178 (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) 179 180(define_insn "movv4hi_internal" 181 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r") 182 (match_operand:V4HI 1 "general_operand" "y,y,mi,y,r,mi"))] 183 "TARGET_REALLY_IWMMXT" 184 "* 185 switch (which_alternative) 186 { 187 case 0: return \"wmov%?\\t%0, %1\"; 188 case 1: return \"wstrd%?\\t%1, %0\"; 189 case 2: return \"wldrd%?\\t%0, %1\"; 190 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; 191 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; 192 default: return output_move_double (operands); 193 }" 194 [(set_attr "predicable" "yes") 195 (set_attr "length" "4, 4, 4,4,4, 8") 196 (set_attr "type" "*,store1,load1,*,*,load1") 197 (set_attr "pool_range" "*, *, 256,*,*, 256") 198 (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) 199 200(define_insn "movv2si_internal" 201 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r") 202 (match_operand:V2SI 1 "general_operand" "y,y,mi,y,r,mi"))] 203 "TARGET_REALLY_IWMMXT" 204 "* 205 switch (which_alternative) 206 { 207 case 0: return \"wmov%?\\t%0, %1\"; 208 case 1: return \"wstrd%?\\t%1, %0\"; 209 case 2: return \"wldrd%?\\t%0, %1\"; 210 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; 211 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; 212 default: return output_move_double (operands); 213 }" 214 [(set_attr "predicable" "yes") 215 (set_attr "length" "4, 4, 4,4,4, 24") 216 (set_attr "type" "*,store1,load1,*,*,load1") 217 (set_attr "pool_range" "*, *, 256,*,*, 256") 218 (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) 219 220;; This pattern should not be needed. It is to match a 221;; wierd case generated by GCC when no optimizations are 222;; enabled. (Try compiling gcc/testsuite/gcc.c-torture/ 223;; compile/simd-5.c at -O0). The mode for operands[1] is 224;; deliberately omitted. 225(define_insn "movv2si_internal_2" 226 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r") 227 (match_operand 1 "immediate_operand" "mi"))] 228 "TARGET_REALLY_IWMMXT" 229 "* return output_move_double (operands);" 230 [(set_attr "predicable" "yes") 231 (set_attr "length" "8") 232 (set_attr "type" "load1") 233 (set_attr "pool_range" "256") 234 (set_attr "neg_pool_range" "244")]) 235 236;; Vector add/subtract 237 238(define_insn "addv8qi3" 239 [(set (match_operand:V8QI 0 "register_operand" "=y") 240 (plus:V8QI (match_operand:V8QI 1 "register_operand" "y") 241 (match_operand:V8QI 2 "register_operand" "y")))] 242 "TARGET_REALLY_IWMMXT" 243 "waddb%?\\t%0, %1, %2" 244 [(set_attr "predicable" "yes")]) 245 246(define_insn "addv4hi3" 247 [(set (match_operand:V4HI 0 "register_operand" "=y") 248 (plus:V4HI (match_operand:V4HI 1 "register_operand" "y") 249 (match_operand:V4HI 2 "register_operand" "y")))] 250 "TARGET_REALLY_IWMMXT" 251 "waddh%?\\t%0, %1, %2" 252 [(set_attr "predicable" "yes")]) 253 254(define_insn "addv2si3" 255 [(set (match_operand:V2SI 0 "register_operand" "=y") 256 (plus:V2SI (match_operand:V2SI 1 "register_operand" "y") 257 (match_operand:V2SI 2 "register_operand" "y")))] 258 "TARGET_REALLY_IWMMXT" 259 "waddw%?\\t%0, %1, %2" 260 [(set_attr "predicable" "yes")]) 261 262(define_insn "ssaddv8qi3" 263 [(set (match_operand:V8QI 0 "register_operand" "=y") 264 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") 265 (match_operand:V8QI 2 "register_operand" "y")))] 266 "TARGET_REALLY_IWMMXT" 267 "waddbss%?\\t%0, %1, %2" 268 [(set_attr "predicable" "yes")]) 269 270(define_insn "ssaddv4hi3" 271 [(set (match_operand:V4HI 0 "register_operand" "=y") 272 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") 273 (match_operand:V4HI 2 "register_operand" "y")))] 274 "TARGET_REALLY_IWMMXT" 275 "waddhss%?\\t%0, %1, %2" 276 [(set_attr "predicable" "yes")]) 277 278(define_insn "ssaddv2si3" 279 [(set (match_operand:V2SI 0 "register_operand" "=y") 280 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") 281 (match_operand:V2SI 2 "register_operand" "y")))] 282 "TARGET_REALLY_IWMMXT" 283 "waddwss%?\\t%0, %1, %2" 284 [(set_attr "predicable" "yes")]) 285 286(define_insn "usaddv8qi3" 287 [(set (match_operand:V8QI 0 "register_operand" "=y") 288 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") 289 (match_operand:V8QI 2 "register_operand" "y")))] 290 "TARGET_REALLY_IWMMXT" 291 "waddbus%?\\t%0, %1, %2" 292 [(set_attr "predicable" "yes")]) 293 294(define_insn "usaddv4hi3" 295 [(set (match_operand:V4HI 0 "register_operand" "=y") 296 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") 297 (match_operand:V4HI 2 "register_operand" "y")))] 298 "TARGET_REALLY_IWMMXT" 299 "waddhus%?\\t%0, %1, %2" 300 [(set_attr "predicable" "yes")]) 301 302(define_insn "usaddv2si3" 303 [(set (match_operand:V2SI 0 "register_operand" "=y") 304 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") 305 (match_operand:V2SI 2 "register_operand" "y")))] 306 "TARGET_REALLY_IWMMXT" 307 "waddwus%?\\t%0, %1, %2" 308 [(set_attr "predicable" "yes")]) 309 310(define_insn "subv8qi3" 311 [(set (match_operand:V8QI 0 "register_operand" "=y") 312 (minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 313 (match_operand:V8QI 2 "register_operand" "y")))] 314 "TARGET_REALLY_IWMMXT" 315 "wsubb%?\\t%0, %1, %2" 316 [(set_attr "predicable" "yes")]) 317 318(define_insn "subv4hi3" 319 [(set (match_operand:V4HI 0 "register_operand" "=y") 320 (minus:V4HI (match_operand:V4HI 1 "register_operand" "y") 321 (match_operand:V4HI 2 "register_operand" "y")))] 322 "TARGET_REALLY_IWMMXT" 323 "wsubh%?\\t%0, %1, %2" 324 [(set_attr "predicable" "yes")]) 325 326(define_insn "subv2si3" 327 [(set (match_operand:V2SI 0 "register_operand" "=y") 328 (minus:V2SI (match_operand:V2SI 1 "register_operand" "y") 329 (match_operand:V2SI 2 "register_operand" "y")))] 330 "TARGET_REALLY_IWMMXT" 331 "wsubw%?\\t%0, %1, %2" 332 [(set_attr "predicable" "yes")]) 333 334(define_insn "sssubv8qi3" 335 [(set (match_operand:V8QI 0 "register_operand" "=y") 336 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 337 (match_operand:V8QI 2 "register_operand" "y")))] 338 "TARGET_REALLY_IWMMXT" 339 "wsubbss%?\\t%0, %1, %2" 340 [(set_attr "predicable" "yes")]) 341 342(define_insn "sssubv4hi3" 343 [(set (match_operand:V4HI 0 "register_operand" "=y") 344 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") 345 (match_operand:V4HI 2 "register_operand" "y")))] 346 "TARGET_REALLY_IWMMXT" 347 "wsubhss%?\\t%0, %1, %2" 348 [(set_attr "predicable" "yes")]) 349 350(define_insn "sssubv2si3" 351 [(set (match_operand:V2SI 0 "register_operand" "=y") 352 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") 353 (match_operand:V2SI 2 "register_operand" "y")))] 354 "TARGET_REALLY_IWMMXT" 355 "wsubwss%?\\t%0, %1, %2" 356 [(set_attr "predicable" "yes")]) 357 358(define_insn "ussubv8qi3" 359 [(set (match_operand:V8QI 0 "register_operand" "=y") 360 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 361 (match_operand:V8QI 2 "register_operand" "y")))] 362 "TARGET_REALLY_IWMMXT" 363 "wsubbus%?\\t%0, %1, %2" 364 [(set_attr "predicable" "yes")]) 365 366(define_insn "ussubv4hi3" 367 [(set (match_operand:V4HI 0 "register_operand" "=y") 368 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") 369 (match_operand:V4HI 2 "register_operand" "y")))] 370 "TARGET_REALLY_IWMMXT" 371 "wsubhus%?\\t%0, %1, %2" 372 [(set_attr "predicable" "yes")]) 373 374(define_insn "ussubv2si3" 375 [(set (match_operand:V2SI 0 "register_operand" "=y") 376 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") 377 (match_operand:V2SI 2 "register_operand" "y")))] 378 "TARGET_REALLY_IWMMXT" 379 "wsubwus%?\\t%0, %1, %2" 380 [(set_attr "predicable" "yes")]) 381 382(define_insn "mulv4hi3" 383 [(set (match_operand:V4HI 0 "register_operand" "=y") 384 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y") 385 (match_operand:V4HI 2 "register_operand" "y")))] 386 "TARGET_REALLY_IWMMXT" 387 "wmulul%?\\t%0, %1, %2" 388 [(set_attr "predicable" "yes")]) 389 390(define_insn "smulv4hi3_highpart" 391 [(set (match_operand:V4HI 0 "register_operand" "=y") 392 (truncate:V4HI 393 (lshiftrt:V4SI 394 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) 395 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) 396 (const_int 16))))] 397 "TARGET_REALLY_IWMMXT" 398 "wmulsm%?\\t%0, %1, %2" 399 [(set_attr "predicable" "yes")]) 400 401(define_insn "umulv4hi3_highpart" 402 [(set (match_operand:V4HI 0 "register_operand" "=y") 403 (truncate:V4HI 404 (lshiftrt:V4SI 405 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) 406 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) 407 (const_int 16))))] 408 "TARGET_REALLY_IWMMXT" 409 "wmulum%?\\t%0, %1, %2" 410 [(set_attr "predicable" "yes")]) 411 412(define_insn "iwmmxt_wmacs" 413 [(set (match_operand:DI 0 "register_operand" "=y") 414 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 415 (match_operand:V4HI 2 "register_operand" "y") 416 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))] 417 "TARGET_REALLY_IWMMXT" 418 "wmacs%?\\t%0, %2, %3" 419 [(set_attr "predicable" "yes")]) 420 421(define_insn "iwmmxt_wmacsz" 422 [(set (match_operand:DI 0 "register_operand" "=y") 423 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") 424 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))] 425 "TARGET_REALLY_IWMMXT" 426 "wmacsz%?\\t%0, %1, %2" 427 [(set_attr "predicable" "yes")]) 428 429(define_insn "iwmmxt_wmacu" 430 [(set (match_operand:DI 0 "register_operand" "=y") 431 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 432 (match_operand:V4HI 2 "register_operand" "y") 433 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))] 434 "TARGET_REALLY_IWMMXT" 435 "wmacu%?\\t%0, %2, %3" 436 [(set_attr "predicable" "yes")]) 437 438(define_insn "iwmmxt_wmacuz" 439 [(set (match_operand:DI 0 "register_operand" "=y") 440 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") 441 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))] 442 "TARGET_REALLY_IWMMXT" 443 "wmacuz%?\\t%0, %1, %2" 444 [(set_attr "predicable" "yes")]) 445 446;; Same as xordi3, but don't show input operands so that we don't think 447;; they are live. 448(define_insn "iwmmxt_clrdi" 449 [(set (match_operand:DI 0 "register_operand" "=y") 450 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))] 451 "TARGET_REALLY_IWMMXT" 452 "wxor%?\\t%0, %0, %0" 453 [(set_attr "predicable" "yes")]) 454 455;; Seems like cse likes to generate these, so we have to support them. 456 457(define_insn "*iwmmxt_clrv8qi" 458 [(set (match_operand:V8QI 0 "register_operand" "=y") 459 (const_vector:V8QI [(const_int 0) (const_int 0) 460 (const_int 0) (const_int 0) 461 (const_int 0) (const_int 0) 462 (const_int 0) (const_int 0)]))] 463 "TARGET_REALLY_IWMMXT" 464 "wxor%?\\t%0, %0, %0" 465 [(set_attr "predicable" "yes")]) 466 467(define_insn "*iwmmxt_clrv4hi" 468 [(set (match_operand:V4HI 0 "register_operand" "=y") 469 (const_vector:V4HI [(const_int 0) (const_int 0) 470 (const_int 0) (const_int 0)]))] 471 "TARGET_REALLY_IWMMXT" 472 "wxor%?\\t%0, %0, %0" 473 [(set_attr "predicable" "yes")]) 474 475(define_insn "*iwmmxt_clrv2si" 476 [(set (match_operand:V2SI 0 "register_operand" "=y") 477 (const_vector:V2SI [(const_int 0) (const_int 0)]))] 478 "TARGET_REALLY_IWMMXT" 479 "wxor%?\\t%0, %0, %0" 480 [(set_attr "predicable" "yes")]) 481 482;; Unsigned averages/sum of absolute differences 483 484(define_insn "iwmmxt_uavgrndv8qi3" 485 [(set (match_operand:V8QI 0 "register_operand" "=y") 486 (ashiftrt:V8QI 487 (plus:V8QI (plus:V8QI 488 (match_operand:V8QI 1 "register_operand" "y") 489 (match_operand:V8QI 2 "register_operand" "y")) 490 (const_vector:V8QI [(const_int 1) 491 (const_int 1) 492 (const_int 1) 493 (const_int 1) 494 (const_int 1) 495 (const_int 1) 496 (const_int 1) 497 (const_int 1)])) 498 (const_int 1)))] 499 "TARGET_REALLY_IWMMXT" 500 "wavg2br%?\\t%0, %1, %2" 501 [(set_attr "predicable" "yes")]) 502 503(define_insn "iwmmxt_uavgrndv4hi3" 504 [(set (match_operand:V4HI 0 "register_operand" "=y") 505 (ashiftrt:V4HI 506 (plus:V4HI (plus:V4HI 507 (match_operand:V4HI 1 "register_operand" "y") 508 (match_operand:V4HI 2 "register_operand" "y")) 509 (const_vector:V4HI [(const_int 1) 510 (const_int 1) 511 (const_int 1) 512 (const_int 1)])) 513 (const_int 1)))] 514 "TARGET_REALLY_IWMMXT" 515 "wavg2hr%?\\t%0, %1, %2" 516 [(set_attr "predicable" "yes")]) 517 518 519(define_insn "iwmmxt_uavgv8qi3" 520 [(set (match_operand:V8QI 0 "register_operand" "=y") 521 (ashiftrt:V8QI (plus:V8QI 522 (match_operand:V8QI 1 "register_operand" "y") 523 (match_operand:V8QI 2 "register_operand" "y")) 524 (const_int 1)))] 525 "TARGET_REALLY_IWMMXT" 526 "wavg2b%?\\t%0, %1, %2" 527 [(set_attr "predicable" "yes")]) 528 529(define_insn "iwmmxt_uavgv4hi3" 530 [(set (match_operand:V4HI 0 "register_operand" "=y") 531 (ashiftrt:V4HI (plus:V4HI 532 (match_operand:V4HI 1 "register_operand" "y") 533 (match_operand:V4HI 2 "register_operand" "y")) 534 (const_int 1)))] 535 "TARGET_REALLY_IWMMXT" 536 "wavg2h%?\\t%0, %1, %2" 537 [(set_attr "predicable" "yes")]) 538 539(define_insn "iwmmxt_psadbw" 540 [(set (match_operand:V8QI 0 "register_operand" "=y") 541 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 542 (match_operand:V8QI 2 "register_operand" "y"))))] 543 "TARGET_REALLY_IWMMXT" 544 "psadbw%?\\t%0, %1, %2" 545 [(set_attr "predicable" "yes")]) 546 547 548;; Insert/extract/shuffle 549 550(define_insn "iwmmxt_tinsrb" 551 [(set (match_operand:V8QI 0 "register_operand" "=y") 552 (vec_merge:V8QI (match_operand:V8QI 1 "register_operand" "0") 553 (vec_duplicate:V8QI 554 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r"))) 555 (match_operand:SI 3 "immediate_operand" "i")))] 556 "TARGET_REALLY_IWMMXT" 557 "tinsrb%?\\t%0, %2, %3" 558 [(set_attr "predicable" "yes")]) 559 560(define_insn "iwmmxt_tinsrh" 561 [(set (match_operand:V4HI 0 "register_operand" "=y") 562 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0") 563 (vec_duplicate:V4HI 564 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r"))) 565 (match_operand:SI 3 "immediate_operand" "i")))] 566 "TARGET_REALLY_IWMMXT" 567 "tinsrh%?\\t%0, %2, %3" 568 [(set_attr "predicable" "yes")]) 569 570(define_insn "iwmmxt_tinsrw" 571 [(set (match_operand:V2SI 0 "register_operand" "=y") 572 (vec_merge:V2SI (match_operand:V2SI 1 "register_operand" "0") 573 (vec_duplicate:V2SI 574 (match_operand:SI 2 "nonimmediate_operand" "r")) 575 (match_operand:SI 3 "immediate_operand" "i")))] 576 "TARGET_REALLY_IWMMXT" 577 "tinsrw%?\\t%0, %2, %3" 578 [(set_attr "predicable" "yes")]) 579 580(define_insn "iwmmxt_textrmub" 581 [(set (match_operand:SI 0 "register_operand" "=r") 582 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") 583 (parallel 584 [(match_operand:SI 2 "immediate_operand" "i")]))))] 585 "TARGET_REALLY_IWMMXT" 586 "textrmub%?\\t%0, %1, %2" 587 [(set_attr "predicable" "yes")]) 588 589(define_insn "iwmmxt_textrmsb" 590 [(set (match_operand:SI 0 "register_operand" "=r") 591 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") 592 (parallel 593 [(match_operand:SI 2 "immediate_operand" "i")]))))] 594 "TARGET_REALLY_IWMMXT" 595 "textrmsb%?\\t%0, %1, %2" 596 [(set_attr "predicable" "yes")]) 597 598(define_insn "iwmmxt_textrmuh" 599 [(set (match_operand:SI 0 "register_operand" "=r") 600 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") 601 (parallel 602 [(match_operand:SI 2 "immediate_operand" "i")]))))] 603 "TARGET_REALLY_IWMMXT" 604 "textrmuh%?\\t%0, %1, %2" 605 [(set_attr "predicable" "yes")]) 606 607(define_insn "iwmmxt_textrmsh" 608 [(set (match_operand:SI 0 "register_operand" "=r") 609 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") 610 (parallel 611 [(match_operand:SI 2 "immediate_operand" "i")]))))] 612 "TARGET_REALLY_IWMMXT" 613 "textrmsh%?\\t%0, %1, %2" 614 [(set_attr "predicable" "yes")]) 615 616;; There are signed/unsigned variants of this instruction, but they are 617;; pointless. 618(define_insn "iwmmxt_textrmw" 619 [(set (match_operand:SI 0 "register_operand" "=r") 620 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 621 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] 622 "TARGET_REALLY_IWMMXT" 623 "textrmsw%?\\t%0, %1, %2" 624 [(set_attr "predicable" "yes")]) 625 626(define_insn "iwmmxt_wshufh" 627 [(set (match_operand:V4HI 0 "register_operand" "=y") 628 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 629 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))] 630 "TARGET_REALLY_IWMMXT" 631 "wshufh%?\\t%0, %1, %2" 632 [(set_attr "predicable" "yes")]) 633 634;; Mask-generating comparisons 635;; 636;; Note - you cannot use patterns like these here: 637;; 638;; (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>))) 639;; 640;; Because GCC will assume that the truth value (1 or 0) is installed 641;; into the entire destination vector, (with the '1' going into the least 642;; significant element of the vector). This is not how these instructions 643;; behave. 644;; 645;; Unfortunately the current patterns are illegal. They are SET insns 646;; without a SET in them. They work in most cases for ordinary code 647;; generation, but there are circumstances where they can cause gcc to fail. 648;; XXX - FIXME. 649 650(define_insn "eqv8qi3" 651 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") 652 (match_operand:V8QI 1 "register_operand" "y") 653 (match_operand:V8QI 2 "register_operand" "y")] 654 VUNSPEC_WCMP_EQ)] 655 "TARGET_REALLY_IWMMXT" 656 "wcmpeqb%?\\t%0, %1, %2" 657 [(set_attr "predicable" "yes")]) 658 659(define_insn "eqv4hi3" 660 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") 661 (match_operand:V4HI 1 "register_operand" "y") 662 (match_operand:V4HI 2 "register_operand" "y")] 663 VUNSPEC_WCMP_EQ)] 664 "TARGET_REALLY_IWMMXT" 665 "wcmpeqh%?\\t%0, %1, %2" 666 [(set_attr "predicable" "yes")]) 667 668(define_insn "eqv2si3" 669 [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y") 670 (match_operand:V2SI 1 "register_operand" "y") 671 (match_operand:V2SI 2 "register_operand" "y")] 672 VUNSPEC_WCMP_EQ)] 673 "TARGET_REALLY_IWMMXT" 674 "wcmpeqw%?\\t%0, %1, %2" 675 [(set_attr "predicable" "yes")]) 676 677(define_insn "gtuv8qi3" 678 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") 679 (match_operand:V8QI 1 "register_operand" "y") 680 (match_operand:V8QI 2 "register_operand" "y")] 681 VUNSPEC_WCMP_GTU)] 682 "TARGET_REALLY_IWMMXT" 683 "wcmpgtub%?\\t%0, %1, %2" 684 [(set_attr "predicable" "yes")]) 685 686(define_insn "gtuv4hi3" 687 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") 688 (match_operand:V4HI 1 "register_operand" "y") 689 (match_operand:V4HI 2 "register_operand" "y")] 690 VUNSPEC_WCMP_GTU)] 691 "TARGET_REALLY_IWMMXT" 692 "wcmpgtuh%?\\t%0, %1, %2" 693 [(set_attr "predicable" "yes")]) 694 695(define_insn "gtuv2si3" 696 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y") 697 (match_operand:V2SI 1 "register_operand" "y") 698 (match_operand:V2SI 2 "register_operand" "y")] 699 VUNSPEC_WCMP_GTU)] 700 "TARGET_REALLY_IWMMXT" 701 "wcmpgtuw%?\\t%0, %1, %2" 702 [(set_attr "predicable" "yes")]) 703 704(define_insn "gtv8qi3" 705 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") 706 (match_operand:V8QI 1 "register_operand" "y") 707 (match_operand:V8QI 2 "register_operand" "y")] 708 VUNSPEC_WCMP_GT)] 709 "TARGET_REALLY_IWMMXT" 710 "wcmpgtsb%?\\t%0, %1, %2" 711 [(set_attr "predicable" "yes")]) 712 713(define_insn "gtv4hi3" 714 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") 715 (match_operand:V4HI 1 "register_operand" "y") 716 (match_operand:V4HI 2 "register_operand" "y")] 717 VUNSPEC_WCMP_GT)] 718 "TARGET_REALLY_IWMMXT" 719 "wcmpgtsh%?\\t%0, %1, %2" 720 [(set_attr "predicable" "yes")]) 721 722(define_insn "gtv2si3" 723 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y") 724 (match_operand:V2SI 1 "register_operand" "y") 725 (match_operand:V2SI 2 "register_operand" "y")] 726 VUNSPEC_WCMP_GT)] 727 "TARGET_REALLY_IWMMXT" 728 "wcmpgtsw%?\\t%0, %1, %2" 729 [(set_attr "predicable" "yes")]) 730 731;; Max/min insns 732 733(define_insn "smaxv8qi3" 734 [(set (match_operand:V8QI 0 "register_operand" "=y") 735 (smax:V8QI (match_operand:V8QI 1 "register_operand" "y") 736 (match_operand:V8QI 2 "register_operand" "y")))] 737 "TARGET_REALLY_IWMMXT" 738 "wmaxsb%?\\t%0, %1, %2" 739 [(set_attr "predicable" "yes")]) 740 741(define_insn "umaxv8qi3" 742 [(set (match_operand:V8QI 0 "register_operand" "=y") 743 (umax:V8QI (match_operand:V8QI 1 "register_operand" "y") 744 (match_operand:V8QI 2 "register_operand" "y")))] 745 "TARGET_REALLY_IWMMXT" 746 "wmaxub%?\\t%0, %1, %2" 747 [(set_attr "predicable" "yes")]) 748 749(define_insn "smaxv4hi3" 750 [(set (match_operand:V4HI 0 "register_operand" "=y") 751 (smax:V4HI (match_operand:V4HI 1 "register_operand" "y") 752 (match_operand:V4HI 2 "register_operand" "y")))] 753 "TARGET_REALLY_IWMMXT" 754 "wmaxsh%?\\t%0, %1, %2" 755 [(set_attr "predicable" "yes")]) 756 757(define_insn "umaxv4hi3" 758 [(set (match_operand:V4HI 0 "register_operand" "=y") 759 (umax:V4HI (match_operand:V4HI 1 "register_operand" "y") 760 (match_operand:V4HI 2 "register_operand" "y")))] 761 "TARGET_REALLY_IWMMXT" 762 "wmaxuh%?\\t%0, %1, %2" 763 [(set_attr "predicable" "yes")]) 764 765(define_insn "smaxv2si3" 766 [(set (match_operand:V2SI 0 "register_operand" "=y") 767 (smax:V2SI (match_operand:V2SI 1 "register_operand" "y") 768 (match_operand:V2SI 2 "register_operand" "y")))] 769 "TARGET_REALLY_IWMMXT" 770 "wmaxsw%?\\t%0, %1, %2" 771 [(set_attr "predicable" "yes")]) 772 773(define_insn "umaxv2si3" 774 [(set (match_operand:V2SI 0 "register_operand" "=y") 775 (umax:V2SI (match_operand:V2SI 1 "register_operand" "y") 776 (match_operand:V2SI 2 "register_operand" "y")))] 777 "TARGET_REALLY_IWMMXT" 778 "wmaxuw%?\\t%0, %1, %2" 779 [(set_attr "predicable" "yes")]) 780 781(define_insn "sminv8qi3" 782 [(set (match_operand:V8QI 0 "register_operand" "=y") 783 (smin:V8QI (match_operand:V8QI 1 "register_operand" "y") 784 (match_operand:V8QI 2 "register_operand" "y")))] 785 "TARGET_REALLY_IWMMXT" 786 "wminsb%?\\t%0, %1, %2" 787 [(set_attr "predicable" "yes")]) 788 789(define_insn "uminv8qi3" 790 [(set (match_operand:V8QI 0 "register_operand" "=y") 791 (umin:V8QI (match_operand:V8QI 1 "register_operand" "y") 792 (match_operand:V8QI 2 "register_operand" "y")))] 793 "TARGET_REALLY_IWMMXT" 794 "wminub%?\\t%0, %1, %2" 795 [(set_attr "predicable" "yes")]) 796 797(define_insn "sminv4hi3" 798 [(set (match_operand:V4HI 0 "register_operand" "=y") 799 (smin:V4HI (match_operand:V4HI 1 "register_operand" "y") 800 (match_operand:V4HI 2 "register_operand" "y")))] 801 "TARGET_REALLY_IWMMXT" 802 "wminsh%?\\t%0, %1, %2" 803 [(set_attr "predicable" "yes")]) 804 805(define_insn "uminv4hi3" 806 [(set (match_operand:V4HI 0 "register_operand" "=y") 807 (umin:V4HI (match_operand:V4HI 1 "register_operand" "y") 808 (match_operand:V4HI 2 "register_operand" "y")))] 809 "TARGET_REALLY_IWMMXT" 810 "wminuh%?\\t%0, %1, %2" 811 [(set_attr "predicable" "yes")]) 812 813(define_insn "sminv2si3" 814 [(set (match_operand:V2SI 0 "register_operand" "=y") 815 (smin:V2SI (match_operand:V2SI 1 "register_operand" "y") 816 (match_operand:V2SI 2 "register_operand" "y")))] 817 "TARGET_REALLY_IWMMXT" 818 "wminsw%?\\t%0, %1, %2" 819 [(set_attr "predicable" "yes")]) 820 821(define_insn "uminv2si3" 822 [(set (match_operand:V2SI 0 "register_operand" "=y") 823 (umin:V2SI (match_operand:V2SI 1 "register_operand" "y") 824 (match_operand:V2SI 2 "register_operand" "y")))] 825 "TARGET_REALLY_IWMMXT" 826 "wminuw%?\\t%0, %1, %2" 827 [(set_attr "predicable" "yes")]) 828 829;; Pack/unpack insns. 830 831(define_insn "iwmmxt_wpackhss" 832 [(set (match_operand:V8QI 0 "register_operand" "=y") 833 (vec_concat:V8QI 834 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) 835 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] 836 "TARGET_REALLY_IWMMXT" 837 "wpackhss%?\\t%0, %1, %2" 838 [(set_attr "predicable" "yes")]) 839 840(define_insn "iwmmxt_wpackwss" 841 [(set (match_operand:V4HI 0 "register_operand" "=y") 842 (vec_concat:V4HI 843 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) 844 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] 845 "TARGET_REALLY_IWMMXT" 846 "wpackwss%?\\t%0, %1, %2" 847 [(set_attr "predicable" "yes")]) 848 849(define_insn "iwmmxt_wpackdss" 850 [(set (match_operand:V2SI 0 "register_operand" "=y") 851 (vec_concat:V2SI 852 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y")) 853 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] 854 "TARGET_REALLY_IWMMXT" 855 "wpackdss%?\\t%0, %1, %2" 856 [(set_attr "predicable" "yes")]) 857 858(define_insn "iwmmxt_wpackhus" 859 [(set (match_operand:V8QI 0 "register_operand" "=y") 860 (vec_concat:V8QI 861 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) 862 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] 863 "TARGET_REALLY_IWMMXT" 864 "wpackhus%?\\t%0, %1, %2" 865 [(set_attr "predicable" "yes")]) 866 867(define_insn "iwmmxt_wpackwus" 868 [(set (match_operand:V4HI 0 "register_operand" "=y") 869 (vec_concat:V4HI 870 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) 871 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] 872 "TARGET_REALLY_IWMMXT" 873 "wpackwus%?\\t%0, %1, %2" 874 [(set_attr "predicable" "yes")]) 875 876(define_insn "iwmmxt_wpackdus" 877 [(set (match_operand:V2SI 0 "register_operand" "=y") 878 (vec_concat:V2SI 879 (us_truncate:SI (match_operand:DI 1 "register_operand" "y")) 880 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] 881 "TARGET_REALLY_IWMMXT" 882 "wpackdus%?\\t%0, %1, %2" 883 [(set_attr "predicable" "yes")]) 884 885 886(define_insn "iwmmxt_wunpckihb" 887 [(set (match_operand:V8QI 0 "register_operand" "=y") 888 (vec_merge:V8QI 889 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") 890 (parallel [(const_int 4) 891 (const_int 0) 892 (const_int 5) 893 (const_int 1) 894 (const_int 6) 895 (const_int 2) 896 (const_int 7) 897 (const_int 3)])) 898 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") 899 (parallel [(const_int 0) 900 (const_int 4) 901 (const_int 1) 902 (const_int 5) 903 (const_int 2) 904 (const_int 6) 905 (const_int 3) 906 (const_int 7)])) 907 (const_int 85)))] 908 "TARGET_REALLY_IWMMXT" 909 "wunpckihb%?\\t%0, %1, %2" 910 [(set_attr "predicable" "yes")]) 911 912(define_insn "iwmmxt_wunpckihh" 913 [(set (match_operand:V4HI 0 "register_operand" "=y") 914 (vec_merge:V4HI 915 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") 916 (parallel [(const_int 0) 917 (const_int 2) 918 (const_int 1) 919 (const_int 3)])) 920 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") 921 (parallel [(const_int 2) 922 (const_int 0) 923 (const_int 3) 924 (const_int 1)])) 925 (const_int 5)))] 926 "TARGET_REALLY_IWMMXT" 927 "wunpckihh%?\\t%0, %1, %2" 928 [(set_attr "predicable" "yes")]) 929 930(define_insn "iwmmxt_wunpckihw" 931 [(set (match_operand:V2SI 0 "register_operand" "=y") 932 (vec_merge:V2SI 933 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") 934 (parallel [(const_int 0) 935 (const_int 1)])) 936 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") 937 (parallel [(const_int 1) 938 (const_int 0)])) 939 (const_int 1)))] 940 "TARGET_REALLY_IWMMXT" 941 "wunpckihw%?\\t%0, %1, %2" 942 [(set_attr "predicable" "yes")]) 943 944(define_insn "iwmmxt_wunpckilb" 945 [(set (match_operand:V8QI 0 "register_operand" "=y") 946 (vec_merge:V8QI 947 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") 948 (parallel [(const_int 0) 949 (const_int 4) 950 (const_int 1) 951 (const_int 5) 952 (const_int 2) 953 (const_int 6) 954 (const_int 3) 955 (const_int 7)])) 956 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") 957 (parallel [(const_int 4) 958 (const_int 0) 959 (const_int 5) 960 (const_int 1) 961 (const_int 6) 962 (const_int 2) 963 (const_int 7) 964 (const_int 3)])) 965 (const_int 85)))] 966 "TARGET_REALLY_IWMMXT" 967 "wunpckilb%?\\t%0, %1, %2" 968 [(set_attr "predicable" "yes")]) 969 970(define_insn "iwmmxt_wunpckilh" 971 [(set (match_operand:V4HI 0 "register_operand" "=y") 972 (vec_merge:V4HI 973 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") 974 (parallel [(const_int 2) 975 (const_int 0) 976 (const_int 3) 977 (const_int 1)])) 978 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") 979 (parallel [(const_int 0) 980 (const_int 2) 981 (const_int 1) 982 (const_int 3)])) 983 (const_int 5)))] 984 "TARGET_REALLY_IWMMXT" 985 "wunpckilh%?\\t%0, %1, %2" 986 [(set_attr "predicable" "yes")]) 987 988(define_insn "iwmmxt_wunpckilw" 989 [(set (match_operand:V2SI 0 "register_operand" "=y") 990 (vec_merge:V2SI 991 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") 992 (parallel [(const_int 1) 993 (const_int 0)])) 994 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") 995 (parallel [(const_int 0) 996 (const_int 1)])) 997 (const_int 1)))] 998 "TARGET_REALLY_IWMMXT" 999 "wunpckilw%?\\t%0, %1, %2" 1000 [(set_attr "predicable" "yes")]) 1001 1002(define_insn "iwmmxt_wunpckehub" 1003 [(set (match_operand:V4HI 0 "register_operand" "=y") 1004 (zero_extend:V4HI 1005 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1006 (parallel [(const_int 4) (const_int 5) 1007 (const_int 6) (const_int 7)]))))] 1008 "TARGET_REALLY_IWMMXT" 1009 "wunpckehub%?\\t%0, %1" 1010 [(set_attr "predicable" "yes")]) 1011 1012(define_insn "iwmmxt_wunpckehuh" 1013 [(set (match_operand:V2SI 0 "register_operand" "=y") 1014 (zero_extend:V2SI 1015 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1016 (parallel [(const_int 2) (const_int 3)]))))] 1017 "TARGET_REALLY_IWMMXT" 1018 "wunpckehuh%?\\t%0, %1" 1019 [(set_attr "predicable" "yes")]) 1020 1021(define_insn "iwmmxt_wunpckehuw" 1022 [(set (match_operand:DI 0 "register_operand" "=y") 1023 (zero_extend:DI 1024 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1025 (parallel [(const_int 1)]))))] 1026 "TARGET_REALLY_IWMMXT" 1027 "wunpckehuw%?\\t%0, %1" 1028 [(set_attr "predicable" "yes")]) 1029 1030(define_insn "iwmmxt_wunpckehsb" 1031 [(set (match_operand:V4HI 0 "register_operand" "=y") 1032 (sign_extend:V4HI 1033 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1034 (parallel [(const_int 4) (const_int 5) 1035 (const_int 6) (const_int 7)]))))] 1036 "TARGET_REALLY_IWMMXT" 1037 "wunpckehsb%?\\t%0, %1" 1038 [(set_attr "predicable" "yes")]) 1039 1040(define_insn "iwmmxt_wunpckehsh" 1041 [(set (match_operand:V2SI 0 "register_operand" "=y") 1042 (sign_extend:V2SI 1043 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1044 (parallel [(const_int 2) (const_int 3)]))))] 1045 "TARGET_REALLY_IWMMXT" 1046 "wunpckehsh%?\\t%0, %1" 1047 [(set_attr "predicable" "yes")]) 1048 1049(define_insn "iwmmxt_wunpckehsw" 1050 [(set (match_operand:DI 0 "register_operand" "=y") 1051 (sign_extend:DI 1052 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1053 (parallel [(const_int 1)]))))] 1054 "TARGET_REALLY_IWMMXT" 1055 "wunpckehsw%?\\t%0, %1" 1056 [(set_attr "predicable" "yes")]) 1057 1058(define_insn "iwmmxt_wunpckelub" 1059 [(set (match_operand:V4HI 0 "register_operand" "=y") 1060 (zero_extend:V4HI 1061 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1062 (parallel [(const_int 0) (const_int 1) 1063 (const_int 2) (const_int 3)]))))] 1064 "TARGET_REALLY_IWMMXT" 1065 "wunpckelub%?\\t%0, %1" 1066 [(set_attr "predicable" "yes")]) 1067 1068(define_insn "iwmmxt_wunpckeluh" 1069 [(set (match_operand:V2SI 0 "register_operand" "=y") 1070 (zero_extend:V2SI 1071 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1072 (parallel [(const_int 0) (const_int 1)]))))] 1073 "TARGET_REALLY_IWMMXT" 1074 "wunpckeluh%?\\t%0, %1" 1075 [(set_attr "predicable" "yes")]) 1076 1077(define_insn "iwmmxt_wunpckeluw" 1078 [(set (match_operand:DI 0 "register_operand" "=y") 1079 (zero_extend:DI 1080 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1081 (parallel [(const_int 0)]))))] 1082 "TARGET_REALLY_IWMMXT" 1083 "wunpckeluw%?\\t%0, %1" 1084 [(set_attr "predicable" "yes")]) 1085 1086(define_insn "iwmmxt_wunpckelsb" 1087 [(set (match_operand:V4HI 0 "register_operand" "=y") 1088 (sign_extend:V4HI 1089 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1090 (parallel [(const_int 0) (const_int 1) 1091 (const_int 2) (const_int 3)]))))] 1092 "TARGET_REALLY_IWMMXT" 1093 "wunpckelsb%?\\t%0, %1" 1094 [(set_attr "predicable" "yes")]) 1095 1096(define_insn "iwmmxt_wunpckelsh" 1097 [(set (match_operand:V2SI 0 "register_operand" "=y") 1098 (sign_extend:V2SI 1099 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1100 (parallel [(const_int 0) (const_int 1)]))))] 1101 "TARGET_REALLY_IWMMXT" 1102 "wunpckelsh%?\\t%0, %1" 1103 [(set_attr "predicable" "yes")]) 1104 1105(define_insn "iwmmxt_wunpckelsw" 1106 [(set (match_operand:DI 0 "register_operand" "=y") 1107 (sign_extend:DI 1108 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1109 (parallel [(const_int 0)]))))] 1110 "TARGET_REALLY_IWMMXT" 1111 "wunpckelsw%?\\t%0, %1" 1112 [(set_attr "predicable" "yes")]) 1113 1114;; Shifts 1115 1116(define_insn "rorv4hi3" 1117 [(set (match_operand:V4HI 0 "register_operand" "=y") 1118 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y") 1119 (match_operand:SI 2 "register_operand" "z")))] 1120 "TARGET_REALLY_IWMMXT" 1121 "wrorhg%?\\t%0, %1, %2" 1122 [(set_attr "predicable" "yes")]) 1123 1124(define_insn "rorv2si3" 1125 [(set (match_operand:V2SI 0 "register_operand" "=y") 1126 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y") 1127 (match_operand:SI 2 "register_operand" "z")))] 1128 "TARGET_REALLY_IWMMXT" 1129 "wrorwg%?\\t%0, %1, %2" 1130 [(set_attr "predicable" "yes")]) 1131 1132(define_insn "rordi3" 1133 [(set (match_operand:DI 0 "register_operand" "=y") 1134 (rotatert:DI (match_operand:DI 1 "register_operand" "y") 1135 (match_operand:SI 2 "register_operand" "z")))] 1136 "TARGET_REALLY_IWMMXT" 1137 "wrordg%?\\t%0, %1, %2" 1138 [(set_attr "predicable" "yes")]) 1139 1140(define_insn "ashrv4hi3" 1141 [(set (match_operand:V4HI 0 "register_operand" "=y") 1142 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1143 (match_operand:SI 2 "register_operand" "z")))] 1144 "TARGET_REALLY_IWMMXT" 1145 "wsrahg%?\\t%0, %1, %2" 1146 [(set_attr "predicable" "yes")]) 1147 1148(define_insn "ashrv2si3" 1149 [(set (match_operand:V2SI 0 "register_operand" "=y") 1150 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1151 (match_operand:SI 2 "register_operand" "z")))] 1152 "TARGET_REALLY_IWMMXT" 1153 "wsrawg%?\\t%0, %1, %2" 1154 [(set_attr "predicable" "yes")]) 1155 1156(define_insn "ashrdi3_iwmmxt" 1157 [(set (match_operand:DI 0 "register_operand" "=y") 1158 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y") 1159 (match_operand:SI 2 "register_operand" "z")))] 1160 "TARGET_REALLY_IWMMXT" 1161 "wsradg%?\\t%0, %1, %2" 1162 [(set_attr "predicable" "yes")]) 1163 1164(define_insn "lshrv4hi3" 1165 [(set (match_operand:V4HI 0 "register_operand" "=y") 1166 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1167 (match_operand:SI 2 "register_operand" "z")))] 1168 "TARGET_REALLY_IWMMXT" 1169 "wsrlhg%?\\t%0, %1, %2" 1170 [(set_attr "predicable" "yes")]) 1171 1172(define_insn "lshrv2si3" 1173 [(set (match_operand:V2SI 0 "register_operand" "=y") 1174 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1175 (match_operand:SI 2 "register_operand" "z")))] 1176 "TARGET_REALLY_IWMMXT" 1177 "wsrlwg%?\\t%0, %1, %2" 1178 [(set_attr "predicable" "yes")]) 1179 1180(define_insn "lshrdi3_iwmmxt" 1181 [(set (match_operand:DI 0 "register_operand" "=y") 1182 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y") 1183 (match_operand:SI 2 "register_operand" "z")))] 1184 "TARGET_REALLY_IWMMXT" 1185 "wsrldg%?\\t%0, %1, %2" 1186 [(set_attr "predicable" "yes")]) 1187 1188(define_insn "ashlv4hi3" 1189 [(set (match_operand:V4HI 0 "register_operand" "=y") 1190 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y") 1191 (match_operand:SI 2 "register_operand" "z")))] 1192 "TARGET_REALLY_IWMMXT" 1193 "wsllhg%?\\t%0, %1, %2" 1194 [(set_attr "predicable" "yes")]) 1195 1196(define_insn "ashlv2si3" 1197 [(set (match_operand:V2SI 0 "register_operand" "=y") 1198 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y") 1199 (match_operand:SI 2 "register_operand" "z")))] 1200 "TARGET_REALLY_IWMMXT" 1201 "wsllwg%?\\t%0, %1, %2" 1202 [(set_attr "predicable" "yes")]) 1203 1204(define_insn "ashldi3_iwmmxt" 1205 [(set (match_operand:DI 0 "register_operand" "=y") 1206 (ashift:DI (match_operand:DI 1 "register_operand" "y") 1207 (match_operand:SI 2 "register_operand" "z")))] 1208 "TARGET_REALLY_IWMMXT" 1209 "wslldg%?\\t%0, %1, %2" 1210 [(set_attr "predicable" "yes")]) 1211 1212(define_insn "rorv4hi3_di" 1213 [(set (match_operand:V4HI 0 "register_operand" "=y") 1214 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y") 1215 (match_operand:DI 2 "register_operand" "y")))] 1216 "TARGET_REALLY_IWMMXT" 1217 "wrorh%?\\t%0, %1, %2" 1218 [(set_attr "predicable" "yes")]) 1219 1220(define_insn "rorv2si3_di" 1221 [(set (match_operand:V2SI 0 "register_operand" "=y") 1222 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y") 1223 (match_operand:DI 2 "register_operand" "y")))] 1224 "TARGET_REALLY_IWMMXT" 1225 "wrorw%?\\t%0, %1, %2" 1226 [(set_attr "predicable" "yes")]) 1227 1228(define_insn "rordi3_di" 1229 [(set (match_operand:DI 0 "register_operand" "=y") 1230 (rotatert:DI (match_operand:DI 1 "register_operand" "y") 1231 (match_operand:DI 2 "register_operand" "y")))] 1232 "TARGET_REALLY_IWMMXT" 1233 "wrord%?\\t%0, %1, %2" 1234 [(set_attr "predicable" "yes")]) 1235 1236(define_insn "ashrv4hi3_di" 1237 [(set (match_operand:V4HI 0 "register_operand" "=y") 1238 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1239 (match_operand:DI 2 "register_operand" "y")))] 1240 "TARGET_REALLY_IWMMXT" 1241 "wsrah%?\\t%0, %1, %2" 1242 [(set_attr "predicable" "yes")]) 1243 1244(define_insn "ashrv2si3_di" 1245 [(set (match_operand:V2SI 0 "register_operand" "=y") 1246 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1247 (match_operand:DI 2 "register_operand" "y")))] 1248 "TARGET_REALLY_IWMMXT" 1249 "wsraw%?\\t%0, %1, %2" 1250 [(set_attr "predicable" "yes")]) 1251 1252(define_insn "ashrdi3_di" 1253 [(set (match_operand:DI 0 "register_operand" "=y") 1254 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y") 1255 (match_operand:DI 2 "register_operand" "y")))] 1256 "TARGET_REALLY_IWMMXT" 1257 "wsrad%?\\t%0, %1, %2" 1258 [(set_attr "predicable" "yes")]) 1259 1260(define_insn "lshrv4hi3_di" 1261 [(set (match_operand:V4HI 0 "register_operand" "=y") 1262 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1263 (match_operand:DI 2 "register_operand" "y")))] 1264 "TARGET_REALLY_IWMMXT" 1265 "wsrlh%?\\t%0, %1, %2" 1266 [(set_attr "predicable" "yes")]) 1267 1268(define_insn "lshrv2si3_di" 1269 [(set (match_operand:V2SI 0 "register_operand" "=y") 1270 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1271 (match_operand:DI 2 "register_operand" "y")))] 1272 "TARGET_REALLY_IWMMXT" 1273 "wsrlw%?\\t%0, %1, %2" 1274 [(set_attr "predicable" "yes")]) 1275 1276(define_insn "lshrdi3_di" 1277 [(set (match_operand:DI 0 "register_operand" "=y") 1278 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y") 1279 (match_operand:DI 2 "register_operand" "y")))] 1280 "TARGET_REALLY_IWMMXT" 1281 "wsrld%?\\t%0, %1, %2" 1282 [(set_attr "predicable" "yes")]) 1283 1284(define_insn "ashlv4hi3_di" 1285 [(set (match_operand:V4HI 0 "register_operand" "=y") 1286 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y") 1287 (match_operand:DI 2 "register_operand" "y")))] 1288 "TARGET_REALLY_IWMMXT" 1289 "wsllh%?\\t%0, %1, %2" 1290 [(set_attr "predicable" "yes")]) 1291 1292(define_insn "ashlv2si3_di" 1293 [(set (match_operand:V2SI 0 "register_operand" "=y") 1294 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y") 1295 (match_operand:DI 2 "register_operand" "y")))] 1296 "TARGET_REALLY_IWMMXT" 1297 "wsllw%?\\t%0, %1, %2" 1298 [(set_attr "predicable" "yes")]) 1299 1300(define_insn "ashldi3_di" 1301 [(set (match_operand:DI 0 "register_operand" "=y") 1302 (ashift:DI (match_operand:DI 1 "register_operand" "y") 1303 (match_operand:DI 2 "register_operand" "y")))] 1304 "TARGET_REALLY_IWMMXT" 1305 "wslld%?\\t%0, %1, %2" 1306 [(set_attr "predicable" "yes")]) 1307 1308(define_insn "iwmmxt_wmadds" 1309 [(set (match_operand:V4HI 0 "register_operand" "=y") 1310 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1311 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))] 1312 "TARGET_REALLY_IWMMXT" 1313 "wmadds%?\\t%0, %1, %2" 1314 [(set_attr "predicable" "yes")]) 1315 1316(define_insn "iwmmxt_wmaddu" 1317 [(set (match_operand:V4HI 0 "register_operand" "=y") 1318 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1319 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))] 1320 "TARGET_REALLY_IWMMXT" 1321 "wmaddu%?\\t%0, %1, %2" 1322 [(set_attr "predicable" "yes")]) 1323 1324(define_insn "iwmmxt_tmia" 1325 [(set (match_operand:DI 0 "register_operand" "=y") 1326 (plus:DI (match_operand:DI 1 "register_operand" "0") 1327 (mult:DI (sign_extend:DI 1328 (match_operand:SI 2 "register_operand" "r")) 1329 (sign_extend:DI 1330 (match_operand:SI 3 "register_operand" "r")))))] 1331 "TARGET_REALLY_IWMMXT" 1332 "tmia%?\\t%0, %2, %3" 1333 [(set_attr "predicable" "yes")]) 1334 1335(define_insn "iwmmxt_tmiaph" 1336 [(set (match_operand:DI 0 "register_operand" "=y") 1337 (plus:DI (match_operand:DI 1 "register_operand" "0") 1338 (plus:DI 1339 (mult:DI (sign_extend:DI 1340 (truncate:HI (match_operand:SI 2 "register_operand" "r"))) 1341 (sign_extend:DI 1342 (truncate:HI (match_operand:SI 3 "register_operand" "r")))) 1343 (mult:DI (sign_extend:DI 1344 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16)))) 1345 (sign_extend:DI 1346 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))] 1347 "TARGET_REALLY_IWMMXT" 1348 "tmiaph%?\\t%0, %2, %3" 1349 [(set_attr "predicable" "yes")]) 1350 1351(define_insn "iwmmxt_tmiabb" 1352 [(set (match_operand:DI 0 "register_operand" "=y") 1353 (plus:DI (match_operand:DI 1 "register_operand" "0") 1354 (mult:DI (sign_extend:DI 1355 (truncate:HI (match_operand:SI 2 "register_operand" "r"))) 1356 (sign_extend:DI 1357 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] 1358 "TARGET_REALLY_IWMMXT" 1359 "tmiabb%?\\t%0, %2, %3" 1360 [(set_attr "predicable" "yes")]) 1361 1362(define_insn "iwmmxt_tmiatb" 1363 [(set (match_operand:DI 0 "register_operand" "=y") 1364 (plus:DI (match_operand:DI 1 "register_operand" "0") 1365 (mult:DI (sign_extend:DI 1366 (truncate:HI (ashiftrt:SI 1367 (match_operand:SI 2 "register_operand" "r") 1368 (const_int 16)))) 1369 (sign_extend:DI 1370 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] 1371 "TARGET_REALLY_IWMMXT" 1372 "tmiatb%?\\t%0, %2, %3" 1373 [(set_attr "predicable" "yes")]) 1374 1375(define_insn "iwmmxt_tmiabt" 1376 [(set (match_operand:DI 0 "register_operand" "=y") 1377 (plus:DI (match_operand:DI 1 "register_operand" "0") 1378 (mult:DI (sign_extend:DI 1379 (truncate:HI (match_operand:SI 2 "register_operand" "r"))) 1380 (sign_extend:DI 1381 (truncate:HI (ashiftrt:SI 1382 (match_operand:SI 3 "register_operand" "r") 1383 (const_int 16)))))))] 1384 "TARGET_REALLY_IWMMXT" 1385 "tmiabt%?\\t%0, %2, %3" 1386 [(set_attr "predicable" "yes")]) 1387 1388(define_insn "iwmmxt_tmiatt" 1389 [(set (match_operand:DI 0 "register_operand" "=y") 1390 (plus:DI (match_operand:DI 1 "register_operand" "0") 1391 (mult:DI (sign_extend:DI 1392 (truncate:HI (ashiftrt:SI 1393 (match_operand:SI 2 "register_operand" "r") 1394 (const_int 16)))) 1395 (sign_extend:DI 1396 (truncate:HI (ashiftrt:SI 1397 (match_operand:SI 3 "register_operand" "r") 1398 (const_int 16)))))))] 1399 "TARGET_REALLY_IWMMXT" 1400 "tmiatt%?\\t%0, %2, %3" 1401 [(set_attr "predicable" "yes")]) 1402 1403(define_insn "iwmmxt_tbcstqi" 1404 [(set (match_operand:V8QI 0 "register_operand" "=y") 1405 (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))] 1406 "TARGET_REALLY_IWMMXT" 1407 "tbcstb%?\\t%0, %1" 1408 [(set_attr "predicable" "yes")]) 1409 1410(define_insn "iwmmxt_tbcsthi" 1411 [(set (match_operand:V4HI 0 "register_operand" "=y") 1412 (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))] 1413 "TARGET_REALLY_IWMMXT" 1414 "tbcsth%?\\t%0, %1" 1415 [(set_attr "predicable" "yes")]) 1416 1417(define_insn "iwmmxt_tbcstsi" 1418 [(set (match_operand:V2SI 0 "register_operand" "=y") 1419 (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))] 1420 "TARGET_REALLY_IWMMXT" 1421 "tbcstw%?\\t%0, %1" 1422 [(set_attr "predicable" "yes")]) 1423 1424(define_insn "iwmmxt_tmovmskb" 1425 [(set (match_operand:SI 0 "register_operand" "=r") 1426 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] 1427 "TARGET_REALLY_IWMMXT" 1428 "tmovmskb%?\\t%0, %1" 1429 [(set_attr "predicable" "yes")]) 1430 1431(define_insn "iwmmxt_tmovmskh" 1432 [(set (match_operand:SI 0 "register_operand" "=r") 1433 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] 1434 "TARGET_REALLY_IWMMXT" 1435 "tmovmskh%?\\t%0, %1" 1436 [(set_attr "predicable" "yes")]) 1437 1438(define_insn "iwmmxt_tmovmskw" 1439 [(set (match_operand:SI 0 "register_operand" "=r") 1440 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] 1441 "TARGET_REALLY_IWMMXT" 1442 "tmovmskw%?\\t%0, %1" 1443 [(set_attr "predicable" "yes")]) 1444 1445(define_insn "iwmmxt_waccb" 1446 [(set (match_operand:DI 0 "register_operand" "=y") 1447 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))] 1448 "TARGET_REALLY_IWMMXT" 1449 "waccb%?\\t%0, %1" 1450 [(set_attr "predicable" "yes")]) 1451 1452(define_insn "iwmmxt_wacch" 1453 [(set (match_operand:DI 0 "register_operand" "=y") 1454 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))] 1455 "TARGET_REALLY_IWMMXT" 1456 "wacch%?\\t%0, %1" 1457 [(set_attr "predicable" "yes")]) 1458 1459(define_insn "iwmmxt_waccw" 1460 [(set (match_operand:DI 0 "register_operand" "=y") 1461 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))] 1462 "TARGET_REALLY_IWMMXT" 1463 "waccw%?\\t%0, %1" 1464 [(set_attr "predicable" "yes")]) 1465 1466(define_insn "iwmmxt_walign" 1467 [(set (match_operand:V8QI 0 "register_operand" "=y,y") 1468 (subreg:V8QI (ashiftrt:TI 1469 (subreg:TI (vec_concat:V16QI 1470 (match_operand:V8QI 1 "register_operand" "y,y") 1471 (match_operand:V8QI 2 "register_operand" "y,y")) 0) 1472 (mult:SI 1473 (match_operand:SI 3 "nonmemory_operand" "i,z") 1474 (const_int 8))) 0))] 1475 "TARGET_REALLY_IWMMXT" 1476 "@ 1477 waligni%?\\t%0, %1, %2, %3 1478 walignr%U3%?\\t%0, %1, %2" 1479 [(set_attr "predicable" "yes")]) 1480 1481(define_insn "iwmmxt_tmrc" 1482 [(set (match_operand:SI 0 "register_operand" "=r") 1483 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] 1484 VUNSPEC_TMRC))] 1485 "TARGET_REALLY_IWMMXT" 1486 "tmrc%?\\t%0, %w1" 1487 [(set_attr "predicable" "yes")]) 1488 1489(define_insn "iwmmxt_tmcr" 1490 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i") 1491 (match_operand:SI 1 "register_operand" "r")] 1492 VUNSPEC_TMCR)] 1493 "TARGET_REALLY_IWMMXT" 1494 "tmcr%?\\t%w0, %1" 1495 [(set_attr "predicable" "yes")]) 1496 1497(define_insn "iwmmxt_wsadb" 1498 [(set (match_operand:V8QI 0 "register_operand" "=y") 1499 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 1500 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))] 1501 "TARGET_REALLY_IWMMXT" 1502 "wsadb%?\\t%0, %1, %2" 1503 [(set_attr "predicable" "yes")]) 1504 1505(define_insn "iwmmxt_wsadh" 1506 [(set (match_operand:V4HI 0 "register_operand" "=y") 1507 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1508 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))] 1509 "TARGET_REALLY_IWMMXT" 1510 "wsadh%?\\t%0, %1, %2" 1511 [(set_attr "predicable" "yes")]) 1512 1513(define_insn "iwmmxt_wsadbz" 1514 [(set (match_operand:V8QI 0 "register_operand" "=y") 1515 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 1516 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))] 1517 "TARGET_REALLY_IWMMXT" 1518 "wsadbz%?\\t%0, %1, %2" 1519 [(set_attr "predicable" "yes")]) 1520 1521(define_insn "iwmmxt_wsadhz" 1522 [(set (match_operand:V4HI 0 "register_operand" "=y") 1523 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1524 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))] 1525 "TARGET_REALLY_IWMMXT" 1526 "wsadhz%?\\t%0, %1, %2" 1527 [(set_attr "predicable" "yes")]) 1528 1529