isa_dma.c revision 92765
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 * $FreeBSD: head/sys/i386/isa/isa_dma.c 92765 2002-03-20 07:51:46Z alfred $ 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/bus.h> 53#include <sys/kernel.h> 54#include <sys/malloc.h> 55#include <sys/lock.h> 56#include <sys/proc.h> 57#include <sys/mutex.h> 58#include <sys/module.h> 59#include <vm/vm.h> 60#include <vm/vm_param.h> 61#include <vm/pmap.h> 62#include <i386/isa/isa.h> 63#include <dev/ic/i8237.h> 64#include <isa/isavar.h> 65 66/* 67** Register definitions for DMA controller 1 (channels 0..3): 68*/ 69#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 70#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 71#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 72#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 73 74/* 75** Register definitions for DMA controller 2 (channels 4..7): 76*/ 77#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 78#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 79#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 80#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 81 82static int isa_dmarangecheck(caddr_t va, u_int length, int chan); 83 84static caddr_t dma_bouncebuf[8]; 85static u_int dma_bouncebufsize[8]; 86static u_int8_t dma_bounced = 0; 87static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 88static u_int8_t dma_inuse = 0; /* User for acquire/release */ 89static u_int8_t dma_auto_mode = 0; 90 91#define VALID_DMA_MASK (7) 92 93/* high byte of address is stored in this port for i-th dma channel */ 94static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 95 96/* 97 * Setup a DMA channel's bounce buffer. 98 */ 99void 100isa_dmainit(chan, bouncebufsize) 101 int chan; 102 u_int bouncebufsize; 103{ 104 void *buf; 105 106#ifdef DIAGNOSTIC 107 if (chan & ~VALID_DMA_MASK) 108 panic("isa_dmainit: channel out of range"); 109 110 if (dma_bouncebuf[chan] != NULL) 111 panic("isa_dmainit: impossible request"); 112#endif 113 114 dma_bouncebufsize[chan] = bouncebufsize; 115 116 /* Try malloc() first. It works better if it works. */ 117 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 118 if (buf != NULL) { 119 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 120 dma_bouncebuf[chan] = buf; 121 return; 122 } 123 free(buf, M_DEVBUF); 124 } 125 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 126 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 127 if (buf == NULL) 128 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 129 else 130 dma_bouncebuf[chan] = buf; 131} 132 133/* 134 * Register a DMA channel's usage. Usually called from a device driver 135 * in open() or during its initialization. 136 */ 137int 138isa_dma_acquire(chan) 139 int chan; 140{ 141#ifdef DIAGNOSTIC 142 if (chan & ~VALID_DMA_MASK) 143 panic("isa_dma_acquire: channel out of range"); 144#endif 145 146 if (dma_inuse & (1 << chan)) { 147 printf("isa_dma_acquire: channel %d already in use\n", chan); 148 return (EBUSY); 149 } 150 dma_inuse |= (1 << chan); 151 dma_auto_mode &= ~(1 << chan); 152 153 return (0); 154} 155 156/* 157 * Unregister a DMA channel's usage. Usually called from a device driver 158 * during close() or during its shutdown. 159 */ 160void 161isa_dma_release(chan) 162 int chan; 163{ 164#ifdef DIAGNOSTIC 165 if (chan & ~VALID_DMA_MASK) 166 panic("isa_dma_release: channel out of range"); 167 168 if ((dma_inuse & (1 << chan)) == 0) 169 printf("isa_dma_release: channel %d not in use\n", chan); 170#endif 171 172 if (dma_busy & (1 << chan)) { 173 dma_busy &= ~(1 << chan); 174 /* 175 * XXX We should also do "dma_bounced &= (1 << chan);" 176 * because we are acting on behalf of isa_dmadone() which 177 * was not called to end the last DMA operation. This does 178 * not matter now, but it may in the future. 179 */ 180 } 181 182 dma_inuse &= ~(1 << chan); 183 dma_auto_mode &= ~(1 << chan); 184} 185 186/* 187 * isa_dmacascade(): program 8237 DMA controller channel to accept 188 * external dma control by a board. 189 */ 190void 191isa_dmacascade(chan) 192 int chan; 193{ 194#ifdef DIAGNOSTIC 195 if (chan & ~VALID_DMA_MASK) 196 panic("isa_dmacascade: channel out of range"); 197#endif 198 199 /* set dma channel mode, and set dma channel mode */ 200 if ((chan & 4) == 0) { 201 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 202 outb(DMA1_SMSK, chan); 203 } else { 204 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 205 outb(DMA2_SMSK, chan & 3); 206 } 207} 208 209/* 210 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 211 * problems by using a bounce buffer. 212 */ 213void 214isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 215{ 216 vm_offset_t phys; 217 int waport; 218 caddr_t newaddr; 219 220 GIANT_REQUIRED; 221 222#ifdef DIAGNOSTIC 223 if (chan & ~VALID_DMA_MASK) 224 panic("isa_dmastart: channel out of range"); 225 226 if ((chan < 4 && nbytes > (1<<16)) 227 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 228 panic("isa_dmastart: impossible request"); 229 230 if ((dma_inuse & (1 << chan)) == 0) 231 printf("isa_dmastart: channel %d not acquired\n", chan); 232#endif 233 234#if 0 235 /* 236 * XXX This should be checked, but drivers like ad1848 only call 237 * isa_dmastart() once because they use Auto DMA mode. If we 238 * leave this in, drivers that do this will print this continuously. 239 */ 240 if (dma_busy & (1 << chan)) 241 printf("isa_dmastart: channel %d busy\n", chan); 242#endif 243 244 dma_busy |= (1 << chan); 245 246 if (isa_dmarangecheck(addr, nbytes, chan)) { 247 if (dma_bouncebuf[chan] == NULL 248 || dma_bouncebufsize[chan] < nbytes) 249 panic("isa_dmastart: bad bounce buffer"); 250 dma_bounced |= (1 << chan); 251 newaddr = dma_bouncebuf[chan]; 252 253 /* copy bounce buffer on write */ 254 if (!(flags & ISADMA_READ)) 255 bcopy(addr, newaddr, nbytes); 256 addr = newaddr; 257 } 258 259 /* translate to physical */ 260 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 261 262 if (flags & ISADMA_RAW) { 263 dma_auto_mode |= (1 << chan); 264 } else { 265 dma_auto_mode &= ~(1 << chan); 266 } 267 268 if ((chan & 4) == 0) { 269 /* 270 * Program one of DMA channels 0..3. These are 271 * byte mode channels. 272 */ 273 /* set dma channel mode, and reset address ff */ 274 275 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 276 if (flags & ISADMA_RAW) { 277 if (flags & ISADMA_READ) 278 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 279 else 280 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 281 } 282 else 283 if (flags & ISADMA_READ) 284 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 285 else 286 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 287 outb(DMA1_FFC, 0); 288 289 /* send start address */ 290 waport = DMA1_CHN(chan); 291 outb(waport, phys); 292 outb(waport, phys>>8); 293 outb(dmapageport[chan], phys>>16); 294 295 /* send count */ 296 outb(waport + 1, --nbytes); 297 outb(waport + 1, nbytes>>8); 298 299 /* unmask channel */ 300 outb(DMA1_SMSK, chan); 301 } else { 302 /* 303 * Program one of DMA channels 4..7. These are 304 * word mode channels. 305 */ 306 /* set dma channel mode, and reset address ff */ 307 308 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 309 if (flags & ISADMA_RAW) { 310 if (flags & ISADMA_READ) 311 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 312 else 313 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 314 } 315 else 316 if (flags & ISADMA_READ) 317 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 318 else 319 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 320 outb(DMA2_FFC, 0); 321 322 /* send start address */ 323 waport = DMA2_CHN(chan - 4); 324 outb(waport, phys>>1); 325 outb(waport, phys>>9); 326 outb(dmapageport[chan], phys>>16); 327 328 /* send count */ 329 nbytes >>= 1; 330 outb(waport + 2, --nbytes); 331 outb(waport + 2, nbytes>>8); 332 333 /* unmask channel */ 334 outb(DMA2_SMSK, chan & 3); 335 } 336} 337 338void 339isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 340{ 341#ifdef DIAGNOSTIC 342 if (chan & ~VALID_DMA_MASK) 343 panic("isa_dmadone: channel out of range"); 344 345 if ((dma_inuse & (1 << chan)) == 0) 346 printf("isa_dmadone: channel %d not acquired\n", chan); 347#endif 348 349 if (((dma_busy & (1 << chan)) == 0) && 350 (dma_auto_mode & (1 << chan)) == 0 ) 351 printf("isa_dmadone: channel %d not busy\n", chan); 352 353 if ((dma_auto_mode & (1 << chan)) == 0) 354 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 355 356 if (dma_bounced & (1 << chan)) { 357 /* copy bounce buffer on read */ 358 if (flags & ISADMA_READ) 359 bcopy(dma_bouncebuf[chan], addr, nbytes); 360 361 dma_bounced &= ~(1 << chan); 362 } 363 dma_busy &= ~(1 << chan); 364} 365 366/* 367 * Check for problems with the address range of a DMA transfer 368 * (non-contiguous physical pages, outside of bus address space, 369 * crossing DMA page boundaries). 370 * Return true if special handling needed. 371 */ 372 373static int 374isa_dmarangecheck(caddr_t va, u_int length, int chan) 375{ 376 vm_offset_t phys, priorpage = 0, endva; 377 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 378 379 GIANT_REQUIRED; 380 381 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 382 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 383 phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 384#define ISARAM_END RAM_END 385 if (phys == 0) 386 panic("isa_dmacheck: no physical page present"); 387 if (phys >= ISARAM_END) 388 return (1); 389 if (priorpage) { 390 if (priorpage + PAGE_SIZE != phys) 391 return (1); 392 /* check if crossing a DMA page boundary */ 393 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 394 return (1); 395 } 396 priorpage = phys; 397 } 398 return (0); 399} 400 401/* 402 * Query the progress of a transfer on a DMA channel. 403 * 404 * To avoid having to interrupt a transfer in progress, we sample 405 * each of the high and low databytes twice, and apply the following 406 * logic to determine the correct count. 407 * 408 * Reads are performed with interrupts disabled, thus it is to be 409 * expected that the time between reads is very small. At most 410 * one rollover in the low count byte can be expected within the 411 * four reads that are performed. 412 * 413 * There are three gaps in which a rollover can occur : 414 * 415 * - read low1 416 * gap1 417 * - read high1 418 * gap2 419 * - read low2 420 * gap3 421 * - read high2 422 * 423 * If a rollover occurs in gap1 or gap2, the low2 value will be 424 * greater than the low1 value. In this case, low2 and high2 are a 425 * corresponding pair. 426 * 427 * In any other case, low1 and high1 can be considered to be correct. 428 * 429 * The function returns the number of bytes remaining in the transfer, 430 * or -1 if the channel requested is not active. 431 * 432 */ 433int 434isa_dmastatus(int chan) 435{ 436 u_long cnt = 0; 437 int ffport, waport; 438 u_long low1, high1, low2, high2; 439 440 /* channel active? */ 441 if ((dma_inuse & (1 << chan)) == 0) { 442 printf("isa_dmastatus: channel %d not active\n", chan); 443 return(-1); 444 } 445 /* channel busy? */ 446 447 if (((dma_busy & (1 << chan)) == 0) && 448 (dma_auto_mode & (1 << chan)) == 0 ) { 449 printf("chan %d not busy\n", chan); 450 return -2 ; 451 } 452 if (chan < 4) { /* low DMA controller */ 453 ffport = DMA1_FFC; 454 waport = DMA1_CHN(chan) + 1; 455 } else { /* high DMA controller */ 456 ffport = DMA2_FFC; 457 waport = DMA2_CHN(chan - 4) + 2; 458 } 459 460 disable_intr(); /* no interrupts Mr Jones! */ 461 outb(ffport, 0); /* clear register LSB flipflop */ 462 low1 = inb(waport); 463 high1 = inb(waport); 464 outb(ffport, 0); /* clear again */ 465 low2 = inb(waport); 466 high2 = inb(waport); 467 enable_intr(); /* enable interrupts again */ 468 469 /* 470 * Now decide if a wrap has tried to skew our results. 471 * Note that after TC, the count will read 0xffff, while we want 472 * to return zero, so we add and then mask to compensate. 473 */ 474 if (low1 >= low2) { 475 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 476 } else { 477 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 478 } 479 480 if (chan >= 4) /* high channels move words */ 481 cnt *= 2; 482 return(cnt); 483} 484 485/* 486 * Stop a DMA transfer currently in progress. 487 */ 488int 489isa_dmastop(int chan) 490{ 491 if ((dma_inuse & (1 << chan)) == 0) 492 printf("isa_dmastop: channel %d not acquired\n", chan); 493 494 if (((dma_busy & (1 << chan)) == 0) && 495 ((dma_auto_mode & (1 << chan)) == 0)) { 496 printf("chan %d not busy\n", chan); 497 return -2 ; 498 } 499 500 if ((chan & 4) == 0) { 501 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 502 } else { 503 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 504 } 505 return(isa_dmastatus(chan)); 506} 507 508/* 509 * Attach to the ISA PnP descriptor for the AT DMA controller 510 */ 511static struct isa_pnp_id atdma_ids[] = { 512 { 0x0002d041 /* PNP0200 */, "AT DMA controller" }, 513 { 0 } 514}; 515 516static int 517atdma_probe(device_t dev) 518{ 519 int result; 520 521 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0) 522 device_quiet(dev); 523 return(result); 524} 525 526static int 527atdma_attach(device_t dev) 528{ 529 return(0); 530} 531 532static device_method_t atdma_methods[] = { 533 /* Device interface */ 534 DEVMETHOD(device_probe, atdma_probe), 535 DEVMETHOD(device_attach, atdma_attach), 536 DEVMETHOD(device_detach, bus_generic_detach), 537 DEVMETHOD(device_shutdown, bus_generic_shutdown), 538 DEVMETHOD(device_suspend, bus_generic_suspend), 539 DEVMETHOD(device_resume, bus_generic_resume), 540 { 0, 0 } 541}; 542 543static driver_t atdma_driver = { 544 "atdma", 545 atdma_methods, 546 1, /* no softc */ 547}; 548 549static devclass_t atdma_devclass; 550 551DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0); 552DRIVER_MODULE(atdma, acpi, atdma_driver, atdma_devclass, 0, 0); 553