isa_dma.c revision 77081
1230557Sjimharris/*-
2230557Sjimharris * Copyright (c) 1991 The Regents of the University of California.
3230557Sjimharris * All rights reserved.
4230557Sjimharris *
5230557Sjimharris * This code is derived from software contributed to Berkeley by
6230557Sjimharris * William Jolitz.
7230557Sjimharris *
8230557Sjimharris * Redistribution and use in source and binary forms, with or without
9230557Sjimharris * modification, are permitted provided that the following conditions
10230557Sjimharris * are met:
11230557Sjimharris * 1. Redistributions of source code must retain the above copyright
12230557Sjimharris *    notice, this list of conditions and the following disclaimer.
13230557Sjimharris * 2. Redistributions in binary form must reproduce the above copyright
14230557Sjimharris *    notice, this list of conditions and the following disclaimer in the
15230557Sjimharris *    documentation and/or other materials provided with the distribution.
16230557Sjimharris * 3. All advertising materials mentioning features or use of this software
17230557Sjimharris *    must display the following acknowledgement:
18230557Sjimharris *	This product includes software developed by the University of
19230557Sjimharris *	California, Berkeley and its contributors.
20230557Sjimharris * 4. Neither the name of the University nor the names of its contributors
21230557Sjimharris *    may be used to endorse or promote products derived from this software
22230557Sjimharris *    without specific prior written permission.
23230557Sjimharris *
24230557Sjimharris * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25230557Sjimharris * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26230557Sjimharris * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27230557Sjimharris * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28230557Sjimharris * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29230557Sjimharris * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30230557Sjimharris * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31230557Sjimharris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32230557Sjimharris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33230557Sjimharris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34230557Sjimharris * SUCH DAMAGE.
35230557Sjimharris *
36230557Sjimharris *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
37230557Sjimharris * $FreeBSD: head/sys/i386/isa/isa_dma.c 77081 2001-05-23 22:13:58Z alfred $
38230557Sjimharris */
39230557Sjimharris
40230557Sjimharris/*
41230557Sjimharris * code to manage AT bus
42230557Sjimharris *
43230557Sjimharris * 92/08/18  Frank P. MacLachlan (fpm@crash.cts.com):
44230557Sjimharris * Fixed uninitialized variable problem and added code to deal
45230557Sjimharris * with DMA page boundaries in isa_dmarangecheck().  Fixed word
46230557Sjimharris * mode DMA count compution and reorganized DMA setup code in
47230557Sjimharris * isa_dmastart()
48230557Sjimharris */
49230557Sjimharris
50230557Sjimharris#include <sys/param.h>
51230557Sjimharris#include <sys/systm.h>
52230557Sjimharris#include <sys/bus.h>
53230557Sjimharris#include <sys/kernel.h>
54230557Sjimharris#include <sys/malloc.h>
55230557Sjimharris#include <sys/lock.h>
56230557Sjimharris#include <sys/mutex.h>
57230557Sjimharris#include <sys/module.h>
58230557Sjimharris#include <vm/vm.h>
59230557Sjimharris#include <vm/vm_param.h>
60230557Sjimharris#include <vm/pmap.h>
61230557Sjimharris#include <i386/isa/isa.h>
62230557Sjimharris#include <i386/isa/ic/i8237.h>
63230557Sjimharris#include <isa/isavar.h>
64230557Sjimharris
65230557Sjimharris/*
66230557Sjimharris**  Register definitions for DMA controller 1 (channels 0..3):
67230557Sjimharris*/
68230557Sjimharris#define	DMA1_CHN(c)	(IO_DMA1 + 1*(2*(c)))	/* addr reg for channel c */
69230557Sjimharris#define	DMA1_SMSK	(IO_DMA1 + 1*10)	/* single mask register */
70230557Sjimharris#define	DMA1_MODE	(IO_DMA1 + 1*11)	/* mode register */
71230557Sjimharris#define	DMA1_FFC	(IO_DMA1 + 1*12)	/* clear first/last FF */
72230557Sjimharris
73230557Sjimharris/*
74230557Sjimharris**  Register definitions for DMA controller 2 (channels 4..7):
75230557Sjimharris*/
76230557Sjimharris#define	DMA2_CHN(c)	(IO_DMA2 + 2*(2*(c)))	/* addr reg for channel c */
77230557Sjimharris#define	DMA2_SMSK	(IO_DMA2 + 2*10)	/* single mask register */
78230557Sjimharris#define	DMA2_MODE	(IO_DMA2 + 2*11)	/* mode register */
79230557Sjimharris#define	DMA2_FFC	(IO_DMA2 + 2*12)	/* clear first/last FF */
80230557Sjimharris
81230557Sjimharrisstatic int isa_dmarangecheck __P((caddr_t va, u_int length, int chan));
82230557Sjimharris
83230557Sjimharrisstatic caddr_t	dma_bouncebuf[8];
84230557Sjimharrisstatic u_int	dma_bouncebufsize[8];
85230557Sjimharrisstatic u_int8_t	dma_bounced = 0;
86230557Sjimharrisstatic u_int8_t	dma_busy = 0;		/* Used in isa_dmastart() */
87230557Sjimharrisstatic u_int8_t	dma_inuse = 0;		/* User for acquire/release */
88230557Sjimharrisstatic u_int8_t dma_auto_mode = 0;
89230557Sjimharris
90230557Sjimharris#define VALID_DMA_MASK (7)
91230557Sjimharris
92230557Sjimharris/* high byte of address is stored in this port for i-th dma channel */
93230557Sjimharrisstatic int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
94230557Sjimharris
95230557Sjimharris/*
96230557Sjimharris * Setup a DMA channel's bounce buffer.
97230557Sjimharris */
98230557Sjimharrisvoid
99230557Sjimharrisisa_dmainit(chan, bouncebufsize)
100230557Sjimharris	int chan;
101230557Sjimharris	u_int bouncebufsize;
102230557Sjimharris{
103230557Sjimharris	void *buf;
104230557Sjimharris
105230557Sjimharris#ifdef DIAGNOSTIC
106230557Sjimharris	if (chan & ~VALID_DMA_MASK)
107230557Sjimharris		panic("isa_dmainit: channel out of range");
108230557Sjimharris
109230557Sjimharris	if (dma_bouncebuf[chan] != NULL)
110230557Sjimharris		panic("isa_dmainit: impossible request");
111230557Sjimharris#endif
112230557Sjimharris
113230557Sjimharris	dma_bouncebufsize[chan] = bouncebufsize;
114230557Sjimharris
115230557Sjimharris	/* Try malloc() first.  It works better if it works. */
116230557Sjimharris	buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT);
117230557Sjimharris	if (buf != NULL) {
118230557Sjimharris		if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) {
119230557Sjimharris			dma_bouncebuf[chan] = buf;
120230557Sjimharris			return;
121230557Sjimharris		}
122230557Sjimharris		free(buf, M_DEVBUF);
123230557Sjimharris	}
124230557Sjimharris	buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful,
125230557Sjimharris			   1ul, chan & 4 ? 0x20000ul : 0x10000ul);
126230557Sjimharris	if (buf == NULL)
127230557Sjimharris		printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize);
128230557Sjimharris	else
129230557Sjimharris		dma_bouncebuf[chan] = buf;
130230557Sjimharris}
131230557Sjimharris
132230557Sjimharris/*
133230557Sjimharris * Register a DMA channel's usage.  Usually called from a device driver
134230557Sjimharris * in open() or during its initialization.
135230557Sjimharris */
136230557Sjimharrisint
137230557Sjimharrisisa_dma_acquire(chan)
138230557Sjimharris	int chan;
139230557Sjimharris{
140230557Sjimharris#ifdef DIAGNOSTIC
141230557Sjimharris	if (chan & ~VALID_DMA_MASK)
142230557Sjimharris		panic("isa_dma_acquire: channel out of range");
143230557Sjimharris#endif
144230557Sjimharris
145230557Sjimharris	if (dma_inuse & (1 << chan)) {
146230557Sjimharris		printf("isa_dma_acquire: channel %d already in use\n", chan);
147230557Sjimharris		return (EBUSY);
148230557Sjimharris	}
149230557Sjimharris	dma_inuse |= (1 << chan);
150230557Sjimharris	dma_auto_mode &= ~(1 << chan);
151230557Sjimharris
152230557Sjimharris	return (0);
153230557Sjimharris}
154230557Sjimharris
155230557Sjimharris/*
156230557Sjimharris * Unregister a DMA channel's usage.  Usually called from a device driver
157230557Sjimharris * during close() or during its shutdown.
158230557Sjimharris */
159230557Sjimharrisvoid
160230557Sjimharrisisa_dma_release(chan)
161230557Sjimharris	int chan;
162230557Sjimharris{
163230557Sjimharris#ifdef DIAGNOSTIC
164230557Sjimharris	if (chan & ~VALID_DMA_MASK)
165230557Sjimharris		panic("isa_dma_release: channel out of range");
166230557Sjimharris
167230557Sjimharris	if ((dma_inuse & (1 << chan)) == 0)
168230557Sjimharris		printf("isa_dma_release: channel %d not in use\n", chan);
169230557Sjimharris#endif
170230557Sjimharris
171230557Sjimharris	if (dma_busy & (1 << chan)) {
172230557Sjimharris		dma_busy &= ~(1 << chan);
173230557Sjimharris		/*
174230557Sjimharris		 * XXX We should also do "dma_bounced &= (1 << chan);"
175230557Sjimharris		 * because we are acting on behalf of isa_dmadone() which
176230557Sjimharris		 * was not called to end the last DMA operation.  This does
177230557Sjimharris		 * not matter now, but it may in the future.
178230557Sjimharris		 */
179230557Sjimharris	}
180230557Sjimharris
181230557Sjimharris	dma_inuse &= ~(1 << chan);
182230557Sjimharris	dma_auto_mode &= ~(1 << chan);
183230557Sjimharris}
184230557Sjimharris
185230557Sjimharris/*
186230557Sjimharris * isa_dmacascade(): program 8237 DMA controller channel to accept
187230557Sjimharris * external dma control by a board.
188230557Sjimharris */
189230557Sjimharrisvoid
190230557Sjimharrisisa_dmacascade(chan)
191230557Sjimharris	int chan;
192230557Sjimharris{
193230557Sjimharris#ifdef DIAGNOSTIC
194230557Sjimharris	if (chan & ~VALID_DMA_MASK)
195230557Sjimharris		panic("isa_dmacascade: channel out of range");
196230557Sjimharris#endif
197230557Sjimharris
198230557Sjimharris	/* set dma channel mode, and set dma channel mode */
199230557Sjimharris	if ((chan & 4) == 0) {
200230557Sjimharris		outb(DMA1_MODE, DMA37MD_CASCADE | chan);
201230557Sjimharris		outb(DMA1_SMSK, chan);
202230557Sjimharris	} else {
203230557Sjimharris		outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
204230557Sjimharris		outb(DMA2_SMSK, chan & 3);
205230557Sjimharris	}
206230557Sjimharris}
207230557Sjimharris
208230557Sjimharris/*
209230557Sjimharris * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
210230557Sjimharris * problems by using a bounce buffer.
211230557Sjimharris */
212230557Sjimharrisvoid
213230557Sjimharrisisa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan)
214230557Sjimharris{
215230557Sjimharris	vm_offset_t phys;
216230557Sjimharris	int waport;
217230557Sjimharris	caddr_t newaddr;
218230557Sjimharris
219230557Sjimharris#ifdef DIAGNOSTIC
220230557Sjimharris	if (chan & ~VALID_DMA_MASK)
221230557Sjimharris		panic("isa_dmastart: channel out of range");
222230557Sjimharris
223230557Sjimharris	if ((chan < 4 && nbytes > (1<<16))
224230557Sjimharris	    || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1)))
225230557Sjimharris		panic("isa_dmastart: impossible request");
226230557Sjimharris
227230557Sjimharris	if ((dma_inuse & (1 << chan)) == 0)
228230557Sjimharris		printf("isa_dmastart: channel %d not acquired\n", chan);
229230557Sjimharris#endif
230230557Sjimharris
231230557Sjimharris#if 0
232230557Sjimharris	/*
233230557Sjimharris	 * XXX This should be checked, but drivers like ad1848 only call
234230557Sjimharris	 * isa_dmastart() once because they use Auto DMA mode.  If we
235230557Sjimharris	 * leave this in, drivers that do this will print this continuously.
236230557Sjimharris	 */
237230557Sjimharris	if (dma_busy & (1 << chan))
238230557Sjimharris		printf("isa_dmastart: channel %d busy\n", chan);
239230557Sjimharris#endif
240230557Sjimharris
241230557Sjimharris	dma_busy |= (1 << chan);
242230557Sjimharris
243230557Sjimharris	if (isa_dmarangecheck(addr, nbytes, chan)) {
244230557Sjimharris		if (dma_bouncebuf[chan] == NULL
245230557Sjimharris		    || dma_bouncebufsize[chan] < nbytes)
246230557Sjimharris			panic("isa_dmastart: bad bounce buffer");
247230557Sjimharris		dma_bounced |= (1 << chan);
248230557Sjimharris		newaddr = dma_bouncebuf[chan];
249230557Sjimharris
250230557Sjimharris		/* copy bounce buffer on write */
251230557Sjimharris		if (!(flags & ISADMA_READ))
252230557Sjimharris			bcopy(addr, newaddr, nbytes);
253230557Sjimharris		addr = newaddr;
254230557Sjimharris	}
255230557Sjimharris
256230557Sjimharris	/* translate to physical */
257230557Sjimharris	mtx_lock(&vm_mtx);	/*
258230557Sjimharris				 * XXX: need to hold for longer period to
259230557Sjimharris				 * ensure that mappings don't change
260230557Sjimharris				 */
261230557Sjimharris	phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr);
262230557Sjimharris	mtx_unlock(&vm_mtx);
263230557Sjimharris
264230557Sjimharris	if (flags & ISADMA_RAW) {
265230557Sjimharris	    dma_auto_mode |= (1 << chan);
266230557Sjimharris	} else {
267230557Sjimharris	    dma_auto_mode &= ~(1 << chan);
268230557Sjimharris	}
269230557Sjimharris
270230557Sjimharris	if ((chan & 4) == 0) {
271230557Sjimharris		/*
272230557Sjimharris		 * Program one of DMA channels 0..3.  These are
273230557Sjimharris		 * byte mode channels.
274230557Sjimharris		 */
275230557Sjimharris		/* set dma channel mode, and reset address ff */
276230557Sjimharris
277230557Sjimharris		/* If ISADMA_RAW flag is set, then use autoinitialise mode */
278230557Sjimharris		if (flags & ISADMA_RAW) {
279230557Sjimharris		  if (flags & ISADMA_READ)
280230557Sjimharris			outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan);
281230557Sjimharris		  else
282230557Sjimharris			outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan);
283230557Sjimharris		}
284230557Sjimharris		else
285230557Sjimharris		if (flags & ISADMA_READ)
286230557Sjimharris			outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
287230557Sjimharris		else
288230557Sjimharris			outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
289230557Sjimharris		outb(DMA1_FFC, 0);
290230557Sjimharris
291230557Sjimharris		/* send start address */
292230557Sjimharris		waport =  DMA1_CHN(chan);
293230557Sjimharris		outb(waport, phys);
294230557Sjimharris		outb(waport, phys>>8);
295230557Sjimharris		outb(dmapageport[chan], phys>>16);
296230557Sjimharris
297230557Sjimharris		/* send count */
298230557Sjimharris		outb(waport + 1, --nbytes);
299230557Sjimharris		outb(waport + 1, nbytes>>8);
300230557Sjimharris
301230557Sjimharris		/* unmask channel */
302230557Sjimharris		outb(DMA1_SMSK, chan);
303230557Sjimharris	} else {
304230557Sjimharris		/*
305230557Sjimharris		 * Program one of DMA channels 4..7.  These are
306		 * word mode channels.
307		 */
308		/* set dma channel mode, and reset address ff */
309
310		/* If ISADMA_RAW flag is set, then use autoinitialise mode */
311		if (flags & ISADMA_RAW) {
312		  if (flags & ISADMA_READ)
313			outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3));
314		  else
315			outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3));
316		}
317		else
318		if (flags & ISADMA_READ)
319			outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
320		else
321			outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
322		outb(DMA2_FFC, 0);
323
324		/* send start address */
325		waport = DMA2_CHN(chan - 4);
326		outb(waport, phys>>1);
327		outb(waport, phys>>9);
328		outb(dmapageport[chan], phys>>16);
329
330		/* send count */
331		nbytes >>= 1;
332		outb(waport + 2, --nbytes);
333		outb(waport + 2, nbytes>>8);
334
335		/* unmask channel */
336		outb(DMA2_SMSK, chan & 3);
337	}
338}
339
340void
341isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
342{
343#ifdef DIAGNOSTIC
344	if (chan & ~VALID_DMA_MASK)
345		panic("isa_dmadone: channel out of range");
346
347	if ((dma_inuse & (1 << chan)) == 0)
348		printf("isa_dmadone: channel %d not acquired\n", chan);
349#endif
350
351	if (((dma_busy & (1 << chan)) == 0) &&
352	    (dma_auto_mode & (1 << chan)) == 0 )
353		printf("isa_dmadone: channel %d not busy\n", chan);
354
355	if ((dma_auto_mode & (1 << chan)) == 0)
356		outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4);
357
358	if (dma_bounced & (1 << chan)) {
359		/* copy bounce buffer on read */
360		if (flags & ISADMA_READ)
361			bcopy(dma_bouncebuf[chan], addr, nbytes);
362
363		dma_bounced &= ~(1 << chan);
364	}
365	dma_busy &= ~(1 << chan);
366}
367
368/*
369 * Check for problems with the address range of a DMA transfer
370 * (non-contiguous physical pages, outside of bus address space,
371 * crossing DMA page boundaries).
372 * Return true if special handling needed.
373 */
374
375static int
376isa_dmarangecheck(caddr_t va, u_int length, int chan)
377{
378	vm_offset_t phys, priorpage = 0, endva;
379	u_int dma_pgmsk = (chan & 4) ?  ~(128*1024-1) : ~(64*1024-1);
380
381	endva = (vm_offset_t)round_page((vm_offset_t)va + length);
382	for (; va < (caddr_t) endva ; va += PAGE_SIZE) {
383		mtx_lock(&vm_mtx);
384		phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va));
385		mtx_unlock(&vm_mtx);
386#define ISARAM_END	RAM_END
387		if (phys == 0)
388			panic("isa_dmacheck: no physical page present");
389		if (phys >= ISARAM_END)
390			return (1);
391		if (priorpage) {
392			if (priorpage + PAGE_SIZE != phys)
393				return (1);
394			/* check if crossing a DMA page boundary */
395			if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
396				return (1);
397		}
398		priorpage = phys;
399	}
400	return (0);
401}
402
403/*
404 * Query the progress of a transfer on a DMA channel.
405 *
406 * To avoid having to interrupt a transfer in progress, we sample
407 * each of the high and low databytes twice, and apply the following
408 * logic to determine the correct count.
409 *
410 * Reads are performed with interrupts disabled, thus it is to be
411 * expected that the time between reads is very small.  At most
412 * one rollover in the low count byte can be expected within the
413 * four reads that are performed.
414 *
415 * There are three gaps in which a rollover can occur :
416 *
417 * - read low1
418 *              gap1
419 * - read high1
420 *              gap2
421 * - read low2
422 *              gap3
423 * - read high2
424 *
425 * If a rollover occurs in gap1 or gap2, the low2 value will be
426 * greater than the low1 value.  In this case, low2 and high2 are a
427 * corresponding pair.
428 *
429 * In any other case, low1 and high1 can be considered to be correct.
430 *
431 * The function returns the number of bytes remaining in the transfer,
432 * or -1 if the channel requested is not active.
433 *
434 */
435int
436isa_dmastatus(int chan)
437{
438	u_long	cnt = 0;
439	int	ffport, waport;
440	u_long	low1, high1, low2, high2;
441
442	/* channel active? */
443	if ((dma_inuse & (1 << chan)) == 0) {
444		printf("isa_dmastatus: channel %d not active\n", chan);
445		return(-1);
446	}
447	/* channel busy? */
448
449	if (((dma_busy & (1 << chan)) == 0) &&
450	    (dma_auto_mode & (1 << chan)) == 0 ) {
451	    printf("chan %d not busy\n", chan);
452	    return -2 ;
453	}
454	if (chan < 4) {			/* low DMA controller */
455		ffport = DMA1_FFC;
456		waport = DMA1_CHN(chan) + 1;
457	} else {			/* high DMA controller */
458		ffport = DMA2_FFC;
459		waport = DMA2_CHN(chan - 4) + 2;
460	}
461
462	disable_intr();			/* no interrupts Mr Jones! */
463	outb(ffport, 0);		/* clear register LSB flipflop */
464	low1 = inb(waport);
465	high1 = inb(waport);
466	outb(ffport, 0);		/* clear again */
467	low2 = inb(waport);
468	high2 = inb(waport);
469	enable_intr();			/* enable interrupts again */
470
471	/*
472	 * Now decide if a wrap has tried to skew our results.
473	 * Note that after TC, the count will read 0xffff, while we want
474	 * to return zero, so we add and then mask to compensate.
475	 */
476	if (low1 >= low2) {
477		cnt = (low1 + (high1 << 8) + 1) & 0xffff;
478	} else {
479		cnt = (low2 + (high2 << 8) + 1) & 0xffff;
480	}
481
482	if (chan >= 4)			/* high channels move words */
483		cnt *= 2;
484	return(cnt);
485}
486
487/*
488 * Stop a DMA transfer currently in progress.
489 */
490int
491isa_dmastop(int chan)
492{
493	if ((dma_inuse & (1 << chan)) == 0)
494		printf("isa_dmastop: channel %d not acquired\n", chan);
495
496	if (((dma_busy & (1 << chan)) == 0) &&
497	    ((dma_auto_mode & (1 << chan)) == 0)) {
498		printf("chan %d not busy\n", chan);
499		return -2 ;
500	}
501
502	if ((chan & 4) == 0) {
503		outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */);
504	} else {
505		outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */);
506	}
507	return(isa_dmastatus(chan));
508}
509
510/*
511 * Attach to the ISA PnP descriptor for the AT DMA controller
512 */
513static struct isa_pnp_id atdma_ids[] = {
514	{ 0x0002d041 /* PNP0200 */, "AT DMA controller" },
515	{ 0 }
516};
517
518static int
519atdma_probe(device_t dev)
520{
521	int result;
522
523	if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0)
524		device_quiet(dev);
525	return(result);
526}
527
528static int
529atdma_attach(device_t dev)
530{
531	return(0);
532}
533
534static device_method_t atdma_methods[] = {
535	/* Device interface */
536	DEVMETHOD(device_probe,		atdma_probe),
537	DEVMETHOD(device_attach,	atdma_attach),
538	DEVMETHOD(device_detach,	bus_generic_detach),
539	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
540	DEVMETHOD(device_suspend,	bus_generic_suspend),
541	DEVMETHOD(device_resume,	bus_generic_resume),
542	{ 0, 0 }
543};
544
545static driver_t atdma_driver = {
546	"atdma",
547	atdma_methods,
548	1,		/* no softc */
549};
550
551static devclass_t atdma_devclass;
552
553DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0);
554