isa_dma.c revision 45897
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 * $Id: isa_dma.c,v 1.1 1999/04/16 21:22:24 peter Exp $ 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/buf.h> 53#include <sys/malloc.h> 54#include <machine/ipl.h> 55#include <machine/md_var.h> 56#ifdef APIC_IO 57#include <machine/smp.h> 58#endif /* APIC_IO */ 59#include <vm/vm.h> 60#include <vm/vm_param.h> 61#include <vm/pmap.h> 62#include <i386/isa/isa_device.h> 63#include <i386/isa/isa.h> 64#include <i386/isa/ic/i8237.h> 65 66#include <sys/interrupt.h> 67 68#include "pnp.h" 69#if NPNP > 0 70#include <i386/isa/pnp.h> 71#endif 72 73/* 74** Register definitions for DMA controller 1 (channels 0..3): 75*/ 76#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 77#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 78#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 79#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 80 81/* 82** Register definitions for DMA controller 2 (channels 4..7): 83*/ 84#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 85#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 86#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 87#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 88 89static int isa_dmarangecheck __P((caddr_t va, u_int length, int chan)); 90 91static caddr_t dma_bouncebuf[8]; 92static u_int dma_bouncebufsize[8]; 93static u_int8_t dma_bounced = 0; 94static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 95static u_int8_t dma_inuse = 0; /* User for acquire/release */ 96static u_int8_t dma_auto_mode = 0; 97 98#define VALID_DMA_MASK (7) 99 100/* high byte of address is stored in this port for i-th dma channel */ 101static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 102 103/* 104 * Setup a DMA channel's bounce buffer. 105 */ 106void 107isa_dmainit(chan, bouncebufsize) 108 int chan; 109 u_int bouncebufsize; 110{ 111 void *buf; 112 113#ifdef DIAGNOSTIC 114 if (chan & ~VALID_DMA_MASK) 115 panic("isa_dmainit: channel out of range"); 116 117 if (dma_bouncebuf[chan] != NULL) 118 panic("isa_dmainit: impossible request"); 119#endif 120 121 dma_bouncebufsize[chan] = bouncebufsize; 122 123 /* Try malloc() first. It works better if it works. */ 124 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 125 if (buf != NULL) { 126 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 127 dma_bouncebuf[chan] = buf; 128 return; 129 } 130 free(buf, M_DEVBUF); 131 } 132 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 133 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 134 if (buf == NULL) 135 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 136 else 137 dma_bouncebuf[chan] = buf; 138} 139 140/* 141 * Register a DMA channel's usage. Usually called from a device driver 142 * in open() or during its initialization. 143 */ 144int 145isa_dma_acquire(chan) 146 int chan; 147{ 148#ifdef DIAGNOSTIC 149 if (chan & ~VALID_DMA_MASK) 150 panic("isa_dma_acquire: channel out of range"); 151#endif 152 153 if (dma_inuse & (1 << chan)) { 154 printf("isa_dma_acquire: channel %d already in use\n", chan); 155 return (EBUSY); 156 } 157 dma_inuse |= (1 << chan); 158 dma_auto_mode &= ~(1 << chan); 159 160 return (0); 161} 162 163/* 164 * Unregister a DMA channel's usage. Usually called from a device driver 165 * during close() or during its shutdown. 166 */ 167void 168isa_dma_release(chan) 169 int chan; 170{ 171#ifdef DIAGNOSTIC 172 if (chan & ~VALID_DMA_MASK) 173 panic("isa_dma_release: channel out of range"); 174 175 if ((dma_inuse & (1 << chan)) == 0) 176 printf("isa_dma_release: channel %d not in use\n", chan); 177#endif 178 179 if (dma_busy & (1 << chan)) { 180 dma_busy &= ~(1 << chan); 181 /* 182 * XXX We should also do "dma_bounced &= (1 << chan);" 183 * because we are acting on behalf of isa_dmadone() which 184 * was not called to end the last DMA operation. This does 185 * not matter now, but it may in the future. 186 */ 187 } 188 189 dma_inuse &= ~(1 << chan); 190 dma_auto_mode &= ~(1 << chan); 191} 192 193/* 194 * isa_dmacascade(): program 8237 DMA controller channel to accept 195 * external dma control by a board. 196 */ 197void 198isa_dmacascade(chan) 199 int chan; 200{ 201#ifdef DIAGNOSTIC 202 if (chan & ~VALID_DMA_MASK) 203 panic("isa_dmacascade: channel out of range"); 204#endif 205 206 /* set dma channel mode, and set dma channel mode */ 207 if ((chan & 4) == 0) { 208 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 209 outb(DMA1_SMSK, chan); 210 } else { 211 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 212 outb(DMA2_SMSK, chan & 3); 213 } 214} 215 216/* 217 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 218 * problems by using a bounce buffer. 219 */ 220void 221isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 222{ 223 vm_offset_t phys; 224 int waport; 225 caddr_t newaddr; 226 227#ifdef DIAGNOSTIC 228 if (chan & ~VALID_DMA_MASK) 229 panic("isa_dmastart: channel out of range"); 230 231 if ((chan < 4 && nbytes > (1<<16)) 232 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 233 panic("isa_dmastart: impossible request"); 234 235 if ((dma_inuse & (1 << chan)) == 0) 236 printf("isa_dmastart: channel %d not acquired\n", chan); 237#endif 238 239#if 0 240 /* 241 * XXX This should be checked, but drivers like ad1848 only call 242 * isa_dmastart() once because they use Auto DMA mode. If we 243 * leave this in, drivers that do this will print this continuously. 244 */ 245 if (dma_busy & (1 << chan)) 246 printf("isa_dmastart: channel %d busy\n", chan); 247#endif 248 249 dma_busy |= (1 << chan); 250 251 if (isa_dmarangecheck(addr, nbytes, chan)) { 252 if (dma_bouncebuf[chan] == NULL 253 || dma_bouncebufsize[chan] < nbytes) 254 panic("isa_dmastart: bad bounce buffer"); 255 dma_bounced |= (1 << chan); 256 newaddr = dma_bouncebuf[chan]; 257 258 /* copy bounce buffer on write */ 259 if (!(flags & B_READ)) 260 bcopy(addr, newaddr, nbytes); 261 addr = newaddr; 262 } 263 264 /* translate to physical */ 265 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 266 267 if (flags & B_RAW) { 268 dma_auto_mode |= (1 << chan); 269 } else { 270 dma_auto_mode &= ~(1 << chan); 271 } 272 273 if ((chan & 4) == 0) { 274 /* 275 * Program one of DMA channels 0..3. These are 276 * byte mode channels. 277 */ 278 /* set dma channel mode, and reset address ff */ 279 280 /* If B_RAW flag is set, then use autoinitialise mode */ 281 if (flags & B_RAW) { 282 if (flags & B_READ) 283 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 284 else 285 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 286 } 287 else 288 if (flags & B_READ) 289 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 290 else 291 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 292 outb(DMA1_FFC, 0); 293 294 /* send start address */ 295 waport = DMA1_CHN(chan); 296 outb(waport, phys); 297 outb(waport, phys>>8); 298 outb(dmapageport[chan], phys>>16); 299 300 /* send count */ 301 outb(waport + 1, --nbytes); 302 outb(waport + 1, nbytes>>8); 303 304 /* unmask channel */ 305 outb(DMA1_SMSK, chan); 306 } else { 307 /* 308 * Program one of DMA channels 4..7. These are 309 * word mode channels. 310 */ 311 /* set dma channel mode, and reset address ff */ 312 313 /* If B_RAW flag is set, then use autoinitialise mode */ 314 if (flags & B_RAW) { 315 if (flags & B_READ) 316 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 317 else 318 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 319 } 320 else 321 if (flags & B_READ) 322 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 323 else 324 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 325 outb(DMA2_FFC, 0); 326 327 /* send start address */ 328 waport = DMA2_CHN(chan - 4); 329 outb(waport, phys>>1); 330 outb(waport, phys>>9); 331 outb(dmapageport[chan], phys>>16); 332 333 /* send count */ 334 nbytes >>= 1; 335 outb(waport + 2, --nbytes); 336 outb(waport + 2, nbytes>>8); 337 338 /* unmask channel */ 339 outb(DMA2_SMSK, chan & 3); 340 } 341} 342 343void 344isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 345{ 346#ifdef DIAGNOSTIC 347 if (chan & ~VALID_DMA_MASK) 348 panic("isa_dmadone: channel out of range"); 349 350 if ((dma_inuse & (1 << chan)) == 0) 351 printf("isa_dmadone: channel %d not acquired\n", chan); 352#endif 353 354 if (((dma_busy & (1 << chan)) == 0) && 355 (dma_auto_mode & (1 << chan)) == 0 ) 356 printf("isa_dmadone: channel %d not busy\n", chan); 357 358 if ((dma_auto_mode & (1 << chan)) == 0) 359 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 360 361 if (dma_bounced & (1 << chan)) { 362 /* copy bounce buffer on read */ 363 if (flags & B_READ) 364 bcopy(dma_bouncebuf[chan], addr, nbytes); 365 366 dma_bounced &= ~(1 << chan); 367 } 368 dma_busy &= ~(1 << chan); 369} 370 371/* 372 * Check for problems with the address range of a DMA transfer 373 * (non-contiguous physical pages, outside of bus address space, 374 * crossing DMA page boundaries). 375 * Return true if special handling needed. 376 */ 377 378static int 379isa_dmarangecheck(caddr_t va, u_int length, int chan) 380{ 381 vm_offset_t phys, priorpage = 0, endva; 382 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 383 384 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 385 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 386 phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 387#define ISARAM_END RAM_END 388 if (phys == 0) 389 panic("isa_dmacheck: no physical page present"); 390 if (phys >= ISARAM_END) 391 return (1); 392 if (priorpage) { 393 if (priorpage + PAGE_SIZE != phys) 394 return (1); 395 /* check if crossing a DMA page boundary */ 396 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 397 return (1); 398 } 399 priorpage = phys; 400 } 401 return (0); 402} 403 404/* 405 * Query the progress of a transfer on a DMA channel. 406 * 407 * To avoid having to interrupt a transfer in progress, we sample 408 * each of the high and low databytes twice, and apply the following 409 * logic to determine the correct count. 410 * 411 * Reads are performed with interrupts disabled, thus it is to be 412 * expected that the time between reads is very small. At most 413 * one rollover in the low count byte can be expected within the 414 * four reads that are performed. 415 * 416 * There are three gaps in which a rollover can occur : 417 * 418 * - read low1 419 * gap1 420 * - read high1 421 * gap2 422 * - read low2 423 * gap3 424 * - read high2 425 * 426 * If a rollover occurs in gap1 or gap2, the low2 value will be 427 * greater than the low1 value. In this case, low2 and high2 are a 428 * corresponding pair. 429 * 430 * In any other case, low1 and high1 can be considered to be correct. 431 * 432 * The function returns the number of bytes remaining in the transfer, 433 * or -1 if the channel requested is not active. 434 * 435 */ 436int 437isa_dmastatus(int chan) 438{ 439 u_long cnt = 0; 440 int ffport, waport; 441 u_long low1, high1, low2, high2; 442 443 /* channel active? */ 444 if ((dma_inuse & (1 << chan)) == 0) { 445 printf("isa_dmastatus: channel %d not active\n", chan); 446 return(-1); 447 } 448 /* channel busy? */ 449 450 if (((dma_busy & (1 << chan)) == 0) && 451 (dma_auto_mode & (1 << chan)) == 0 ) { 452 printf("chan %d not busy\n", chan); 453 return -2 ; 454 } 455 if (chan < 4) { /* low DMA controller */ 456 ffport = DMA1_FFC; 457 waport = DMA1_CHN(chan) + 1; 458 } else { /* high DMA controller */ 459 ffport = DMA2_FFC; 460 waport = DMA2_CHN(chan - 4) + 2; 461 } 462 463 disable_intr(); /* no interrupts Mr Jones! */ 464 outb(ffport, 0); /* clear register LSB flipflop */ 465 low1 = inb(waport); 466 high1 = inb(waport); 467 outb(ffport, 0); /* clear again */ 468 low2 = inb(waport); 469 high2 = inb(waport); 470 enable_intr(); /* enable interrupts again */ 471 472 /* 473 * Now decide if a wrap has tried to skew our results. 474 * Note that after TC, the count will read 0xffff, while we want 475 * to return zero, so we add and then mask to compensate. 476 */ 477 if (low1 >= low2) { 478 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 479 } else { 480 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 481 } 482 483 if (chan >= 4) /* high channels move words */ 484 cnt *= 2; 485 return(cnt); 486} 487 488/* 489 * Stop a DMA transfer currently in progress. 490 */ 491int 492isa_dmastop(int chan) 493{ 494 if ((dma_inuse & (1 << chan)) == 0) 495 printf("isa_dmastop: channel %d not acquired\n", chan); 496 497 if (((dma_busy & (1 << chan)) == 0) && 498 ((dma_auto_mode & (1 << chan)) == 0)) { 499 printf("chan %d not busy\n", chan); 500 return -2 ; 501 } 502 503 if ((chan & 4) == 0) { 504 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 505 } else { 506 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 507 } 508 return(isa_dmastatus(chan)); 509} 510