isa_dma.c revision 45720
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 * $Id: isa.c,v 1.117 1998/11/29 15:42:40 phk Exp $ 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/buf.h> 53#include <sys/malloc.h> 54#include <machine/ipl.h> 55#include <machine/md_var.h> 56#ifdef APIC_IO 57#include <machine/smp.h> 58#endif /* APIC_IO */ 59#include <vm/vm.h> 60#include <vm/vm_param.h> 61#include <vm/pmap.h> 62#include <i386/isa/isa_device.h> 63#include <i386/isa/intr_machdep.h> 64#include <i386/isa/isa.h> 65#include <i386/isa/ic/i8237.h> 66 67#include <sys/interrupt.h> 68 69#include "pnp.h" 70#if NPNP > 0 71#include <i386/isa/pnp.h> 72#endif 73 74/* 75** Register definitions for DMA controller 1 (channels 0..3): 76*/ 77#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 78#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 79#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 80#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 81 82/* 83** Register definitions for DMA controller 2 (channels 4..7): 84*/ 85#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 86#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 87#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 88#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 89 90static int isa_dmarangecheck __P((caddr_t va, u_int length, int chan)); 91 92static caddr_t dma_bouncebuf[8]; 93static u_int dma_bouncebufsize[8]; 94static u_int8_t dma_bounced = 0; 95static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 96static u_int8_t dma_inuse = 0; /* User for acquire/release */ 97static u_int8_t dma_auto_mode = 0; 98 99#define VALID_DMA_MASK (7) 100 101/* high byte of address is stored in this port for i-th dma channel */ 102static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 103 104/* 105 * Setup a DMA channel's bounce buffer. 106 */ 107void 108isa_dmainit(chan, bouncebufsize) 109 int chan; 110 u_int bouncebufsize; 111{ 112 void *buf; 113 114#ifdef DIAGNOSTIC 115 if (chan & ~VALID_DMA_MASK) 116 panic("isa_dmainit: channel out of range"); 117 118 if (dma_bouncebuf[chan] != NULL) 119 panic("isa_dmainit: impossible request"); 120#endif 121 122 dma_bouncebufsize[chan] = bouncebufsize; 123 124 /* Try malloc() first. It works better if it works. */ 125 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 126 if (buf != NULL) { 127 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 128 dma_bouncebuf[chan] = buf; 129 return; 130 } 131 free(buf, M_DEVBUF); 132 } 133 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 134 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 135 if (buf == NULL) 136 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 137 else 138 dma_bouncebuf[chan] = buf; 139} 140 141/* 142 * Register a DMA channel's usage. Usually called from a device driver 143 * in open() or during its initialization. 144 */ 145int 146isa_dma_acquire(chan) 147 int chan; 148{ 149#ifdef DIAGNOSTIC 150 if (chan & ~VALID_DMA_MASK) 151 panic("isa_dma_acquire: channel out of range"); 152#endif 153 154 if (dma_inuse & (1 << chan)) { 155 printf("isa_dma_acquire: channel %d already in use\n", chan); 156 return (EBUSY); 157 } 158 dma_inuse |= (1 << chan); 159 dma_auto_mode &= ~(1 << chan); 160 161 return (0); 162} 163 164/* 165 * Unregister a DMA channel's usage. Usually called from a device driver 166 * during close() or during its shutdown. 167 */ 168void 169isa_dma_release(chan) 170 int chan; 171{ 172#ifdef DIAGNOSTIC 173 if (chan & ~VALID_DMA_MASK) 174 panic("isa_dma_release: channel out of range"); 175 176 if ((dma_inuse & (1 << chan)) == 0) 177 printf("isa_dma_release: channel %d not in use\n", chan); 178#endif 179 180 if (dma_busy & (1 << chan)) { 181 dma_busy &= ~(1 << chan); 182 /* 183 * XXX We should also do "dma_bounced &= (1 << chan);" 184 * because we are acting on behalf of isa_dmadone() which 185 * was not called to end the last DMA operation. This does 186 * not matter now, but it may in the future. 187 */ 188 } 189 190 dma_inuse &= ~(1 << chan); 191 dma_auto_mode &= ~(1 << chan); 192} 193 194/* 195 * isa_dmacascade(): program 8237 DMA controller channel to accept 196 * external dma control by a board. 197 */ 198void 199isa_dmacascade(chan) 200 int chan; 201{ 202#ifdef DIAGNOSTIC 203 if (chan & ~VALID_DMA_MASK) 204 panic("isa_dmacascade: channel out of range"); 205#endif 206 207 /* set dma channel mode, and set dma channel mode */ 208 if ((chan & 4) == 0) { 209 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 210 outb(DMA1_SMSK, chan); 211 } else { 212 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 213 outb(DMA2_SMSK, chan & 3); 214 } 215} 216 217/* 218 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 219 * problems by using a bounce buffer. 220 */ 221void 222isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 223{ 224 vm_offset_t phys; 225 int waport; 226 caddr_t newaddr; 227 228#ifdef DIAGNOSTIC 229 if (chan & ~VALID_DMA_MASK) 230 panic("isa_dmastart: channel out of range"); 231 232 if ((chan < 4 && nbytes > (1<<16)) 233 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 234 panic("isa_dmastart: impossible request"); 235 236 if ((dma_inuse & (1 << chan)) == 0) 237 printf("isa_dmastart: channel %d not acquired\n", chan); 238#endif 239 240#if 0 241 /* 242 * XXX This should be checked, but drivers like ad1848 only call 243 * isa_dmastart() once because they use Auto DMA mode. If we 244 * leave this in, drivers that do this will print this continuously. 245 */ 246 if (dma_busy & (1 << chan)) 247 printf("isa_dmastart: channel %d busy\n", chan); 248#endif 249 250 dma_busy |= (1 << chan); 251 252 if (isa_dmarangecheck(addr, nbytes, chan)) { 253 if (dma_bouncebuf[chan] == NULL 254 || dma_bouncebufsize[chan] < nbytes) 255 panic("isa_dmastart: bad bounce buffer"); 256 dma_bounced |= (1 << chan); 257 newaddr = dma_bouncebuf[chan]; 258 259 /* copy bounce buffer on write */ 260 if (!(flags & B_READ)) 261 bcopy(addr, newaddr, nbytes); 262 addr = newaddr; 263 } 264 265 /* translate to physical */ 266 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 267 268 if (flags & B_RAW) { 269 dma_auto_mode |= (1 << chan); 270 } else { 271 dma_auto_mode &= ~(1 << chan); 272 } 273 274 if ((chan & 4) == 0) { 275 /* 276 * Program one of DMA channels 0..3. These are 277 * byte mode channels. 278 */ 279 /* set dma channel mode, and reset address ff */ 280 281 /* If B_RAW flag is set, then use autoinitialise mode */ 282 if (flags & B_RAW) { 283 if (flags & B_READ) 284 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 285 else 286 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 287 } 288 else 289 if (flags & B_READ) 290 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 291 else 292 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 293 outb(DMA1_FFC, 0); 294 295 /* send start address */ 296 waport = DMA1_CHN(chan); 297 outb(waport, phys); 298 outb(waport, phys>>8); 299 outb(dmapageport[chan], phys>>16); 300 301 /* send count */ 302 outb(waport + 1, --nbytes); 303 outb(waport + 1, nbytes>>8); 304 305 /* unmask channel */ 306 outb(DMA1_SMSK, chan); 307 } else { 308 /* 309 * Program one of DMA channels 4..7. These are 310 * word mode channels. 311 */ 312 /* set dma channel mode, and reset address ff */ 313 314 /* If B_RAW flag is set, then use autoinitialise mode */ 315 if (flags & B_RAW) { 316 if (flags & B_READ) 317 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 318 else 319 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 320 } 321 else 322 if (flags & B_READ) 323 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 324 else 325 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 326 outb(DMA2_FFC, 0); 327 328 /* send start address */ 329 waport = DMA2_CHN(chan - 4); 330 outb(waport, phys>>1); 331 outb(waport, phys>>9); 332 outb(dmapageport[chan], phys>>16); 333 334 /* send count */ 335 nbytes >>= 1; 336 outb(waport + 2, --nbytes); 337 outb(waport + 2, nbytes>>8); 338 339 /* unmask channel */ 340 outb(DMA2_SMSK, chan & 3); 341 } 342} 343 344void 345isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 346{ 347#ifdef DIAGNOSTIC 348 if (chan & ~VALID_DMA_MASK) 349 panic("isa_dmadone: channel out of range"); 350 351 if ((dma_inuse & (1 << chan)) == 0) 352 printf("isa_dmadone: channel %d not acquired\n", chan); 353#endif 354 355 if (((dma_busy & (1 << chan)) == 0) && 356 (dma_auto_mode & (1 << chan)) == 0 ) 357 printf("isa_dmadone: channel %d not busy\n", chan); 358 359 if ((dma_auto_mode & (1 << chan)) == 0) 360 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 361 362 if (dma_bounced & (1 << chan)) { 363 /* copy bounce buffer on read */ 364 if (flags & B_READ) 365 bcopy(dma_bouncebuf[chan], addr, nbytes); 366 367 dma_bounced &= ~(1 << chan); 368 } 369 dma_busy &= ~(1 << chan); 370} 371 372/* 373 * Check for problems with the address range of a DMA transfer 374 * (non-contiguous physical pages, outside of bus address space, 375 * crossing DMA page boundaries). 376 * Return true if special handling needed. 377 */ 378 379static int 380isa_dmarangecheck(caddr_t va, u_int length, int chan) 381{ 382 vm_offset_t phys, priorpage = 0, endva; 383 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 384 385 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 386 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 387 phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 388#define ISARAM_END RAM_END 389 if (phys == 0) 390 panic("isa_dmacheck: no physical page present"); 391 if (phys >= ISARAM_END) 392 return (1); 393 if (priorpage) { 394 if (priorpage + PAGE_SIZE != phys) 395 return (1); 396 /* check if crossing a DMA page boundary */ 397 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 398 return (1); 399 } 400 priorpage = phys; 401 } 402 return (0); 403} 404 405/* 406 * Query the progress of a transfer on a DMA channel. 407 * 408 * To avoid having to interrupt a transfer in progress, we sample 409 * each of the high and low databytes twice, and apply the following 410 * logic to determine the correct count. 411 * 412 * Reads are performed with interrupts disabled, thus it is to be 413 * expected that the time between reads is very small. At most 414 * one rollover in the low count byte can be expected within the 415 * four reads that are performed. 416 * 417 * There are three gaps in which a rollover can occur : 418 * 419 * - read low1 420 * gap1 421 * - read high1 422 * gap2 423 * - read low2 424 * gap3 425 * - read high2 426 * 427 * If a rollover occurs in gap1 or gap2, the low2 value will be 428 * greater than the low1 value. In this case, low2 and high2 are a 429 * corresponding pair. 430 * 431 * In any other case, low1 and high1 can be considered to be correct. 432 * 433 * The function returns the number of bytes remaining in the transfer, 434 * or -1 if the channel requested is not active. 435 * 436 */ 437int 438isa_dmastatus(int chan) 439{ 440 u_long cnt = 0; 441 int ffport, waport; 442 u_long low1, high1, low2, high2; 443 444 /* channel active? */ 445 if ((dma_inuse & (1 << chan)) == 0) { 446 printf("isa_dmastatus: channel %d not active\n", chan); 447 return(-1); 448 } 449 /* channel busy? */ 450 451 if (((dma_busy & (1 << chan)) == 0) && 452 (dma_auto_mode & (1 << chan)) == 0 ) { 453 printf("chan %d not busy\n", chan); 454 return -2 ; 455 } 456 if (chan < 4) { /* low DMA controller */ 457 ffport = DMA1_FFC; 458 waport = DMA1_CHN(chan) + 1; 459 } else { /* high DMA controller */ 460 ffport = DMA2_FFC; 461 waport = DMA2_CHN(chan - 4) + 2; 462 } 463 464 disable_intr(); /* no interrupts Mr Jones! */ 465 outb(ffport, 0); /* clear register LSB flipflop */ 466 low1 = inb(waport); 467 high1 = inb(waport); 468 outb(ffport, 0); /* clear again */ 469 low2 = inb(waport); 470 high2 = inb(waport); 471 enable_intr(); /* enable interrupts again */ 472 473 /* 474 * Now decide if a wrap has tried to skew our results. 475 * Note that after TC, the count will read 0xffff, while we want 476 * to return zero, so we add and then mask to compensate. 477 */ 478 if (low1 >= low2) { 479 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 480 } else { 481 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 482 } 483 484 if (chan >= 4) /* high channels move words */ 485 cnt *= 2; 486 return(cnt); 487} 488 489/* 490 * Stop a DMA transfer currently in progress. 491 */ 492int 493isa_dmastop(int chan) 494{ 495 if ((dma_inuse & (1 << chan)) == 0) 496 printf("isa_dmastop: channel %d not acquired\n", chan); 497 498 if (((dma_busy & (1 << chan)) == 0) && 499 ((dma_auto_mode & (1 << chan)) == 0)) { 500 printf("chan %d not busy\n", chan); 501 return -2 ; 502 } 503 504 if ((chan & 4) == 0) { 505 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 506 } else { 507 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 508 } 509 return(isa_dmastatus(chan)); 510} 511