isa_dma.c revision 115703
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 */ 38 39#include <sys/cdefs.h> 40__FBSDID("$FreeBSD: head/sys/i386/isa/isa_dma.c 115703 2003-06-02 16:32:55Z obrien $"); 41 42/* 43 * code to manage AT bus 44 * 45 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 46 * Fixed uninitialized variable problem and added code to deal 47 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 48 * mode DMA count compution and reorganized DMA setup code in 49 * isa_dmastart() 50 */ 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/bus.h> 55#include <sys/kernel.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/proc.h> 59#include <sys/mutex.h> 60#include <sys/module.h> 61#include <vm/vm.h> 62#include <vm/vm_param.h> 63#include <vm/pmap.h> 64#include <i386/isa/isa.h> 65#include <dev/ic/i8237.h> 66#include <isa/isavar.h> 67 68/* 69** Register definitions for DMA controller 1 (channels 0..3): 70*/ 71#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 72#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 73#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 74#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 75 76/* 77** Register definitions for DMA controller 2 (channels 4..7): 78*/ 79#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 80#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 81#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 82#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 83 84static int isa_dmarangecheck(caddr_t va, u_int length, int chan); 85 86static caddr_t dma_bouncebuf[8]; 87static u_int dma_bouncebufsize[8]; 88static u_int8_t dma_bounced = 0; 89static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 90static u_int8_t dma_inuse = 0; /* User for acquire/release */ 91static u_int8_t dma_auto_mode = 0; 92 93#define VALID_DMA_MASK (7) 94 95/* high byte of address is stored in this port for i-th dma channel */ 96static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 97 98/* 99 * Setup a DMA channel's bounce buffer. 100 */ 101void 102isa_dmainit(chan, bouncebufsize) 103 int chan; 104 u_int bouncebufsize; 105{ 106 void *buf; 107 108#ifdef DIAGNOSTIC 109 if (chan & ~VALID_DMA_MASK) 110 panic("isa_dmainit: channel out of range"); 111 112 if (dma_bouncebuf[chan] != NULL) 113 panic("isa_dmainit: impossible request"); 114#endif 115 116 dma_bouncebufsize[chan] = bouncebufsize; 117 118 /* Try malloc() first. It works better if it works. */ 119 buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 120 if (buf != NULL) { 121 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 122 dma_bouncebuf[chan] = buf; 123 return; 124 } 125 free(buf, M_DEVBUF); 126 } 127 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 128 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 129 if (buf == NULL) 130 printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 131 else 132 dma_bouncebuf[chan] = buf; 133} 134 135/* 136 * Register a DMA channel's usage. Usually called from a device driver 137 * in open() or during its initialization. 138 */ 139int 140isa_dma_acquire(chan) 141 int chan; 142{ 143#ifdef DIAGNOSTIC 144 if (chan & ~VALID_DMA_MASK) 145 panic("isa_dma_acquire: channel out of range"); 146#endif 147 148 if (dma_inuse & (1 << chan)) { 149 printf("isa_dma_acquire: channel %d already in use\n", chan); 150 return (EBUSY); 151 } 152 dma_inuse |= (1 << chan); 153 dma_auto_mode &= ~(1 << chan); 154 155 return (0); 156} 157 158/* 159 * Unregister a DMA channel's usage. Usually called from a device driver 160 * during close() or during its shutdown. 161 */ 162void 163isa_dma_release(chan) 164 int chan; 165{ 166#ifdef DIAGNOSTIC 167 if (chan & ~VALID_DMA_MASK) 168 panic("isa_dma_release: channel out of range"); 169 170 if ((dma_inuse & (1 << chan)) == 0) 171 printf("isa_dma_release: channel %d not in use\n", chan); 172#endif 173 174 if (dma_busy & (1 << chan)) { 175 dma_busy &= ~(1 << chan); 176 /* 177 * XXX We should also do "dma_bounced &= (1 << chan);" 178 * because we are acting on behalf of isa_dmadone() which 179 * was not called to end the last DMA operation. This does 180 * not matter now, but it may in the future. 181 */ 182 } 183 184 dma_inuse &= ~(1 << chan); 185 dma_auto_mode &= ~(1 << chan); 186} 187 188/* 189 * isa_dmacascade(): program 8237 DMA controller channel to accept 190 * external dma control by a board. 191 */ 192void 193isa_dmacascade(chan) 194 int chan; 195{ 196#ifdef DIAGNOSTIC 197 if (chan & ~VALID_DMA_MASK) 198 panic("isa_dmacascade: channel out of range"); 199#endif 200 201 /* set dma channel mode, and set dma channel mode */ 202 if ((chan & 4) == 0) { 203 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 204 outb(DMA1_SMSK, chan); 205 } else { 206 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 207 outb(DMA2_SMSK, chan & 3); 208 } 209} 210 211/* 212 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 213 * problems by using a bounce buffer. 214 */ 215void 216isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 217{ 218 vm_paddr_t phys; 219 int waport; 220 caddr_t newaddr; 221 222 GIANT_REQUIRED; 223 224#ifdef DIAGNOSTIC 225 if (chan & ~VALID_DMA_MASK) 226 panic("isa_dmastart: channel out of range"); 227 228 if ((chan < 4 && nbytes > (1<<16)) 229 || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 230 panic("isa_dmastart: impossible request"); 231 232 if ((dma_inuse & (1 << chan)) == 0) 233 printf("isa_dmastart: channel %d not acquired\n", chan); 234#endif 235 236#if 0 237 /* 238 * XXX This should be checked, but drivers like ad1848 only call 239 * isa_dmastart() once because they use Auto DMA mode. If we 240 * leave this in, drivers that do this will print this continuously. 241 */ 242 if (dma_busy & (1 << chan)) 243 printf("isa_dmastart: channel %d busy\n", chan); 244#endif 245 246 dma_busy |= (1 << chan); 247 248 if (isa_dmarangecheck(addr, nbytes, chan)) { 249 if (dma_bouncebuf[chan] == NULL 250 || dma_bouncebufsize[chan] < nbytes) 251 panic("isa_dmastart: bad bounce buffer"); 252 dma_bounced |= (1 << chan); 253 newaddr = dma_bouncebuf[chan]; 254 255 /* copy bounce buffer on write */ 256 if (!(flags & ISADMA_READ)) 257 bcopy(addr, newaddr, nbytes); 258 addr = newaddr; 259 } 260 261 /* translate to physical */ 262 phys = pmap_extract(kernel_pmap, (vm_offset_t)addr); 263 264 if (flags & ISADMA_RAW) { 265 dma_auto_mode |= (1 << chan); 266 } else { 267 dma_auto_mode &= ~(1 << chan); 268 } 269 270 if ((chan & 4) == 0) { 271 /* 272 * Program one of DMA channels 0..3. These are 273 * byte mode channels. 274 */ 275 /* set dma channel mode, and reset address ff */ 276 277 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 278 if (flags & ISADMA_RAW) { 279 if (flags & ISADMA_READ) 280 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 281 else 282 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 283 } 284 else 285 if (flags & ISADMA_READ) 286 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 287 else 288 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 289 outb(DMA1_FFC, 0); 290 291 /* send start address */ 292 waport = DMA1_CHN(chan); 293 outb(waport, phys); 294 outb(waport, phys>>8); 295 outb(dmapageport[chan], phys>>16); 296 297 /* send count */ 298 outb(waport + 1, --nbytes); 299 outb(waport + 1, nbytes>>8); 300 301 /* unmask channel */ 302 outb(DMA1_SMSK, chan); 303 } else { 304 /* 305 * Program one of DMA channels 4..7. These are 306 * word mode channels. 307 */ 308 /* set dma channel mode, and reset address ff */ 309 310 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 311 if (flags & ISADMA_RAW) { 312 if (flags & ISADMA_READ) 313 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 314 else 315 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 316 } 317 else 318 if (flags & ISADMA_READ) 319 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 320 else 321 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 322 outb(DMA2_FFC, 0); 323 324 /* send start address */ 325 waport = DMA2_CHN(chan - 4); 326 outb(waport, phys>>1); 327 outb(waport, phys>>9); 328 outb(dmapageport[chan], phys>>16); 329 330 /* send count */ 331 nbytes >>= 1; 332 outb(waport + 2, --nbytes); 333 outb(waport + 2, nbytes>>8); 334 335 /* unmask channel */ 336 outb(DMA2_SMSK, chan & 3); 337 } 338} 339 340void 341isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 342{ 343#ifdef DIAGNOSTIC 344 if (chan & ~VALID_DMA_MASK) 345 panic("isa_dmadone: channel out of range"); 346 347 if ((dma_inuse & (1 << chan)) == 0) 348 printf("isa_dmadone: channel %d not acquired\n", chan); 349#endif 350 351 if (((dma_busy & (1 << chan)) == 0) && 352 (dma_auto_mode & (1 << chan)) == 0 ) 353 printf("isa_dmadone: channel %d not busy\n", chan); 354 355 if ((dma_auto_mode & (1 << chan)) == 0) 356 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 357 358 if (dma_bounced & (1 << chan)) { 359 /* copy bounce buffer on read */ 360 if (flags & ISADMA_READ) 361 bcopy(dma_bouncebuf[chan], addr, nbytes); 362 363 dma_bounced &= ~(1 << chan); 364 } 365 dma_busy &= ~(1 << chan); 366} 367 368/* 369 * Check for problems with the address range of a DMA transfer 370 * (non-contiguous physical pages, outside of bus address space, 371 * crossing DMA page boundaries). 372 * Return true if special handling needed. 373 */ 374 375static int 376isa_dmarangecheck(caddr_t va, u_int length, int chan) 377{ 378 vm_paddr_t phys, priorpage = 0; 379 vm_offset_t endva; 380 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 381 382 GIANT_REQUIRED; 383 384 endva = (vm_offset_t)round_page((vm_offset_t)va + length); 385 for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 386 phys = trunc_page(pmap_extract(kernel_pmap, (vm_offset_t)va)); 387#define ISARAM_END RAM_END 388 if (phys == 0) 389 panic("isa_dmacheck: no physical page present"); 390 if (phys >= ISARAM_END) 391 return (1); 392 if (priorpage) { 393 if (priorpage + PAGE_SIZE != phys) 394 return (1); 395 /* check if crossing a DMA page boundary */ 396 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 397 return (1); 398 } 399 priorpage = phys; 400 } 401 return (0); 402} 403 404/* 405 * Query the progress of a transfer on a DMA channel. 406 * 407 * To avoid having to interrupt a transfer in progress, we sample 408 * each of the high and low databytes twice, and apply the following 409 * logic to determine the correct count. 410 * 411 * Reads are performed with interrupts disabled, thus it is to be 412 * expected that the time between reads is very small. At most 413 * one rollover in the low count byte can be expected within the 414 * four reads that are performed. 415 * 416 * There are three gaps in which a rollover can occur : 417 * 418 * - read low1 419 * gap1 420 * - read high1 421 * gap2 422 * - read low2 423 * gap3 424 * - read high2 425 * 426 * If a rollover occurs in gap1 or gap2, the low2 value will be 427 * greater than the low1 value. In this case, low2 and high2 are a 428 * corresponding pair. 429 * 430 * In any other case, low1 and high1 can be considered to be correct. 431 * 432 * The function returns the number of bytes remaining in the transfer, 433 * or -1 if the channel requested is not active. 434 * 435 */ 436int 437isa_dmastatus(int chan) 438{ 439 u_long cnt = 0; 440 int ffport, waport; 441 u_long low1, high1, low2, high2; 442 443 /* channel active? */ 444 if ((dma_inuse & (1 << chan)) == 0) { 445 printf("isa_dmastatus: channel %d not active\n", chan); 446 return(-1); 447 } 448 /* channel busy? */ 449 450 if (((dma_busy & (1 << chan)) == 0) && 451 (dma_auto_mode & (1 << chan)) == 0 ) { 452 printf("chan %d not busy\n", chan); 453 return -2 ; 454 } 455 if (chan < 4) { /* low DMA controller */ 456 ffport = DMA1_FFC; 457 waport = DMA1_CHN(chan) + 1; 458 } else { /* high DMA controller */ 459 ffport = DMA2_FFC; 460 waport = DMA2_CHN(chan - 4) + 2; 461 } 462 463 disable_intr(); /* no interrupts Mr Jones! */ 464 outb(ffport, 0); /* clear register LSB flipflop */ 465 low1 = inb(waport); 466 high1 = inb(waport); 467 outb(ffport, 0); /* clear again */ 468 low2 = inb(waport); 469 high2 = inb(waport); 470 enable_intr(); /* enable interrupts again */ 471 472 /* 473 * Now decide if a wrap has tried to skew our results. 474 * Note that after TC, the count will read 0xffff, while we want 475 * to return zero, so we add and then mask to compensate. 476 */ 477 if (low1 >= low2) { 478 cnt = (low1 + (high1 << 8) + 1) & 0xffff; 479 } else { 480 cnt = (low2 + (high2 << 8) + 1) & 0xffff; 481 } 482 483 if (chan >= 4) /* high channels move words */ 484 cnt *= 2; 485 return(cnt); 486} 487 488/* 489 * Stop a DMA transfer currently in progress. 490 */ 491int 492isa_dmastop(int chan) 493{ 494 if ((dma_inuse & (1 << chan)) == 0) 495 printf("isa_dmastop: channel %d not acquired\n", chan); 496 497 if (((dma_busy & (1 << chan)) == 0) && 498 ((dma_auto_mode & (1 << chan)) == 0)) { 499 printf("chan %d not busy\n", chan); 500 return -2 ; 501 } 502 503 if ((chan & 4) == 0) { 504 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 505 } else { 506 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 507 } 508 return(isa_dmastatus(chan)); 509} 510 511/* 512 * Attach to the ISA PnP descriptor for the AT DMA controller 513 */ 514static struct isa_pnp_id atdma_ids[] = { 515 { 0x0002d041 /* PNP0200 */, "AT DMA controller" }, 516 { 0 } 517}; 518 519static int 520atdma_probe(device_t dev) 521{ 522 int result; 523 524 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0) 525 device_quiet(dev); 526 return(result); 527} 528 529static int 530atdma_attach(device_t dev) 531{ 532 return(0); 533} 534 535static device_method_t atdma_methods[] = { 536 /* Device interface */ 537 DEVMETHOD(device_probe, atdma_probe), 538 DEVMETHOD(device_attach, atdma_attach), 539 DEVMETHOD(device_detach, bus_generic_detach), 540 DEVMETHOD(device_shutdown, bus_generic_shutdown), 541 DEVMETHOD(device_suspend, bus_generic_suspend), 542 DEVMETHOD(device_resume, bus_generic_resume), 543 { 0, 0 } 544}; 545 546static driver_t atdma_driver = { 547 "atdma", 548 atdma_methods, 549 1, /* no softc */ 550}; 551 552static devclass_t atdma_devclass; 553 554DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0); 555DRIVER_MODULE(atdma, acpi, atdma_driver, atdma_devclass, 0, 0); 556