isa_dma.c revision 57973
145720Speter/*- 245720Speter * Copyright (c) 1991 The Regents of the University of California. 345720Speter * All rights reserved. 445720Speter * 545720Speter * This code is derived from software contributed to Berkeley by 645720Speter * William Jolitz. 745720Speter * 845720Speter * Redistribution and use in source and binary forms, with or without 945720Speter * modification, are permitted provided that the following conditions 1045720Speter * are met: 1145720Speter * 1. Redistributions of source code must retain the above copyright 1245720Speter * notice, this list of conditions and the following disclaimer. 1345720Speter * 2. Redistributions in binary form must reproduce the above copyright 1445720Speter * notice, this list of conditions and the following disclaimer in the 1545720Speter * documentation and/or other materials provided with the distribution. 1645720Speter * 3. All advertising materials mentioning features or use of this software 1745720Speter * must display the following acknowledgement: 1845720Speter * This product includes software developed by the University of 1945720Speter * California, Berkeley and its contributors. 2045720Speter * 4. Neither the name of the University nor the names of its contributors 2145720Speter * may be used to endorse or promote products derived from this software 2245720Speter * without specific prior written permission. 2345720Speter * 2445720Speter * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 2545720Speter * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2645720Speter * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2745720Speter * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2845720Speter * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2945720Speter * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3045720Speter * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3145720Speter * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3245720Speter * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3345720Speter * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3445720Speter * SUCH DAMAGE. 3545720Speter * 3645720Speter * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 3750477Speter * $FreeBSD: head/sys/i386/isa/isa_dma.c 57973 2000-03-13 10:19:32Z phk $ 3845720Speter */ 3945720Speter 4045720Speter/* 4145720Speter * code to manage AT bus 4245720Speter * 4345720Speter * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 4445720Speter * Fixed uninitialized variable problem and added code to deal 4545720Speter * with DMA page boundaries in isa_dmarangecheck(). Fixed word 4645720Speter * mode DMA count compution and reorganized DMA setup code in 4745720Speter * isa_dmastart() 4845720Speter */ 4945720Speter 5045720Speter#include <sys/param.h> 5145720Speter#include <sys/systm.h> 5245720Speter#include <sys/malloc.h> 5345720Speter#include <vm/vm.h> 5445720Speter#include <vm/vm_param.h> 5545720Speter#include <vm/pmap.h> 5645720Speter#include <i386/isa/isa.h> 5746849Speter#include <i386/isa/isa_dma.h> 5845720Speter#include <i386/isa/ic/i8237.h> 5945720Speter 6045720Speter/* 6145720Speter** Register definitions for DMA controller 1 (channels 0..3): 6245720Speter*/ 6345720Speter#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 6445720Speter#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 6545720Speter#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 6645720Speter#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 6745720Speter 6845720Speter/* 6945720Speter** Register definitions for DMA controller 2 (channels 4..7): 7045720Speter*/ 7145720Speter#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 7245720Speter#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 7345720Speter#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 7445720Speter#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 7545720Speter 7645720Speterstatic int isa_dmarangecheck __P((caddr_t va, u_int length, int chan)); 7745720Speter 7845720Speterstatic caddr_t dma_bouncebuf[8]; 7945720Speterstatic u_int dma_bouncebufsize[8]; 8045720Speterstatic u_int8_t dma_bounced = 0; 8145720Speterstatic u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ 8245720Speterstatic u_int8_t dma_inuse = 0; /* User for acquire/release */ 8345720Speterstatic u_int8_t dma_auto_mode = 0; 8445720Speter 8545720Speter#define VALID_DMA_MASK (7) 8645720Speter 8745720Speter/* high byte of address is stored in this port for i-th dma channel */ 8845720Speterstatic int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 8945720Speter 9045720Speter/* 9145720Speter * Setup a DMA channel's bounce buffer. 9245720Speter */ 9345720Spetervoid 9445720Speterisa_dmainit(chan, bouncebufsize) 9545720Speter int chan; 9645720Speter u_int bouncebufsize; 9745720Speter{ 9845720Speter void *buf; 9945720Speter 10045720Speter#ifdef DIAGNOSTIC 10145720Speter if (chan & ~VALID_DMA_MASK) 10245720Speter panic("isa_dmainit: channel out of range"); 10345720Speter 10445720Speter if (dma_bouncebuf[chan] != NULL) 10545720Speter panic("isa_dmainit: impossible request"); 10645720Speter#endif 10745720Speter 10845720Speter dma_bouncebufsize[chan] = bouncebufsize; 10945720Speter 11045720Speter /* Try malloc() first. It works better if it works. */ 11145720Speter buf = malloc(bouncebufsize, M_DEVBUF, M_NOWAIT); 11245720Speter if (buf != NULL) { 11345720Speter if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) { 11445720Speter dma_bouncebuf[chan] = buf; 11545720Speter return; 11645720Speter } 11745720Speter free(buf, M_DEVBUF); 11845720Speter } 11945720Speter buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful, 12045720Speter 1ul, chan & 4 ? 0x20000ul : 0x10000ul); 12145720Speter if (buf == NULL) 12245720Speter printf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize); 12345720Speter else 12445720Speter dma_bouncebuf[chan] = buf; 12545720Speter} 12645720Speter 12745720Speter/* 12845720Speter * Register a DMA channel's usage. Usually called from a device driver 12945720Speter * in open() or during its initialization. 13045720Speter */ 13145720Speterint 13245720Speterisa_dma_acquire(chan) 13345720Speter int chan; 13445720Speter{ 13545720Speter#ifdef DIAGNOSTIC 13645720Speter if (chan & ~VALID_DMA_MASK) 13745720Speter panic("isa_dma_acquire: channel out of range"); 13845720Speter#endif 13945720Speter 14045720Speter if (dma_inuse & (1 << chan)) { 14145720Speter printf("isa_dma_acquire: channel %d already in use\n", chan); 14245720Speter return (EBUSY); 14345720Speter } 14445720Speter dma_inuse |= (1 << chan); 14545720Speter dma_auto_mode &= ~(1 << chan); 14645720Speter 14745720Speter return (0); 14845720Speter} 14945720Speter 15045720Speter/* 15145720Speter * Unregister a DMA channel's usage. Usually called from a device driver 15245720Speter * during close() or during its shutdown. 15345720Speter */ 15445720Spetervoid 15545720Speterisa_dma_release(chan) 15645720Speter int chan; 15745720Speter{ 15845720Speter#ifdef DIAGNOSTIC 15945720Speter if (chan & ~VALID_DMA_MASK) 16045720Speter panic("isa_dma_release: channel out of range"); 16145720Speter 16245720Speter if ((dma_inuse & (1 << chan)) == 0) 16345720Speter printf("isa_dma_release: channel %d not in use\n", chan); 16445720Speter#endif 16545720Speter 16645720Speter if (dma_busy & (1 << chan)) { 16745720Speter dma_busy &= ~(1 << chan); 16845720Speter /* 16945720Speter * XXX We should also do "dma_bounced &= (1 << chan);" 17045720Speter * because we are acting on behalf of isa_dmadone() which 17145720Speter * was not called to end the last DMA operation. This does 17245720Speter * not matter now, but it may in the future. 17345720Speter */ 17445720Speter } 17545720Speter 17645720Speter dma_inuse &= ~(1 << chan); 17745720Speter dma_auto_mode &= ~(1 << chan); 17845720Speter} 17945720Speter 18045720Speter/* 18145720Speter * isa_dmacascade(): program 8237 DMA controller channel to accept 18245720Speter * external dma control by a board. 18345720Speter */ 18445720Spetervoid 18545720Speterisa_dmacascade(chan) 18645720Speter int chan; 18745720Speter{ 18845720Speter#ifdef DIAGNOSTIC 18945720Speter if (chan & ~VALID_DMA_MASK) 19045720Speter panic("isa_dmacascade: channel out of range"); 19145720Speter#endif 19245720Speter 19345720Speter /* set dma channel mode, and set dma channel mode */ 19445720Speter if ((chan & 4) == 0) { 19545720Speter outb(DMA1_MODE, DMA37MD_CASCADE | chan); 19645720Speter outb(DMA1_SMSK, chan); 19745720Speter } else { 19845720Speter outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 19945720Speter outb(DMA2_SMSK, chan & 3); 20045720Speter } 20145720Speter} 20245720Speter 20345720Speter/* 20445720Speter * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 20545720Speter * problems by using a bounce buffer. 20645720Speter */ 20745720Spetervoid 20845720Speterisa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) 20945720Speter{ 21045720Speter vm_offset_t phys; 21145720Speter int waport; 21245720Speter caddr_t newaddr; 21345720Speter 21445720Speter#ifdef DIAGNOSTIC 21545720Speter if (chan & ~VALID_DMA_MASK) 21645720Speter panic("isa_dmastart: channel out of range"); 21745720Speter 21845720Speter if ((chan < 4 && nbytes > (1<<16)) 21945720Speter || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1))) 22045720Speter panic("isa_dmastart: impossible request"); 22145720Speter 22245720Speter if ((dma_inuse & (1 << chan)) == 0) 22345720Speter printf("isa_dmastart: channel %d not acquired\n", chan); 22445720Speter#endif 22545720Speter 22645720Speter#if 0 22745720Speter /* 22845720Speter * XXX This should be checked, but drivers like ad1848 only call 22945720Speter * isa_dmastart() once because they use Auto DMA mode. If we 23045720Speter * leave this in, drivers that do this will print this continuously. 23145720Speter */ 23245720Speter if (dma_busy & (1 << chan)) 23345720Speter printf("isa_dmastart: channel %d busy\n", chan); 23445720Speter#endif 23545720Speter 23645720Speter dma_busy |= (1 << chan); 23745720Speter 23845720Speter if (isa_dmarangecheck(addr, nbytes, chan)) { 23945720Speter if (dma_bouncebuf[chan] == NULL 24045720Speter || dma_bouncebufsize[chan] < nbytes) 24145720Speter panic("isa_dmastart: bad bounce buffer"); 24245720Speter dma_bounced |= (1 << chan); 24345720Speter newaddr = dma_bouncebuf[chan]; 24445720Speter 24545720Speter /* copy bounce buffer on write */ 24657973Sphk if (!(flags & ISADMA_READ)) 24745720Speter bcopy(addr, newaddr, nbytes); 24845720Speter addr = newaddr; 24945720Speter } 25045720Speter 25145720Speter /* translate to physical */ 25245720Speter phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 25345720Speter 25457973Sphk if (flags & ISADMA_RAW) { 25545720Speter dma_auto_mode |= (1 << chan); 25645720Speter } else { 25745720Speter dma_auto_mode &= ~(1 << chan); 25845720Speter } 25945720Speter 26045720Speter if ((chan & 4) == 0) { 26145720Speter /* 26245720Speter * Program one of DMA channels 0..3. These are 26345720Speter * byte mode channels. 26445720Speter */ 26545720Speter /* set dma channel mode, and reset address ff */ 26645720Speter 26757973Sphk /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 26857973Sphk if (flags & ISADMA_RAW) { 26957973Sphk if (flags & ISADMA_READ) 27045720Speter outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 27145720Speter else 27245720Speter outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 27345720Speter } 27445720Speter else 27557973Sphk if (flags & ISADMA_READ) 27645720Speter outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 27745720Speter else 27845720Speter outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 27945720Speter outb(DMA1_FFC, 0); 28045720Speter 28145720Speter /* send start address */ 28245720Speter waport = DMA1_CHN(chan); 28345720Speter outb(waport, phys); 28445720Speter outb(waport, phys>>8); 28545720Speter outb(dmapageport[chan], phys>>16); 28645720Speter 28745720Speter /* send count */ 28845720Speter outb(waport + 1, --nbytes); 28945720Speter outb(waport + 1, nbytes>>8); 29045720Speter 29145720Speter /* unmask channel */ 29245720Speter outb(DMA1_SMSK, chan); 29345720Speter } else { 29445720Speter /* 29545720Speter * Program one of DMA channels 4..7. These are 29645720Speter * word mode channels. 29745720Speter */ 29845720Speter /* set dma channel mode, and reset address ff */ 29945720Speter 30057973Sphk /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 30157973Sphk if (flags & ISADMA_RAW) { 30257973Sphk if (flags & ISADMA_READ) 30345720Speter outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 30445720Speter else 30545720Speter outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 30645720Speter } 30745720Speter else 30857973Sphk if (flags & ISADMA_READ) 30945720Speter outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 31045720Speter else 31145720Speter outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 31245720Speter outb(DMA2_FFC, 0); 31345720Speter 31445720Speter /* send start address */ 31545720Speter waport = DMA2_CHN(chan - 4); 31645720Speter outb(waport, phys>>1); 31745720Speter outb(waport, phys>>9); 31845720Speter outb(dmapageport[chan], phys>>16); 31945720Speter 32045720Speter /* send count */ 32145720Speter nbytes >>= 1; 32245720Speter outb(waport + 2, --nbytes); 32345720Speter outb(waport + 2, nbytes>>8); 32445720Speter 32545720Speter /* unmask channel */ 32645720Speter outb(DMA2_SMSK, chan & 3); 32745720Speter } 32845720Speter} 32945720Speter 33045720Spetervoid 33145720Speterisa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 33245720Speter{ 33345720Speter#ifdef DIAGNOSTIC 33445720Speter if (chan & ~VALID_DMA_MASK) 33545720Speter panic("isa_dmadone: channel out of range"); 33645720Speter 33745720Speter if ((dma_inuse & (1 << chan)) == 0) 33845720Speter printf("isa_dmadone: channel %d not acquired\n", chan); 33945720Speter#endif 34045720Speter 34145720Speter if (((dma_busy & (1 << chan)) == 0) && 34245720Speter (dma_auto_mode & (1 << chan)) == 0 ) 34345720Speter printf("isa_dmadone: channel %d not busy\n", chan); 34445720Speter 34545720Speter if ((dma_auto_mode & (1 << chan)) == 0) 34645720Speter outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 34745720Speter 34845720Speter if (dma_bounced & (1 << chan)) { 34945720Speter /* copy bounce buffer on read */ 35057973Sphk if (flags & ISADMA_READ) 35145720Speter bcopy(dma_bouncebuf[chan], addr, nbytes); 35245720Speter 35345720Speter dma_bounced &= ~(1 << chan); 35445720Speter } 35545720Speter dma_busy &= ~(1 << chan); 35645720Speter} 35745720Speter 35845720Speter/* 35945720Speter * Check for problems with the address range of a DMA transfer 36045720Speter * (non-contiguous physical pages, outside of bus address space, 36145720Speter * crossing DMA page boundaries). 36245720Speter * Return true if special handling needed. 36345720Speter */ 36445720Speter 36545720Speterstatic int 36645720Speterisa_dmarangecheck(caddr_t va, u_int length, int chan) 36745720Speter{ 36845720Speter vm_offset_t phys, priorpage = 0, endva; 36945720Speter u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 37045720Speter 37145720Speter endva = (vm_offset_t)round_page((vm_offset_t)va + length); 37245720Speter for (; va < (caddr_t) endva ; va += PAGE_SIZE) { 37345720Speter phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va)); 37445720Speter#define ISARAM_END RAM_END 37545720Speter if (phys == 0) 37645720Speter panic("isa_dmacheck: no physical page present"); 37745720Speter if (phys >= ISARAM_END) 37845720Speter return (1); 37945720Speter if (priorpage) { 38045720Speter if (priorpage + PAGE_SIZE != phys) 38145720Speter return (1); 38245720Speter /* check if crossing a DMA page boundary */ 38345720Speter if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) 38445720Speter return (1); 38545720Speter } 38645720Speter priorpage = phys; 38745720Speter } 38845720Speter return (0); 38945720Speter} 39045720Speter 39145720Speter/* 39245720Speter * Query the progress of a transfer on a DMA channel. 39345720Speter * 39445720Speter * To avoid having to interrupt a transfer in progress, we sample 39545720Speter * each of the high and low databytes twice, and apply the following 39645720Speter * logic to determine the correct count. 39745720Speter * 39845720Speter * Reads are performed with interrupts disabled, thus it is to be 39945720Speter * expected that the time between reads is very small. At most 40045720Speter * one rollover in the low count byte can be expected within the 40145720Speter * four reads that are performed. 40245720Speter * 40345720Speter * There are three gaps in which a rollover can occur : 40445720Speter * 40545720Speter * - read low1 40645720Speter * gap1 40745720Speter * - read high1 40845720Speter * gap2 40945720Speter * - read low2 41045720Speter * gap3 41145720Speter * - read high2 41245720Speter * 41345720Speter * If a rollover occurs in gap1 or gap2, the low2 value will be 41445720Speter * greater than the low1 value. In this case, low2 and high2 are a 41545720Speter * corresponding pair. 41645720Speter * 41745720Speter * In any other case, low1 and high1 can be considered to be correct. 41845720Speter * 41945720Speter * The function returns the number of bytes remaining in the transfer, 42045720Speter * or -1 if the channel requested is not active. 42145720Speter * 42245720Speter */ 42345720Speterint 42445720Speterisa_dmastatus(int chan) 42545720Speter{ 42645720Speter u_long cnt = 0; 42745720Speter int ffport, waport; 42845720Speter u_long low1, high1, low2, high2; 42945720Speter 43045720Speter /* channel active? */ 43145720Speter if ((dma_inuse & (1 << chan)) == 0) { 43245720Speter printf("isa_dmastatus: channel %d not active\n", chan); 43345720Speter return(-1); 43445720Speter } 43545720Speter /* channel busy? */ 43645720Speter 43745720Speter if (((dma_busy & (1 << chan)) == 0) && 43845720Speter (dma_auto_mode & (1 << chan)) == 0 ) { 43945720Speter printf("chan %d not busy\n", chan); 44045720Speter return -2 ; 44145720Speter } 44245720Speter if (chan < 4) { /* low DMA controller */ 44345720Speter ffport = DMA1_FFC; 44445720Speter waport = DMA1_CHN(chan) + 1; 44545720Speter } else { /* high DMA controller */ 44645720Speter ffport = DMA2_FFC; 44745720Speter waport = DMA2_CHN(chan - 4) + 2; 44845720Speter } 44945720Speter 45045720Speter disable_intr(); /* no interrupts Mr Jones! */ 45145720Speter outb(ffport, 0); /* clear register LSB flipflop */ 45245720Speter low1 = inb(waport); 45345720Speter high1 = inb(waport); 45445720Speter outb(ffport, 0); /* clear again */ 45545720Speter low2 = inb(waport); 45645720Speter high2 = inb(waport); 45745720Speter enable_intr(); /* enable interrupts again */ 45845720Speter 45945720Speter /* 46045720Speter * Now decide if a wrap has tried to skew our results. 46145720Speter * Note that after TC, the count will read 0xffff, while we want 46245720Speter * to return zero, so we add and then mask to compensate. 46345720Speter */ 46445720Speter if (low1 >= low2) { 46545720Speter cnt = (low1 + (high1 << 8) + 1) & 0xffff; 46645720Speter } else { 46745720Speter cnt = (low2 + (high2 << 8) + 1) & 0xffff; 46845720Speter } 46945720Speter 47045720Speter if (chan >= 4) /* high channels move words */ 47145720Speter cnt *= 2; 47245720Speter return(cnt); 47345720Speter} 47445720Speter 47545720Speter/* 47645720Speter * Stop a DMA transfer currently in progress. 47745720Speter */ 47845720Speterint 47945720Speterisa_dmastop(int chan) 48045720Speter{ 48145720Speter if ((dma_inuse & (1 << chan)) == 0) 48245720Speter printf("isa_dmastop: channel %d not acquired\n", chan); 48345720Speter 48445720Speter if (((dma_busy & (1 << chan)) == 0) && 48545720Speter ((dma_auto_mode & (1 << chan)) == 0)) { 48645720Speter printf("chan %d not busy\n", chan); 48745720Speter return -2 ; 48845720Speter } 48945720Speter 49045720Speter if ((chan & 4) == 0) { 49145720Speter outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); 49245720Speter } else { 49345720Speter outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); 49445720Speter } 49545720Speter return(isa_dmastatus(chan)); 49645720Speter} 497