1145287Snjl/*- 2145287Snjl * Copyright (c) 2005 Bruno Ducrot 3145287Snjl * 4145287Snjl * Redistribution and use in source and binary forms, with or without 5145287Snjl * modification, are permitted provided that the following conditions 6145287Snjl * are met: 7145287Snjl * 1. Redistributions of source code must retain the above copyright 8145287Snjl * notice, this list of conditions and the following disclaimer. 9145287Snjl * 2. Redistributions in binary form must reproduce the above copyright 10145287Snjl * notice, this list of conditions and the following disclaimer in the 11145287Snjl * documentation and/or other materials provided with the distribution. 12145287Snjl * 13145287Snjl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14145287Snjl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15145287Snjl * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16145287Snjl * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17145287Snjl * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18145287Snjl * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19145287Snjl * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20145287Snjl * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21145287Snjl * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22145287Snjl * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23145287Snjl */ 24145287Snjl 25145287Snjl/* 26145287Snjl * This driver is based upon information found by examining speedstep-0.5 27145287Snjl * from Marc Lehman, which includes all the reverse engineering effort of 28145287Snjl * Malik Martin (function 1 and 2 of the GSI). 29145287Snjl * 30145287Snjl * The correct way for the OS to take ownership from the BIOS was found by 31145287Snjl * Hiroshi Miura (function 0 of the GSI). 32145287Snjl * 33145287Snjl * Finally, the int 15h call interface was (partially) documented by Intel. 34145287Snjl * 35145287Snjl * Many thanks to Jon Noack for testing and debugging this driver. 36145287Snjl */ 37145287Snjl 38145287Snjl#include <sys/cdefs.h> 39145287Snjl__FBSDID("$FreeBSD$"); 40145287Snjl 41145287Snjl#include <sys/param.h> 42145287Snjl#include <sys/bus.h> 43145287Snjl#include <sys/cpu.h> 44145287Snjl#include <sys/kernel.h> 45145287Snjl#include <sys/module.h> 46145287Snjl#include <sys/systm.h> 47145287Snjl 48170874Snjl#include <machine/bus.h> 49187597Sjkim#include <machine/cputypes.h> 50145287Snjl#include <machine/md_var.h> 51145287Snjl#include <machine/vm86.h> 52145287Snjl 53145287Snjl#include <dev/pci/pcivar.h> 54145287Snjl#include <dev/pci/pcireg.h> 55145287Snjl 56145287Snjl#include <vm/vm.h> 57145287Snjl#include <vm/pmap.h> 58145287Snjl 59145287Snjl#include "cpufreq_if.h" 60145287Snjl 61145287Snjl#if 0 62145287Snjl#define DPRINT(dev, x...) device_printf(dev, x) 63145287Snjl#else 64145287Snjl#define DPRINT(dev, x...) 65145287Snjl#endif 66145287Snjl 67145287Snjlstruct smist_softc { 68145287Snjl device_t dev; 69145287Snjl int smi_cmd; 70145287Snjl int smi_data; 71145287Snjl int command; 72145287Snjl int flags; 73145287Snjl struct cf_setting sets[2]; /* Only two settings. */ 74145287Snjl}; 75145287Snjl 76170874Snjlstatic char smist_magic[] = "Copyright (c) 1999 Intel Corporation"; 77170874Snjl 78145287Snjlstatic void smist_identify(driver_t *driver, device_t parent); 79145287Snjlstatic int smist_probe(device_t dev); 80145287Snjlstatic int smist_attach(device_t dev); 81145287Snjlstatic int smist_detach(device_t dev); 82145287Snjlstatic int smist_settings(device_t dev, struct cf_setting *sets, 83145287Snjl int *count); 84145287Snjlstatic int smist_set(device_t dev, const struct cf_setting *set); 85145287Snjlstatic int smist_get(device_t dev, struct cf_setting *set); 86145287Snjlstatic int smist_type(device_t dev, int *type); 87145287Snjl 88145287Snjlstatic device_method_t smist_methods[] = { 89145287Snjl /* Device interface */ 90145287Snjl DEVMETHOD(device_identify, smist_identify), 91145287Snjl DEVMETHOD(device_probe, smist_probe), 92145287Snjl DEVMETHOD(device_attach, smist_attach), 93145287Snjl DEVMETHOD(device_detach, smist_detach), 94145287Snjl 95145287Snjl /* cpufreq interface */ 96145287Snjl DEVMETHOD(cpufreq_drv_set, smist_set), 97145287Snjl DEVMETHOD(cpufreq_drv_get, smist_get), 98145287Snjl DEVMETHOD(cpufreq_drv_type, smist_type), 99145287Snjl DEVMETHOD(cpufreq_drv_settings, smist_settings), 100145287Snjl 101145287Snjl {0, 0} 102145287Snjl}; 103145287Snjl 104145287Snjlstatic driver_t smist_driver = { 105145287Snjl "smist", smist_methods, sizeof(struct smist_softc) 106145287Snjl}; 107145287Snjlstatic devclass_t smist_devclass; 108145287SnjlDRIVER_MODULE(smist, cpu, smist_driver, smist_devclass, 0, 0); 109145287Snjl 110145287Snjlstruct piix4_pci_device { 111145287Snjl uint16_t vendor; 112145287Snjl uint16_t device; 113145287Snjl char *desc; 114145287Snjl}; 115145287Snjl 116145287Snjlstatic struct piix4_pci_device piix4_pci_devices[] = { 117145287Snjl {0x8086, 0x7113, "Intel PIIX4 ISA bridge"}, 118145287Snjl {0x8086, 0x719b, "Intel PIIX4 ISA bridge (embedded in MX440 chipset)"}, 119145287Snjl 120145287Snjl {0, 0, NULL}, 121145287Snjl}; 122145287Snjl 123145287Snjl#define SET_OWNERSHIP 0 124145287Snjl#define GET_STATE 1 125145287Snjl#define SET_STATE 2 126145287Snjl 127145287Snjlstatic int 128145287Snjlint15_gsic_call(int *sig, int *smi_cmd, int *command, int *smi_data, int *flags) 129145287Snjl{ 130145287Snjl struct vm86frame vmf; 131145287Snjl 132145287Snjl bzero(&vmf, sizeof(vmf)); 133145287Snjl vmf.vmf_eax = 0x0000E980; /* IST support */ 134145287Snjl vmf.vmf_edx = 0x47534943; /* 'GSIC' in ASCII */ 135145287Snjl vm86_intcall(0x15, &vmf); 136145287Snjl 137145287Snjl if (vmf.vmf_eax == 0x47534943) { 138145287Snjl *sig = vmf.vmf_eax; 139145287Snjl *smi_cmd = vmf.vmf_ebx & 0xff; 140145287Snjl *command = (vmf.vmf_ebx >> 16) & 0xff; 141145287Snjl *smi_data = vmf.vmf_ecx; 142145287Snjl *flags = vmf.vmf_edx; 143145287Snjl } else { 144145287Snjl *sig = -1; 145145287Snjl *smi_cmd = -1; 146145287Snjl *command = -1; 147145287Snjl *smi_data = -1; 148145287Snjl *flags = -1; 149145287Snjl } 150145287Snjl 151145287Snjl return (0); 152145287Snjl} 153145287Snjl 154170874Snjl/* Temporary structure to hold mapped page and status. */ 155170874Snjlstruct set_ownership_data { 156170874Snjl int smi_cmd; 157170874Snjl int command; 158170874Snjl int result; 159170874Snjl void *buf; 160170874Snjl}; 161170874Snjl 162170874Snjl/* Perform actual SMI call to enable SpeedStep. */ 163170874Snjlstatic void 164170874Snjlset_ownership_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 165145287Snjl{ 166170874Snjl struct set_ownership_data *data; 167145287Snjl 168170874Snjl data = arg; 169170874Snjl if (error) { 170170874Snjl data->result = error; 171170874Snjl return; 172170874Snjl } 173145287Snjl 174170874Snjl /* Copy in the magic string and send it by writing to the SMI port. */ 175170874Snjl strlcpy(data->buf, smist_magic, PAGE_SIZE); 176145287Snjl __asm __volatile( 177145287Snjl "movl $-1, %%edi\n\t" 178145287Snjl "out %%al, (%%dx)\n" 179170874Snjl : "=D" (data->result) 180170874Snjl : "a" (data->command), 181145287Snjl "b" (0), 182145287Snjl "c" (0), 183170874Snjl "d" (data->smi_cmd), 184170874Snjl "S" ((uint32_t)segs[0].ds_addr) 185145287Snjl ); 186170874Snjl} 187145287Snjl 188170874Snjlstatic int 189170874Snjlset_ownership(device_t dev) 190170874Snjl{ 191170874Snjl struct smist_softc *sc; 192170874Snjl struct set_ownership_data cb_data; 193170874Snjl bus_dma_tag_t tag; 194170874Snjl bus_dmamap_t map; 195145287Snjl 196170874Snjl /* 197170874Snjl * Specify the region to store the magic string. Since its address is 198170874Snjl * passed to the BIOS in a 32-bit register, we have to make sure it is 199170874Snjl * located in a physical page below 4 GB (i.e., for PAE.) 200170874Snjl */ 201170874Snjl sc = device_get_softc(dev); 202170874Snjl if (bus_dma_tag_create(/*parent*/ NULL, 203170874Snjl /*alignment*/ PAGE_SIZE, /*no boundary*/ 0, 204170874Snjl /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, /*highaddr*/ BUS_SPACE_MAXADDR, 205170874Snjl NULL, NULL, /*maxsize*/ PAGE_SIZE, /*segments*/ 1, 206170874Snjl /*maxsegsize*/ PAGE_SIZE, 0, busdma_lock_mutex, &Giant, 207170874Snjl &tag) != 0) { 208170874Snjl device_printf(dev, "can't create mem tag\n"); 209170874Snjl return (ENXIO); 210170874Snjl } 211170874Snjl if (bus_dmamem_alloc(tag, &cb_data.buf, BUS_DMA_NOWAIT, &map) != 0) { 212170874Snjl bus_dma_tag_destroy(tag); 213170874Snjl device_printf(dev, "can't alloc mapped mem\n"); 214170874Snjl return (ENXIO); 215170874Snjl } 216170874Snjl 217170874Snjl /* Load the physical page map and take ownership in the callback. */ 218170874Snjl cb_data.smi_cmd = sc->smi_cmd; 219170874Snjl cb_data.command = sc->command; 220170874Snjl if (bus_dmamap_load(tag, map, cb_data.buf, PAGE_SIZE, set_ownership_cb, 221170874Snjl &cb_data, BUS_DMA_NOWAIT) != 0) { 222170874Snjl bus_dmamem_free(tag, cb_data.buf, map); 223170874Snjl bus_dma_tag_destroy(tag); 224170874Snjl device_printf(dev, "can't load mem\n"); 225170874Snjl return (ENXIO); 226297793Spfg } 227170874Snjl DPRINT(dev, "taking ownership over BIOS return %d\n", cb_data.result); 228170874Snjl bus_dmamap_unload(tag, map); 229170874Snjl bus_dmamem_free(tag, cb_data.buf, map); 230170874Snjl bus_dma_tag_destroy(tag); 231170874Snjl return (cb_data.result ? ENXIO : 0); 232145287Snjl} 233145287Snjl 234145287Snjlstatic int 235145287Snjlgetset_state(struct smist_softc *sc, int *state, int function) 236145287Snjl{ 237145287Snjl int new_state; 238145287Snjl int result; 239145287Snjl int eax; 240145287Snjl 241145287Snjl if (!sc) 242145287Snjl return (ENXIO); 243145287Snjl 244145287Snjl if (function != GET_STATE && function != SET_STATE) 245145287Snjl return (EINVAL); 246145287Snjl 247145287Snjl DPRINT(sc->dev, "calling GSI\n"); 248145287Snjl 249145287Snjl __asm __volatile( 250145287Snjl "movl $-1, %%edi\n\t" 251145287Snjl "out %%al, (%%dx)\n" 252145287Snjl : "=a" (eax), 253145287Snjl "=b" (new_state), 254145287Snjl "=D" (result) 255145287Snjl : "a" (sc->command), 256145287Snjl "b" (function), 257145287Snjl "c" (*state), 258145287Snjl "d" (sc->smi_cmd) 259145287Snjl ); 260145287Snjl 261145287Snjl DPRINT(sc->dev, "GSI returned: eax %.8x ebx %.8x edi %.8x\n", 262145287Snjl eax, new_state, result); 263145287Snjl 264145287Snjl *state = new_state & 1; 265145287Snjl 266145287Snjl switch (function) { 267145287Snjl case GET_STATE: 268145287Snjl if (eax) 269145287Snjl return (ENXIO); 270145287Snjl break; 271145287Snjl case SET_STATE: 272145287Snjl if (result) 273145287Snjl return (ENXIO); 274145287Snjl break; 275145287Snjl } 276145287Snjl return (0); 277145287Snjl} 278145287Snjl 279145287Snjlstatic void 280145287Snjlsmist_identify(driver_t *driver, device_t parent) 281145287Snjl{ 282145287Snjl struct piix4_pci_device *id; 283145287Snjl device_t piix4 = NULL; 284145287Snjl 285145287Snjl if (resource_disabled("ichst", 0)) 286145287Snjl return; 287145287Snjl 288145287Snjl /* Check for a supported processor */ 289187594Sjkim if (cpu_vendor_id != CPU_VENDOR_INTEL) 290145287Snjl return; 291145287Snjl switch (cpu_id & 0xff0) { 292145287Snjl case 0x680: /* Pentium III [coppermine] */ 293145287Snjl case 0x6a0: /* Pentium III [Tualatin] */ 294145287Snjl break; 295145287Snjl default: 296145287Snjl return; 297145287Snjl } 298145287Snjl 299145287Snjl /* Check for a supported PCI-ISA bridge */ 300145287Snjl for (id = piix4_pci_devices; id->desc != NULL; ++id) { 301145287Snjl if ((piix4 = pci_find_device(id->vendor, id->device)) != NULL) 302145287Snjl break; 303145287Snjl } 304145287Snjl if (!piix4) 305145287Snjl return; 306145287Snjl 307145287Snjl if (bootverbose) 308145287Snjl printf("smist: found supported isa bridge %s\n", id->desc); 309145287Snjl 310145287Snjl if (device_find_child(parent, "smist", -1) != NULL) 311145287Snjl return; 312181691Sjhb if (BUS_ADD_CHILD(parent, 30, "smist", -1) == NULL) 313145287Snjl device_printf(parent, "smist: add child failed\n"); 314145287Snjl} 315145287Snjl 316145287Snjlstatic int 317145287Snjlsmist_probe(device_t dev) 318145287Snjl{ 319145287Snjl struct smist_softc *sc; 320145287Snjl device_t ichss_dev, perf_dev; 321145287Snjl int sig, smi_cmd, command, smi_data, flags; 322145287Snjl int type; 323145287Snjl int rv; 324145287Snjl 325145287Snjl if (resource_disabled("smist", 0)) 326145287Snjl return (ENXIO); 327145287Snjl 328145287Snjl sc = device_get_softc(dev); 329145287Snjl 330145287Snjl /* 331145287Snjl * If the ACPI perf or ICH SpeedStep drivers have attached and not 332145287Snjl * just offering info, let them manage things. 333145287Snjl */ 334145287Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 335145287Snjl if (perf_dev && device_is_attached(perf_dev)) { 336145287Snjl rv = CPUFREQ_DRV_TYPE(perf_dev, &type); 337145287Snjl if (rv == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 338145287Snjl return (ENXIO); 339145287Snjl } 340145287Snjl ichss_dev = device_find_child(device_get_parent(dev), "ichss", -1); 341145287Snjl if (ichss_dev && device_is_attached(ichss_dev)) 342145287Snjl return (ENXIO); 343145287Snjl 344145287Snjl int15_gsic_call(&sig, &smi_cmd, &command, &smi_data, &flags); 345145287Snjl if (bootverbose) 346145287Snjl device_printf(dev, "sig %.8x smi_cmd %.4x command %.2x " 347145287Snjl "smi_data %.4x flags %.8x\n", 348145287Snjl sig, smi_cmd, command, smi_data, flags); 349145287Snjl 350145287Snjl if (sig != -1) { 351145287Snjl sc->smi_cmd = smi_cmd; 352145287Snjl sc->smi_data = smi_data; 353145287Snjl 354145287Snjl /* 355145287Snjl * Sometimes int 15h 'GSIC' returns 0x80 for command, when 356145287Snjl * it is actually 0x82. The Windows driver will overwrite 357145287Snjl * this value given by the registry. 358145287Snjl */ 359145287Snjl if (command == 0x80) { 360145287Snjl device_printf(dev, 361145287Snjl "GSIC returned cmd 0x80, should be 0x82\n"); 362145287Snjl command = 0x82; 363145287Snjl } 364145287Snjl sc->command = (sig & 0xffffff00) | (command & 0xff); 365145287Snjl sc->flags = flags; 366145287Snjl } else { 367145287Snjl /* Give some default values */ 368145287Snjl sc->smi_cmd = 0xb2; 369145287Snjl sc->smi_data = 0xb3; 370145287Snjl sc->command = 0x47534982; 371145287Snjl sc->flags = 0; 372145287Snjl } 373145287Snjl 374145287Snjl device_set_desc(dev, "SpeedStep SMI"); 375145287Snjl 376145287Snjl return (-1500); 377145287Snjl} 378145287Snjl 379145287Snjlstatic int 380145287Snjlsmist_attach(device_t dev) 381145287Snjl{ 382145287Snjl struct smist_softc *sc; 383145287Snjl 384145287Snjl sc = device_get_softc(dev); 385145287Snjl sc->dev = dev; 386145287Snjl 387145287Snjl /* If we can't take ownership over BIOS, then bail out */ 388145287Snjl if (set_ownership(dev) != 0) 389145287Snjl return (ENXIO); 390145287Snjl 391145287Snjl /* Setup some defaults for our exported settings. */ 392145287Snjl sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; 393145287Snjl sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; 394145287Snjl sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; 395145287Snjl sc->sets[0].lat = 1000; 396145287Snjl sc->sets[0].dev = dev; 397145287Snjl sc->sets[1] = sc->sets[0]; 398145287Snjl 399145287Snjl cpufreq_register(dev); 400145287Snjl 401145287Snjl return (0); 402145287Snjl} 403145287Snjl 404145287Snjlstatic int 405145287Snjlsmist_detach(device_t dev) 406145287Snjl{ 407182401Sjhb 408182401Sjhb return (cpufreq_unregister(dev)); 409145287Snjl} 410145287Snjl 411145287Snjlstatic int 412145287Snjlsmist_settings(device_t dev, struct cf_setting *sets, int *count) 413145287Snjl{ 414145287Snjl struct smist_softc *sc; 415145287Snjl struct cf_setting set; 416145287Snjl int first, i; 417145287Snjl 418145287Snjl if (sets == NULL || count == NULL) 419145287Snjl return (EINVAL); 420145287Snjl if (*count < 2) { 421145287Snjl *count = 2; 422145287Snjl return (E2BIG); 423145287Snjl } 424145287Snjl sc = device_get_softc(dev); 425145287Snjl 426145287Snjl /* 427145287Snjl * Estimate frequencies for both levels, temporarily switching to 428145287Snjl * the other one if we haven't calibrated it yet. 429145287Snjl */ 430145287Snjl for (i = 0; i < 2; i++) { 431145287Snjl if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) { 432145287Snjl first = (i == 0) ? 1 : 0; 433145287Snjl smist_set(dev, &sc->sets[i]); 434145287Snjl smist_get(dev, &set); 435145287Snjl smist_set(dev, &sc->sets[first]); 436145287Snjl } 437145287Snjl } 438145287Snjl 439145287Snjl bcopy(sc->sets, sets, sizeof(sc->sets)); 440145287Snjl *count = 2; 441145287Snjl 442145287Snjl return (0); 443145287Snjl} 444145287Snjl 445145287Snjlstatic int 446145287Snjlsmist_set(device_t dev, const struct cf_setting *set) 447145287Snjl{ 448145287Snjl struct smist_softc *sc; 449145287Snjl int rv, state, req_state, try; 450145287Snjl 451145287Snjl /* Look up appropriate bit value based on frequency. */ 452145287Snjl sc = device_get_softc(dev); 453145287Snjl if (CPUFREQ_CMP(set->freq, sc->sets[0].freq)) 454145287Snjl req_state = 0; 455145287Snjl else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq)) 456145287Snjl req_state = 1; 457145287Snjl else 458145287Snjl return (EINVAL); 459145287Snjl 460145287Snjl DPRINT(dev, "requested setting %d\n", req_state); 461145287Snjl 462145287Snjl rv = getset_state(sc, &state, GET_STATE); 463145287Snjl if (state == req_state) 464145287Snjl return (0); 465145287Snjl 466145287Snjl try = 3; 467145287Snjl do { 468145287Snjl rv = getset_state(sc, &req_state, SET_STATE); 469145287Snjl 470145287Snjl /* Sleep for 200 microseconds. This value is just a guess. */ 471145287Snjl if (rv) 472145287Snjl DELAY(200); 473145287Snjl } while (rv && --try); 474145287Snjl DPRINT(dev, "set_state return %d, tried %d times\n", 475145287Snjl rv, 4 - try); 476145287Snjl 477145287Snjl return (rv); 478145287Snjl} 479145287Snjl 480145287Snjlstatic int 481145287Snjlsmist_get(device_t dev, struct cf_setting *set) 482145287Snjl{ 483145287Snjl struct smist_softc *sc; 484145287Snjl uint64_t rate; 485145287Snjl int state; 486145287Snjl int rv; 487145287Snjl 488145287Snjl sc = device_get_softc(dev); 489145287Snjl rv = getset_state(sc, &state, GET_STATE); 490145287Snjl if (rv != 0) 491145287Snjl return (rv); 492145287Snjl 493145287Snjl /* If we haven't changed settings yet, estimate the current value. */ 494145287Snjl if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) { 495145287Snjl cpu_est_clockrate(0, &rate); 496145287Snjl sc->sets[state].freq = rate / 1000000; 497145287Snjl DPRINT(dev, "get calibrated new rate of %d\n", 498145287Snjl sc->sets[state].freq); 499145287Snjl } 500145287Snjl *set = sc->sets[state]; 501145287Snjl 502145287Snjl return (0); 503145287Snjl} 504145287Snjl 505145287Snjlstatic int 506145287Snjlsmist_type(device_t dev, int *type) 507145287Snjl{ 508145287Snjl 509145287Snjl if (type == NULL) 510145287Snjl return (EINVAL); 511145287Snjl 512145287Snjl *type = CPUFREQ_TYPE_ABSOLUTE; 513145287Snjl return (0); 514145287Snjl} 515