1/*-
2 * Copyright (c) 2005 Bruno Ducrot
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25/*
26 * This driver is based upon information found by examining speedstep-0.5
27 * from Marc Lehman, which includes all the reverse engineering effort of
28 * Malik Martin (function 1 and 2 of the GSI).
29 *
30 * The correct way for the OS to take ownership from the BIOS was found by
31 * Hiroshi Miura (function 0 of the GSI).
32 *
33 * Finally, the int 15h call interface was (partially) documented by Intel.
34 *
35 * Many thanks to Jon Noack for testing and debugging this driver.
36 */
37
38#include <sys/cdefs.h>
39__FBSDID("$FreeBSD$");
40
41#include <sys/param.h>
42#include <sys/bus.h>
43#include <sys/cpu.h>
44#include <sys/kernel.h>
45#include <sys/module.h>
46#include <sys/systm.h>
47
48#include <machine/bus.h>
49#include <machine/cputypes.h>
50#include <machine/md_var.h>
51#include <machine/vm86.h>
52
53#include <dev/pci/pcivar.h>
54#include <dev/pci/pcireg.h>
55
56#include <vm/vm.h>
57#include <vm/pmap.h>
58
59#include "cpufreq_if.h"
60
61#if 0
62#define DPRINT(dev, x...)	device_printf(dev, x)
63#else
64#define DPRINT(dev, x...)
65#endif
66
67struct smist_softc {
68	device_t		 dev;
69	int			 smi_cmd;
70	int			 smi_data;
71	int			 command;
72	int			 flags;
73	struct cf_setting	 sets[2];	/* Only two settings. */
74};
75
76static char smist_magic[] = "Copyright (c) 1999 Intel Corporation";
77
78static void	smist_identify(driver_t *driver, device_t parent);
79static int	smist_probe(device_t dev);
80static int	smist_attach(device_t dev);
81static int	smist_detach(device_t dev);
82static int	smist_settings(device_t dev, struct cf_setting *sets,
83		    int *count);
84static int	smist_set(device_t dev, const struct cf_setting *set);
85static int	smist_get(device_t dev, struct cf_setting *set);
86static int	smist_type(device_t dev, int *type);
87
88static device_method_t smist_methods[] = {
89	/* Device interface */
90	DEVMETHOD(device_identify,	smist_identify),
91	DEVMETHOD(device_probe,		smist_probe),
92	DEVMETHOD(device_attach,	smist_attach),
93	DEVMETHOD(device_detach,	smist_detach),
94
95	/* cpufreq interface */
96	DEVMETHOD(cpufreq_drv_set,	smist_set),
97	DEVMETHOD(cpufreq_drv_get,	smist_get),
98	DEVMETHOD(cpufreq_drv_type,	smist_type),
99	DEVMETHOD(cpufreq_drv_settings,	smist_settings),
100
101	{0, 0}
102};
103
104static driver_t smist_driver = {
105	"smist", smist_methods, sizeof(struct smist_softc)
106};
107static devclass_t smist_devclass;
108DRIVER_MODULE(smist, cpu, smist_driver, smist_devclass, 0, 0);
109
110struct piix4_pci_device {
111	uint16_t		 vendor;
112	uint16_t		 device;
113	char			*desc;
114};
115
116static struct piix4_pci_device piix4_pci_devices[] = {
117	{0x8086, 0x7113, "Intel PIIX4 ISA bridge"},
118	{0x8086, 0x719b, "Intel PIIX4 ISA bridge (embedded in MX440 chipset)"},
119
120	{0, 0, NULL},
121};
122
123#define SET_OWNERSHIP		0
124#define GET_STATE		1
125#define SET_STATE		2
126
127static int
128int15_gsic_call(int *sig, int *smi_cmd, int *command, int *smi_data, int *flags)
129{
130	struct vm86frame vmf;
131
132	bzero(&vmf, sizeof(vmf));
133	vmf.vmf_eax = 0x0000E980;	/* IST support */
134	vmf.vmf_edx = 0x47534943;	/* 'GSIC' in ASCII */
135	vm86_intcall(0x15, &vmf);
136
137	if (vmf.vmf_eax == 0x47534943) {
138		*sig = vmf.vmf_eax;
139		*smi_cmd = vmf.vmf_ebx & 0xff;
140		*command = (vmf.vmf_ebx >> 16) & 0xff;
141		*smi_data = vmf.vmf_ecx;
142		*flags = vmf.vmf_edx;
143	} else {
144		*sig = -1;
145		*smi_cmd = -1;
146		*command = -1;
147		*smi_data = -1;
148		*flags = -1;
149	}
150
151	return (0);
152}
153
154/* Temporary structure to hold mapped page and status. */
155struct set_ownership_data {
156	int	smi_cmd;
157	int	command;
158	int	result;
159	void	*buf;
160};
161
162/* Perform actual SMI call to enable SpeedStep. */
163static void
164set_ownership_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
165{
166	struct set_ownership_data *data;
167
168	data = arg;
169	if (error) {
170		data->result = error;
171		return;
172	}
173
174	/* Copy in the magic string and send it by writing to the SMI port. */
175	strlcpy(data->buf, smist_magic, PAGE_SIZE);
176	__asm __volatile(
177	    "movl $-1, %%edi\n\t"
178	    "out %%al, (%%dx)\n"
179	    : "=D" (data->result)
180	    : "a" (data->command),
181	      "b" (0),
182	      "c" (0),
183	      "d" (data->smi_cmd),
184	      "S" ((uint32_t)segs[0].ds_addr)
185	);
186}
187
188static int
189set_ownership(device_t dev)
190{
191	struct smist_softc *sc;
192	struct set_ownership_data cb_data;
193	bus_dma_tag_t tag;
194	bus_dmamap_t map;
195
196	/*
197	 * Specify the region to store the magic string.  Since its address is
198	 * passed to the BIOS in a 32-bit register, we have to make sure it is
199	 * located in a physical page below 4 GB (i.e., for PAE.)
200	 */
201	sc = device_get_softc(dev);
202	if (bus_dma_tag_create(/*parent*/ NULL,
203	    /*alignment*/ PAGE_SIZE, /*no boundary*/ 0,
204	    /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, /*highaddr*/ BUS_SPACE_MAXADDR,
205	    NULL, NULL, /*maxsize*/ PAGE_SIZE, /*segments*/ 1,
206	    /*maxsegsize*/ PAGE_SIZE, 0, busdma_lock_mutex, &Giant,
207	    &tag) != 0) {
208		device_printf(dev, "can't create mem tag\n");
209		return (ENXIO);
210	}
211	if (bus_dmamem_alloc(tag, &cb_data.buf, BUS_DMA_NOWAIT, &map) != 0) {
212		bus_dma_tag_destroy(tag);
213		device_printf(dev, "can't alloc mapped mem\n");
214		return (ENXIO);
215	}
216
217	/* Load the physical page map and take ownership in the callback. */
218	cb_data.smi_cmd = sc->smi_cmd;
219	cb_data.command = sc->command;
220	if (bus_dmamap_load(tag, map, cb_data.buf, PAGE_SIZE, set_ownership_cb,
221	    &cb_data, BUS_DMA_NOWAIT) != 0) {
222		bus_dmamem_free(tag, cb_data.buf, map);
223		bus_dma_tag_destroy(tag);
224		device_printf(dev, "can't load mem\n");
225		return (ENXIO);
226	}
227	DPRINT(dev, "taking ownership over BIOS return %d\n", cb_data.result);
228	bus_dmamap_unload(tag, map);
229	bus_dmamem_free(tag, cb_data.buf, map);
230	bus_dma_tag_destroy(tag);
231	return (cb_data.result ? ENXIO : 0);
232}
233
234static int
235getset_state(struct smist_softc *sc, int *state, int function)
236{
237	int new_state;
238	int result;
239	int eax;
240
241	if (!sc)
242		return (ENXIO);
243
244	if (function != GET_STATE && function != SET_STATE)
245		return (EINVAL);
246
247	DPRINT(sc->dev, "calling GSI\n");
248
249	__asm __volatile(
250	     "movl $-1, %%edi\n\t"
251	     "out %%al, (%%dx)\n"
252	   : "=a" (eax),
253	     "=b" (new_state),
254	     "=D" (result)
255	   : "a" (sc->command),
256	     "b" (function),
257	     "c" (*state),
258	     "d" (sc->smi_cmd)
259	);
260
261	DPRINT(sc->dev, "GSI returned: eax %.8x ebx %.8x edi %.8x\n",
262	    eax, new_state, result);
263
264	*state = new_state & 1;
265
266	switch (function) {
267	case GET_STATE:
268		if (eax)
269			return (ENXIO);
270		break;
271	case SET_STATE:
272		if (result)
273			return (ENXIO);
274		break;
275	}
276	return (0);
277}
278
279static void
280smist_identify(driver_t *driver, device_t parent)
281{
282	struct piix4_pci_device *id;
283	device_t piix4 = NULL;
284
285	if (resource_disabled("ichst", 0))
286		return;
287
288	/* Check for a supported processor */
289	if (cpu_vendor_id != CPU_VENDOR_INTEL)
290		return;
291	switch (cpu_id & 0xff0) {
292	case 0x680:	/* Pentium III [coppermine] */
293	case 0x6a0:	/* Pentium III [Tualatin] */
294		break;
295	default:
296		return;
297	}
298
299	/* Check for a supported PCI-ISA bridge */
300	for (id = piix4_pci_devices; id->desc != NULL; ++id) {
301		if ((piix4 = pci_find_device(id->vendor, id->device)) != NULL)
302			break;
303	}
304	if (!piix4)
305		return;
306
307	if (bootverbose)
308		printf("smist: found supported isa bridge %s\n", id->desc);
309
310	if (device_find_child(parent, "smist", -1) != NULL)
311		return;
312	if (BUS_ADD_CHILD(parent, 30, "smist", -1) == NULL)
313		device_printf(parent, "smist: add child failed\n");
314}
315
316static int
317smist_probe(device_t dev)
318{
319	struct smist_softc *sc;
320	device_t ichss_dev, perf_dev;
321	int sig, smi_cmd, command, smi_data, flags;
322	int type;
323	int rv;
324
325	if (resource_disabled("smist", 0))
326		return (ENXIO);
327
328	sc = device_get_softc(dev);
329
330	/*
331	 * If the ACPI perf or ICH SpeedStep drivers have attached and not
332	 * just offering info, let them manage things.
333	 */
334	perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
335	if (perf_dev && device_is_attached(perf_dev)) {
336		rv = CPUFREQ_DRV_TYPE(perf_dev, &type);
337		if (rv == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
338			return (ENXIO);
339	}
340	ichss_dev = device_find_child(device_get_parent(dev), "ichss", -1);
341	if (ichss_dev && device_is_attached(ichss_dev))
342		return (ENXIO);
343
344	int15_gsic_call(&sig, &smi_cmd, &command, &smi_data, &flags);
345	if (bootverbose)
346		device_printf(dev, "sig %.8x smi_cmd %.4x command %.2x "
347		    "smi_data %.4x flags %.8x\n",
348		    sig, smi_cmd, command, smi_data, flags);
349
350	if (sig != -1) {
351		sc->smi_cmd = smi_cmd;
352		sc->smi_data = smi_data;
353
354		/*
355		 * Sometimes int 15h 'GSIC' returns 0x80 for command, when
356		 * it is actually 0x82.  The Windows driver will overwrite
357		 * this value given by the registry.
358		 */
359		if (command == 0x80) {
360			device_printf(dev,
361			    "GSIC returned cmd 0x80, should be 0x82\n");
362			command = 0x82;
363		}
364		sc->command = (sig & 0xffffff00) | (command & 0xff);
365		sc->flags = flags;
366	} else {
367		/* Give some default values */
368		sc->smi_cmd = 0xb2;
369		sc->smi_data = 0xb3;
370		sc->command = 0x47534982;
371		sc->flags = 0;
372	}
373
374	device_set_desc(dev, "SpeedStep SMI");
375
376	return (-1500);
377}
378
379static int
380smist_attach(device_t dev)
381{
382	struct smist_softc *sc;
383
384	sc = device_get_softc(dev);
385	sc->dev = dev;
386
387	/* If we can't take ownership over BIOS, then bail out */
388	if (set_ownership(dev) != 0)
389		return (ENXIO);
390
391	/* Setup some defaults for our exported settings. */
392	sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
393	sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
394	sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
395	sc->sets[0].lat = 1000;
396	sc->sets[0].dev = dev;
397	sc->sets[1] = sc->sets[0];
398
399	cpufreq_register(dev);
400
401	return (0);
402}
403
404static int
405smist_detach(device_t dev)
406{
407
408	return (cpufreq_unregister(dev));
409}
410
411static int
412smist_settings(device_t dev, struct cf_setting *sets, int *count)
413{
414	struct smist_softc *sc;
415	struct cf_setting set;
416	int first, i;
417
418	if (sets == NULL || count == NULL)
419		return (EINVAL);
420	if (*count < 2) {
421		*count = 2;
422		return (E2BIG);
423	}
424	sc = device_get_softc(dev);
425
426	/*
427	 * Estimate frequencies for both levels, temporarily switching to
428	 * the other one if we haven't calibrated it yet.
429	 */
430	for (i = 0; i < 2; i++) {
431		if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
432			first = (i == 0) ? 1 : 0;
433			smist_set(dev, &sc->sets[i]);
434			smist_get(dev, &set);
435			smist_set(dev, &sc->sets[first]);
436		}
437	}
438
439	bcopy(sc->sets, sets, sizeof(sc->sets));
440	*count = 2;
441
442	return (0);
443}
444
445static int
446smist_set(device_t dev, const struct cf_setting *set)
447{
448	struct smist_softc *sc;
449	int rv, state, req_state, try;
450
451	/* Look up appropriate bit value based on frequency. */
452	sc = device_get_softc(dev);
453	if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
454		req_state = 0;
455	else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
456		req_state = 1;
457	else
458		return (EINVAL);
459
460	DPRINT(dev, "requested setting %d\n", req_state);
461
462	rv = getset_state(sc, &state, GET_STATE);
463	if (state == req_state)
464		return (0);
465
466	try = 3;
467	do {
468		rv = getset_state(sc, &req_state, SET_STATE);
469
470		/* Sleep for 200 microseconds.  This value is just a guess. */
471		if (rv)
472			DELAY(200);
473	} while (rv && --try);
474	DPRINT(dev, "set_state return %d, tried %d times\n",
475	    rv, 4 - try);
476
477	return (rv);
478}
479
480static int
481smist_get(device_t dev, struct cf_setting *set)
482{
483	struct smist_softc *sc;
484	uint64_t rate;
485	int state;
486	int rv;
487
488	sc = device_get_softc(dev);
489	rv = getset_state(sc, &state, GET_STATE);
490	if (rv != 0)
491		return (rv);
492
493	/* If we haven't changed settings yet, estimate the current value. */
494	if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
495		cpu_est_clockrate(0, &rate);
496		sc->sets[state].freq = rate / 1000000;
497		DPRINT(dev, "get calibrated new rate of %d\n",
498		    sc->sets[state].freq);
499	}
500	*set = sc->sets[state];
501
502	return (0);
503}
504
505static int
506smist_type(device_t dev, int *type)
507{
508
509	if (type == NULL)
510		return (EINVAL);
511
512	*type = CPUFREQ_TYPE_ABSOLUTE;
513	return (0);
514}
515