1/*- 2 * Copyright (c) 2010 - 2011 Marius Strobl <marius@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32 33#include <machine/asi.h> 34#include <machine/cache.h> 35#include <machine/cpu.h> 36#include <machine/cpufunc.h> 37#include <machine/mcntl.h> 38#include <machine/lsu.h> 39#include <machine/tlb.h> 40#include <machine/tte.h> 41#include <machine/vmparam.h> 42 43#define ZEUS_FTLB_ENTRIES 32 44#define ZEUS_STLB_ENTRIES 2048 45 46/* 47 * CPU-specific initialization for Fujitsu Zeus CPUs 48 */ 49void 50zeus_init(u_int cpu_impl) 51{ 52 u_long val; 53 54 /* Ensure the TSB Extension Registers hold 0 as TSB_Base. */ 55 56 stxa(AA_DMMU_TSB_PEXT_REG, ASI_DMMU, 0); 57 stxa(AA_IMMU_TSB_PEXT_REG, ASI_IMMU, 0); 58 membar(Sync); 59 60 stxa(AA_DMMU_TSB_SEXT_REG, ASI_DMMU, 0); 61 /* 62 * NB: the secondary context was removed from the iMMU. 63 */ 64 membar(Sync); 65 66 stxa(AA_DMMU_TSB_NEXT_REG, ASI_DMMU, 0); 67 stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0); 68 membar(Sync); 69 70 val = ldxa(AA_MCNTL, ASI_MCNTL); 71 /* Ensure MCNTL_JPS1_TSBP is 0. */ 72 val &= ~MCNTL_JPS1_TSBP; 73 /* 74 * Ensure 4-Mbyte page entries are stored in the 1024-entry, 2-way set 75 * associative TLB. 76 */ 77 val = (val & ~MCNTL_RMD_MASK) | MCNTL_RMD_1024; 78 stxa(AA_MCNTL, ASI_MCNTL, val); 79} 80 81/* 82 * Enable level 1 caches. 83 */ 84void 85zeus_cache_enable(u_int cpu_impl) 86{ 87 u_long lsu; 88 89 lsu = ldxa(0, ASI_LSU_CTL_REG); 90 stxa(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC); 91 flush(KERNBASE); 92} 93 94/* 95 * Flush all lines from the level 1 caches. 96 */ 97void 98zeus_cache_flush(void) 99{ 100 101 stxa_sync(0, ASI_FLUSH_L1I, 0); 102} 103 104/* 105 * Flush a physical page from the data cache. Data cache consistency is 106 * maintained by hardware. 107 */ 108void 109zeus_dcache_page_inval(vm_paddr_t spa __unused) 110{ 111 112} 113 114/* 115 * Flush a physical page from the intsruction cache. Instruction cache 116 * consistency is maintained by hardware. 117 */ 118void 119zeus_icache_page_inval(vm_paddr_t pa __unused) 120{ 121 122} 123 124/* 125 * Flush all non-locked mappings from the TLBs. 126 */ 127void 128zeus_tlb_flush_nonlocked(void) 129{ 130 131 stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0); 132 stxa(TLB_DEMAP_ALL, ASI_IMMU_DEMAP, 0); 133 flush(KERNBASE); 134} 135 136/* 137 * Flush all user mappings from the TLBs. 138 */ 139void 140zeus_tlb_flush_user(void) 141{ 142 u_long data, tag; 143 u_int i, slot; 144 145 for (i = 0; i < ZEUS_FTLB_ENTRIES; i++) { 146 slot = TLB_DAR_SLOT(TLB_DAR_FTLB, i); 147 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 148 tag = ldxa(slot, ASI_DTLB_TAG_READ_REG); 149 if ((data & TD_V) != 0 && (data & TD_L) == 0 && 150 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 151 stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0); 152 data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 153 tag = ldxa(slot, ASI_ITLB_TAG_READ_REG); 154 if ((data & TD_V) != 0 && (data & TD_L) == 0 && 155 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 156 stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0); 157 } 158 for (i = 0; i < ZEUS_STLB_ENTRIES; i++) { 159 slot = TLB_DAR_SLOT(TLB_DAR_STLB, i); 160 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 161 tag = ldxa(slot, ASI_DTLB_TAG_READ_REG); 162 if ((data & TD_V) != 0 && (data & TD_L) == 0 && 163 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 164 stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0); 165 data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 166 tag = ldxa(slot, ASI_ITLB_TAG_READ_REG); 167 if ((data & TD_V) != 0 && (data & TD_L) == 0 && 168 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 169 stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0); 170 } 171} 172