fsr.h revision 166105
186530Sjake/*- 286530Sjake * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 386530Sjake * 486530Sjake * Redistribution and use in source and binary forms, with or without 586530Sjake * modification, are permitted provided that the following conditions 686530Sjake * are met: 786530Sjake * 1. Redistributions of source code must retain the above copyright 886530Sjake * notice, this list of conditions and the following disclaimer. 986530Sjake * 2. Redistributions in binary form must reproduce the above copyright 1086530Sjake * notice, this list of conditions and the following disclaimer in the 1186530Sjake * documentation and/or other materials provided with the distribution. 1286530Sjake * 1386530Sjake * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1486530Sjake * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1586530Sjake * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1686530Sjake * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 1786530Sjake * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 1886530Sjake * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 1986530Sjake * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 2086530Sjake * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2186530Sjake * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 2286530Sjake * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2386530Sjake * 2486530Sjake * $FreeBSD: head/sys/sparc64/include/fsr.h 166105 2007-01-19 11:15:34Z marius $ 2586530Sjake */ 2686530Sjake 2786530Sjake#ifndef _MACHINE_FSR_H_ 2886530Sjake#define _MACHINE_FSR_H_ 2986530Sjake 3086530Sjake#define FPRS_DL (1 << 0) 3186530Sjake#define FPRS_DU (1 << 1) 3286530Sjake#define FPRS_FEF (1 << 2) 3386530Sjake 34166105Smarius#ifndef LOCORE 35166105Smarius 3686530Sjake#define FSR_EXC_BITS 5 3792051Stmm#define FSR_EXC_MASK ((1UL << FSR_EXC_BITS) - 1) 3886530Sjake#define FSR_CEXC_SHIFT 0 3986530Sjake#define FSR_CEXC_MASK (FSR_EXC_MASK << FSR_CEXC_SHIFT) 40103321Stmm#define FSR_CEXC(b) ((unsigned long)(b) << FSR_CEXC_SHIFT) 41103321Stmm#define FSR_GET_CEXC(x) (((x) & FSR_CEXC_MASK) >> FSR_CEXC_SHIFT) 4286530Sjake#define FSR_AEXC_SHIFT 5 4386530Sjake#define FSR_AEXC_MASK (FSR_EXC_MASK << FSR_AEXC_SHIFT) 44103321Stmm#define FSR_AEXC(b) ((unsigned long)(b) << FSR_AEXC_SHIFT) 45103321Stmm#define FSR_GET_AEXC(x) (((x) & FSR_AEXC_MASK) >> FSR_AEXC_SHIFT) 4692051Stmm#define FSR_QNE (1UL << 13) 4792051Stmm#define FSR_NS (1UL << 22) 4886530Sjake#define FSR_TEM_SHIFT 23 4986530Sjake#define FSR_TEM_MASK (FSR_EXC_MASK << FSR_TEM_SHIFT) 50103321Stmm#define FSR_TEM(b) ((unsigned long)(b) << FSR_TEM_SHIFT) 51103321Stmm#define FSR_GET_TEM(x) (((x) & FSR_TEM_MASK) >> FSR_TEM_SHIFT) 5286530Sjake#define FSR_FCC0_SHIFT 10 5386530Sjake#define FSR_FCC0_BITS 2 5492051Stmm#define FSR_FCC0_MASK (((1UL << FSR_FCC0_BITS) - 1) << FSR_FCC0_SHIFT) 55103321Stmm#define FSR_FCC0(x) ((unsigned long)(x) << FSR_FCC0_SHIFT) 56103321Stmm#define FSR_GET_FCC0(x) (((x) & FSR_FCC0_MASK) >> FSR_FCC0_SHIFT) 5786530Sjake#define FSR_FTT_SHIFT 14 5886530Sjake#define FSR_FTT_BITS 3 5992051Stmm#define FSR_FTT_MASK (((1UL << FSR_FTT_BITS) - 1) << FSR_FTT_SHIFT) 60103321Stmm#define FSR_FTT(x) ((unsigned long)(x) << FSR_FTT_SHIFT) 6186530Sjake#define FSR_GET_FTT(x) (((x) & FSR_FTT_MASK) >> FSR_FTT_SHIFT) 6286530Sjake#define FSR_VER_SHIFT 17 6386530Sjake#define FSR_GET_VER(x) (((x) >> FSR_VER_SHIFT) & 7) 6486530Sjake#define FSR_RD_SHIFT 30 6586530Sjake#define FSR_RD_BITS 2 6692051Stmm#define FSR_RD_MASK (((1UL << FSR_RD_BITS) - 1) << FSR_RD_SHIFT) 67103321Stmm#define FSR_RD(x) ((unsigned long)(x) << FSR_RD_SHIFT) 68103321Stmm#define FSR_GET_RD(x) (((x) & FSR_RD_MASK) >> FSR_RD_SHIFT) 6986530Sjake#define FSR_FCC1_SHIFT 32 7086530Sjake#define FSR_FCC1_BITS 2 7192051Stmm#define FSR_FCC1_MASK (((1UL << FSR_FCC1_BITS) - 1) << FSR_FCC1_SHIFT) 72103321Stmm#define FSR_FCC1(x) ((unsigned long)(x) << FSR_FCC1_SHIFT) 73103321Stmm#define FSR_GET_FCC1(x) (((x) & FSR_FCC1_MASK) >> FSR_FCC1_SHIFT) 7486530Sjake#define FSR_FCC2_SHIFT 34 7586530Sjake#define FSR_FCC2_BITS 2 7692051Stmm#define FSR_FCC2_MASK (((1UL << FSR_FCC2_BITS) - 1) << FSR_FCC2_SHIFT) 77103321Stmm#define FSR_FCC2(x) ((unsigned long)(x) << FSR_FCC2_SHIFT) 78103321Stmm#define FSR_GET_FCC2(x) (((x) & FSR_FCC2_MASK) >> FSR_FCC2_SHIFT) 7986530Sjake#define FSR_FCC3_SHIFT 36 8086530Sjake#define FSR_FCC3_BITS 2 8192051Stmm#define FSR_FCC3_MASK (((1UL << FSR_FCC3_BITS) - 1) << FSR_FCC3_SHIFT) 82103321Stmm#define FSR_FCC3(x) ((unsigned long)(x) << FSR_FCC3_SHIFT) 83103321Stmm#define FSR_GET_FCC3(x) (((x) & FSR_FCC3_MASK) >> FSR_FCC3_SHIFT) 8486530Sjake 8586530Sjake/* CEXC/AEXC/TEM exception values */ 8686530Sjake#define FSR_NX (1 << 0) 8786530Sjake#define FSR_DZ (1 << 1) 8886530Sjake#define FSR_UF (1 << 2) 8986530Sjake#define FSR_OF (1 << 3) 9086530Sjake#define FSR_NV (1 << 4) 9186530Sjake/* FTT values. */ 9286530Sjake#define FSR_FTT_NONE 0 9386530Sjake#define FSR_FTT_IEEE 1 9486530Sjake#define FSR_FTT_UNFIN 2 9586530Sjake#define FSR_FTT_UNIMP 3 9686530Sjake#define FSR_FTT_SEQERR 4 9786530Sjake#define FSR_FTT_HWERR 5 9886530Sjake#define FSR_FTT_INVREG 6 9986530Sjake/* RD values */ 10086530Sjake#define FSR_RD_N 0 /* nearest */ 10186530Sjake#define FSR_RD_Z 1 /* zero */ 10286530Sjake#define FSR_RD_PINF 2 /* +infinity */ 10386530Sjake#define FSR_RD_NINF 3 /* -infinity */ 10486530Sjake/* condition codes */ 10586530Sjake#define FSR_CC_EQ 0 /* a = b */ 10686530Sjake#define FSR_CC_LT 1 /* a < b */ 10786530Sjake#define FSR_CC_GT 2 /* a > b */ 10886530Sjake#define FSR_CC_UO 3 /* unordered */ 10986530Sjake 110166105Smarius#endif /* !LOCORE */ 111166105Smarius 11286530Sjake#endif /* !_MACHINE_FSR_H_ */ 113