1/*- 2 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 20 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 22 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * $FreeBSD$ 25 */ 26 27#ifndef _MACHINE_FSR_H_ 28#define _MACHINE_FSR_H_ 29 30#define FPRS_DL (1 << 0) 31#define FPRS_DU (1 << 1) 32#define FPRS_FEF (1 << 2) 33 34#define VIS_BLOCKSIZE 64 35 36#ifndef LOCORE 37 38#define FSR_EXC_BITS 5 39#define FSR_EXC_MASK ((1UL << FSR_EXC_BITS) - 1) 40#define FSR_CEXC_SHIFT 0 41#define FSR_CEXC_MASK (FSR_EXC_MASK << FSR_CEXC_SHIFT) 42#define FSR_CEXC(b) ((unsigned long)(b) << FSR_CEXC_SHIFT) 43#define FSR_GET_CEXC(x) (((x) & FSR_CEXC_MASK) >> FSR_CEXC_SHIFT) 44#define FSR_AEXC_SHIFT 5 45#define FSR_AEXC_MASK (FSR_EXC_MASK << FSR_AEXC_SHIFT) 46#define FSR_AEXC(b) ((unsigned long)(b) << FSR_AEXC_SHIFT) 47#define FSR_GET_AEXC(x) (((x) & FSR_AEXC_MASK) >> FSR_AEXC_SHIFT) 48#define FSR_QNE (1UL << 13) 49#define FSR_NS (1UL << 22) 50#define FSR_TEM_SHIFT 23 51#define FSR_TEM_MASK (FSR_EXC_MASK << FSR_TEM_SHIFT) 52#define FSR_TEM(b) ((unsigned long)(b) << FSR_TEM_SHIFT) 53#define FSR_GET_TEM(x) (((x) & FSR_TEM_MASK) >> FSR_TEM_SHIFT) 54#define FSR_FCC0_SHIFT 10 55#define FSR_FCC0_BITS 2 56#define FSR_FCC0_MASK (((1UL << FSR_FCC0_BITS) - 1) << FSR_FCC0_SHIFT) 57#define FSR_FCC0(x) ((unsigned long)(x) << FSR_FCC0_SHIFT) 58#define FSR_GET_FCC0(x) (((x) & FSR_FCC0_MASK) >> FSR_FCC0_SHIFT) 59#define FSR_FTT_SHIFT 14 60#define FSR_FTT_BITS 3 61#define FSR_FTT_MASK (((1UL << FSR_FTT_BITS) - 1) << FSR_FTT_SHIFT) 62#define FSR_FTT(x) ((unsigned long)(x) << FSR_FTT_SHIFT) 63#define FSR_GET_FTT(x) (((x) & FSR_FTT_MASK) >> FSR_FTT_SHIFT) 64#define FSR_VER_SHIFT 17 65#define FSR_GET_VER(x) (((x) >> FSR_VER_SHIFT) & 7) 66#define FSR_RD_SHIFT 30 67#define FSR_RD_BITS 2 68#define FSR_RD_MASK (((1UL << FSR_RD_BITS) - 1) << FSR_RD_SHIFT) 69#define FSR_RD(x) ((unsigned long)(x) << FSR_RD_SHIFT) 70#define FSR_GET_RD(x) (((x) & FSR_RD_MASK) >> FSR_RD_SHIFT) 71#define FSR_FCC1_SHIFT 32 72#define FSR_FCC1_BITS 2 73#define FSR_FCC1_MASK (((1UL << FSR_FCC1_BITS) - 1) << FSR_FCC1_SHIFT) 74#define FSR_FCC1(x) ((unsigned long)(x) << FSR_FCC1_SHIFT) 75#define FSR_GET_FCC1(x) (((x) & FSR_FCC1_MASK) >> FSR_FCC1_SHIFT) 76#define FSR_FCC2_SHIFT 34 77#define FSR_FCC2_BITS 2 78#define FSR_FCC2_MASK (((1UL << FSR_FCC2_BITS) - 1) << FSR_FCC2_SHIFT) 79#define FSR_FCC2(x) ((unsigned long)(x) << FSR_FCC2_SHIFT) 80#define FSR_GET_FCC2(x) (((x) & FSR_FCC2_MASK) >> FSR_FCC2_SHIFT) 81#define FSR_FCC3_SHIFT 36 82#define FSR_FCC3_BITS 2 83#define FSR_FCC3_MASK (((1UL << FSR_FCC3_BITS) - 1) << FSR_FCC3_SHIFT) 84#define FSR_FCC3(x) ((unsigned long)(x) << FSR_FCC3_SHIFT) 85#define FSR_GET_FCC3(x) (((x) & FSR_FCC3_MASK) >> FSR_FCC3_SHIFT) 86 87/* CEXC/AEXC/TEM exception values */ 88#define FSR_NX (1 << 0) 89#define FSR_DZ (1 << 1) 90#define FSR_UF (1 << 2) 91#define FSR_OF (1 << 3) 92#define FSR_NV (1 << 4) 93/* FTT values. */ 94#define FSR_FTT_NONE 0 95#define FSR_FTT_IEEE 1 96#define FSR_FTT_UNFIN 2 97#define FSR_FTT_UNIMP 3 98#define FSR_FTT_SEQERR 4 99#define FSR_FTT_HWERR 5 100#define FSR_FTT_INVREG 6 101/* RD values */ 102#define FSR_RD_N 0 /* nearest */ 103#define FSR_RD_Z 1 /* zero */ 104#define FSR_RD_PINF 2 /* +infinity */ 105#define FSR_RD_NINF 3 /* -infinity */ 106/* condition codes */ 107#define FSR_CC_EQ 0 /* a = b */ 108#define FSR_CC_LT 1 /* a < b */ 109#define FSR_CC_GT 2 /* a > b */ 110#define FSR_CC_UO 3 /* unordered */ 111 112#endif /* !LOCORE */ 113 114#endif /* !_MACHINE_FSR_H_ */ 115