cpufunc.h revision 338514
1292407Sbr/*- 2292407Sbr * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3292407Sbr * All rights reserved. 4292407Sbr * 5292407Sbr * Portions of this software were developed by SRI International and the 6292407Sbr * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7292407Sbr * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8292407Sbr * 9292407Sbr * Portions of this software were developed by the University of Cambridge 10292407Sbr * Computer Laboratory as part of the CTSRD Project, with support from the 11292407Sbr * UK Higher Education Innovation Fund (HEIF). 12292407Sbr * 13292407Sbr * Redistribution and use in source and binary forms, with or without 14292407Sbr * modification, are permitted provided that the following conditions 15292407Sbr * are met: 16292407Sbr * 1. Redistributions of source code must retain the above copyright 17292407Sbr * notice, this list of conditions and the following disclaimer. 18292407Sbr * 2. Redistributions in binary form must reproduce the above copyright 19292407Sbr * notice, this list of conditions and the following disclaimer in the 20292407Sbr * documentation and/or other materials provided with the distribution. 21292407Sbr * 22292407Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23292407Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24292407Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25292407Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26292407Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27292407Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28292407Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29292407Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30292407Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31292407Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32292407Sbr * SUCH DAMAGE. 33292407Sbr * 34292407Sbr * $FreeBSD: stable/11/sys/riscv/include/cpufunc.h 338514 2018-09-06 22:23:39Z jhb $ 35292407Sbr */ 36292407Sbr 37292407Sbr#ifndef _MACHINE_CPUFUNC_H_ 38292407Sbr#define _MACHINE_CPUFUNC_H_ 39292407Sbr 40292407Sbrstatic __inline void 41292407Sbrbreakpoint(void) 42292407Sbr{ 43292407Sbr 44292407Sbr __asm("ebreak"); 45292407Sbr} 46292407Sbr 47338514Sjhb#ifdef _KERNEL 48338514Sjhb 49338514Sjhb#include <machine/riscvreg.h> 50338514Sjhb 51292407Sbrstatic __inline register_t 52292407Sbrintr_disable(void) 53292407Sbr{ 54292407Sbr uint64_t ret; 55292407Sbr 56292407Sbr __asm __volatile( 57292407Sbr "csrrci %0, sstatus, 1" 58292407Sbr : "=&r" (ret) 59292407Sbr ); 60292407Sbr 61292407Sbr return (ret & SSTATUS_IE); 62292407Sbr} 63292407Sbr 64292407Sbrstatic __inline void 65292407Sbrintr_restore(register_t s) 66292407Sbr{ 67292407Sbr 68292407Sbr __asm __volatile( 69292407Sbr "csrs sstatus, %0" 70292407Sbr :: "r" (s) 71292407Sbr ); 72292407Sbr} 73292407Sbr 74292407Sbrstatic __inline void 75292407Sbrintr_enable(void) 76292407Sbr{ 77292407Sbr 78292407Sbr __asm __volatile( 79292407Sbr "csrsi sstatus, 1" 80292407Sbr ); 81292407Sbr} 82292407Sbr 83292407Sbrstatic __inline register_t 84292407Sbrmachine_command(uint64_t cmd, uint64_t arg) 85292407Sbr{ 86292407Sbr uint64_t res; 87292407Sbr 88292407Sbr __asm __volatile( 89292407Sbr "mv t5, %2\n" 90292407Sbr "mv t6, %1\n" 91292407Sbr "ecall\n" 92292407Sbr "mv %0, t6" : "=&r"(res) : "r"(arg), "r"(cmd) 93292407Sbr ); 94292407Sbr 95292407Sbr return (res); 96292407Sbr} 97292407Sbr 98292407Sbr#define cpu_nullop() riscv_nullop() 99292407Sbr#define cpufunc_nullop() riscv_nullop() 100292407Sbr#define cpu_setttb(a) riscv_setttb(a) 101292407Sbr 102292407Sbr#define cpu_tlb_flushID() riscv_tlb_flushID() 103292407Sbr#define cpu_tlb_flushID_SE(e) riscv_tlb_flushID_SE(e) 104292407Sbr 105292407Sbr#define cpu_dcache_wbinv_range(a, s) riscv_dcache_wbinv_range((a), (s)) 106292407Sbr#define cpu_dcache_inv_range(a, s) riscv_dcache_inv_range((a), (s)) 107292407Sbr#define cpu_dcache_wb_range(a, s) riscv_dcache_wb_range((a), (s)) 108292407Sbr 109292407Sbr#define cpu_idcache_wbinv_range(a, s) riscv_idcache_wbinv_range((a), (s)) 110292407Sbr#define cpu_icache_sync_range(a, s) riscv_icache_sync_range((a), (s)) 111292407Sbr 112292407Sbrvoid riscv_nullop(void); 113292407Sbrvoid riscv_setttb(vm_offset_t); 114292407Sbrvoid riscv_tlb_flushID(void); 115292407Sbrvoid riscv_tlb_flushID_SE(vm_offset_t); 116292407Sbrvoid riscv_icache_sync_range(vm_offset_t, vm_size_t); 117292407Sbrvoid riscv_idcache_wbinv_range(vm_offset_t, vm_size_t); 118292407Sbrvoid riscv_dcache_wbinv_range(vm_offset_t, vm_size_t); 119292407Sbrvoid riscv_dcache_inv_range(vm_offset_t, vm_size_t); 120292407Sbrvoid riscv_dcache_wb_range(vm_offset_t, vm_size_t); 121292407Sbr 122292407Sbr#endif /* _KERNEL */ 123292407Sbr#endif /* _MACHINE_CPUFUNC_H_ */ 124