1/*-
2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: stable/11/sys/riscv/include/cpufunc.h 338514 2018-09-06 22:23:39Z jhb $
35 */
36
37#ifndef _MACHINE_CPUFUNC_H_
38#define	_MACHINE_CPUFUNC_H_
39
40static __inline void
41breakpoint(void)
42{
43
44	__asm("ebreak");
45}
46
47#ifdef _KERNEL
48
49#include <machine/riscvreg.h>
50
51static __inline register_t
52intr_disable(void)
53{
54	uint64_t ret;
55
56	__asm __volatile(
57		"csrrci %0, sstatus, 1"
58		: "=&r" (ret)
59	);
60
61	return (ret & SSTATUS_IE);
62}
63
64static __inline void
65intr_restore(register_t s)
66{
67
68	__asm __volatile(
69		"csrs sstatus, %0"
70		:: "r" (s)
71	);
72}
73
74static __inline void
75intr_enable(void)
76{
77
78	__asm __volatile(
79		"csrsi sstatus, 1"
80	);
81}
82
83static __inline register_t
84machine_command(uint64_t cmd, uint64_t arg)
85{
86	uint64_t res;
87
88	__asm __volatile(
89		"mv	t5, %2\n"
90		"mv	t6, %1\n"
91		"ecall\n"
92		"mv	%0, t6" : "=&r"(res) : "r"(arg), "r"(cmd)
93	);
94
95	return (res);
96}
97
98#define	cpu_nullop()			riscv_nullop()
99#define	cpufunc_nullop()		riscv_nullop()
100#define	cpu_setttb(a)			riscv_setttb(a)
101
102#define	cpu_tlb_flushID()		riscv_tlb_flushID()
103#define	cpu_tlb_flushID_SE(e)		riscv_tlb_flushID_SE(e)
104
105#define	cpu_dcache_wbinv_range(a, s)	riscv_dcache_wbinv_range((a), (s))
106#define	cpu_dcache_inv_range(a, s)	riscv_dcache_inv_range((a), (s))
107#define	cpu_dcache_wb_range(a, s)	riscv_dcache_wb_range((a), (s))
108
109#define	cpu_idcache_wbinv_range(a, s)	riscv_idcache_wbinv_range((a), (s))
110#define	cpu_icache_sync_range(a, s)	riscv_icache_sync_range((a), (s))
111
112void riscv_nullop(void);
113void riscv_setttb(vm_offset_t);
114void riscv_tlb_flushID(void);
115void riscv_tlb_flushID_SE(vm_offset_t);
116void riscv_icache_sync_range(vm_offset_t, vm_size_t);
117void riscv_idcache_wbinv_range(vm_offset_t, vm_size_t);
118void riscv_dcache_wbinv_range(vm_offset_t, vm_size_t);
119void riscv_dcache_inv_range(vm_offset_t, vm_size_t);
120void riscv_dcache_wb_range(vm_offset_t, vm_size_t);
121
122#endif	/* _KERNEL */
123#endif	/* _MACHINE_CPUFUNC_H_ */
124