platform_bare.c revision 209908
1/*- 2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/powerpc/booke/platform_bare.c 209908 2010-07-11 21:08:29Z raj $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <sys/pcpu.h> 35#include <sys/proc.h> 36#include <sys/smp.h> 37 38#include <machine/bus.h> 39#include <machine/cpu.h> 40#include <machine/hid.h> 41#include <machine/platform.h> 42#include <machine/platformvar.h> 43#include <machine/smp.h> 44#include <machine/spr.h> 45#include <machine/vmparam.h> 46 47#include <dev/fdt/fdt_common.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50#include <dev/ofw/openfirm.h> 51 52#include <powerpc/mpc85xx/mpc85xx.h> 53 54#include "platform_if.h" 55 56#ifdef SMP 57extern void *ap_pcpu; 58extern uint8_t __boot_page[]; /* Boot page body */ 59extern uint32_t kernload; /* Kernel physical load address */ 60#endif 61 62static int cpu, maxcpu; 63 64static int bare_probe(platform_t); 65static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz, 66 struct mem_region **avail, int *availsz); 67static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref); 68static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref); 69static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref); 70static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref); 71static int bare_smp_start_cpu(platform_t, struct pcpu *cpu); 72 73static platform_method_t bare_methods[] = { 74 PLATFORMMETHOD(platform_probe, bare_probe), 75 PLATFORMMETHOD(platform_mem_regions, bare_mem_regions), 76 PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq), 77 78 PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu), 79 PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu), 80 PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp), 81 PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu), 82 83 { 0, 0 } 84}; 85 86static platform_def_t bare_platform = { 87 "bare metal", 88 bare_methods, 89 0 90}; 91 92PLATFORM_DEF(bare_platform); 93 94static int 95bare_probe(platform_t plat) 96{ 97 uint32_t ver, sr; 98 int i, law_max, tgt; 99 100 ver = SVR_VER(mfspr(SPR_SVR)); 101 if (ver == SVR_MPC8572E || ver == SVR_MPC8572) 102 maxcpu = 2; 103 else 104 maxcpu = 1; 105 106 /* 107 * Clear local access windows. Skip DRAM entries, so we don't shoot 108 * ourselves in the foot. 109 */ 110 law_max = law_getmax(); 111 for (i = 0; i < law_max; i++) { 112 sr = ccsr_read4(OCP85XX_LAWSR(i)); 113 if ((sr & 0x80000000) == 0) 114 continue; 115 tgt = (sr & 0x01f00000) >> 20; 116 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 117 tgt == OCP85XX_TGTIF_RAM_INTL) 118 continue; 119 120 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 121 } 122 123 return (BUS_PROBE_GENERIC); 124} 125 126#define MEM_REGIONS 8 127static struct mem_region avail_regions[MEM_REGIONS]; 128 129void 130bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 131 struct mem_region **avail, int *availsz) 132{ 133 uint32_t memsize; 134 int i, rv; 135 136 rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 137 138 if (rv != 0) 139 return; 140 141 for (i = 0; i < *availsz; i++) { 142 if (avail_regions[i].mr_start < 1048576) { 143 avail_regions[i].mr_size = 144 avail_regions[i].mr_size - 145 (1048576 - avail_regions[i].mr_start); 146 avail_regions[i].mr_start = 1048576; 147 } 148 } 149 *avail = avail_regions; 150 151 /* On the bare metal platform phys == avail memory */ 152 *physsz = *availsz; 153 *phys = *avail; 154} 155 156static u_long 157bare_timebase_freq(platform_t plat, struct cpuref *cpuref) 158{ 159 u_long ticks = -1; 160 phandle_t cpus, child; 161 pcell_t freq; 162 163 if ((cpus = OF_finddevice("/cpus")) == 0) 164 goto out; 165 166 if ((child = OF_child(cpus)) == 0) 167 goto out; 168 169 if (OF_getprop(child, "bus-frequency", (void *)&freq, 170 sizeof(freq)) <= 0) 171 goto out; 172 /* 173 * Time Base and Decrementer are updated every 8 CCB bus clocks. 174 * HID0[SEL_TBCLK] = 0 175 */ 176 ticks = freq / 8; 177out: 178 if (ticks <= 0) 179 panic("Unable to determine timebase frequency!"); 180 181 return (ticks); 182} 183 184static int 185bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 186{ 187 188 cpu = 0; 189 cpuref->cr_cpuid = cpu; 190 cpuref->cr_hwref = cpuref->cr_cpuid; 191 if (bootverbose) 192 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 193 cpu++; 194 195 return (0); 196} 197 198static int 199bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 200{ 201 202 if (cpu >= maxcpu) 203 return (ENOENT); 204 205 cpuref->cr_cpuid = cpu++; 206 cpuref->cr_hwref = cpuref->cr_cpuid; 207 if (bootverbose) 208 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 209 210 return (0); 211} 212 213static int 214bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 215{ 216 217 cpuref->cr_cpuid = mfspr(SPR_PIR); 218 cpuref->cr_hwref = cpuref->cr_cpuid; 219 220 return (0); 221} 222 223static int 224bare_smp_start_cpu(platform_t plat, struct pcpu *pc) 225{ 226#ifdef SMP 227 uint32_t bptr, eebpcr; 228 int timeout; 229 230 eebpcr = ccsr_read4(OCP85XX_EEBPCR); 231 if ((eebpcr & (pc->pc_cpumask << 24)) != 0) { 232 printf("%s: CPU=%d already out of hold-off state!\n", 233 __func__, pc->pc_cpuid); 234 return (ENXIO); 235 } 236 237 ap_pcpu = pc; 238 __asm __volatile("msync; isync"); 239 240 /* 241 * Set BPTR to the physical address of the boot page 242 */ 243 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload; 244 ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000); 245 246 /* 247 * Release AP from hold-off state 248 */ 249 eebpcr |= (pc->pc_cpumask << 24); 250 ccsr_write4(OCP85XX_EEBPCR, eebpcr); 251 __asm __volatile("isync; msync"); 252 253 timeout = 500; 254 while (!pc->pc_awake && timeout--) 255 DELAY(1000); /* wait 1ms */ 256 257 return ((pc->pc_awake) ? 0 : EBUSY); 258#else 259 /* No SMP support */ 260 return (ENXIO); 261#endif 262} 263