1/*- 2 * Copyright (C) 2006-2012 Semihalf 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25/*- 26 * Copyright (C) 2001 Benno Rice 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 1. Redistributions of source code must retain the above copyright 33 * notice, this list of conditions and the following disclaimer. 34 * 2. Redistributions in binary form must reproduce the above copyright 35 * notice, this list of conditions and the following disclaimer in the 36 * documentation and/or other materials provided with the distribution. 37 * 38 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 39 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 40 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 41 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 43 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 44 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 45 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 46 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 47 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 49 */ 50/*- 51 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 52 * Copyright (C) 1995, 1996 TooLs GmbH. 53 * All rights reserved. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 3. All advertising materials mentioning features or use of this software 64 * must display the following acknowledgement: 65 * This product includes software developed by TooLs GmbH. 66 * 4. The name of TooLs GmbH may not be used to endorse or promote products 67 * derived from this software without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 73 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81#include <sys/cdefs.h> 82__FBSDID("$FreeBSD$"); 83 84#include "opt_compat.h" 85#include "opt_ddb.h" 86#include "opt_hwpmc_hooks.h" 87#include "opt_kstack_pages.h" 88#include "opt_platform.h" 89 90#include <sys/cdefs.h> 91#include <sys/types.h> 92#include <sys/param.h> 93#include <sys/proc.h> 94#include <sys/systm.h> 95#include <sys/time.h> 96#include <sys/bio.h> 97#include <sys/buf.h> 98#include <sys/bus.h> 99#include <sys/cons.h> 100#include <sys/cpu.h> 101#include <sys/kdb.h> 102#include <sys/kernel.h> 103#include <sys/lock.h> 104#include <sys/mutex.h> 105#include <sys/rwlock.h> 106#include <sys/sysctl.h> 107#include <sys/exec.h> 108#include <sys/ktr.h> 109#include <sys/syscallsubr.h> 110#include <sys/sysproto.h> 111#include <sys/signalvar.h> 112#include <sys/sysent.h> 113#include <sys/imgact.h> 114#include <sys/msgbuf.h> 115#include <sys/ptrace.h> 116 117#include <vm/vm.h> 118#include <vm/pmap.h> 119#include <vm/vm_page.h> 120#include <vm/vm_object.h> 121#include <vm/vm_pager.h> 122 123#include <machine/cpu.h> 124#include <machine/kdb.h> 125#include <machine/reg.h> 126#include <machine/vmparam.h> 127#include <machine/spr.h> 128#include <machine/hid.h> 129#include <machine/psl.h> 130#include <machine/trap.h> 131#include <machine/md_var.h> 132#include <machine/mmuvar.h> 133#include <machine/sigframe.h> 134#include <machine/machdep.h> 135#include <machine/metadata.h> 136#include <machine/platform.h> 137 138#include <sys/linker.h> 139#include <sys/reboot.h> 140 141#include <contrib/libfdt/libfdt.h> 142#include <dev/fdt/fdt_common.h> 143#include <dev/ofw/openfirm.h> 144 145#if defined(MPC85XX) || defined(QORIQ_DPAA) 146#include <powerpc/mpc85xx/mpc85xx.h> 147#endif 148 149#ifdef DDB 150#include <ddb/ddb.h> 151#endif 152 153#ifdef DEBUG 154#define debugf(fmt, args...) printf(fmt, ##args) 155#else 156#define debugf(fmt, args...) 157#endif 158 159extern unsigned char _etext[]; 160extern unsigned char _edata[]; 161extern unsigned char __bss_start[]; 162extern unsigned char __sbss_start[]; 163extern unsigned char __sbss_end[]; 164extern unsigned char _end[]; 165extern vm_offset_t __endkernel; 166 167/* 168 * Bootinfo is passed to us by legacy loaders. Save the address of the 169 * structure to handle backward compatibility. 170 */ 171uint32_t *bootinfo; 172 173void print_kernel_section_addr(void); 174void print_kenv(void); 175uintptr_t booke_init(u_long, u_long); 176void ivor_setup(void); 177 178extern void *interrupt_vector_base; 179extern void *int_critical_input; 180extern void *int_machine_check; 181extern void *int_data_storage; 182extern void *int_instr_storage; 183extern void *int_external_input; 184extern void *int_alignment; 185extern void *int_fpu; 186extern void *int_program; 187extern void *int_syscall; 188extern void *int_decrementer; 189extern void *int_fixed_interval_timer; 190extern void *int_watchdog; 191extern void *int_data_tlb_error; 192extern void *int_inst_tlb_error; 193extern void *int_debug; 194extern void *int_vec; 195extern void *int_vecast; 196#ifdef HWPMC_HOOKS 197extern void *int_performance_counter; 198#endif 199 200#define SET_TRAP(ivor, handler) \ 201 KASSERT(((uintptr_t)(&handler) & ~0xffffUL) == \ 202 ((uintptr_t)(&interrupt_vector_base) & ~0xffffUL), \ 203 ("Handler " #handler " too far from interrupt vector base")); \ 204 mtspr(ivor, (uintptr_t)(&handler) & 0xffffUL); 205 206uintptr_t powerpc_init(vm_offset_t fdt, vm_offset_t, vm_offset_t, void *mdp); 207void booke_cpu_init(void); 208 209void 210booke_cpu_init(void) 211{ 212 213 cpu_features |= PPC_FEATURE_BOOKE; 214 215 pmap_mmu_install(MMU_TYPE_BOOKE, BUS_PROBE_GENERIC); 216} 217 218void 219ivor_setup(void) 220{ 221 222 mtspr(SPR_IVPR, ((uintptr_t)&interrupt_vector_base) & 0xffff0000); 223 224 SET_TRAP(SPR_IVOR0, int_critical_input); 225 SET_TRAP(SPR_IVOR1, int_machine_check); 226 SET_TRAP(SPR_IVOR2, int_data_storage); 227 SET_TRAP(SPR_IVOR3, int_instr_storage); 228 SET_TRAP(SPR_IVOR4, int_external_input); 229 SET_TRAP(SPR_IVOR5, int_alignment); 230 SET_TRAP(SPR_IVOR6, int_program); 231 SET_TRAP(SPR_IVOR8, int_syscall); 232 SET_TRAP(SPR_IVOR10, int_decrementer); 233 SET_TRAP(SPR_IVOR11, int_fixed_interval_timer); 234 SET_TRAP(SPR_IVOR12, int_watchdog); 235 SET_TRAP(SPR_IVOR13, int_data_tlb_error); 236 SET_TRAP(SPR_IVOR14, int_inst_tlb_error); 237 SET_TRAP(SPR_IVOR15, int_debug); 238#ifdef HWPMC_HOOKS 239 SET_TRAP(SPR_IVOR35, int_performance_counter); 240#endif 241 switch ((mfpvr() >> 16) & 0xffff) { 242 case FSL_E6500: 243 SET_TRAP(SPR_IVOR32, int_vec); 244 SET_TRAP(SPR_IVOR33, int_vecast); 245 /* FALLTHROUGH */ 246 case FSL_E500mc: 247 case FSL_E5500: 248 SET_TRAP(SPR_IVOR7, int_fpu); 249 } 250} 251 252static int 253booke_check_for_fdt(uint32_t arg1, vm_offset_t *dtbp) 254{ 255 void *ptr; 256 257 if (arg1 % 8 != 0) 258 return (-1); 259 260 ptr = (void *)pmap_early_io_map(arg1, PAGE_SIZE); 261 if (fdt_check_header(ptr) != 0) 262 return (-1); 263 264 *dtbp = (vm_offset_t)ptr; 265 266 return (0); 267} 268 269uintptr_t 270booke_init(u_long arg1, u_long arg2) 271{ 272 uintptr_t ret; 273 void *mdp; 274 vm_offset_t dtbp, end; 275 276 end = (uintptr_t)_end; 277 dtbp = (vm_offset_t)NULL; 278 279 /* Set up TLB initially */ 280 bootinfo = NULL; 281 bzero(__sbss_start, __sbss_end - __sbss_start); 282 bzero(__bss_start, _end - __bss_start); 283 tlb1_init(); 284 285 /* 286 * Handle the various ways we can get loaded and started: 287 * - FreeBSD's loader passes the pointer to the metadata 288 * in arg1, with arg2 undefined. arg1 has a value that's 289 * relative to the kernel's link address (i.e. larger 290 * than 0xc0000000). 291 * - Juniper's loader passes the metadata pointer in arg2 292 * and sets arg1 to zero. This is to signal that the 293 * loader maps the kernel and starts it at its link 294 * address (unlike the FreeBSD loader). 295 * - U-Boot passes the standard argc and argv parameters 296 * in arg1 and arg2 (resp). arg1 is between 1 and some 297 * relatively small number, such as 64K. arg2 is the 298 * physical address of the argv vector. 299 * - ePAPR loaders pass an FDT blob in r3 (arg1) and the magic hex 300 * string 0x45504150 ('EPAP') in r6 (which has been lost by now). 301 * r4 (arg2) is supposed to be set to zero, but is not always. 302 */ 303 304 if (arg1 == 0) /* Juniper loader */ 305 mdp = (void *)arg2; 306 else if (booke_check_for_fdt(arg1, &dtbp) == 0) { /* ePAPR */ 307 end = roundup(end, 8); 308 memmove((void *)end, (void *)dtbp, fdt_totalsize((void *)dtbp)); 309 dtbp = end; 310 end += fdt_totalsize((void *)dtbp); 311 __endkernel = end; 312 mdp = NULL; 313 } else if (arg1 > (uintptr_t)btext) /* FreeBSD loader */ 314 mdp = (void *)arg1; 315 else /* U-Boot */ 316 mdp = NULL; 317 318 /* Default to 32 byte cache line size. */ 319 switch ((mfpvr()) >> 16) { 320 case FSL_E500mc: 321 case FSL_E5500: 322 case FSL_E6500: 323 cacheline_size = 64; 324 break; 325 } 326 327 ret = powerpc_init(dtbp, 0, 0, mdp); 328 329 /* Enable caches */ 330 booke_enable_l1_cache(); 331 booke_enable_l2_cache(); 332 333 booke_enable_bpred(); 334 335 return (ret); 336} 337 338#define RES_GRANULE 32 339extern uint32_t tlb0_miss_locks[]; 340 341/* Initialise a struct pcpu. */ 342void 343cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz) 344{ 345 346 pcpu->pc_tid_next = TID_MIN; 347 348#ifdef SMP 349 uint32_t *ptr; 350 int words_per_gran = RES_GRANULE / sizeof(uint32_t); 351 352 ptr = &tlb0_miss_locks[cpuid * words_per_gran]; 353 pcpu->pc_booke_tlb_lock = ptr; 354 *ptr = TLB_UNLOCKED; 355 *(ptr + 1) = 0; /* recurse counter */ 356#endif 357} 358 359/* Shutdown the CPU as much as possible. */ 360void 361cpu_halt(void) 362{ 363 364 mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE)); 365 while (1) 366 ; 367} 368 369int 370ptrace_single_step(struct thread *td) 371{ 372 struct trapframe *tf; 373 374 tf = td->td_frame; 375 tf->srr1 |= PSL_DE; 376 tf->cpu.booke.dbcr0 |= (DBCR0_IDM | DBCR0_IC); 377 return (0); 378} 379 380int 381ptrace_clear_single_step(struct thread *td) 382{ 383 struct trapframe *tf; 384 385 tf = td->td_frame; 386 tf->srr1 &= ~PSL_DE; 387 tf->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC); 388 return (0); 389} 390 391void 392kdb_cpu_clear_singlestep(void) 393{ 394 register_t r; 395 396 r = mfspr(SPR_DBCR0); 397 mtspr(SPR_DBCR0, r & ~DBCR0_IC); 398 kdb_frame->srr1 &= ~PSL_DE; 399} 400 401void 402kdb_cpu_set_singlestep(void) 403{ 404 register_t r; 405 406 r = mfspr(SPR_DBCR0); 407 mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM); 408 kdb_frame->srr1 |= PSL_DE; 409} 410 411