trap_subr32.S revision 275268
1/* $FreeBSD: head/sys/powerpc/aim/trap_subr32.S 275268 2014-11-29 20:54:33Z jhibbits $ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* 43 * Save/restore segment registers 44 */ 45#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46 lwz sr,1*4(pmap); mtsr 1,sr; \ 47 lwz sr,2*4(pmap); mtsr 2,sr; \ 48 lwz sr,3*4(pmap); mtsr 3,sr; \ 49 lwz sr,4*4(pmap); mtsr 4,sr; \ 50 lwz sr,5*4(pmap); mtsr 5,sr; \ 51 lwz sr,6*4(pmap); mtsr 6,sr; \ 52 lwz sr,7*4(pmap); mtsr 7,sr; \ 53 lwz sr,8*4(pmap); mtsr 8,sr; \ 54 lwz sr,9*4(pmap); mtsr 9,sr; \ 55 lwz sr,10*4(pmap); mtsr 10,sr; \ 56 lwz sr,11*4(pmap); mtsr 11,sr; \ 57 /* Skip segment 12 (USER_SR), which is restored differently */ \ 58 lwz sr,13*4(pmap); mtsr 13,sr; \ 59 lwz sr,14*4(pmap); mtsr 14,sr; \ 60 lwz sr,15*4(pmap); mtsr 15,sr; isync; 61 62/* 63 * User SRs are loaded through a pointer to the current pmap. 64 */ 65#define RESTORE_USER_SRS(pmap,sr) \ 66 GET_CPUINFO(pmap); \ 67 lwz pmap,PC_CURPMAP(pmap); \ 68 lwzu sr,PM_SR(pmap); \ 69 RESTORE_SRS(pmap,sr) \ 70 /* Restore SR 12 */ \ 71 lwz sr,12*4(pmap); mtsr 12,sr 72 73/* 74 * Kernel SRs are loaded directly from kernel_pmap_ 75 */ 76#define RESTORE_KERN_SRS(pmap,sr) \ 77 lis pmap,CNAME(kernel_pmap_store)@ha; \ 78 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \ 79 RESTORE_SRS(pmap,sr) 80 81/* 82 * FRAME_SETUP assumes: 83 * SPRG1 SP (1) 84 * SPRG3 trap type 85 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 86 * r28 LR 87 * r29 CR 88 * r30 scratch 89 * r31 scratch 90 * r1 kernel stack 91 * SRR0/1 as at start of trap 92 */ 93#define FRAME_SETUP(savearea) \ 94/* Have to enable translation to allow access of kernel stack: */ \ 95 GET_CPUINFO(%r31); \ 96 mfsrr0 %r30; \ 97 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 98 mfsrr1 %r30; \ 99 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 100 mfmsr %r30; \ 101 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 102 mtmsr %r30; /* stack can now be accessed */ \ 103 isync; \ 104 mfsprg1 %r31; /* get saved SP */ \ 105 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 106 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 107 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 108 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 109 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 110 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 111 GET_CPUINFO(%r2); \ 112 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 113 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 114 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 115 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 116 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 117 stw %r4, FRAME_4+8(%r1); \ 118 stw %r5, FRAME_5+8(%r1); \ 119 stw %r6, FRAME_6+8(%r1); \ 120 stw %r7, FRAME_7+8(%r1); \ 121 stw %r8, FRAME_8+8(%r1); \ 122 stw %r9, FRAME_9+8(%r1); \ 123 stw %r10, FRAME_10+8(%r1); \ 124 stw %r11, FRAME_11+8(%r1); \ 125 stw %r12, FRAME_12+8(%r1); \ 126 stw %r13, FRAME_13+8(%r1); \ 127 stw %r14, FRAME_14+8(%r1); \ 128 stw %r15, FRAME_15+8(%r1); \ 129 stw %r16, FRAME_16+8(%r1); \ 130 stw %r17, FRAME_17+8(%r1); \ 131 stw %r18, FRAME_18+8(%r1); \ 132 stw %r19, FRAME_19+8(%r1); \ 133 stw %r20, FRAME_20+8(%r1); \ 134 stw %r21, FRAME_21+8(%r1); \ 135 stw %r22, FRAME_22+8(%r1); \ 136 stw %r23, FRAME_23+8(%r1); \ 137 stw %r24, FRAME_24+8(%r1); \ 138 stw %r25, FRAME_25+8(%r1); \ 139 stw %r26, FRAME_26+8(%r1); \ 140 stw %r27, FRAME_27+8(%r1); \ 141 stw %r28, FRAME_28+8(%r1); \ 142 stw %r29, FRAME_29+8(%r1); \ 143 stw %r30, FRAME_30+8(%r1); \ 144 stw %r31, FRAME_31+8(%r1); \ 145 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 146 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 147 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 148 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 149 mfxer %r3; \ 150 mfctr %r4; \ 151 mfsprg3 %r5; \ 152 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 153 stw %r4, FRAME_CTR+8(1); \ 154 stw %r5, FRAME_EXC+8(1); \ 155 stw %r28,FRAME_AIM_DAR+8(1); \ 156 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 157 stw %r30,FRAME_SRR0+8(1); \ 158 stw %r31,FRAME_SRR1+8(1); \ 159 lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */ 160 161#define FRAME_LEAVE(savearea) \ 162/* Disable exceptions: */ \ 163 mfmsr %r2; \ 164 andi. %r2,%r2,~PSL_EE@l; \ 165 mtmsr %r2; \ 166 isync; \ 167/* Now restore regs: */ \ 168 lwz %r2,FRAME_SRR0+8(%r1); \ 169 lwz %r3,FRAME_SRR1+8(%r1); \ 170 lwz %r4,FRAME_CTR+8(%r1); \ 171 lwz %r5,FRAME_XER+8(%r1); \ 172 lwz %r6,FRAME_LR+8(%r1); \ 173 GET_CPUINFO(%r7); \ 174 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 175 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 176 lwz %r7,FRAME_CR+8(%r1); \ 177 mtctr %r4; \ 178 mtxer %r5; \ 179 mtlr %r6; \ 180 mtsprg1 %r7; /* save cr */ \ 181 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 182 lwz %r30,FRAME_30+8(%r1); \ 183 lwz %r29,FRAME_29+8(%r1); \ 184 lwz %r28,FRAME_28+8(%r1); \ 185 lwz %r27,FRAME_27+8(%r1); \ 186 lwz %r26,FRAME_26+8(%r1); \ 187 lwz %r25,FRAME_25+8(%r1); \ 188 lwz %r24,FRAME_24+8(%r1); \ 189 lwz %r23,FRAME_23+8(%r1); \ 190 lwz %r22,FRAME_22+8(%r1); \ 191 lwz %r21,FRAME_21+8(%r1); \ 192 lwz %r20,FRAME_20+8(%r1); \ 193 lwz %r19,FRAME_19+8(%r1); \ 194 lwz %r18,FRAME_18+8(%r1); \ 195 lwz %r17,FRAME_17+8(%r1); \ 196 lwz %r16,FRAME_16+8(%r1); \ 197 lwz %r15,FRAME_15+8(%r1); \ 198 lwz %r14,FRAME_14+8(%r1); \ 199 lwz %r13,FRAME_13+8(%r1); \ 200 lwz %r12,FRAME_12+8(%r1); \ 201 lwz %r11,FRAME_11+8(%r1); \ 202 lwz %r10,FRAME_10+8(%r1); \ 203 lwz %r9, FRAME_9+8(%r1); \ 204 lwz %r8, FRAME_8+8(%r1); \ 205 lwz %r7, FRAME_7+8(%r1); \ 206 lwz %r6, FRAME_6+8(%r1); \ 207 lwz %r5, FRAME_5+8(%r1); \ 208 lwz %r4, FRAME_4+8(%r1); \ 209 lwz %r3, FRAME_3+8(%r1); \ 210 lwz %r2, FRAME_2+8(%r1); \ 211 lwz %r0, FRAME_0+8(%r1); \ 212 lwz %r1, FRAME_1+8(%r1); \ 213/* Can't touch %r1 from here on */ \ 214 mtsprg2 %r2; /* save r2 & r3 */ \ 215 mtsprg3 %r3; \ 216/* Disable translation, machine check and recoverability: */ \ 217 mfmsr %r2; \ 218 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 219 mtmsr %r2; \ 220 isync; \ 221/* Decide whether we return to user mode: */ \ 222 GET_CPUINFO(%r2); \ 223 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 224 mtcr %r3; \ 225 bf 17,1f; /* branch if PSL_PR is false */ \ 226/* Restore user SRs */ \ 227 RESTORE_USER_SRS(%r2,%r3); \ 2281: mfsprg1 %r2; /* restore cr */ \ 229 mtcr %r2; \ 230 GET_CPUINFO(%r2); \ 231 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 232 mtsrr0 %r3; \ 233 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 234 \ 235 /* Make sure HV bit of MSR propagated to SRR1 */ \ 236 mfmsr %r2; \ 237 or %r3,%r2,%r3; \ 238 \ 239 mtsrr1 %r3; \ 240 mfsprg2 %r2; /* restore r2 & r3 */ \ 241 mfsprg3 %r3 242 243#ifdef KDTRACE_HOOKS 244 .data 245 .globl dtrace_invop_calltrap_addr 246 .align 4 247 .type dtrace_invop_calltrap_addr, @object 248 .size dtrace_invop_calltrap_addr, 4 249dtrace_invop_calltrap_addr: 250 .word 0 251 .word 0 252 253 .text 254#endif 255 256/* 257 * The next two routines are 64-bit glue code. The first is used to test if 258 * we are on a 64-bit system. By copying it to the illegal instruction 259 * handler, we can test for 64-bit mode by trying to execute a 64-bit 260 * instruction and seeing what happens. The second gets copied in front 261 * of all the other handlers to restore 32-bit bridge mode when traps 262 * are taken. 263 */ 264 265/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 266 267 .globl CNAME(testppc64),CNAME(testppc64size) 268CNAME(testppc64): 269 mtsprg1 %r31 270 mfsrr0 %r31 271 addi %r31, %r31, 4 272 mtsrr0 %r31 273 274 li %r31, 0 275 mtsprg2 %r31 276 mfsprg1 %r31 277 278 rfi 279CNAME(testppc64size) = .-CNAME(testppc64) 280 281 282/* 64-bit bridge mode restore snippet. Gets copied in front of everything else 283 * on 64-bit systems. */ 284 285 .globl CNAME(restorebridge),CNAME(restorebridgesize) 286CNAME(restorebridge): 287 mtsprg1 %r31 288 mfmsr %r31 289 clrldi %r31,%r31,1 290 mtmsrd %r31 291 mfsprg1 %r31 292 isync 293CNAME(restorebridgesize) = .-CNAME(restorebridge) 294 295/* 296 * Processor reset exception handler. These are typically 297 * the first instructions the processor executes after a 298 * software reset. We do this in two bits so that we are 299 * not still hanging around in the trap handling region 300 * once the MMU is turned on. 301 */ 302 .globl CNAME(rstcode), CNAME(rstsize) 303CNAME(rstcode): 304 ba cpu_reset 305CNAME(rstsize) = . - CNAME(rstcode) 306 307cpu_reset: 308 bl 1f 309 310 .space 124 311 3121: 313 mflr %r1 314 addi %r1,%r1,(124-16)@l 315 316 bla CNAME(cpudep_ap_early_bootstrap) 317 lis %r3,1@l 318 bla CNAME(pmap_cpu_bootstrap) 319 bla CNAME(cpudep_ap_bootstrap) 320 mr %r1,%r3 321 bla CNAME(cpudep_ap_setup) 322 GET_CPUINFO(%r5) 323 lwz %r3,(PC_RESTORE)(%r5) 324 cmplwi %cr0,%r3,0 325 beq %cr0,2f 326 li %r4, 1 327 b CNAME(longjmp) 3282: 329#ifdef SMP 330 bla CNAME(machdep_ap_bootstrap) 331#endif 332 333 /* Should not be reached */ 3349: 335 b 9b 336 337/* 338 * This code gets copied to all the trap vectors 339 * (except ISI/DSI, ALI, and the interrupts) 340 */ 341 342 .globl CNAME(trapcode),CNAME(trapsize) 343CNAME(trapcode): 344 mtsprg1 %r1 /* save SP */ 345 mflr %r1 /* Save the old LR in r1 */ 346 mtsprg2 %r1 /* And then in SPRG2 */ 347 li %r1, 0x20 /* How to get the vector from LR */ 348 bla generictrap /* LR & SPRG3 is exception # */ 349CNAME(trapsize) = .-CNAME(trapcode) 350 351/* 352 * 64-bit version of trapcode. Identical, except it calls generictrap64. 353 */ 354 .globl CNAME(trapcode64) 355CNAME(trapcode64): 356 mtsprg1 %r1 /* save SP */ 357 mflr %r1 /* Save the old LR in r1 */ 358 mtsprg2 %r1 /* And then in SPRG2 */ 359 li %r1, 0x20 /* How to get the vector from LR */ 360 bla generictrap64 /* LR & SPRG3 is exception # */ 361 362/* 363 * For ALI: has to save DSISR and DAR 364 */ 365 .globl CNAME(alitrap),CNAME(alisize) 366CNAME(alitrap): 367 mtsprg1 %r1 /* save SP */ 368 GET_CPUINFO(%r1) 369 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 370 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 371 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 372 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 373 mfdar %r30 374 mfdsisr %r31 375 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 376 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 377 mfsprg1 %r1 /* restore SP, in case of branch */ 378 mflr %r28 /* save LR */ 379 mfcr %r29 /* save CR */ 380 381 /* Put our exception vector in SPRG3 */ 382 li %r31, EXC_ALI 383 mtsprg3 %r31 384 385 /* Test whether we already had PR set */ 386 mfsrr1 %r31 387 mtcr %r31 388 bla s_trap 389CNAME(alisize) = .-CNAME(alitrap) 390 391/* 392 * G2 specific: instuction TLB miss. 393 */ 394 .globl CNAME(imisstrap),CNAME(imisssize) 395CNAME(imisstrap): 396 mfspr %r2, SPR_HASH1 /* get first pointer */ 397 addi %r1, 0, 8 /* load 8 for counter */ 398 mfctr %r0 /* save counter */ 399 mfspr %r3, SPR_ICMP /* get first compare value */ 400 addi %r2, %r2, -8 /* pre dec the pointer */ 401im0: 402 mtctr %r1 /* load counter */ 403im1: 404 lwzu %r1, 8(%r2) /* get next pte */ 405 cmp 0, %r1, %r3 /* see if found pte */ 406 bdnzf 2, im1 /* dec count br if cmp ne and if 407 * count not zero */ 408 bne instr_sec_hash /* if not found set up second hash 409 * or exit */ 410 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 411 andi. %r3, %r1, 8 /* check G bit */ 412 bne do_isi_prot /* if guarded, take an ISI */ 413 mtctr %r0 /* restore counter */ 414 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ 415 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 416 mtcrf 0x80, %r3 /* restore CR0 */ 417 mtspr SPR_RPA, %r1 /* set the pte */ 418 ori %r1, %r1, 0x100 /* set reference bit */ 419 srwi %r1, %r1, 8 /* get byte 7 of pte */ 420 tlbli %r0 /* load the itlb */ 421 stb %r1, +6(%r2) /* update page table */ 422 rfi /* return to executing program */ 423 424instr_sec_hash: 425 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 426 bne do_isi /* if so, go to ISI interrupt */ 427 mfspr %r2, SPR_HASH2 /* get the second pointer */ 428 ori %r3, %r3, 0x0040 /* change the compare value */ 429 addi %r1, %r0, 8 /* load 8 for counter */ 430 addi %r2, %r2, -8 /* pre dec for update on load */ 431 b im0 /* try second hash */ 432 433/* Create a faked ISI interrupt as the address was not found */ 434do_isi_prot: 435 mfspr %r3, SPR_SRR1 /* get srr1 */ 436 andi. %r2, %r3, 0xffff /* clean upper srr1 */ 437 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot 438 * violation */ 439 b isi1 440do_isi: 441 mfspr %r3, SPR_SRR1 /* get srr1 */ 442 andi. %r2, %r3, 0xffff /* clean srr1 */ 443 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte 444 * not found */ 445isi1: 446 mtctr %r0 /* restore counter */ 447 mtspr SPR_SRR1, %r2 /* set srr1 */ 448 mfmsr %r0 /* get msr */ 449 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 450 mtcrf 0x80, %r3 /* restore CR0 */ 451 mtmsr %r0 /* flip back to the native gprs */ 452 ba EXC_ISI /* go to instr. access interrupt */ 453 454CNAME(imisssize) = .-CNAME(imisstrap) 455 456/* 457 * G2 specific: data load TLB miss. 458 */ 459 .globl CNAME(dlmisstrap),CNAME(dlmisssize) 460CNAME(dlmisstrap): 461 mfspr %r2, SPR_HASH1 /* get first pointer */ 462 addi %r1, 0, 8 /* load 8 for counter */ 463 mfctr %r0 /* save counter */ 464 mfspr %r3, SPR_DCMP /* get first compare value */ 465 addi %r2, %r2, -8 /* pre dec the pointer */ 466dm0: 467 mtctr %r1 /* load counter */ 468dm1: 469 lwzu %r1, 8(%r2) /* get next pte */ 470 cmp 0, 0, %r1, %r3 /* see if found pte */ 471 bdnzf 2, dm1 /* dec count br if cmp ne and if 472 * count not zero */ 473 bne data_sec_hash /* if not found set up second hash 474 * or exit */ 475 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 476 mtctr %r0 /* restore counter */ 477 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 478 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 479 mtcrf 0x80, %r3 /* restore CR0 */ 480 mtspr SPR_RPA, %r1 /* set the pte */ 481 ori %r1, %r1, 0x100 /* set reference bit */ 482 srwi %r1, %r1, 8 /* get byte 7 of pte */ 483 tlbld %r0 /* load the dtlb */ 484 stb %r1, +6(%r2) /* update page table */ 485 rfi /* return to executing program */ 486 487data_sec_hash: 488 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 489 bne do_dsi /* if so, go to DSI interrupt */ 490 mfspr %r2, SPR_HASH2 /* get the second pointer */ 491 ori %r3, %r3, 0x0040 /* change the compare value */ 492 addi %r1, 0, 8 /* load 8 for counter */ 493 addi %r2, %r2, -8 /* pre dec for update on load */ 494 b dm0 /* try second hash */ 495 496CNAME(dlmisssize) = .-CNAME(dlmisstrap) 497 498/* 499 * G2 specific: data store TLB miss. 500 */ 501 .globl CNAME(dsmisstrap),CNAME(dsmisssize) 502CNAME(dsmisstrap): 503 mfspr %r2, SPR_HASH1 /* get first pointer */ 504 addi %r1, 0, 8 /* load 8 for counter */ 505 mfctr %r0 /* save counter */ 506 mfspr %r3, SPR_DCMP /* get first compare value */ 507 addi %r2, %r2, -8 /* pre dec the pointer */ 508ds0: 509 mtctr %r1 /* load counter */ 510ds1: 511 lwzu %r1, 8(%r2) /* get next pte */ 512 cmp 0, 0, %r1, %r3 /* see if found pte */ 513 bdnzf 2, ds1 /* dec count br if cmp ne and if 514 * count not zero */ 515 bne data_store_sec_hash /* if not found set up second hash 516 * or exit */ 517 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 518 andi. %r3, %r1, 0x80 /* check the C-bit */ 519 beq data_store_chk_prot /* if (C==0) 520 * go check protection modes */ 521ds2: 522 mtctr %r0 /* restore counter */ 523 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 524 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 525 mtcrf 0x80, %r3 /* restore CR0 */ 526 mtspr SPR_RPA, %r1 /* set the pte */ 527 tlbld %r0 /* load the dtlb */ 528 rfi /* return to executing program */ 529 530data_store_sec_hash: 531 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 532 bne do_dsi /* if so, go to DSI interrupt */ 533 mfspr %r2, SPR_HASH2 /* get the second pointer */ 534 ori %r3, %r3, 0x0040 /* change the compare value */ 535 addi %r1, 0, 8 /* load 8 for counter */ 536 addi %r2, %r2, -8 /* pre dec for update on load */ 537 b ds0 /* try second hash */ 538 539/* Check the protection before setting PTE(c-bit) */ 540data_store_chk_prot: 541 rlwinm. %r3,%r1,30,0,1 /* test PP */ 542 bge- chk0 /* if (PP == 00 or PP == 01) 543 * goto chk0: */ 544 andi. %r3, %r1, 1 /* test PP[0] */ 545 beq+ chk2 /* return if PP[0] == 0 */ 546 b do_dsi_prot /* else DSIp */ 547chk0: 548 mfspr %r3,SPR_SRR1 /* get old msr */ 549 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ 550 beq chk2 /* if (KEY==0) goto chk2: */ 551 b do_dsi_prot /* else do_dsi_prot */ 552chk2: 553 ori %r1, %r1, 0x180 /* set reference and change bit */ 554 sth %r1, 6(%r2) /* update page table */ 555 b ds2 /* and back we go */ 556 557/* Create a faked DSI interrupt as the address was not found */ 558do_dsi: 559 mfspr %r3, SPR_SRR1 /* get srr1 */ 560 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 561 * load/store, zero rest */ 562 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte 563 * not found */ 564 b dsi1 565 566do_dsi_prot: 567 mfspr %r3, SPR_SRR1 /* get srr1 */ 568 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 569 *load/store, zero rest */ 570 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot 571 * violation */ 572 573dsi1: 574 mtctr %r0 /* restore counter */ 575 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ 576 mtspr SPR_SRR1, %r2 /* set srr1 */ 577 mtspr SPR_DSISR, %r1 /* load the dsisr */ 578 mfspr %r1, SPR_DMISS /* get miss address */ 579 rlwinm. %r2,%r2,0,31,31 /* test LE bit */ 580 beq dsi2 /* if little endian then: */ 581 xor %r1, %r1, 0x07 /* de-mung the data address */ 582dsi2: 583 mtspr SPR_DAR, %r1 /* put in dar */ 584 mfmsr %r0 /* get msr */ 585 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 586 mtcrf 0x80, %r3 /* restore CR0 */ 587 mtmsr %r0 /* flip back to the native gprs */ 588 ba EXC_DSI /* branch to DSI interrupt */ 589 590CNAME(dsmisssize) = .-CNAME(dsmisstrap) 591 592/* 593 * Similar to the above for DSI 594 * Has to handle BAT spills 595 * and standard pagetable spills 596 */ 597 .globl CNAME(dsitrap),CNAME(dsisize) 598CNAME(dsitrap): 599 mtsprg1 %r1 /* save SP */ 600 GET_CPUINFO(%r1) 601 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 602 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 603 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 604 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 605 mfsprg1 %r1 /* restore SP */ 606 mfcr %r29 /* save CR */ 607 mfxer %r30 /* save XER */ 608 mtsprg2 %r30 /* in SPRG2 */ 609 mfsrr1 %r31 /* test kernel mode */ 610 mtcr %r31 611 bt 17,1f /* branch if PSL_PR is set */ 612 mfdar %r31 /* get fault address */ 613 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 614 615 /* get batu */ 616 addis %r31,%r31,CNAME(battable)@ha 617 lwz %r30,CNAME(battable)@l(31) 618 mtcr %r30 619 bf 30,1f /* branch if supervisor valid is 620 false */ 621 /* get batl */ 622 lwz %r31,CNAME(battable)+4@l(31) 623/* We randomly use the highest two bat registers here */ 624 mftb %r28 625 andi. %r28,%r28,1 626 bne 2f 627 mtdbatu 2,%r30 628 mtdbatl 2,%r31 629 b 3f 6302: 631 mtdbatu 3,%r30 632 mtdbatl 3,%r31 6333: 634 mfsprg2 %r30 /* restore XER */ 635 mtxer %r30 636 mtcr %r29 /* restore CR */ 637 mtsprg1 %r1 638 GET_CPUINFO(%r1) 639 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 640 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 641 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 642 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 643 mfsprg1 %r1 644 rfi /* return to trapped code */ 6451: 646 mflr %r28 /* save LR (SP already saved) */ 647 bla disitrap 648CNAME(dsisize) = .-CNAME(dsitrap) 649 650/* 651 * Preamble code for DSI/ISI traps 652 */ 653disitrap: 654 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 655 mflr %r1 656 andi. %r1,%r1,0xff00 657 mtsprg3 %r1 658 659 GET_CPUINFO(%r1) 660 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 661 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 662 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 663 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 664 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 665 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 666 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 667 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 668 mfdar %r30 669 mfdsisr %r31 670 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 671 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 672 673#ifdef KDB 674 /* Try to detect a kernel stack overflow */ 675 mfsrr1 %r31 676 mtcr %r31 677 bt 17,realtrap /* branch is user mode */ 678 mfsprg1 %r31 /* get old SP */ 679 clrrwi %r31,%r31,12 /* Round SP down to nearest page */ 680 sub. %r30,%r31,%r30 /* SP - DAR */ 681 bge 1f 682 neg %r30,%r30 /* modulo value */ 6831: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 684 bge %cr0,realtrap /* no, too far away. */ 685 686 /* Now convert this DSI into a DDB trap. */ 687 GET_CPUINFO(%r1) 688 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 689 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 690 lwz %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 691 stw %r31,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 692 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 693 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 694 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 695 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 696 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 697 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 698 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 699 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 700 b dbtrap 701#endif 702 703 /* XXX need stack probe here */ 704realtrap: 705/* Test whether we already had PR set */ 706 mfsrr1 %r1 707 mtcr %r1 708 mfsprg1 %r1 /* restore SP (might have been 709 overwritten) */ 710 bf 17,k_trap /* branch if PSL_PR is false */ 711 GET_CPUINFO(%r1) 712 lwz %r1,PC_CURPCB(%r1) 713 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 714 ba s_trap 715 716/* 717 * generictrap does some standard setup for trap handling to minimize 718 * the code that need be installed in the actual vectors. It expects 719 * the following conditions. 720 * 721 * R1 - Trap vector = LR & (0xff00 | R1) 722 * SPRG1 - Original R1 contents 723 * SPRG2 - Original LR 724 */ 725 726generictrap64: 727 mtsprg3 %r31 728 mfmsr %r31 729 clrldi %r31,%r31,1 730 mtmsrd %r31 731 mfsprg3 %r31 732 isync 733 734generictrap: 735 /* Save R1 for computing the exception vector */ 736 mtsprg3 %r1 737 738 /* Save interesting registers */ 739 GET_CPUINFO(%r1) 740 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 741 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 742 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 743 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 744 mfsprg1 %r1 /* restore SP, in case of branch */ 745 mfsprg2 %r28 /* save LR */ 746 mfcr %r29 /* save CR */ 747 748 /* Compute the exception vector from the link register */ 749 mfsprg3 %r31 750 ori %r31,%r31,0xff00 751 mflr %r30 752 and %r30,%r30,%r31 753 mtsprg3 %r30 754 755 /* Test whether we already had PR set */ 756 mfsrr1 %r31 757 mtcr %r31 758 759s_trap: 760 bf 17,k_trap /* branch if PSL_PR is false */ 761 GET_CPUINFO(%r1) 762u_trap: 763 lwz %r1,PC_CURPCB(%r1) 764 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 765 766/* 767 * Now the common trap catching code. 768 */ 769k_trap: 770 FRAME_SETUP(PC_TEMPSAVE) 771 /* Restore USER_SR */ 772 GET_CPUINFO(%r30) 773 lwz %r30,PC_CURPCB(%r30) 774 lwz %r30,PCB_AIM_USR_VSID(%r30) 775 mtsr USER_SR,%r30; sync; isync 776/* Call C interrupt dispatcher: */ 777trapagain: 778 addi %r3,%r1,8 779 bl CNAME(powerpc_interrupt) 780 .globl CNAME(trapexit) /* backtrace code sentinel */ 781CNAME(trapexit): 782 783/* Disable interrupts: */ 784 mfmsr %r3 785 andi. %r3,%r3,~PSL_EE@l 786 mtmsr %r3 787/* Test AST pending: */ 788 lwz %r5,FRAME_SRR1+8(%r1) 789 mtcr %r5 790 bf 17,1f /* branch if PSL_PR is false */ 791 792 GET_CPUINFO(%r3) /* get per-CPU pointer */ 793 lwz %r4, TD_FLAGS(%r2) /* get thread flags value 794 * (r2 is curthread) */ 795 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 796 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 797 and. %r4,%r4,%r5 798 beq 1f 799 mfmsr %r3 /* re-enable interrupts */ 800 ori %r3,%r3,PSL_EE@l 801 mtmsr %r3 802 isync 803 addi %r3,%r1,8 804 bl CNAME(ast) 805 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 806CNAME(asttrapexit): 807 b trapexit /* test ast ret value ? */ 8081: 809 FRAME_LEAVE(PC_TEMPSAVE) 810 811 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 812CNAME(rfi_patch1): 813 rfi 814 815 .globl CNAME(rfid_patch) 816CNAME(rfid_patch): 817 rfid 818 819#if defined(KDB) 820/* 821 * Deliberate entry to dbtrap 822 */ 823 .globl CNAME(breakpoint) 824CNAME(breakpoint): 825 mtsprg1 %r1 826 mfmsr %r3 827 mtsrr1 %r3 828 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 829 mtmsr %r3 /* disable interrupts */ 830 isync 831 GET_CPUINFO(%r3) 832 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 833 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 834 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 835 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 836 mflr %r28 837 li %r29,EXC_BPT 838 mtlr %r29 839 mfcr %r29 840 mtsrr0 %r28 841 842/* 843 * Now the kdb trap catching code. 844 */ 845dbtrap: 846 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 847 mflr %r1 848 andi. %r1,%r1,0xff00 849 mtsprg3 %r1 850 851 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */ 852 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l 853 854 FRAME_SETUP(PC_DBSAVE) 855/* Call C trap code: */ 856 addi %r3,%r1,8 857 bl CNAME(db_trap_glue) 858 or. %r3,%r3,%r3 859 bne dbleave 860/* This wasn't for KDB, so switch to real trap: */ 861 lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 862 GET_CPUINFO(%r4) 863 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 864 FRAME_LEAVE(PC_DBSAVE) 865 mtsprg1 %r1 /* prepare for entrance to realtrap */ 866 GET_CPUINFO(%r1) 867 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 868 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 869 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 870 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 871 mflr %r28 872 mfcr %r29 873 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 874 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 875 mfsprg1 %r1 876 b realtrap 877dbleave: 878 FRAME_LEAVE(PC_DBSAVE) 879 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 880CNAME(rfi_patch2): 881 rfi 882 883/* 884 * In case of KDB we want a separate trap catcher for it 885 */ 886 .globl CNAME(dblow),CNAME(dbsize) 887CNAME(dblow): 888 mtsprg1 %r1 /* save SP */ 889 mtsprg2 %r29 /* save r29 */ 890 mfcr %r29 /* save CR in r29 */ 891 mfsrr1 %r1 892 mtcr %r1 893 bf 17,1f /* branch if privileged */ 894 /* Unprivileged case */ 895 mtcr %r29 /* put the condition register back */ 896 mfsprg2 %r29 /* ... and r29 */ 897 mflr %r1 /* save LR */ 898 mtsprg2 %r1 /* And then in SPRG2 */ 899 li %r1, 0 /* How to get the vector from LR */ 900 901 bla generictrap /* and we look like a generic trap */ 9021: 903 /* Privileged, so drop to KDB */ 904 GET_CPUINFO(%r1) 905 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 906 mfsprg2 %r28 /* r29 holds cr... */ 907 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 908 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 909 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 910 mflr %r28 /* save LR */ 911 bla dbtrap 912CNAME(dbsize) = .-CNAME(dblow) 913#endif /* KDB */ 914