1/* $FreeBSD: stable/11/sys/powerpc/aim/trap_subr32.S 316369 2017-04-01 19:27:06Z jhibbits $ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* 43 * Save/restore segment registers 44 */ 45#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46 lwz sr,1*4(pmap); mtsr 1,sr; \ 47 lwz sr,2*4(pmap); mtsr 2,sr; \ 48 lwz sr,3*4(pmap); mtsr 3,sr; \ 49 lwz sr,4*4(pmap); mtsr 4,sr; \ 50 lwz sr,5*4(pmap); mtsr 5,sr; \ 51 lwz sr,6*4(pmap); mtsr 6,sr; \ 52 lwz sr,7*4(pmap); mtsr 7,sr; \ 53 lwz sr,8*4(pmap); mtsr 8,sr; \ 54 lwz sr,9*4(pmap); mtsr 9,sr; \ 55 lwz sr,10*4(pmap); mtsr 10,sr; \ 56 lwz sr,11*4(pmap); mtsr 11,sr; \ 57 /* Skip segment 12 (USER_SR), which is restored differently */ \ 58 lwz sr,13*4(pmap); mtsr 13,sr; \ 59 lwz sr,14*4(pmap); mtsr 14,sr; \ 60 lwz sr,15*4(pmap); mtsr 15,sr; isync; 61 62/* 63 * User SRs are loaded through a pointer to the current pmap. 64 */ 65#define RESTORE_USER_SRS(pmap,sr) \ 66 GET_CPUINFO(pmap); \ 67 lwz pmap,PC_CURPMAP(pmap); \ 68 lwzu sr,PM_SR(pmap); \ 69 RESTORE_SRS(pmap,sr) \ 70 /* Restore SR 12 */ \ 71 lwz sr,12*4(pmap); mtsr 12,sr 72 73/* 74 * Kernel SRs are loaded directly from kernel_pmap_ 75 */ 76#define RESTORE_KERN_SRS(pmap,sr) \ 77 lwz pmap,TRAP_TOCBASE(0); \ 78 lwz pmap,CNAME(kernel_pmap_store)@got(pmap); \ 79 lwzu sr,PM_SR(pmap); \ 80 RESTORE_SRS(pmap,sr) 81 82/* 83 * FRAME_SETUP assumes: 84 * SPRG1 SP (1) 85 * SPRG3 trap type 86 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 87 * r28 LR 88 * r29 CR 89 * r30 scratch 90 * r31 scratch 91 * r1 kernel stack 92 * SRR0/1 as at start of trap 93 */ 94#define FRAME_SETUP(savearea) \ 95/* Have to enable translation to allow access of kernel stack: */ \ 96 GET_CPUINFO(%r31); \ 97 mfsrr0 %r30; \ 98 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 99 mfsrr1 %r30; \ 100 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 101 mfmsr %r30; \ 102 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 103 mtmsr %r30; /* stack can now be accessed */ \ 104 isync; \ 105 mfsprg1 %r31; /* get saved SP */ \ 106 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 107 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 108 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 109 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 110 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 111 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 112 GET_CPUINFO(%r2); \ 113 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 114 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 115 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 116 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 117 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 118 stw %r4, FRAME_4+8(%r1); \ 119 stw %r5, FRAME_5+8(%r1); \ 120 stw %r6, FRAME_6+8(%r1); \ 121 stw %r7, FRAME_7+8(%r1); \ 122 stw %r8, FRAME_8+8(%r1); \ 123 stw %r9, FRAME_9+8(%r1); \ 124 stw %r10, FRAME_10+8(%r1); \ 125 stw %r11, FRAME_11+8(%r1); \ 126 stw %r12, FRAME_12+8(%r1); \ 127 stw %r13, FRAME_13+8(%r1); \ 128 stw %r14, FRAME_14+8(%r1); \ 129 stw %r15, FRAME_15+8(%r1); \ 130 stw %r16, FRAME_16+8(%r1); \ 131 stw %r17, FRAME_17+8(%r1); \ 132 stw %r18, FRAME_18+8(%r1); \ 133 stw %r19, FRAME_19+8(%r1); \ 134 stw %r20, FRAME_20+8(%r1); \ 135 stw %r21, FRAME_21+8(%r1); \ 136 stw %r22, FRAME_22+8(%r1); \ 137 stw %r23, FRAME_23+8(%r1); \ 138 stw %r24, FRAME_24+8(%r1); \ 139 stw %r25, FRAME_25+8(%r1); \ 140 stw %r26, FRAME_26+8(%r1); \ 141 stw %r27, FRAME_27+8(%r1); \ 142 stw %r28, FRAME_28+8(%r1); \ 143 stw %r29, FRAME_29+8(%r1); \ 144 stw %r30, FRAME_30+8(%r1); \ 145 stw %r31, FRAME_31+8(%r1); \ 146 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 147 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 148 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 149 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 150 mfxer %r3; \ 151 mfctr %r4; \ 152 mfsprg3 %r5; \ 153 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 154 stw %r4, FRAME_CTR+8(1); \ 155 stw %r5, FRAME_EXC+8(1); \ 156 stw %r28,FRAME_AIM_DAR+8(1); \ 157 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 158 stw %r30,FRAME_SRR0+8(1); \ 159 stw %r31,FRAME_SRR1+8(1); \ 160 lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */ 161 162#define FRAME_LEAVE(savearea) \ 163/* Disable exceptions: */ \ 164 mfmsr %r2; \ 165 andi. %r2,%r2,~PSL_EE@l; \ 166 mtmsr %r2; \ 167 isync; \ 168/* Now restore regs: */ \ 169 lwz %r2,FRAME_SRR0+8(%r1); \ 170 lwz %r3,FRAME_SRR1+8(%r1); \ 171 lwz %r4,FRAME_CTR+8(%r1); \ 172 lwz %r5,FRAME_XER+8(%r1); \ 173 lwz %r6,FRAME_LR+8(%r1); \ 174 GET_CPUINFO(%r7); \ 175 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 176 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 177 lwz %r7,FRAME_CR+8(%r1); \ 178 mtctr %r4; \ 179 mtxer %r5; \ 180 mtlr %r6; \ 181 mtsprg1 %r7; /* save cr */ \ 182 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 183 lwz %r30,FRAME_30+8(%r1); \ 184 lwz %r29,FRAME_29+8(%r1); \ 185 lwz %r28,FRAME_28+8(%r1); \ 186 lwz %r27,FRAME_27+8(%r1); \ 187 lwz %r26,FRAME_26+8(%r1); \ 188 lwz %r25,FRAME_25+8(%r1); \ 189 lwz %r24,FRAME_24+8(%r1); \ 190 lwz %r23,FRAME_23+8(%r1); \ 191 lwz %r22,FRAME_22+8(%r1); \ 192 lwz %r21,FRAME_21+8(%r1); \ 193 lwz %r20,FRAME_20+8(%r1); \ 194 lwz %r19,FRAME_19+8(%r1); \ 195 lwz %r18,FRAME_18+8(%r1); \ 196 lwz %r17,FRAME_17+8(%r1); \ 197 lwz %r16,FRAME_16+8(%r1); \ 198 lwz %r15,FRAME_15+8(%r1); \ 199 lwz %r14,FRAME_14+8(%r1); \ 200 lwz %r13,FRAME_13+8(%r1); \ 201 lwz %r12,FRAME_12+8(%r1); \ 202 lwz %r11,FRAME_11+8(%r1); \ 203 lwz %r10,FRAME_10+8(%r1); \ 204 lwz %r9, FRAME_9+8(%r1); \ 205 lwz %r8, FRAME_8+8(%r1); \ 206 lwz %r7, FRAME_7+8(%r1); \ 207 lwz %r6, FRAME_6+8(%r1); \ 208 lwz %r5, FRAME_5+8(%r1); \ 209 lwz %r4, FRAME_4+8(%r1); \ 210 lwz %r3, FRAME_3+8(%r1); \ 211 lwz %r2, FRAME_2+8(%r1); \ 212 lwz %r0, FRAME_0+8(%r1); \ 213 lwz %r1, FRAME_1+8(%r1); \ 214/* Can't touch %r1 from here on */ \ 215 mtsprg2 %r2; /* save r2 & r3 */ \ 216 mtsprg3 %r3; \ 217/* Disable translation, machine check and recoverability: */ \ 218 mfmsr %r2; \ 219 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 220 mtmsr %r2; \ 221 isync; \ 222/* Decide whether we return to user mode: */ \ 223 GET_CPUINFO(%r2); \ 224 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 225 mtcr %r3; \ 226 bf 17,1f; /* branch if PSL_PR is false */ \ 227/* Restore user SRs */ \ 228 RESTORE_USER_SRS(%r2,%r3); \ 2291: mfsprg1 %r2; /* restore cr */ \ 230 mtcr %r2; \ 231 GET_CPUINFO(%r2); \ 232 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 233 mtsrr0 %r3; \ 234 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 235 \ 236 /* Make sure HV bit of MSR propagated to SRR1 */ \ 237 mfmsr %r2; \ 238 or %r3,%r2,%r3; \ 239 \ 240 mtsrr1 %r3; \ 241 mfsprg2 %r2; /* restore r2 & r3 */ \ 242 mfsprg3 %r3 243 244#ifdef KDTRACE_HOOKS 245 .data 246 .globl dtrace_invop_calltrap_addr 247 .align 4 248 .type dtrace_invop_calltrap_addr, @object 249 .size dtrace_invop_calltrap_addr, 4 250dtrace_invop_calltrap_addr: 251 .word 0 252 .word 0 253 254 .text 255#endif 256 257/* 258 * The next two routines are 64-bit glue code. The first is used to test if 259 * we are on a 64-bit system. By copying it to the illegal instruction 260 * handler, we can test for 64-bit mode by trying to execute a 64-bit 261 * instruction and seeing what happens. The second gets copied in front 262 * of all the other handlers to restore 32-bit bridge mode when traps 263 * are taken. 264 */ 265 266/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 267 268 .globl CNAME(testppc64),CNAME(testppc64size) 269CNAME(testppc64): 270 mtsprg1 %r31 271 mfsrr0 %r31 272 addi %r31, %r31, 4 273 mtsrr0 %r31 274 275 li %r31, 0 276 mtsprg2 %r31 277 mfsprg1 %r31 278 279 rfi 280CNAME(testppc64size) = .-CNAME(testppc64) 281 282 283/* 64-bit bridge mode restore snippet. Gets copied in front of everything else 284 * on 64-bit systems. */ 285 286 .globl CNAME(restorebridge),CNAME(restorebridgesize) 287CNAME(restorebridge): 288 mtsprg1 %r31 289 mfmsr %r31 290 clrldi %r31,%r31,1 291 mtmsrd %r31 292 mfsprg1 %r31 293 isync 294CNAME(restorebridgesize) = .-CNAME(restorebridge) 295 296/* 297 * Processor reset exception handler. These are typically 298 * the first instructions the processor executes after a 299 * software reset. We do this in two bits so that we are 300 * not still hanging around in the trap handling region 301 * once the MMU is turned on. 302 */ 303 .globl CNAME(rstcode), CNAME(rstcodeend) 304CNAME(rstcode): 305 bl 1f 306 .long cpu_reset 3071: mflr %r31 308 lwz %r31,0(%r31) 309 mtlr %r31 310 blrl 311CNAME(rstcodeend): 312 313cpu_reset: 314 bl 1f 315 316 .space 124 317 3181: 319 mflr %r1 320 addi %r1,%r1,(124-16)@l 321 322 bl CNAME(cpudep_ap_early_bootstrap) 323 lis %r3,1@l 324 bl CNAME(pmap_cpu_bootstrap) 325 bl CNAME(cpudep_ap_bootstrap) 326 mr %r1,%r3 327 bl CNAME(cpudep_ap_setup) 328 GET_CPUINFO(%r5) 329 lwz %r3,(PC_RESTORE)(%r5) 330 cmplwi %cr0,%r3,0 331 beq %cr0,2f 332 li %r4, 1 333 b CNAME(longjmp) 3342: 335#ifdef SMP 336 bl CNAME(machdep_ap_bootstrap) 337#endif 338 339 /* Should not be reached */ 3409: 341 b 9b 342 343/* 344 * This code gets copied to all the trap vectors 345 * (except ISI/DSI, ALI, and the interrupts) 346 */ 347 348 .globl CNAME(trapcode),CNAME(trapcodeend) 349CNAME(trapcode): 350 mtsprg1 %r1 /* save SP */ 351 mflr %r1 /* Save the old LR in r1 */ 352 mtsprg2 %r1 /* And then in SPRG2 */ 353 lwz %r1, TRAP_GENTRAP(0) /* Get branch address */ 354 mtlr %r1 355 li %r1, 0xe0 /* How to get the vector from LR */ 356 blrl /* LR & (0xff00 | r1) is exception # */ 357CNAME(trapcodeend): 358 359/* 360 * For ALI: has to save DSISR and DAR 361 */ 362 .globl CNAME(alitrap),CNAME(aliend) 363CNAME(alitrap): 364 mtsprg1 %r1 /* save SP */ 365 GET_CPUINFO(%r1) 366 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 367 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 368 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 369 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 370 mfdar %r30 371 mfdsisr %r31 372 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 373 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 374 mfsprg1 %r1 /* restore SP, in case of branch */ 375 mflr %r28 /* save LR */ 376 mfcr %r29 /* save CR */ 377 378 /* Put our exception vector in SPRG3 */ 379 li %r31, EXC_ALI 380 mtsprg3 %r31 381 382 /* Test whether we already had PR set */ 383 mfsrr1 %r31 384 mtcr %r31 385 386 /* Jump to s_trap */ 387 bl 1f 388 .long s_trap 3891: mflr %r31 390 lwz %r31,0(%r31) 391 mtlr %r31 392 blrl 393CNAME(aliend): 394 395/* 396 * G2 specific: instuction TLB miss. 397 */ 398 .globl CNAME(imisstrap),CNAME(imisssize) 399CNAME(imisstrap): 400 mfspr %r2, SPR_HASH1 /* get first pointer */ 401 addi %r1, 0, 8 /* load 8 for counter */ 402 mfctr %r0 /* save counter */ 403 mfspr %r3, SPR_ICMP /* get first compare value */ 404 addi %r2, %r2, -8 /* pre dec the pointer */ 405im0: 406 mtctr %r1 /* load counter */ 407im1: 408 lwzu %r1, 8(%r2) /* get next pte */ 409 cmp 0, 0, %r1, %r3 /* see if found pte */ 410 bdnzf 2, im1 /* dec count br if cmp ne and if 411 * count not zero */ 412 bne instr_sec_hash /* if not found set up second hash 413 * or exit */ 414 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 415 andi. %r3, %r1, 8 /* check G bit */ 416 bne do_isi_prot /* if guarded, take an ISI */ 417 mtctr %r0 /* restore counter */ 418 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ 419 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 420 mtcrf 0x80, %r3 /* restore CR0 */ 421 mtspr SPR_RPA, %r1 /* set the pte */ 422 ori %r1, %r1, 0x100 /* set reference bit */ 423 srwi %r1, %r1, 8 /* get byte 7 of pte */ 424 tlbli %r0 /* load the itlb */ 425 stb %r1, +6(%r2) /* update page table */ 426 rfi /* return to executing program */ 427 428instr_sec_hash: 429 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 430 bne do_isi /* if so, go to ISI interrupt */ 431 mfspr %r2, SPR_HASH2 /* get the second pointer */ 432 ori %r3, %r3, 0x0040 /* change the compare value */ 433 addi %r1, %r0, 8 /* load 8 for counter */ 434 addi %r2, %r2, -8 /* pre dec for update on load */ 435 b im0 /* try second hash */ 436 437/* Create a faked ISI interrupt as the address was not found */ 438do_isi_prot: 439 mfspr %r3, SPR_SRR1 /* get srr1 */ 440 andi. %r2, %r3, 0xffff /* clean upper srr1 */ 441 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot 442 * violation */ 443 b isi1 444do_isi: 445 mfspr %r3, SPR_SRR1 /* get srr1 */ 446 andi. %r2, %r3, 0xffff /* clean srr1 */ 447 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte 448 * not found */ 449isi1: 450 mtctr %r0 /* restore counter */ 451 mtspr SPR_SRR1, %r2 /* set srr1 */ 452 mfmsr %r0 /* get msr */ 453 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 454 mtcrf 0x80, %r3 /* restore CR0 */ 455 mtmsr %r0 /* flip back to the native gprs */ 456 ba EXC_ISI /* go to instr. access interrupt */ 457 458CNAME(imisssize) = .-CNAME(imisstrap) 459 460/* 461 * G2 specific: data load TLB miss. 462 */ 463 .globl CNAME(dlmisstrap),CNAME(dlmisssize) 464CNAME(dlmisstrap): 465 mfspr %r2, SPR_HASH1 /* get first pointer */ 466 addi %r1, 0, 8 /* load 8 for counter */ 467 mfctr %r0 /* save counter */ 468 mfspr %r3, SPR_DCMP /* get first compare value */ 469 addi %r2, %r2, -8 /* pre dec the pointer */ 470dm0: 471 mtctr %r1 /* load counter */ 472dm1: 473 lwzu %r1, 8(%r2) /* get next pte */ 474 cmp 0, 0, %r1, %r3 /* see if found pte */ 475 bdnzf 2, dm1 /* dec count br if cmp ne and if 476 * count not zero */ 477 bne data_sec_hash /* if not found set up second hash 478 * or exit */ 479 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 480 mtctr %r0 /* restore counter */ 481 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 482 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 483 mtcrf 0x80, %r3 /* restore CR0 */ 484 mtspr SPR_RPA, %r1 /* set the pte */ 485 ori %r1, %r1, 0x100 /* set reference bit */ 486 srwi %r1, %r1, 8 /* get byte 7 of pte */ 487 tlbld %r0 /* load the dtlb */ 488 stb %r1, +6(%r2) /* update page table */ 489 rfi /* return to executing program */ 490 491data_sec_hash: 492 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 493 bne do_dsi /* if so, go to DSI interrupt */ 494 mfspr %r2, SPR_HASH2 /* get the second pointer */ 495 ori %r3, %r3, 0x0040 /* change the compare value */ 496 addi %r1, 0, 8 /* load 8 for counter */ 497 addi %r2, %r2, -8 /* pre dec for update on load */ 498 b dm0 /* try second hash */ 499 500CNAME(dlmisssize) = .-CNAME(dlmisstrap) 501 502/* 503 * G2 specific: data store TLB miss. 504 */ 505 .globl CNAME(dsmisstrap),CNAME(dsmisssize) 506CNAME(dsmisstrap): 507 mfspr %r2, SPR_HASH1 /* get first pointer */ 508 addi %r1, 0, 8 /* load 8 for counter */ 509 mfctr %r0 /* save counter */ 510 mfspr %r3, SPR_DCMP /* get first compare value */ 511 addi %r2, %r2, -8 /* pre dec the pointer */ 512ds0: 513 mtctr %r1 /* load counter */ 514ds1: 515 lwzu %r1, 8(%r2) /* get next pte */ 516 cmp 0, 0, %r1, %r3 /* see if found pte */ 517 bdnzf 2, ds1 /* dec count br if cmp ne and if 518 * count not zero */ 519 bne data_store_sec_hash /* if not found set up second hash 520 * or exit */ 521 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 522 andi. %r3, %r1, 0x80 /* check the C-bit */ 523 beq data_store_chk_prot /* if (C==0) 524 * go check protection modes */ 525ds2: 526 mtctr %r0 /* restore counter */ 527 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 528 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 529 mtcrf 0x80, %r3 /* restore CR0 */ 530 mtspr SPR_RPA, %r1 /* set the pte */ 531 tlbld %r0 /* load the dtlb */ 532 rfi /* return to executing program */ 533 534data_store_sec_hash: 535 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 536 bne do_dsi /* if so, go to DSI interrupt */ 537 mfspr %r2, SPR_HASH2 /* get the second pointer */ 538 ori %r3, %r3, 0x0040 /* change the compare value */ 539 addi %r1, 0, 8 /* load 8 for counter */ 540 addi %r2, %r2, -8 /* pre dec for update on load */ 541 b ds0 /* try second hash */ 542 543/* Check the protection before setting PTE(c-bit) */ 544data_store_chk_prot: 545 rlwinm. %r3,%r1,30,0,1 /* test PP */ 546 bge- chk0 /* if (PP == 00 or PP == 01) 547 * goto chk0: */ 548 andi. %r3, %r1, 1 /* test PP[0] */ 549 beq+ chk2 /* return if PP[0] == 0 */ 550 b do_dsi_prot /* else DSIp */ 551chk0: 552 mfspr %r3,SPR_SRR1 /* get old msr */ 553 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ 554 beq chk2 /* if (KEY==0) goto chk2: */ 555 b do_dsi_prot /* else do_dsi_prot */ 556chk2: 557 ori %r1, %r1, 0x180 /* set reference and change bit */ 558 sth %r1, 6(%r2) /* update page table */ 559 b ds2 /* and back we go */ 560 561/* Create a faked DSI interrupt as the address was not found */ 562do_dsi: 563 mfspr %r3, SPR_SRR1 /* get srr1 */ 564 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 565 * load/store, zero rest */ 566 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte 567 * not found */ 568 b dsi1 569 570do_dsi_prot: 571 mfspr %r3, SPR_SRR1 /* get srr1 */ 572 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 573 *load/store, zero rest */ 574 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot 575 * violation */ 576 577dsi1: 578 mtctr %r0 /* restore counter */ 579 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ 580 mtspr SPR_SRR1, %r2 /* set srr1 */ 581 mtspr SPR_DSISR, %r1 /* load the dsisr */ 582 mfspr %r1, SPR_DMISS /* get miss address */ 583 rlwinm. %r2,%r2,0,31,31 /* test LE bit */ 584 beq dsi2 /* if little endian then: */ 585 xor %r1, %r1, 0x07 /* de-mung the data address */ 586dsi2: 587 mtspr SPR_DAR, %r1 /* put in dar */ 588 mfmsr %r0 /* get msr */ 589 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 590 mtcrf 0x80, %r3 /* restore CR0 */ 591 mtmsr %r0 /* flip back to the native gprs */ 592 ba EXC_DSI /* branch to DSI interrupt */ 593 594CNAME(dsmisssize) = .-CNAME(dsmisstrap) 595 596/* 597 * Similar to the above for DSI 598 * Has to handle BAT spills 599 * and standard pagetable spills 600 */ 601 .globl CNAME(dsitrap),CNAME(dsiend) 602CNAME(dsitrap): 603 mtsprg1 %r1 /* save SP */ 604 GET_CPUINFO(%r1) 605 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 606 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 607 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 608 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 609 mfsprg1 %r1 /* restore SP */ 610 mfcr %r29 /* save CR */ 611 mfxer %r30 /* save XER */ 612 mtsprg2 %r30 /* in SPRG2 */ 613 mfsrr1 %r31 /* test kernel mode */ 614 mtcr %r31 615 bt 17,1f /* branch if PSL_PR is set */ 616 mfdar %r31 /* get fault address */ 617 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 618 619 /* get batu */ 620 lwz %r30,TRAP_TOCBASE(0) 621 lwz %r30,CNAME(battable)@got(%r30) 622 add %r31,%r30,%r31 623 lwz %r30,0(%r31) 624 mtcr %r30 625 bf 30,1f /* branch if supervisor valid is 626 false */ 627 /* get batl */ 628 lwz %r31,4(%r31) 629/* We randomly use the highest two bat registers here */ 630 mftb %r28 631 andi. %r28,%r28,1 632 bne 2f 633 mtdbatu 2,%r30 634 mtdbatl 2,%r31 635 b 3f 6362: 637 mtdbatu 3,%r30 638 mtdbatl 3,%r31 6393: 640 mfsprg2 %r30 /* restore XER */ 641 mtxer %r30 642 mtcr %r29 /* restore CR */ 643 mtsprg1 %r1 644 GET_CPUINFO(%r1) 645 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 646 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 647 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 648 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 649 mfsprg1 %r1 650 rfi /* return to trapped code */ 6511: 652 mflr %r28 /* save LR (SP already saved) */ 653 654 /* Jump to disitrap */ 655 bl 4f 656 .long disitrap 6574: mflr %r1 658 lwz %r1,0(%r1) 659 mtlr %r1 660 blrl 661CNAME(dsiend): 662 663/* 664 * Preamble code for DSI/ISI traps 665 */ 666disitrap: 667 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 668 mflr %r1 669 andi. %r1,%r1,0xff00 670 mtsprg3 %r1 671 672 GET_CPUINFO(%r1) 673 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 674 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 675 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 676 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 677 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 678 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 679 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 680 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 681 mfdar %r30 682 mfdsisr %r31 683 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 684 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 685 686#ifdef KDB 687 /* Try to detect a kernel stack overflow */ 688 mfsrr1 %r31 689 mtcr %r31 690 bt 17,realtrap /* branch is user mode */ 691 mfsprg1 %r31 /* get old SP */ 692 clrrwi %r31,%r31,12 /* Round SP down to nearest page */ 693 sub. %r30,%r31,%r30 /* SP - DAR */ 694 bge 1f 695 neg %r30,%r30 /* modulo value */ 6961: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 697 bge %cr0,realtrap /* no, too far away. */ 698 699 /* Now convert this DSI into a DDB trap. */ 700 GET_CPUINFO(%r1) 701 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 702 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 703 lwz %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 704 stw %r31,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 705 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 706 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 707 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 708 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 709 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 710 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 711 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 712 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 713 b dbtrap 714#endif 715 716 /* XXX need stack probe here */ 717realtrap: 718/* Test whether we already had PR set */ 719 mfsrr1 %r1 720 mtcr %r1 721 mfsprg1 %r1 /* restore SP (might have been 722 overwritten) */ 723 bf 17,k_trap /* branch if PSL_PR is false */ 724 GET_CPUINFO(%r1) 725 lwz %r1,PC_CURPCB(%r1) 726 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 727 b s_trap 728 729/* 730 * generictrap does some standard setup for trap handling to minimize 731 * the code that need be installed in the actual vectors. It expects 732 * the following conditions. 733 * 734 * R1 - Trap vector = LR & (0xff00 | R1) 735 * SPRG1 - Original R1 contents 736 * SPRG2 - Original LR 737 */ 738 739 .globl CNAME(generictrap64) 740generictrap64: 741 mtsprg3 %r31 742 mfmsr %r31 743 clrldi %r31,%r31,1 744 mtmsrd %r31 745 mfsprg3 %r31 746 isync 747 748 .globl CNAME(generictrap) 749generictrap: 750 /* Save R1 for computing the exception vector */ 751 mtsprg3 %r1 752 753 /* Save interesting registers */ 754 GET_CPUINFO(%r1) 755 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 756 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 757 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 758 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 759 mfsprg1 %r1 /* restore SP, in case of branch */ 760 mfsprg2 %r28 /* save LR */ 761 mfcr %r29 /* save CR */ 762 763 /* Compute the exception vector from the link register */ 764 mfsprg3 %r31 765 ori %r31,%r31,0xff00 766 mflr %r30 767 and %r30,%r30,%r31 768 mtsprg3 %r30 769 770 /* Test whether we already had PR set */ 771 mfsrr1 %r31 772 mtcr %r31 773 774s_trap: 775 bf 17,k_trap /* branch if PSL_PR is false */ 776 GET_CPUINFO(%r1) 777u_trap: 778 lwz %r1,PC_CURPCB(%r1) 779 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 780 781/* 782 * Now the common trap catching code. 783 */ 784k_trap: 785 FRAME_SETUP(PC_TEMPSAVE) 786 /* Restore USER_SR */ 787 GET_CPUINFO(%r30) 788 lwz %r30,PC_CURPCB(%r30) 789 lwz %r30,PCB_AIM_USR_VSID(%r30) 790 mtsr USER_SR,%r30; sync; isync 791/* Call C interrupt dispatcher: */ 792trapagain: 793 addi %r3,%r1,8 794 bl CNAME(powerpc_interrupt) 795 .globl CNAME(trapexit) /* backtrace code sentinel */ 796CNAME(trapexit): 797 798/* Disable interrupts: */ 799 mfmsr %r3 800 andi. %r3,%r3,~PSL_EE@l 801 mtmsr %r3 802/* Test AST pending: */ 803 lwz %r5,FRAME_SRR1+8(%r1) 804 mtcr %r5 805 bf 17,1f /* branch if PSL_PR is false */ 806 807 GET_CPUINFO(%r3) /* get per-CPU pointer */ 808 lwz %r4, TD_FLAGS(%r2) /* get thread flags value 809 * (r2 is curthread) */ 810 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 811 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 812 and. %r4,%r4,%r5 813 beq 1f 814 mfmsr %r3 /* re-enable interrupts */ 815 ori %r3,%r3,PSL_EE@l 816 mtmsr %r3 817 isync 818 addi %r3,%r1,8 819 bl CNAME(ast) 820 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 821CNAME(asttrapexit): 822 b trapexit /* test ast ret value ? */ 8231: 824 FRAME_LEAVE(PC_TEMPSAVE) 825 826 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 827CNAME(rfi_patch1): 828 rfi 829 830 .globl CNAME(rfid_patch) 831CNAME(rfid_patch): 832 rfid 833 834#if defined(KDB) 835/* 836 * Deliberate entry to dbtrap 837 */ 838 .globl CNAME(breakpoint) 839CNAME(breakpoint): 840 mtsprg1 %r1 841 mfmsr %r3 842 mtsrr1 %r3 843 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 844 mtmsr %r3 /* disable interrupts */ 845 isync 846 GET_CPUINFO(%r3) 847 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 848 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 849 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 850 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 851 mflr %r28 852 li %r29,EXC_BPT 853 mtlr %r29 854 mfcr %r29 855 mtsrr0 %r28 856 857/* 858 * Now the kdb trap catching code. 859 */ 860dbtrap: 861 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 862 mflr %r1 863 andi. %r1,%r1,0xff00 864 mtsprg3 %r1 865 866 lwz %r1,TRAP_TOCBASE(0) /* get new SP */ 867 lwz %r1,tmpstk@got(%r1) 868 addi %r1,%r1,TMPSTKSZ-16 869 870 FRAME_SETUP(PC_DBSAVE) 871/* Call C trap code: */ 872 addi %r3,%r1,8 873 bl CNAME(db_trap_glue) 874 or. %r3,%r3,%r3 875 bne dbleave 876/* This wasn't for KDB, so switch to real trap: */ 877 lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 878 GET_CPUINFO(%r4) 879 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 880 FRAME_LEAVE(PC_DBSAVE) 881 mtsprg1 %r1 /* prepare for entrance to realtrap */ 882 GET_CPUINFO(%r1) 883 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 884 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 885 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 886 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 887 mflr %r28 888 mfcr %r29 889 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 890 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 891 mfsprg1 %r1 892 b realtrap 893dbleave: 894 FRAME_LEAVE(PC_DBSAVE) 895 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 896CNAME(rfi_patch2): 897 rfi 898 899/* 900 * In case of KDB we want a separate trap catcher for it 901 */ 902 .globl CNAME(dblow),CNAME(dbend) 903CNAME(dblow): 904 mtsprg1 %r1 /* save SP */ 905 mtsprg2 %r29 /* save r29 */ 906 mfcr %r29 /* save CR in r29 */ 907 mfsrr1 %r1 908 mtcr %r1 909 bf 17,1f /* branch if privileged */ 910 /* Unprivileged case */ 911 mtcr %r29 /* put the condition register back */ 912 mfsprg2 %r29 /* ... and r29 */ 913 mflr %r1 /* save LR */ 914 mtsprg2 %r1 /* And then in SPRG2 */ 915 916 lwz %r1, TRAP_GENTRAP(0) /* Get branch address */ 917 mtlr %r1 918 li %r1, 0 /* How to get the vector from LR */ 919 blrl /* LR & (0xff00 | r1) is exception # */ 9201: 921 /* Privileged, so drop to KDB */ 922 GET_CPUINFO(%r1) 923 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 924 mfsprg2 %r28 /* r29 holds cr... */ 925 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 926 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 927 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 928 mflr %r28 /* save LR */ 929 930 /* Jump to dbtrap */ 931 bl 2f 932 .long dbtrap 9332: mflr %r1 934 lwz %r1,0(%r1) 935 mtlr %r1 936 blrl 937CNAME(dbend): 938#endif /* KDB */ 939