1/*- 2 * Copyright (c) 2003-2012 Broadcom Corporation 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31#ifndef __NLM_UCORE_LOADER_H__ 32#define __NLM_UCORE_LOADER_H__ 33 34/** 35* @file_name ucore_loader.h 36* @author Netlogic Microsystems 37* @brief Ucore loader API header 38*/ 39 40#define CODE_SIZE_PER_UCORE (4 << 10) 41 42static __inline__ void 43nlm_ucore_load_image(uint64_t nae_base, int ucore) 44{ 45 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET + 46 (ucore * CODE_SIZE_PER_UCORE); 47 uint32_t *p = (uint32_t *)ucore_app_bin; 48 int i, size; 49 50 size = sizeof(ucore_app_bin)/sizeof(uint32_t); 51 for (i = 0; i < size; i++, addr += 4) 52 nlm_store_word_daddr(addr, htobe32(p[i])); 53 54 /* add a 'nop' if number of instructions are odd */ 55 if (size & 0x1) 56 nlm_store_word_daddr(addr, 0x0); 57} 58 59static __inline int 60nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data) 61{ 62 uint32_t ucore_cfg; 63 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET; 64 65 if (index > 128) 66 return (-1); 67 68 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); 69 /* set iram to zero */ 70 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, 71 (ucore_cfg & ~(0x1 << 7))); 72 73 nlm_store_word_daddr(addr + (index * 4), data); 74 75 /* restore ucore config */ 76 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); 77 return (0); 78} 79 80static __inline uint32_t 81nlm_ucore_read_sharedmem(uint64_t nae_base, int index) 82{ 83 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET; 84 uint32_t ucore_cfg, val; 85 86 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); 87 /* set iram to zero */ 88 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, 89 (ucore_cfg & ~(0x1 << 7))); 90 91 val = nlm_load_word_daddr(addr + (index * 4)); 92 93 /* restore ucore config */ 94 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); 95 96 return val; 97} 98 99static __inline__ int 100nlm_ucore_load_all(uint64_t nae_base, uint32_t ucore_mask, int nae_reset_done) 101{ 102 int i, count = 0; 103 uint32_t mask; 104 uint32_t ucore_cfg = 0; 105 106 mask = ucore_mask & 0xffff; 107 108 /* Stop all ucores */ 109 if (nae_reset_done == 0) { /* Skip the Ucore reset if NAE reset is done */ 110 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); 111 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, 112 ucore_cfg | (1 << 24)); 113 114 /* poll for ucore to get in to a wait state */ 115 do { 116 ucore_cfg = nlm_read_nae_reg(nae_base, 117 NAE_RX_UCORE_CFG); 118 } while ((ucore_cfg & (1 << 25)) == 0); 119 } 120 121 for (i = 0; i < sizeof(ucore_mask) * NBBY; i++) { 122 if ((mask & (1 << i)) == 0) 123 continue; 124 nlm_ucore_load_image(nae_base, i); 125 count++; 126 } 127 128 /* Enable per-domain ucores */ 129 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); 130 131 /* write one to reset bits to put the ucores in reset */ 132 ucore_cfg = ucore_cfg | (((mask) & 0xffff) << 8); 133 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); 134 135 /* write zero to reset bits to pull them out of reset */ 136 ucore_cfg = ucore_cfg & (~(((mask) & 0xffff) << 8)) & ~(1 << 24); 137 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); 138 139 return (count); 140} 141#endif 142