sys.h revision 245879
1219820Sjeff/*- 2219820Sjeff * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3219820Sjeff * reserved. 4219820Sjeff * 5219820Sjeff * Redistribution and use in source and binary forms, with or without 6219820Sjeff * modification, are permitted provided that the following conditions are 7219820Sjeff * met: 8219820Sjeff * 9219820Sjeff * 1. Redistributions of source code must retain the above copyright 10219820Sjeff * notice, this list of conditions and the following disclaimer. 11219820Sjeff * 2. Redistributions in binary form must reproduce the above copyright 12219820Sjeff * notice, this list of conditions and the following disclaimer in 13219820Sjeff * the documentation and/or other materials provided with the 14219820Sjeff * distribution. 15219820Sjeff * 16219820Sjeff * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17219820Sjeff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18219820Sjeff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19219820Sjeff * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20219820Sjeff * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21219820Sjeff * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22219820Sjeff * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23219820Sjeff * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24219820Sjeff * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25219820Sjeff * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26219820Sjeff * THE POSSIBILITY OF SUCH DAMAGE. 27219820Sjeff * 28219820Sjeff * NETLOGIC_BSD 29219820Sjeff * $FreeBSD: head/sys/mips/nlm/hal/sys.h 245879 2013-01-24 14:33:25Z jchandra $ 30219820Sjeff */ 31219820Sjeff 32219820Sjeff#ifndef __NLM_HAL_SYS_H__ 33219820Sjeff#define __NLM_HAL_SYS_H__ 34219820Sjeff 35219820Sjeff/** 36219820Sjeff* @file_name sys.h 37219820Sjeff* @author Netlogic Microsystems 38219820Sjeff* @brief HAL for System configuration registers 39219820Sjeff*/ 40219820Sjeff#define SYS_CHIP_RESET 0x00 41219820Sjeff#define SYS_POWER_ON_RESET_CFG 0x01 42219820Sjeff#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02 43219820Sjeff#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03 44219820Sjeff#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04 45219820Sjeff#define SYS_EFUSE_DEVICE_CFG3 0x05 46219820Sjeff#define SYS_EFUSE_DEVICE_CFG4 0x06 47219820Sjeff#define SYS_EFUSE_DEVICE_CFG5 0x07 48219820Sjeff#define SYS_EFUSE_DEVICE_CFG6 0x08 49219820Sjeff#define SYS_EFUSE_DEVICE_CFG7 0x09 50219820Sjeff#define SYS_PLL_CTRL 0x0a 51219820Sjeff#define SYS_CPU_RESET 0x0b 52219820Sjeff#define SYS_CPU_NONCOHERENT_MODE 0x0d 53219820Sjeff#define SYS_CORE_DFS_DIS_CTRL 0x0e 54219820Sjeff#define SYS_CORE_DFS_RST_CTRL 0x0f 55219820Sjeff#define SYS_CORE_DFS_BYP_CTRL 0x10 56219820Sjeff#define SYS_CORE_DFS_PHA_CTRL 0x11 57219820Sjeff#define SYS_CORE_DFS_DIV_INC_CTRL 0x12 58219820Sjeff#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13 59219820Sjeff#define SYS_CORE_DFS_DIV_VALUE 0x14 60219820Sjeff#define SYS_RESET 0x15 61219820Sjeff#define SYS_DFS_DIS_CTRL 0x16 62219820Sjeff#define SYS_DFS_RST_CTRL 0x17 63219820Sjeff#define SYS_DFS_BYP_CTRL 0x18 64219820Sjeff#define SYS_DFS_DIV_INC_CTRL 0x19 65219820Sjeff#define SYS_DFS_DIV_DEC_CTRL 0x1a 66219820Sjeff#define SYS_DFS_DIV_VALUE0 0x1b 67219820Sjeff#define SYS_DFS_DIV_VALUE1 0x1c 68219820Sjeff#define SYS_SENSE_AMP_DLY 0x1d 69219820Sjeff#define SYS_SOC_SENSE_AMP_DLY 0x1e 70219820Sjeff#define SYS_CTRL0 0x1f 71219820Sjeff#define SYS_CTRL1 0x20 72219820Sjeff#define SYS_TIMEOUT_BS1 0x21 73219820Sjeff#define SYS_BYTE_SWAP 0x22 74219820Sjeff#define SYS_VRM_VID 0x23 75219820Sjeff#define SYS_PWR_RAM_CMD 0x24 76219820Sjeff#define SYS_PWR_RAM_ADDR 0x25 77219820Sjeff#define SYS_PWR_RAM_DATA0 0x26 78219820Sjeff#define SYS_PWR_RAM_DATA1 0x27 79219820Sjeff#define SYS_PWR_RAM_DATA2 0x28 80219820Sjeff#define SYS_PWR_UCODE 0x29 81219820Sjeff#define SYS_CPU0_PWR_STATUS 0x2a 82219820Sjeff#define SYS_CPU1_PWR_STATUS 0x2b 83219820Sjeff#define SYS_CPU2_PWR_STATUS 0x2c 84219820Sjeff#define SYS_CPU3_PWR_STATUS 0x2d 85219820Sjeff#define SYS_CPU4_PWR_STATUS 0x2e 86219820Sjeff#define SYS_CPU5_PWR_STATUS 0x2f 87219820Sjeff#define SYS_CPU6_PWR_STATUS 0x30 88219820Sjeff#define SYS_CPU7_PWR_STATUS 0x31 89219820Sjeff#define SYS_STATUS 0x32 90219820Sjeff#define SYS_INT_POL 0x33 91219820Sjeff#define SYS_INT_TYPE 0x34 92219820Sjeff#define SYS_INT_STATUS 0x35 93219820Sjeff#define SYS_INT_MASK0 0x36 94219820Sjeff#define SYS_INT_MASK1 0x37 95219820Sjeff#define SYS_UCO_S_ECC 0x38 96219820Sjeff#define SYS_UCO_M_ECC 0x39 97219820Sjeff#define SYS_UCO_ADDR 0x3a 98219820Sjeff#define SYS_UCO_INSTR 0x3b 99219820Sjeff#define SYS_MEM_BIST0 0x3c 100219820Sjeff#define SYS_MEM_BIST1 0x3d 101219820Sjeff#define SYS_MEM_BIST2 0x3e 102219820Sjeff#define SYS_MEM_BIST3 0x3f 103219820Sjeff#define SYS_MEM_BIST4 0x40 104219820Sjeff#define SYS_MEM_BIST5 0x41 105219820Sjeff#define SYS_MEM_BIST6 0x42 106219820Sjeff#define SYS_MEM_BIST7 0x43 107219820Sjeff#define SYS_MEM_BIST8 0x44 108219820Sjeff#define SYS_MEM_BIST9 0x45 109219820Sjeff#define SYS_MEM_BIST10 0x46 110219820Sjeff#define SYS_MEM_BIST11 0x47 111219820Sjeff#define SYS_MEM_BIST12 0x48 112219820Sjeff#define SYS_SCRTCH0 0x49 113219820Sjeff#define SYS_SCRTCH1 0x4a 114219820Sjeff#define SYS_SCRTCH2 0x4b 115219820Sjeff#define SYS_SCRTCH3 0x4c 116219820Sjeff 117219820Sjeff#if !defined(LOCORE) && !defined(__ASSEMBLY__) 118219820Sjeff 119219820Sjeff#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 120219820Sjeff#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) 121219820Sjeff#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 122219820Sjeff#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 123219820Sjeff 124219820Sjeffenum { 125219820Sjeff /* Don't change order and it must start from zero */ 126219820Sjeff DFS_DEVICE_NAE = 0, 127219820Sjeff DFS_DEVICE_SAE, 128219820Sjeff DFS_DEVICE_RSA, 129219820Sjeff DFS_DEVICE_DTRE, 130219820Sjeff DFS_DEVICE_CMP, 131219820Sjeff DFS_DEVICE_KBP, 132219820Sjeff DFS_DEVICE_DMC, 133219820Sjeff DFS_DEVICE_NAND, 134219820Sjeff DFS_DEVICE_MMC, 135219820Sjeff DFS_DEVICE_NOR, 136219820Sjeff DFS_DEVICE_CORE, 137219820Sjeff DFS_DEVICE_REGEX_SLOW, 138219820Sjeff DFS_DEVICE_REGEX_FAST, 139219820Sjeff DFS_DEVICE_SATA, 140219820Sjeff INVALID_DFS_DEVICE = 0xFF 141219820Sjeff}; 142219820Sjeff 143219820Sjeffstatic __inline 144219820Sjeffvoid nlm_sys_enable_block(uint64_t sys_base, int block) 145219820Sjeff{ 146219820Sjeff uint32_t dfsdis, mask; 147219820Sjeff 148219820Sjeff mask = 1 << block; 149219820Sjeff dfsdis = nlm_read_sys_reg(sys_base, SYS_DFS_DIS_CTRL); 150219820Sjeff if ((dfsdis & mask) == 0) 151219820Sjeff return; /* already enabled, nothing to do */ 152219820Sjeff dfsdis &= ~mask; 153219820Sjeff nlm_write_sys_reg(sys_base, SYS_DFS_DIS_CTRL, dfsdis); 154219820Sjeff} 155219820Sjeff 156219820Sjeff#endif 157219820Sjeff#endif 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