sys.h revision 233533 
1/*-
2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
3 * reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in
13 *    the documentation and/or other materials provided with the
14 *    distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * NETLOGIC_BSD
29 * $FreeBSD: head/sys/mips/nlm/hal/sys.h 233533 2012-03-27 07:39:05Z jchandra $
30 */
31
32#ifndef __NLM_HAL_SYS_H__
33#define	__NLM_HAL_SYS_H__
34
35/**
36* @file_name sys.h
37* @author Netlogic Microsystems
38* @brief HAL for System configuration registers
39*/
40#define	SYS_CHIP_RESET				0x00
41#define	SYS_POWER_ON_RESET_CFG			0x01
42#define	SYS_EFUSE_DEVICE_CFG_STATUS0		0x02
43#define	SYS_EFUSE_DEVICE_CFG_STATUS1		0x03
44#define	SYS_EFUSE_DEVICE_CFG_STATUS2		0x04
45#define	SYS_EFUSE_DEVICE_CFG3			0x05
46#define	SYS_EFUSE_DEVICE_CFG4			0x06
47#define	SYS_EFUSE_DEVICE_CFG5			0x07
48#define	SYS_EFUSE_DEVICE_CFG6			0x08
49#define	SYS_EFUSE_DEVICE_CFG7			0x09
50#define	SYS_PLL_CTRL				0x0a
51#define	SYS_CPU_RESET				0x0b
52#define	SYS_CPU_NONCOHERENT_MODE		0x0d
53#define	SYS_CORE_DFS_DIS_CTRL			0x0e
54#define	SYS_CORE_DFS_RST_CTRL			0x0f
55#define	SYS_CORE_DFS_BYP_CTRL			0x10
56#define	SYS_CORE_DFS_PHA_CTRL			0x11
57#define	SYS_CORE_DFS_DIV_INC_CTRL		0x12
58#define	SYS_CORE_DFS_DIV_DEC_CTRL		0x13
59#define	SYS_CORE_DFS_DIV_VALUE			0x14
60#define	SYS_RESET				0x15
61#define	SYS_DFS_DIS_CTRL			0x16
62#define	SYS_DFS_RST_CTRL			0x17
63#define	SYS_DFS_BYP_CTRL			0x18
64#define	SYS_DFS_DIV_INC_CTRL			0x19
65#define	SYS_DFS_DIV_DEC_CTRL			0x1a
66#define	SYS_DFS_DIV_VALUE0			0x1b
67#define	SYS_DFS_DIV_VALUE1			0x1c
68#define	SYS_SENSE_AMP_DLY			0x1d
69#define	SYS_SOC_SENSE_AMP_DLY			0x1e
70#define	SYS_CTRL0				0x1f
71#define	SYS_CTRL1				0x20
72#define	SYS_TIMEOUT_BS1				0x21
73#define	SYS_BYTE_SWAP				0x22
74#define	SYS_VRM_VID				0x23
75#define	SYS_PWR_RAM_CMD				0x24
76#define	SYS_PWR_RAM_ADDR			0x25
77#define	SYS_PWR_RAM_DATA0			0x26
78#define	SYS_PWR_RAM_DATA1			0x27
79#define	SYS_PWR_RAM_DATA2			0x28
80#define	SYS_PWR_UCODE				0x29
81#define	SYS_CPU0_PWR_STATUS			0x2a
82#define	SYS_CPU1_PWR_STATUS			0x2b
83#define	SYS_CPU2_PWR_STATUS			0x2c
84#define	SYS_CPU3_PWR_STATUS			0x2d
85#define	SYS_CPU4_PWR_STATUS			0x2e
86#define	SYS_CPU5_PWR_STATUS			0x2f
87#define	SYS_CPU6_PWR_STATUS			0x30
88#define	SYS_CPU7_PWR_STATUS			0x31
89#define	SYS_STATUS				0x32
90#define	SYS_INT_POL				0x33
91#define	SYS_INT_TYPE				0x34
92#define	SYS_INT_STATUS				0x35
93#define	SYS_INT_MASK0				0x36
94#define	SYS_INT_MASK1				0x37
95#define	SYS_UCO_S_ECC				0x38
96#define	SYS_UCO_M_ECC				0x39
97#define	SYS_UCO_ADDR				0x3a
98#define	SYS_UCO_INSTR				0x3b
99#define	SYS_MEM_BIST0				0x3c
100#define	SYS_MEM_BIST1				0x3d
101#define	SYS_MEM_BIST2				0x3e
102#define	SYS_MEM_BIST3				0x3f
103#define	SYS_MEM_BIST4				0x40
104#define	SYS_MEM_BIST5				0x41
105#define	SYS_MEM_BIST6				0x42
106#define	SYS_MEM_BIST7				0x43
107#define	SYS_MEM_BIST8				0x44
108#define	SYS_MEM_BIST9				0x45
109#define	SYS_MEM_BIST10				0x46
110#define	SYS_MEM_BIST11				0x47
111#define	SYS_MEM_BIST12				0x48
112#define	SYS_SCRTCH0				0x49
113#define	SYS_SCRTCH1				0x4a
114#define	SYS_SCRTCH2				0x4b
115#define	SYS_SCRTCH3				0x4c
116
117#if !defined(LOCORE) && !defined(__ASSEMBLY__)
118
119#define	nlm_read_sys_reg(b, r)		nlm_read_reg(b, r)
120#define	nlm_write_sys_reg(b, r, v)	nlm_write_reg(b, r, v)
121#define	nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
122#define	nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
123
124enum {
125	/* Don't change order and it must start from zero */
126	DFS_DEVICE_NAE = 0,
127	DFS_DEVICE_SAE,
128	DFS_DEVICE_RSA,
129	DFS_DEVICE_DTRE,
130	DFS_DEVICE_CMP,
131	DFS_DEVICE_KBP,
132	DFS_DEVICE_DMC,
133	DFS_DEVICE_NAND,
134	DFS_DEVICE_MMC,
135	DFS_DEVICE_NOR,
136	DFS_DEVICE_CORE,
137	DFS_DEVICE_REGEX_SLOW,
138	DFS_DEVICE_REGEX_FAST,
139	DFS_DEVICE_SATA,
140	INVALID_DFS_DEVICE = 0xFF
141};
142
143#endif
144#endif
145